1 /* 2 * Texas Instruments DSPS platforms "glue layer" 3 * 4 * Copyright (C) 2012, by Texas Instruments 5 * 6 * Based on the am35x "glue layer" code. 7 * 8 * This file is part of the Inventra Controller Driver for Linux. 9 * 10 * The Inventra Controller Driver for Linux is free software; you 11 * can redistribute it and/or modify it under the terms of the GNU 12 * General Public License version 2 as published by the Free Software 13 * Foundation. 14 * 15 * The Inventra Controller Driver for Linux is distributed in 16 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 17 * without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 * License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with The Inventra Controller Driver for Linux ; if not, 23 * write to the Free Software Foundation, Inc., 59 Temple Place, 24 * Suite 330, Boston, MA 02111-1307 USA 25 * 26 * musb_dsps.c will be a common file for all the TI DSPS platforms 27 * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x. 28 * For now only ti81x is using this and in future davinci.c, am35x.c 29 * da8xx.c would be merged to this file after testing. 30 */ 31 32 #include <linux/io.h> 33 #include <linux/err.h> 34 #include <linux/platform_device.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/module.h> 38 #include <linux/usb/usb_phy_generic.h> 39 #include <linux/platform_data/usb-omap.h> 40 #include <linux/sizes.h> 41 42 #include <linux/of.h> 43 #include <linux/of_device.h> 44 #include <linux/of_address.h> 45 #include <linux/of_irq.h> 46 #include <linux/usb/of.h> 47 48 #include <linux/debugfs.h> 49 50 #include "musb_core.h" 51 52 static const struct of_device_id musb_dsps_of_match[]; 53 54 /** 55 * DSPS musb wrapper register offset. 56 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS 57 * musb ips. 58 */ 59 struct dsps_musb_wrapper { 60 u16 revision; 61 u16 control; 62 u16 status; 63 u16 epintr_set; 64 u16 epintr_clear; 65 u16 epintr_status; 66 u16 coreintr_set; 67 u16 coreintr_clear; 68 u16 coreintr_status; 69 u16 phy_utmi; 70 u16 mode; 71 u16 tx_mode; 72 u16 rx_mode; 73 74 /* bit positions for control */ 75 unsigned reset:5; 76 77 /* bit positions for interrupt */ 78 unsigned usb_shift:5; 79 u32 usb_mask; 80 u32 usb_bitmap; 81 unsigned drvvbus:5; 82 83 unsigned txep_shift:5; 84 u32 txep_mask; 85 u32 txep_bitmap; 86 87 unsigned rxep_shift:5; 88 u32 rxep_mask; 89 u32 rxep_bitmap; 90 91 /* bit positions for phy_utmi */ 92 unsigned otg_disable:5; 93 94 /* bit positions for mode */ 95 unsigned iddig:5; 96 unsigned iddig_mux:5; 97 /* miscellaneous stuff */ 98 unsigned poll_timeout; 99 }; 100 101 /* 102 * register shadow for suspend 103 */ 104 struct dsps_context { 105 u32 control; 106 u32 epintr; 107 u32 coreintr; 108 u32 phy_utmi; 109 u32 mode; 110 u32 tx_mode; 111 u32 rx_mode; 112 }; 113 114 /** 115 * DSPS glue structure. 116 */ 117 struct dsps_glue { 118 struct device *dev; 119 struct platform_device *musb; /* child musb pdev */ 120 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */ 121 int vbus_irq; /* optional vbus irq */ 122 struct timer_list timer; /* otg_workaround timer */ 123 unsigned long last_timer; /* last timer data for each instance */ 124 bool sw_babble_enabled; 125 void __iomem *usbss_base; 126 127 struct dsps_context context; 128 struct debugfs_regset32 regset; 129 struct dentry *dbgfs_root; 130 }; 131 132 static const struct debugfs_reg32 dsps_musb_regs[] = { 133 { "revision", 0x00 }, 134 { "control", 0x14 }, 135 { "status", 0x18 }, 136 { "eoi", 0x24 }, 137 { "intr0_stat", 0x30 }, 138 { "intr1_stat", 0x34 }, 139 { "intr0_set", 0x38 }, 140 { "intr1_set", 0x3c }, 141 { "txmode", 0x70 }, 142 { "rxmode", 0x74 }, 143 { "autoreq", 0xd0 }, 144 { "srpfixtime", 0xd4 }, 145 { "tdown", 0xd8 }, 146 { "phy_utmi", 0xe0 }, 147 { "mode", 0xe8 }, 148 }; 149 150 static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms) 151 { 152 int wait; 153 154 if (wait_ms < 0) 155 wait = msecs_to_jiffies(glue->wrp->poll_timeout); 156 else 157 wait = msecs_to_jiffies(wait_ms); 158 159 mod_timer(&glue->timer, jiffies + wait); 160 } 161 162 /* 163 * If no vbus irq from the PMIC is configured, we need to poll VBUS status. 164 */ 165 static void dsps_mod_timer_optional(struct dsps_glue *glue) 166 { 167 if (glue->vbus_irq) 168 return; 169 170 dsps_mod_timer(glue, -1); 171 } 172 173 /* USBSS / USB AM335x */ 174 #define USBSS_IRQ_STATUS 0x28 175 #define USBSS_IRQ_ENABLER 0x2c 176 #define USBSS_IRQ_CLEARR 0x30 177 178 #define USBSS_IRQ_PD_COMP (1 << 2) 179 180 /** 181 * dsps_musb_enable - enable interrupts 182 */ 183 static void dsps_musb_enable(struct musb *musb) 184 { 185 struct device *dev = musb->controller; 186 struct platform_device *pdev = to_platform_device(dev->parent); 187 struct dsps_glue *glue = platform_get_drvdata(pdev); 188 const struct dsps_musb_wrapper *wrp = glue->wrp; 189 void __iomem *reg_base = musb->ctrl_base; 190 u32 epmask, coremask; 191 192 /* Workaround: setup IRQs through both register sets. */ 193 epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) | 194 ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift); 195 coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF); 196 197 musb_writel(reg_base, wrp->epintr_set, epmask); 198 musb_writel(reg_base, wrp->coreintr_set, coremask); 199 /* start polling for ID change in dual-role idle mode */ 200 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE && 201 musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) 202 dsps_mod_timer(glue, -1); 203 } 204 205 /** 206 * dsps_musb_disable - disable HDRC and flush interrupts 207 */ 208 static void dsps_musb_disable(struct musb *musb) 209 { 210 struct device *dev = musb->controller; 211 struct platform_device *pdev = to_platform_device(dev->parent); 212 struct dsps_glue *glue = platform_get_drvdata(pdev); 213 const struct dsps_musb_wrapper *wrp = glue->wrp; 214 void __iomem *reg_base = musb->ctrl_base; 215 216 musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); 217 musb_writel(reg_base, wrp->epintr_clear, 218 wrp->txep_bitmap | wrp->rxep_bitmap); 219 del_timer_sync(&glue->timer); 220 } 221 222 /* Caller must take musb->lock */ 223 static int dsps_check_status(struct musb *musb, void *unused) 224 { 225 void __iomem *mregs = musb->mregs; 226 struct device *dev = musb->controller; 227 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 228 const struct dsps_musb_wrapper *wrp = glue->wrp; 229 u8 devctl; 230 int skip_session = 0; 231 232 if (glue->vbus_irq) 233 del_timer(&glue->timer); 234 235 /* 236 * We poll because DSPS IP's won't expose several OTG-critical 237 * status change events (from the transceiver) otherwise. 238 */ 239 devctl = musb_readb(mregs, MUSB_DEVCTL); 240 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 241 usb_otg_state_string(musb->xceiv->otg->state)); 242 243 switch (musb->xceiv->otg->state) { 244 case OTG_STATE_A_WAIT_VRISE: 245 dsps_mod_timer_optional(glue); 246 break; 247 case OTG_STATE_A_WAIT_BCON: 248 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 249 skip_session = 1; 250 /* fall */ 251 252 case OTG_STATE_A_IDLE: 253 case OTG_STATE_B_IDLE: 254 if (!glue->vbus_irq) { 255 if (devctl & MUSB_DEVCTL_BDEVICE) { 256 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 257 MUSB_DEV_MODE(musb); 258 } else { 259 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 260 MUSB_HST_MODE(musb); 261 } 262 if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session) 263 musb_writeb(mregs, MUSB_DEVCTL, 264 MUSB_DEVCTL_SESSION); 265 } 266 dsps_mod_timer_optional(glue); 267 break; 268 case OTG_STATE_A_WAIT_VFALL: 269 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 270 musb_writel(musb->ctrl_base, wrp->coreintr_set, 271 MUSB_INTR_VBUSERROR << wrp->usb_shift); 272 break; 273 default: 274 break; 275 } 276 277 return 0; 278 } 279 280 static void otg_timer(unsigned long _musb) 281 { 282 struct musb *musb = (void *)_musb; 283 struct device *dev = musb->controller; 284 unsigned long flags; 285 int err; 286 287 err = pm_runtime_get(dev); 288 if ((err != -EINPROGRESS) && err < 0) { 289 dev_err(dev, "Poll could not pm_runtime_get: %i\n", err); 290 pm_runtime_put_noidle(dev); 291 292 return; 293 } 294 295 spin_lock_irqsave(&musb->lock, flags); 296 err = musb_queue_resume_work(musb, dsps_check_status, NULL); 297 if (err < 0) 298 dev_err(dev, "%s resume work: %i\n", __func__, err); 299 spin_unlock_irqrestore(&musb->lock, flags); 300 pm_runtime_mark_last_busy(dev); 301 pm_runtime_put_autosuspend(dev); 302 } 303 304 static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum) 305 { 306 u32 epintr; 307 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent); 308 const struct dsps_musb_wrapper *wrp = glue->wrp; 309 310 /* musb->lock might already been held */ 311 epintr = (1 << epnum) << wrp->rxep_shift; 312 musb_writel(musb->ctrl_base, wrp->epintr_status, epintr); 313 } 314 315 static irqreturn_t dsps_interrupt(int irq, void *hci) 316 { 317 struct musb *musb = hci; 318 void __iomem *reg_base = musb->ctrl_base; 319 struct device *dev = musb->controller; 320 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 321 const struct dsps_musb_wrapper *wrp = glue->wrp; 322 unsigned long flags; 323 irqreturn_t ret = IRQ_NONE; 324 u32 epintr, usbintr; 325 326 spin_lock_irqsave(&musb->lock, flags); 327 328 /* Get endpoint interrupts */ 329 epintr = musb_readl(reg_base, wrp->epintr_status); 330 musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift; 331 musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift; 332 333 if (epintr) 334 musb_writel(reg_base, wrp->epintr_status, epintr); 335 336 /* Get usb core interrupts */ 337 usbintr = musb_readl(reg_base, wrp->coreintr_status); 338 if (!usbintr && !epintr) 339 goto out; 340 341 musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift; 342 if (usbintr) 343 musb_writel(reg_base, wrp->coreintr_status, usbintr); 344 345 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", 346 usbintr, epintr); 347 348 if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) { 349 int drvvbus = musb_readl(reg_base, wrp->status); 350 void __iomem *mregs = musb->mregs; 351 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 352 int err; 353 354 err = musb->int_usb & MUSB_INTR_VBUSERROR; 355 if (err) { 356 /* 357 * The Mentor core doesn't debounce VBUS as needed 358 * to cope with device connect current spikes. This 359 * means it's not uncommon for bus-powered devices 360 * to get VBUS errors during enumeration. 361 * 362 * This is a workaround, but newer RTL from Mentor 363 * seems to allow a better one: "re"-starting sessions 364 * without waiting for VBUS to stop registering in 365 * devctl. 366 */ 367 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 368 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 369 dsps_mod_timer_optional(glue); 370 WARNING("VBUS error workaround (delay coming)\n"); 371 } else if (drvvbus) { 372 MUSB_HST_MODE(musb); 373 musb->xceiv->otg->default_a = 1; 374 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 375 dsps_mod_timer_optional(glue); 376 } else { 377 musb->is_active = 0; 378 MUSB_DEV_MODE(musb); 379 musb->xceiv->otg->default_a = 0; 380 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 381 } 382 383 /* NOTE: this must complete power-on within 100 ms. */ 384 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 385 drvvbus ? "on" : "off", 386 usb_otg_state_string(musb->xceiv->otg->state), 387 err ? " ERROR" : "", 388 devctl); 389 ret = IRQ_HANDLED; 390 } 391 392 if (musb->int_tx || musb->int_rx || musb->int_usb) 393 ret |= musb_interrupt(musb); 394 395 /* Poll for ID change and connect */ 396 switch (musb->xceiv->otg->state) { 397 case OTG_STATE_B_IDLE: 398 case OTG_STATE_A_WAIT_BCON: 399 dsps_mod_timer_optional(glue); 400 break; 401 default: 402 break; 403 } 404 405 out: 406 spin_unlock_irqrestore(&musb->lock, flags); 407 408 return ret; 409 } 410 411 static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue) 412 { 413 struct dentry *root; 414 struct dentry *file; 415 char buf[128]; 416 417 sprintf(buf, "%s.dsps", dev_name(musb->controller)); 418 root = debugfs_create_dir(buf, NULL); 419 if (!root) 420 return -ENOMEM; 421 glue->dbgfs_root = root; 422 423 glue->regset.regs = dsps_musb_regs; 424 glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs); 425 glue->regset.base = musb->ctrl_base; 426 427 file = debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset); 428 if (!file) { 429 debugfs_remove_recursive(root); 430 return -ENOMEM; 431 } 432 return 0; 433 } 434 435 static int dsps_musb_init(struct musb *musb) 436 { 437 struct device *dev = musb->controller; 438 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 439 struct platform_device *parent = to_platform_device(dev->parent); 440 const struct dsps_musb_wrapper *wrp = glue->wrp; 441 void __iomem *reg_base; 442 struct resource *r; 443 u32 rev, val; 444 int ret; 445 446 r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control"); 447 reg_base = devm_ioremap_resource(dev, r); 448 if (IS_ERR(reg_base)) 449 return PTR_ERR(reg_base); 450 musb->ctrl_base = reg_base; 451 452 /* NOP driver needs change if supporting dual instance */ 453 musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0); 454 if (IS_ERR(musb->xceiv)) 455 return PTR_ERR(musb->xceiv); 456 457 musb->phy = devm_phy_get(dev->parent, "usb2-phy"); 458 459 /* Returns zero if e.g. not clocked */ 460 rev = musb_readl(reg_base, wrp->revision); 461 if (!rev) 462 return -ENODEV; 463 464 usb_phy_init(musb->xceiv); 465 if (IS_ERR(musb->phy)) { 466 musb->phy = NULL; 467 } else { 468 ret = phy_init(musb->phy); 469 if (ret < 0) 470 return ret; 471 ret = phy_power_on(musb->phy); 472 if (ret) { 473 phy_exit(musb->phy); 474 return ret; 475 } 476 } 477 478 setup_timer(&glue->timer, otg_timer, (unsigned long) musb); 479 480 /* Reset the musb */ 481 musb_writel(reg_base, wrp->control, (1 << wrp->reset)); 482 483 musb->isr = dsps_interrupt; 484 485 /* reset the otgdisable bit, needed for host mode to work */ 486 val = musb_readl(reg_base, wrp->phy_utmi); 487 val &= ~(1 << wrp->otg_disable); 488 musb_writel(musb->ctrl_base, wrp->phy_utmi, val); 489 490 /* 491 * Check whether the dsps version has babble control enabled. 492 * In latest silicon revision the babble control logic is enabled. 493 * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control 494 * logic enabled. 495 */ 496 val = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 497 if (val & MUSB_BABBLE_RCV_DISABLE) { 498 glue->sw_babble_enabled = true; 499 val |= MUSB_BABBLE_SW_SESSION_CTRL; 500 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val); 501 } 502 503 dsps_mod_timer(glue, -1); 504 505 return dsps_musb_dbg_init(musb, glue); 506 } 507 508 static int dsps_musb_exit(struct musb *musb) 509 { 510 struct device *dev = musb->controller; 511 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 512 513 del_timer_sync(&glue->timer); 514 usb_phy_shutdown(musb->xceiv); 515 phy_power_off(musb->phy); 516 phy_exit(musb->phy); 517 debugfs_remove_recursive(glue->dbgfs_root); 518 519 return 0; 520 } 521 522 static int dsps_musb_set_mode(struct musb *musb, u8 mode) 523 { 524 struct device *dev = musb->controller; 525 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 526 const struct dsps_musb_wrapper *wrp = glue->wrp; 527 void __iomem *ctrl_base = musb->ctrl_base; 528 u32 reg; 529 530 reg = musb_readl(ctrl_base, wrp->mode); 531 532 switch (mode) { 533 case MUSB_HOST: 534 reg &= ~(1 << wrp->iddig); 535 536 /* 537 * if we're setting mode to host-only or device-only, we're 538 * going to ignore whatever the PHY sends us and just force 539 * ID pin status by SW 540 */ 541 reg |= (1 << wrp->iddig_mux); 542 543 musb_writel(ctrl_base, wrp->mode, reg); 544 musb_writel(ctrl_base, wrp->phy_utmi, 0x02); 545 break; 546 case MUSB_PERIPHERAL: 547 reg |= (1 << wrp->iddig); 548 549 /* 550 * if we're setting mode to host-only or device-only, we're 551 * going to ignore whatever the PHY sends us and just force 552 * ID pin status by SW 553 */ 554 reg |= (1 << wrp->iddig_mux); 555 556 musb_writel(ctrl_base, wrp->mode, reg); 557 break; 558 case MUSB_OTG: 559 musb_writel(ctrl_base, wrp->phy_utmi, 0x02); 560 break; 561 default: 562 dev_err(glue->dev, "unsupported mode %d\n", mode); 563 return -EINVAL; 564 } 565 566 return 0; 567 } 568 569 static bool dsps_sw_babble_control(struct musb *musb) 570 { 571 u8 babble_ctl; 572 bool session_restart = false; 573 574 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 575 dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n", 576 babble_ctl); 577 /* 578 * check line monitor flag to check whether babble is 579 * due to noise 580 */ 581 dev_dbg(musb->controller, "STUCK_J is %s\n", 582 babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset"); 583 584 if (babble_ctl & MUSB_BABBLE_STUCK_J) { 585 int timeout = 10; 586 587 /* 588 * babble is due to noise, then set transmit idle (d7 bit) 589 * to resume normal operation 590 */ 591 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 592 babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE; 593 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl); 594 595 /* wait till line monitor flag cleared */ 596 dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n"); 597 do { 598 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 599 udelay(1); 600 } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--); 601 602 /* check whether stuck_at_j bit cleared */ 603 if (babble_ctl & MUSB_BABBLE_STUCK_J) { 604 /* 605 * real babble condition has occurred 606 * restart the controller to start the 607 * session again 608 */ 609 dev_dbg(musb->controller, "J not cleared, misc (%x)\n", 610 babble_ctl); 611 session_restart = true; 612 } 613 } else { 614 session_restart = true; 615 } 616 617 return session_restart; 618 } 619 620 static int dsps_musb_recover(struct musb *musb) 621 { 622 struct device *dev = musb->controller; 623 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 624 int session_restart = 0; 625 626 if (glue->sw_babble_enabled) 627 session_restart = dsps_sw_babble_control(musb); 628 else 629 session_restart = 1; 630 631 return session_restart ? 0 : -EPIPE; 632 } 633 634 /* Similar to am35x, dm81xx support only 32-bit read operation */ 635 static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 636 { 637 void __iomem *fifo = hw_ep->fifo; 638 639 if (len >= 4) { 640 ioread32_rep(fifo, dst, len >> 2); 641 dst += len & ~0x03; 642 len &= 0x03; 643 } 644 645 /* Read any remaining 1 to 3 bytes */ 646 if (len > 0) { 647 u32 val = musb_readl(fifo, 0); 648 memcpy(dst, &val, len); 649 } 650 } 651 652 #ifdef CONFIG_USB_TI_CPPI41_DMA 653 static void dsps_dma_controller_callback(struct dma_controller *c) 654 { 655 struct musb *musb = c->musb; 656 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent); 657 void __iomem *usbss_base = glue->usbss_base; 658 u32 status; 659 660 status = musb_readl(usbss_base, USBSS_IRQ_STATUS); 661 if (status & USBSS_IRQ_PD_COMP) 662 musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP); 663 } 664 665 static struct dma_controller * 666 dsps_dma_controller_create(struct musb *musb, void __iomem *base) 667 { 668 struct dma_controller *controller; 669 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent); 670 void __iomem *usbss_base = glue->usbss_base; 671 672 controller = cppi41_dma_controller_create(musb, base); 673 if (IS_ERR_OR_NULL(controller)) 674 return controller; 675 676 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP); 677 controller->dma_callback = dsps_dma_controller_callback; 678 679 return controller; 680 } 681 682 static void dsps_dma_controller_destroy(struct dma_controller *c) 683 { 684 struct musb *musb = c->musb; 685 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent); 686 void __iomem *usbss_base = glue->usbss_base; 687 688 musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP); 689 cppi41_dma_controller_destroy(c); 690 } 691 692 #ifdef CONFIG_PM_SLEEP 693 static void dsps_dma_controller_suspend(struct dsps_glue *glue) 694 { 695 void __iomem *usbss_base = glue->usbss_base; 696 697 musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP); 698 } 699 700 static void dsps_dma_controller_resume(struct dsps_glue *glue) 701 { 702 void __iomem *usbss_base = glue->usbss_base; 703 704 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP); 705 } 706 #endif 707 #else /* CONFIG_USB_TI_CPPI41_DMA */ 708 #ifdef CONFIG_PM_SLEEP 709 static void dsps_dma_controller_suspend(struct dsps_glue *glue) {} 710 static void dsps_dma_controller_resume(struct dsps_glue *glue) {} 711 #endif 712 #endif /* CONFIG_USB_TI_CPPI41_DMA */ 713 714 static struct musb_platform_ops dsps_ops = { 715 .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP, 716 .init = dsps_musb_init, 717 .exit = dsps_musb_exit, 718 719 #ifdef CONFIG_USB_TI_CPPI41_DMA 720 .dma_init = dsps_dma_controller_create, 721 .dma_exit = dsps_dma_controller_destroy, 722 #endif 723 .enable = dsps_musb_enable, 724 .disable = dsps_musb_disable, 725 726 .set_mode = dsps_musb_set_mode, 727 .recover = dsps_musb_recover, 728 .clear_ep_rxintr = dsps_musb_clear_ep_rxintr, 729 }; 730 731 static u64 musb_dmamask = DMA_BIT_MASK(32); 732 733 static int get_int_prop(struct device_node *dn, const char *s) 734 { 735 int ret; 736 u32 val; 737 738 ret = of_property_read_u32(dn, s, &val); 739 if (ret) 740 return 0; 741 return val; 742 } 743 744 static int get_musb_port_mode(struct device *dev) 745 { 746 enum usb_dr_mode mode; 747 748 mode = usb_get_dr_mode(dev); 749 switch (mode) { 750 case USB_DR_MODE_HOST: 751 return MUSB_PORT_MODE_HOST; 752 753 case USB_DR_MODE_PERIPHERAL: 754 return MUSB_PORT_MODE_GADGET; 755 756 case USB_DR_MODE_UNKNOWN: 757 case USB_DR_MODE_OTG: 758 default: 759 return MUSB_PORT_MODE_DUAL_ROLE; 760 } 761 } 762 763 static int dsps_create_musb_pdev(struct dsps_glue *glue, 764 struct platform_device *parent) 765 { 766 struct musb_hdrc_platform_data pdata; 767 struct resource resources[2]; 768 struct resource *res; 769 struct device *dev = &parent->dev; 770 struct musb_hdrc_config *config; 771 struct platform_device *musb; 772 struct device_node *dn = parent->dev.of_node; 773 int ret, val; 774 775 memset(resources, 0, sizeof(resources)); 776 res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc"); 777 if (!res) { 778 dev_err(dev, "failed to get memory.\n"); 779 return -EINVAL; 780 } 781 resources[0] = *res; 782 783 res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc"); 784 if (!res) { 785 dev_err(dev, "failed to get irq.\n"); 786 return -EINVAL; 787 } 788 resources[1] = *res; 789 790 /* allocate the child platform device */ 791 musb = platform_device_alloc("musb-hdrc", 792 (resources[0].start & 0xFFF) == 0x400 ? 0 : 1); 793 if (!musb) { 794 dev_err(dev, "failed to allocate musb device\n"); 795 return -ENOMEM; 796 } 797 798 musb->dev.parent = dev; 799 musb->dev.dma_mask = &musb_dmamask; 800 musb->dev.coherent_dma_mask = musb_dmamask; 801 802 glue->musb = musb; 803 804 ret = platform_device_add_resources(musb, resources, 805 ARRAY_SIZE(resources)); 806 if (ret) { 807 dev_err(dev, "failed to add resources\n"); 808 goto err; 809 } 810 811 config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL); 812 if (!config) { 813 ret = -ENOMEM; 814 goto err; 815 } 816 pdata.config = config; 817 pdata.platform_ops = &dsps_ops; 818 819 config->num_eps = get_int_prop(dn, "mentor,num-eps"); 820 config->ram_bits = get_int_prop(dn, "mentor,ram-bits"); 821 config->host_port_deassert_reset_at_resume = 1; 822 pdata.mode = get_musb_port_mode(dev); 823 /* DT keeps this entry in mA, musb expects it as per USB spec */ 824 pdata.power = get_int_prop(dn, "mentor,power") / 2; 825 826 ret = of_property_read_u32(dn, "mentor,multipoint", &val); 827 if (!ret && val) 828 config->multipoint = true; 829 830 config->maximum_speed = usb_get_maximum_speed(&parent->dev); 831 switch (config->maximum_speed) { 832 case USB_SPEED_LOW: 833 case USB_SPEED_FULL: 834 break; 835 case USB_SPEED_SUPER: 836 dev_warn(dev, "ignore incorrect maximum_speed " 837 "(super-speed) setting in dts"); 838 /* fall through */ 839 default: 840 config->maximum_speed = USB_SPEED_HIGH; 841 } 842 843 ret = platform_device_add_data(musb, &pdata, sizeof(pdata)); 844 if (ret) { 845 dev_err(dev, "failed to add platform_data\n"); 846 goto err; 847 } 848 849 ret = platform_device_add(musb); 850 if (ret) { 851 dev_err(dev, "failed to register musb device\n"); 852 goto err; 853 } 854 return 0; 855 856 err: 857 platform_device_put(musb); 858 return ret; 859 } 860 861 static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv) 862 { 863 struct dsps_glue *glue = priv; 864 struct musb *musb = platform_get_drvdata(glue->musb); 865 866 if (!musb) 867 return IRQ_NONE; 868 869 dev_dbg(glue->dev, "VBUS interrupt\n"); 870 dsps_mod_timer(glue, 0); 871 872 return IRQ_HANDLED; 873 } 874 875 static int dsps_setup_optional_vbus_irq(struct platform_device *pdev, 876 struct dsps_glue *glue) 877 { 878 int error; 879 880 glue->vbus_irq = platform_get_irq_byname(pdev, "vbus"); 881 if (glue->vbus_irq == -EPROBE_DEFER) 882 return -EPROBE_DEFER; 883 884 if (glue->vbus_irq <= 0) { 885 glue->vbus_irq = 0; 886 return 0; 887 } 888 889 error = devm_request_threaded_irq(glue->dev, glue->vbus_irq, 890 NULL, dsps_vbus_threaded_irq, 891 IRQF_ONESHOT, 892 "vbus", glue); 893 if (error) { 894 glue->vbus_irq = 0; 895 return error; 896 } 897 dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq); 898 899 return 0; 900 } 901 902 static int dsps_probe(struct platform_device *pdev) 903 { 904 const struct of_device_id *match; 905 const struct dsps_musb_wrapper *wrp; 906 struct dsps_glue *glue; 907 int ret; 908 909 if (!strcmp(pdev->name, "musb-hdrc")) 910 return -ENODEV; 911 912 match = of_match_node(musb_dsps_of_match, pdev->dev.of_node); 913 if (!match) { 914 dev_err(&pdev->dev, "fail to get matching of_match struct\n"); 915 return -EINVAL; 916 } 917 wrp = match->data; 918 919 if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816")) 920 dsps_ops.read_fifo = dsps_read_fifo32; 921 922 /* allocate glue */ 923 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 924 if (!glue) 925 return -ENOMEM; 926 927 glue->dev = &pdev->dev; 928 glue->wrp = wrp; 929 glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0); 930 if (!glue->usbss_base) 931 return -ENXIO; 932 933 if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) { 934 ret = dsps_setup_optional_vbus_irq(pdev, glue); 935 if (ret) 936 return ret; 937 } 938 939 platform_set_drvdata(pdev, glue); 940 pm_runtime_enable(&pdev->dev); 941 ret = dsps_create_musb_pdev(glue, pdev); 942 if (ret) 943 goto err; 944 945 return 0; 946 947 err: 948 pm_runtime_disable(&pdev->dev); 949 return ret; 950 } 951 952 static int dsps_remove(struct platform_device *pdev) 953 { 954 struct dsps_glue *glue = platform_get_drvdata(pdev); 955 956 platform_device_unregister(glue->musb); 957 958 pm_runtime_disable(&pdev->dev); 959 960 return 0; 961 } 962 963 static const struct dsps_musb_wrapper am33xx_driver_data = { 964 .revision = 0x00, 965 .control = 0x14, 966 .status = 0x18, 967 .epintr_set = 0x38, 968 .epintr_clear = 0x40, 969 .epintr_status = 0x30, 970 .coreintr_set = 0x3c, 971 .coreintr_clear = 0x44, 972 .coreintr_status = 0x34, 973 .phy_utmi = 0xe0, 974 .mode = 0xe8, 975 .tx_mode = 0x70, 976 .rx_mode = 0x74, 977 .reset = 0, 978 .otg_disable = 21, 979 .iddig = 8, 980 .iddig_mux = 7, 981 .usb_shift = 0, 982 .usb_mask = 0x1ff, 983 .usb_bitmap = (0x1ff << 0), 984 .drvvbus = 8, 985 .txep_shift = 0, 986 .txep_mask = 0xffff, 987 .txep_bitmap = (0xffff << 0), 988 .rxep_shift = 16, 989 .rxep_mask = 0xfffe, 990 .rxep_bitmap = (0xfffe << 16), 991 .poll_timeout = 2000, /* ms */ 992 }; 993 994 static const struct of_device_id musb_dsps_of_match[] = { 995 { .compatible = "ti,musb-am33xx", 996 .data = &am33xx_driver_data, }, 997 { .compatible = "ti,musb-dm816", 998 .data = &am33xx_driver_data, }, 999 { }, 1000 }; 1001 MODULE_DEVICE_TABLE(of, musb_dsps_of_match); 1002 1003 #ifdef CONFIG_PM_SLEEP 1004 static int dsps_suspend(struct device *dev) 1005 { 1006 struct dsps_glue *glue = dev_get_drvdata(dev); 1007 const struct dsps_musb_wrapper *wrp = glue->wrp; 1008 struct musb *musb = platform_get_drvdata(glue->musb); 1009 void __iomem *mbase; 1010 1011 del_timer_sync(&glue->timer); 1012 1013 if (!musb) 1014 /* This can happen if the musb device is in -EPROBE_DEFER */ 1015 return 0; 1016 1017 mbase = musb->ctrl_base; 1018 glue->context.control = musb_readl(mbase, wrp->control); 1019 glue->context.epintr = musb_readl(mbase, wrp->epintr_set); 1020 glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set); 1021 glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi); 1022 glue->context.mode = musb_readl(mbase, wrp->mode); 1023 glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode); 1024 glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode); 1025 1026 dsps_dma_controller_suspend(glue); 1027 1028 return 0; 1029 } 1030 1031 static int dsps_resume(struct device *dev) 1032 { 1033 struct dsps_glue *glue = dev_get_drvdata(dev); 1034 const struct dsps_musb_wrapper *wrp = glue->wrp; 1035 struct musb *musb = platform_get_drvdata(glue->musb); 1036 void __iomem *mbase; 1037 1038 if (!musb) 1039 return 0; 1040 1041 dsps_dma_controller_resume(glue); 1042 1043 mbase = musb->ctrl_base; 1044 musb_writel(mbase, wrp->control, glue->context.control); 1045 musb_writel(mbase, wrp->epintr_set, glue->context.epintr); 1046 musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr); 1047 musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi); 1048 musb_writel(mbase, wrp->mode, glue->context.mode); 1049 musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode); 1050 musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode); 1051 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE && 1052 musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) 1053 dsps_mod_timer(glue, -1); 1054 1055 return 0; 1056 } 1057 #endif 1058 1059 static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume); 1060 1061 static struct platform_driver dsps_usbss_driver = { 1062 .probe = dsps_probe, 1063 .remove = dsps_remove, 1064 .driver = { 1065 .name = "musb-dsps", 1066 .pm = &dsps_pm_ops, 1067 .of_match_table = musb_dsps_of_match, 1068 }, 1069 }; 1070 1071 MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer"); 1072 MODULE_AUTHOR("Ravi B <ravibabu@ti.com>"); 1073 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); 1074 MODULE_LICENSE("GPL v2"); 1075 1076 module_platform_driver(dsps_usbss_driver); 1077