1 #include <linux/device.h> 2 #include <linux/dma-mapping.h> 3 #include <linux/dmaengine.h> 4 #include <linux/sizes.h> 5 #include <linux/platform_device.h> 6 #include <linux/of.h> 7 8 #include "musb_core.h" 9 10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4)) 11 12 #define EP_MODE_AUTOREG_NONE 0 13 #define EP_MODE_AUTOREG_ALL_NEOP 1 14 #define EP_MODE_AUTOREG_ALWAYS 3 15 16 #define EP_MODE_DMA_TRANSPARENT 0 17 #define EP_MODE_DMA_RNDIS 1 18 #define EP_MODE_DMA_GEN_RNDIS 3 19 20 #define USB_CTRL_TX_MODE 0x70 21 #define USB_CTRL_RX_MODE 0x74 22 #define USB_CTRL_AUTOREQ 0xd0 23 #define USB_TDOWN 0xd8 24 25 struct cppi41_dma_channel { 26 struct dma_channel channel; 27 struct cppi41_dma_controller *controller; 28 struct musb_hw_ep *hw_ep; 29 struct dma_chan *dc; 30 dma_cookie_t cookie; 31 u8 port_num; 32 u8 is_tx; 33 u8 is_allocated; 34 u8 usb_toggle; 35 36 dma_addr_t buf_addr; 37 u32 total_len; 38 u32 prog_len; 39 u32 transferred; 40 u32 packet_sz; 41 struct list_head tx_check; 42 int tx_zlp; 43 }; 44 45 #define MUSB_DMA_NUM_CHANNELS 15 46 47 struct cppi41_dma_controller { 48 struct dma_controller controller; 49 struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS]; 50 struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS]; 51 struct musb *musb; 52 struct hrtimer early_tx; 53 struct list_head early_tx_list; 54 u32 rx_mode; 55 u32 tx_mode; 56 u32 auto_req; 57 }; 58 59 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel) 60 { 61 u16 csr; 62 u8 toggle; 63 64 if (cppi41_channel->is_tx) 65 return; 66 if (!is_host_active(cppi41_channel->controller->musb)) 67 return; 68 69 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); 70 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; 71 72 cppi41_channel->usb_toggle = toggle; 73 } 74 75 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel) 76 { 77 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep; 78 struct musb *musb = hw_ep->musb; 79 u16 csr; 80 u8 toggle; 81 82 if (cppi41_channel->is_tx) 83 return; 84 if (!is_host_active(musb)) 85 return; 86 87 musb_ep_select(musb->mregs, hw_ep->epnum); 88 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 89 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; 90 91 /* 92 * AM335x Advisory 1.0.13: Due to internal synchronisation error the 93 * data toggle may reset from DATA1 to DATA0 during receiving data from 94 * more than one endpoint. 95 */ 96 if (!toggle && toggle == cppi41_channel->usb_toggle) { 97 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE; 98 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr); 99 dev_dbg(cppi41_channel->controller->musb->controller, 100 "Restoring DATA1 toggle.\n"); 101 } 102 103 cppi41_channel->usb_toggle = toggle; 104 } 105 106 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep) 107 { 108 u8 epnum = hw_ep->epnum; 109 struct musb *musb = hw_ep->musb; 110 void __iomem *epio = musb->endpoints[epnum].regs; 111 u16 csr; 112 113 musb_ep_select(musb->mregs, hw_ep->epnum); 114 csr = musb_readw(epio, MUSB_TXCSR); 115 if (csr & MUSB_TXCSR_TXPKTRDY) 116 return false; 117 return true; 118 } 119 120 static void cppi41_dma_callback(void *private_data); 121 122 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel) 123 { 124 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep; 125 struct musb *musb = hw_ep->musb; 126 void __iomem *epio = hw_ep->regs; 127 u16 csr; 128 129 if (!cppi41_channel->prog_len || 130 (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) { 131 132 /* done, complete */ 133 cppi41_channel->channel.actual_len = 134 cppi41_channel->transferred; 135 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE; 136 cppi41_channel->channel.rx_packet_done = true; 137 138 /* 139 * transmit ZLP using PIO mode for transfers which size is 140 * multiple of EP packet size. 141 */ 142 if (cppi41_channel->tx_zlp && (cppi41_channel->transferred % 143 cppi41_channel->packet_sz) == 0) { 144 musb_ep_select(musb->mregs, hw_ep->epnum); 145 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY; 146 musb_writew(epio, MUSB_TXCSR, csr); 147 } 148 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx); 149 } else { 150 /* next iteration, reload */ 151 struct dma_chan *dc = cppi41_channel->dc; 152 struct dma_async_tx_descriptor *dma_desc; 153 enum dma_transfer_direction direction; 154 u32 remain_bytes; 155 156 cppi41_channel->buf_addr += cppi41_channel->packet_sz; 157 158 remain_bytes = cppi41_channel->total_len; 159 remain_bytes -= cppi41_channel->transferred; 160 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz); 161 cppi41_channel->prog_len = remain_bytes; 162 163 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV 164 : DMA_DEV_TO_MEM; 165 dma_desc = dmaengine_prep_slave_single(dc, 166 cppi41_channel->buf_addr, 167 remain_bytes, 168 direction, 169 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 170 if (WARN_ON(!dma_desc)) 171 return; 172 173 dma_desc->callback = cppi41_dma_callback; 174 dma_desc->callback_param = &cppi41_channel->channel; 175 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc); 176 dma_async_issue_pending(dc); 177 178 if (!cppi41_channel->is_tx) { 179 musb_ep_select(musb->mregs, hw_ep->epnum); 180 csr = musb_readw(epio, MUSB_RXCSR); 181 csr |= MUSB_RXCSR_H_REQPKT; 182 musb_writew(epio, MUSB_RXCSR, csr); 183 } 184 } 185 } 186 187 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer) 188 { 189 struct cppi41_dma_controller *controller; 190 struct cppi41_dma_channel *cppi41_channel, *n; 191 struct musb *musb; 192 unsigned long flags; 193 enum hrtimer_restart ret = HRTIMER_NORESTART; 194 195 controller = container_of(timer, struct cppi41_dma_controller, 196 early_tx); 197 musb = controller->musb; 198 199 spin_lock_irqsave(&musb->lock, flags); 200 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list, 201 tx_check) { 202 bool empty; 203 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep; 204 205 empty = musb_is_tx_fifo_empty(hw_ep); 206 if (empty) { 207 list_del_init(&cppi41_channel->tx_check); 208 cppi41_trans_done(cppi41_channel); 209 } 210 } 211 212 if (!list_empty(&controller->early_tx_list) && 213 !hrtimer_is_queued(&controller->early_tx)) { 214 ret = HRTIMER_RESTART; 215 hrtimer_forward_now(&controller->early_tx, 216 ktime_set(0, 20 * NSEC_PER_USEC)); 217 } 218 219 spin_unlock_irqrestore(&musb->lock, flags); 220 return ret; 221 } 222 223 static void cppi41_dma_callback(void *private_data) 224 { 225 struct dma_channel *channel = private_data; 226 struct cppi41_dma_channel *cppi41_channel = channel->private_data; 227 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep; 228 struct musb *musb = hw_ep->musb; 229 unsigned long flags; 230 struct dma_tx_state txstate; 231 u32 transferred; 232 bool empty; 233 234 spin_lock_irqsave(&musb->lock, flags); 235 236 dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie, 237 &txstate); 238 transferred = cppi41_channel->prog_len - txstate.residue; 239 cppi41_channel->transferred += transferred; 240 241 dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n", 242 hw_ep->epnum, cppi41_channel->transferred, 243 cppi41_channel->total_len); 244 245 update_rx_toggle(cppi41_channel); 246 247 if (cppi41_channel->transferred == cppi41_channel->total_len || 248 transferred < cppi41_channel->packet_sz) 249 cppi41_channel->prog_len = 0; 250 251 empty = musb_is_tx_fifo_empty(hw_ep); 252 if (empty) { 253 cppi41_trans_done(cppi41_channel); 254 } else { 255 struct cppi41_dma_controller *controller; 256 int is_hs = 0; 257 /* 258 * On AM335x it has been observed that the TX interrupt fires 259 * too early that means the TXFIFO is not yet empty but the DMA 260 * engine says that it is done with the transfer. We don't 261 * receive a FIFO empty interrupt so the only thing we can do is 262 * to poll for the bit. On HS it usually takes 2us, on FS around 263 * 110us - 150us depending on the transfer size. 264 * We spin on HS (no longer than than 25us and setup a timer on 265 * FS to check for the bit and complete the transfer. 266 */ 267 controller = cppi41_channel->controller; 268 269 if (is_host_active(musb)) { 270 if (musb->port1_status & USB_PORT_STAT_HIGH_SPEED) 271 is_hs = 1; 272 } else { 273 if (musb->g.speed == USB_SPEED_HIGH) 274 is_hs = 1; 275 } 276 if (is_hs) { 277 unsigned wait = 25; 278 279 do { 280 empty = musb_is_tx_fifo_empty(hw_ep); 281 if (empty) 282 break; 283 wait--; 284 if (!wait) 285 break; 286 udelay(1); 287 } while (1); 288 289 empty = musb_is_tx_fifo_empty(hw_ep); 290 if (empty) { 291 cppi41_trans_done(cppi41_channel); 292 goto out; 293 } 294 } 295 list_add_tail(&cppi41_channel->tx_check, 296 &controller->early_tx_list); 297 if (!hrtimer_is_queued(&controller->early_tx)) { 298 unsigned long usecs = cppi41_channel->total_len / 10; 299 300 hrtimer_start_range_ns(&controller->early_tx, 301 ktime_set(0, usecs * NSEC_PER_USEC), 302 20 * NSEC_PER_USEC, 303 HRTIMER_MODE_REL); 304 } 305 } 306 out: 307 spin_unlock_irqrestore(&musb->lock, flags); 308 } 309 310 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old) 311 { 312 unsigned shift; 313 314 shift = (ep - 1) * 2; 315 old &= ~(3 << shift); 316 old |= mode << shift; 317 return old; 318 } 319 320 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel, 321 unsigned mode) 322 { 323 struct cppi41_dma_controller *controller = cppi41_channel->controller; 324 u32 port; 325 u32 new_mode; 326 u32 old_mode; 327 328 if (cppi41_channel->is_tx) 329 old_mode = controller->tx_mode; 330 else 331 old_mode = controller->rx_mode; 332 port = cppi41_channel->port_num; 333 new_mode = update_ep_mode(port, mode, old_mode); 334 335 if (new_mode == old_mode) 336 return; 337 if (cppi41_channel->is_tx) { 338 controller->tx_mode = new_mode; 339 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE, 340 new_mode); 341 } else { 342 controller->rx_mode = new_mode; 343 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE, 344 new_mode); 345 } 346 } 347 348 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel, 349 unsigned mode) 350 { 351 struct cppi41_dma_controller *controller = cppi41_channel->controller; 352 u32 port; 353 u32 new_mode; 354 u32 old_mode; 355 356 old_mode = controller->auto_req; 357 port = cppi41_channel->port_num; 358 new_mode = update_ep_mode(port, mode, old_mode); 359 360 if (new_mode == old_mode) 361 return; 362 controller->auto_req = new_mode; 363 musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode); 364 } 365 366 static bool cppi41_configure_channel(struct dma_channel *channel, 367 u16 packet_sz, u8 mode, 368 dma_addr_t dma_addr, u32 len) 369 { 370 struct cppi41_dma_channel *cppi41_channel = channel->private_data; 371 struct dma_chan *dc = cppi41_channel->dc; 372 struct dma_async_tx_descriptor *dma_desc; 373 enum dma_transfer_direction direction; 374 struct musb *musb = cppi41_channel->controller->musb; 375 unsigned use_gen_rndis = 0; 376 377 dev_dbg(musb->controller, 378 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n", 379 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num), 380 packet_sz, mode, (unsigned long long) dma_addr, 381 len, cppi41_channel->is_tx); 382 383 cppi41_channel->buf_addr = dma_addr; 384 cppi41_channel->total_len = len; 385 cppi41_channel->transferred = 0; 386 cppi41_channel->packet_sz = packet_sz; 387 cppi41_channel->tx_zlp = (cppi41_channel->is_tx && mode) ? 1 : 0; 388 389 /* 390 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more 391 * than max packet size at a time. 392 */ 393 if (cppi41_channel->is_tx) 394 use_gen_rndis = 1; 395 396 if (use_gen_rndis) { 397 /* RNDIS mode */ 398 if (len > packet_sz) { 399 musb_writel(musb->ctrl_base, 400 RNDIS_REG(cppi41_channel->port_num), len); 401 /* gen rndis */ 402 cppi41_set_dma_mode(cppi41_channel, 403 EP_MODE_DMA_GEN_RNDIS); 404 405 /* auto req */ 406 cppi41_set_autoreq_mode(cppi41_channel, 407 EP_MODE_AUTOREG_ALL_NEOP); 408 } else { 409 musb_writel(musb->ctrl_base, 410 RNDIS_REG(cppi41_channel->port_num), 0); 411 cppi41_set_dma_mode(cppi41_channel, 412 EP_MODE_DMA_TRANSPARENT); 413 cppi41_set_autoreq_mode(cppi41_channel, 414 EP_MODE_AUTOREG_NONE); 415 } 416 } else { 417 /* fallback mode */ 418 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT); 419 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE); 420 len = min_t(u32, packet_sz, len); 421 } 422 cppi41_channel->prog_len = len; 423 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 424 dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction, 425 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 426 if (!dma_desc) 427 return false; 428 429 dma_desc->callback = cppi41_dma_callback; 430 dma_desc->callback_param = channel; 431 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc); 432 cppi41_channel->channel.rx_packet_done = false; 433 434 save_rx_toggle(cppi41_channel); 435 dma_async_issue_pending(dc); 436 return true; 437 } 438 439 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c, 440 struct musb_hw_ep *hw_ep, u8 is_tx) 441 { 442 struct cppi41_dma_controller *controller = container_of(c, 443 struct cppi41_dma_controller, controller); 444 struct cppi41_dma_channel *cppi41_channel = NULL; 445 u8 ch_num = hw_ep->epnum - 1; 446 447 if (ch_num >= MUSB_DMA_NUM_CHANNELS) 448 return NULL; 449 450 if (is_tx) 451 cppi41_channel = &controller->tx_channel[ch_num]; 452 else 453 cppi41_channel = &controller->rx_channel[ch_num]; 454 455 if (!cppi41_channel->dc) 456 return NULL; 457 458 if (cppi41_channel->is_allocated) 459 return NULL; 460 461 cppi41_channel->hw_ep = hw_ep; 462 cppi41_channel->is_allocated = 1; 463 464 return &cppi41_channel->channel; 465 } 466 467 static void cppi41_dma_channel_release(struct dma_channel *channel) 468 { 469 struct cppi41_dma_channel *cppi41_channel = channel->private_data; 470 471 if (cppi41_channel->is_allocated) { 472 cppi41_channel->is_allocated = 0; 473 channel->status = MUSB_DMA_STATUS_FREE; 474 channel->actual_len = 0; 475 } 476 } 477 478 static int cppi41_dma_channel_program(struct dma_channel *channel, 479 u16 packet_sz, u8 mode, 480 dma_addr_t dma_addr, u32 len) 481 { 482 int ret; 483 struct cppi41_dma_channel *cppi41_channel = channel->private_data; 484 int hb_mult = 0; 485 486 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 487 channel->status == MUSB_DMA_STATUS_BUSY); 488 489 if (is_host_active(cppi41_channel->controller->musb)) { 490 if (cppi41_channel->is_tx) 491 hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult; 492 else 493 hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult; 494 } 495 496 channel->status = MUSB_DMA_STATUS_BUSY; 497 channel->actual_len = 0; 498 499 if (hb_mult) 500 packet_sz = hb_mult * (packet_sz & 0x7FF); 501 502 ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len); 503 if (!ret) 504 channel->status = MUSB_DMA_STATUS_FREE; 505 506 return ret; 507 } 508 509 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket, 510 void *buf, u32 length) 511 { 512 struct cppi41_dma_channel *cppi41_channel = channel->private_data; 513 struct cppi41_dma_controller *controller = cppi41_channel->controller; 514 struct musb *musb = controller->musb; 515 516 if (is_host_active(musb)) { 517 WARN_ON(1); 518 return 1; 519 } 520 if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK) 521 return 0; 522 if (cppi41_channel->is_tx) 523 return 1; 524 /* AM335x Advisory 1.0.13. No workaround for device RX mode */ 525 return 0; 526 } 527 528 static int cppi41_dma_channel_abort(struct dma_channel *channel) 529 { 530 struct cppi41_dma_channel *cppi41_channel = channel->private_data; 531 struct cppi41_dma_controller *controller = cppi41_channel->controller; 532 struct musb *musb = controller->musb; 533 void __iomem *epio = cppi41_channel->hw_ep->regs; 534 int tdbit; 535 int ret; 536 unsigned is_tx; 537 u16 csr; 538 539 is_tx = cppi41_channel->is_tx; 540 dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n", 541 cppi41_channel->port_num, is_tx); 542 543 if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE) 544 return 0; 545 546 list_del_init(&cppi41_channel->tx_check); 547 if (is_tx) { 548 csr = musb_readw(epio, MUSB_TXCSR); 549 csr &= ~MUSB_TXCSR_DMAENAB; 550 musb_writew(epio, MUSB_TXCSR, csr); 551 } else { 552 csr = musb_readw(epio, MUSB_RXCSR); 553 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB); 554 musb_writew(epio, MUSB_RXCSR, csr); 555 556 csr = musb_readw(epio, MUSB_RXCSR); 557 if (csr & MUSB_RXCSR_RXPKTRDY) { 558 csr |= MUSB_RXCSR_FLUSHFIFO; 559 musb_writew(epio, MUSB_RXCSR, csr); 560 musb_writew(epio, MUSB_RXCSR, csr); 561 } 562 } 563 564 tdbit = 1 << cppi41_channel->port_num; 565 if (is_tx) 566 tdbit <<= 16; 567 568 do { 569 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit); 570 ret = dmaengine_terminate_all(cppi41_channel->dc); 571 } while (ret == -EAGAIN); 572 573 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit); 574 575 if (is_tx) { 576 csr = musb_readw(epio, MUSB_TXCSR); 577 if (csr & MUSB_TXCSR_TXPKTRDY) { 578 csr |= MUSB_TXCSR_FLUSHFIFO; 579 musb_writew(epio, MUSB_TXCSR, csr); 580 } 581 } 582 583 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE; 584 return 0; 585 } 586 587 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl) 588 { 589 struct dma_chan *dc; 590 int i; 591 592 for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) { 593 dc = ctrl->tx_channel[i].dc; 594 if (dc) 595 dma_release_channel(dc); 596 dc = ctrl->rx_channel[i].dc; 597 if (dc) 598 dma_release_channel(dc); 599 } 600 } 601 602 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller) 603 { 604 cppi41_release_all_dma_chans(controller); 605 } 606 607 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller) 608 { 609 struct musb *musb = controller->musb; 610 struct device *dev = musb->controller; 611 struct device_node *np = dev->of_node; 612 struct cppi41_dma_channel *cppi41_channel; 613 int count; 614 int i; 615 int ret; 616 617 count = of_property_count_strings(np, "dma-names"); 618 if (count < 0) 619 return count; 620 621 for (i = 0; i < count; i++) { 622 struct dma_chan *dc; 623 struct dma_channel *musb_dma; 624 const char *str; 625 unsigned is_tx; 626 unsigned int port; 627 628 ret = of_property_read_string_index(np, "dma-names", i, &str); 629 if (ret) 630 goto err; 631 if (strstarts(str, "tx")) 632 is_tx = 1; 633 else if (strstarts(str, "rx")) 634 is_tx = 0; 635 else { 636 dev_err(dev, "Wrong dmatype %s\n", str); 637 goto err; 638 } 639 ret = kstrtouint(str + 2, 0, &port); 640 if (ret) 641 goto err; 642 643 ret = -EINVAL; 644 if (port > MUSB_DMA_NUM_CHANNELS || !port) 645 goto err; 646 if (is_tx) 647 cppi41_channel = &controller->tx_channel[port - 1]; 648 else 649 cppi41_channel = &controller->rx_channel[port - 1]; 650 651 cppi41_channel->controller = controller; 652 cppi41_channel->port_num = port; 653 cppi41_channel->is_tx = is_tx; 654 INIT_LIST_HEAD(&cppi41_channel->tx_check); 655 656 musb_dma = &cppi41_channel->channel; 657 musb_dma->private_data = cppi41_channel; 658 musb_dma->status = MUSB_DMA_STATUS_FREE; 659 musb_dma->max_len = SZ_4M; 660 661 dc = dma_request_slave_channel(dev, str); 662 if (!dc) { 663 dev_err(dev, "Failed to request %s.\n", str); 664 ret = -EPROBE_DEFER; 665 goto err; 666 } 667 cppi41_channel->dc = dc; 668 } 669 return 0; 670 err: 671 cppi41_release_all_dma_chans(controller); 672 return ret; 673 } 674 675 void dma_controller_destroy(struct dma_controller *c) 676 { 677 struct cppi41_dma_controller *controller = container_of(c, 678 struct cppi41_dma_controller, controller); 679 680 hrtimer_cancel(&controller->early_tx); 681 cppi41_dma_controller_stop(controller); 682 kfree(controller); 683 } 684 685 struct dma_controller *dma_controller_create(struct musb *musb, 686 void __iomem *base) 687 { 688 struct cppi41_dma_controller *controller; 689 int ret = 0; 690 691 if (!musb->controller->of_node) { 692 dev_err(musb->controller, "Need DT for the DMA engine.\n"); 693 return NULL; 694 } 695 696 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 697 if (!controller) 698 goto kzalloc_fail; 699 700 hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 701 controller->early_tx.function = cppi41_recheck_tx_req; 702 INIT_LIST_HEAD(&controller->early_tx_list); 703 controller->musb = musb; 704 705 controller->controller.channel_alloc = cppi41_dma_channel_allocate; 706 controller->controller.channel_release = cppi41_dma_channel_release; 707 controller->controller.channel_program = cppi41_dma_channel_program; 708 controller->controller.channel_abort = cppi41_dma_channel_abort; 709 controller->controller.is_compatible = cppi41_is_compatible; 710 711 ret = cppi41_dma_controller_start(controller); 712 if (ret) 713 goto plat_get_fail; 714 return &controller->controller; 715 716 plat_get_fail: 717 kfree(controller); 718 kzalloc_fail: 719 if (ret == -EPROBE_DEFER) 720 return ERR_PTR(ret); 721 return NULL; 722 } 723