1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific information 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/list.h> 97 #include <linux/kobject.h> 98 #include <linux/prefetch.h> 99 #include <linux/platform_device.h> 100 #include <linux/io.h> 101 #include <linux/dma-mapping.h> 102 #include <linux/usb.h> 103 #include <linux/usb/of.h> 104 105 #include "musb_core.h" 106 #include "musb_trace.h" 107 108 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 109 110 111 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 112 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 113 114 #define MUSB_VERSION "6.0" 115 116 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 117 118 #define MUSB_DRIVER_NAME "musb-hdrc" 119 const char musb_driver_name[] = MUSB_DRIVER_NAME; 120 121 MODULE_DESCRIPTION(DRIVER_INFO); 122 MODULE_AUTHOR(DRIVER_AUTHOR); 123 MODULE_LICENSE("GPL"); 124 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 125 126 127 /*-------------------------------------------------------------------------*/ 128 129 static inline struct musb *dev_to_musb(struct device *dev) 130 { 131 return dev_get_drvdata(dev); 132 } 133 134 enum musb_mode musb_get_mode(struct device *dev) 135 { 136 enum usb_dr_mode mode; 137 138 mode = usb_get_dr_mode(dev); 139 switch (mode) { 140 case USB_DR_MODE_HOST: 141 return MUSB_HOST; 142 case USB_DR_MODE_PERIPHERAL: 143 return MUSB_PERIPHERAL; 144 case USB_DR_MODE_OTG: 145 case USB_DR_MODE_UNKNOWN: 146 default: 147 return MUSB_OTG; 148 } 149 } 150 EXPORT_SYMBOL_GPL(musb_get_mode); 151 152 /*-------------------------------------------------------------------------*/ 153 154 #ifndef CONFIG_BLACKFIN 155 static int musb_ulpi_read(struct usb_phy *phy, u32 reg) 156 { 157 void __iomem *addr = phy->io_priv; 158 int i = 0; 159 u8 r; 160 u8 power; 161 int ret; 162 163 pm_runtime_get_sync(phy->io_dev); 164 165 /* Make sure the transceiver is not in low power mode */ 166 power = musb_readb(addr, MUSB_POWER); 167 power &= ~MUSB_POWER_SUSPENDM; 168 musb_writeb(addr, MUSB_POWER, power); 169 170 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 171 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 172 */ 173 174 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); 175 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 176 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 177 178 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 179 & MUSB_ULPI_REG_CMPLT)) { 180 i++; 181 if (i == 10000) { 182 ret = -ETIMEDOUT; 183 goto out; 184 } 185 186 } 187 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 188 r &= ~MUSB_ULPI_REG_CMPLT; 189 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 190 191 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 192 193 out: 194 pm_runtime_put(phy->io_dev); 195 196 return ret; 197 } 198 199 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg) 200 { 201 void __iomem *addr = phy->io_priv; 202 int i = 0; 203 u8 r = 0; 204 u8 power; 205 int ret = 0; 206 207 pm_runtime_get_sync(phy->io_dev); 208 209 /* Make sure the transceiver is not in low power mode */ 210 power = musb_readb(addr, MUSB_POWER); 211 power &= ~MUSB_POWER_SUSPENDM; 212 musb_writeb(addr, MUSB_POWER, power); 213 214 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); 215 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val); 216 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 217 218 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 219 & MUSB_ULPI_REG_CMPLT)) { 220 i++; 221 if (i == 10000) { 222 ret = -ETIMEDOUT; 223 goto out; 224 } 225 } 226 227 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 228 r &= ~MUSB_ULPI_REG_CMPLT; 229 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 230 231 out: 232 pm_runtime_put(phy->io_dev); 233 234 return ret; 235 } 236 #else 237 #define musb_ulpi_read NULL 238 #define musb_ulpi_write NULL 239 #endif 240 241 static struct usb_phy_io_ops musb_ulpi_access = { 242 .read = musb_ulpi_read, 243 .write = musb_ulpi_write, 244 }; 245 246 /*-------------------------------------------------------------------------*/ 247 248 static u32 musb_default_fifo_offset(u8 epnum) 249 { 250 return 0x20 + (epnum * 4); 251 } 252 253 /* "flat" mapping: each endpoint has its own i/o address */ 254 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum) 255 { 256 } 257 258 static u32 musb_flat_ep_offset(u8 epnum, u16 offset) 259 { 260 return 0x100 + (0x10 * epnum) + offset; 261 } 262 263 /* "indexed" mapping: INDEX register controls register bank select */ 264 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum) 265 { 266 musb_writeb(mbase, MUSB_INDEX, epnum); 267 } 268 269 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset) 270 { 271 return 0x10 + offset; 272 } 273 274 static u32 musb_default_busctl_offset(u8 epnum, u16 offset) 275 { 276 return 0x80 + (0x08 * epnum) + offset; 277 } 278 279 static u8 musb_default_readb(const void __iomem *addr, unsigned offset) 280 { 281 u8 data = __raw_readb(addr + offset); 282 283 trace_musb_readb(__builtin_return_address(0), addr, offset, data); 284 return data; 285 } 286 287 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data) 288 { 289 trace_musb_writeb(__builtin_return_address(0), addr, offset, data); 290 __raw_writeb(data, addr + offset); 291 } 292 293 static u16 musb_default_readw(const void __iomem *addr, unsigned offset) 294 { 295 u16 data = __raw_readw(addr + offset); 296 297 trace_musb_readw(__builtin_return_address(0), addr, offset, data); 298 return data; 299 } 300 301 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data) 302 { 303 trace_musb_writew(__builtin_return_address(0), addr, offset, data); 304 __raw_writew(data, addr + offset); 305 } 306 307 static u32 musb_default_readl(const void __iomem *addr, unsigned offset) 308 { 309 u32 data = __raw_readl(addr + offset); 310 311 trace_musb_readl(__builtin_return_address(0), addr, offset, data); 312 return data; 313 } 314 315 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data) 316 { 317 trace_musb_writel(__builtin_return_address(0), addr, offset, data); 318 __raw_writel(data, addr + offset); 319 } 320 321 /* 322 * Load an endpoint's FIFO 323 */ 324 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 325 const u8 *src) 326 { 327 struct musb *musb = hw_ep->musb; 328 void __iomem *fifo = hw_ep->fifo; 329 330 if (unlikely(len == 0)) 331 return; 332 333 prefetch((u8 *)src); 334 335 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 336 'T', hw_ep->epnum, fifo, len, src); 337 338 /* we can't assume unaligned reads work */ 339 if (likely((0x01 & (unsigned long) src) == 0)) { 340 u16 index = 0; 341 342 /* best case is 32bit-aligned source address */ 343 if ((0x02 & (unsigned long) src) == 0) { 344 if (len >= 4) { 345 iowrite32_rep(fifo, src + index, len >> 2); 346 index += len & ~0x03; 347 } 348 if (len & 0x02) { 349 __raw_writew(*(u16 *)&src[index], fifo); 350 index += 2; 351 } 352 } else { 353 if (len >= 2) { 354 iowrite16_rep(fifo, src + index, len >> 1); 355 index += len & ~0x01; 356 } 357 } 358 if (len & 0x01) 359 __raw_writeb(src[index], fifo); 360 } else { 361 /* byte aligned */ 362 iowrite8_rep(fifo, src, len); 363 } 364 } 365 366 /* 367 * Unload an endpoint's FIFO 368 */ 369 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 370 { 371 struct musb *musb = hw_ep->musb; 372 void __iomem *fifo = hw_ep->fifo; 373 374 if (unlikely(len == 0)) 375 return; 376 377 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 378 'R', hw_ep->epnum, fifo, len, dst); 379 380 /* we can't assume unaligned writes work */ 381 if (likely((0x01 & (unsigned long) dst) == 0)) { 382 u16 index = 0; 383 384 /* best case is 32bit-aligned destination address */ 385 if ((0x02 & (unsigned long) dst) == 0) { 386 if (len >= 4) { 387 ioread32_rep(fifo, dst, len >> 2); 388 index = len & ~0x03; 389 } 390 if (len & 0x02) { 391 *(u16 *)&dst[index] = __raw_readw(fifo); 392 index += 2; 393 } 394 } else { 395 if (len >= 2) { 396 ioread16_rep(fifo, dst, len >> 1); 397 index = len & ~0x01; 398 } 399 } 400 if (len & 0x01) 401 dst[index] = __raw_readb(fifo); 402 } else { 403 /* byte aligned */ 404 ioread8_rep(fifo, dst, len); 405 } 406 } 407 408 /* 409 * Old style IO functions 410 */ 411 u8 (*musb_readb)(const void __iomem *addr, unsigned offset); 412 EXPORT_SYMBOL_GPL(musb_readb); 413 414 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data); 415 EXPORT_SYMBOL_GPL(musb_writeb); 416 417 u16 (*musb_readw)(const void __iomem *addr, unsigned offset); 418 EXPORT_SYMBOL_GPL(musb_readw); 419 420 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data); 421 EXPORT_SYMBOL_GPL(musb_writew); 422 423 u32 (*musb_readl)(const void __iomem *addr, unsigned offset); 424 EXPORT_SYMBOL_GPL(musb_readl); 425 426 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data); 427 EXPORT_SYMBOL_GPL(musb_writel); 428 429 #ifndef CONFIG_MUSB_PIO_ONLY 430 struct dma_controller * 431 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base); 432 EXPORT_SYMBOL(musb_dma_controller_create); 433 434 void (*musb_dma_controller_destroy)(struct dma_controller *c); 435 EXPORT_SYMBOL(musb_dma_controller_destroy); 436 #endif 437 438 /* 439 * New style IO functions 440 */ 441 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 442 { 443 return hw_ep->musb->io.read_fifo(hw_ep, len, dst); 444 } 445 446 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 447 { 448 return hw_ep->musb->io.write_fifo(hw_ep, len, src); 449 } 450 451 /*-------------------------------------------------------------------------*/ 452 453 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 454 static const u8 musb_test_packet[53] = { 455 /* implicit SYNC then DATA0 to start */ 456 457 /* JKJKJKJK x9 */ 458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 459 /* JJKKJJKK x8 */ 460 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 461 /* JJJJKKKK x8 */ 462 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 463 /* JJJJJJJKKKKKKK x8 */ 464 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 465 /* JJJJJJJK x8 */ 466 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 467 /* JKKKKKKK x10, JK */ 468 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 469 470 /* implicit CRC16 then EOP to end */ 471 }; 472 473 void musb_load_testpacket(struct musb *musb) 474 { 475 void __iomem *regs = musb->endpoints[0].regs; 476 477 musb_ep_select(musb->mregs, 0); 478 musb_write_fifo(musb->control_ep, 479 sizeof(musb_test_packet), musb_test_packet); 480 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 481 } 482 483 /*-------------------------------------------------------------------------*/ 484 485 /* 486 * Handles OTG hnp timeouts, such as b_ase0_brst 487 */ 488 static void musb_otg_timer_func(unsigned long data) 489 { 490 struct musb *musb = (struct musb *)data; 491 unsigned long flags; 492 493 spin_lock_irqsave(&musb->lock, flags); 494 switch (musb->xceiv->otg->state) { 495 case OTG_STATE_B_WAIT_ACON: 496 musb_dbg(musb, 497 "HNP: b_wait_acon timeout; back to b_peripheral"); 498 musb_g_disconnect(musb); 499 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 500 musb->is_active = 0; 501 break; 502 case OTG_STATE_A_SUSPEND: 503 case OTG_STATE_A_WAIT_BCON: 504 musb_dbg(musb, "HNP: %s timeout", 505 usb_otg_state_string(musb->xceiv->otg->state)); 506 musb_platform_set_vbus(musb, 0); 507 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 508 break; 509 default: 510 musb_dbg(musb, "HNP: Unhandled mode %s", 511 usb_otg_state_string(musb->xceiv->otg->state)); 512 } 513 spin_unlock_irqrestore(&musb->lock, flags); 514 } 515 516 /* 517 * Stops the HNP transition. Caller must take care of locking. 518 */ 519 void musb_hnp_stop(struct musb *musb) 520 { 521 struct usb_hcd *hcd = musb->hcd; 522 void __iomem *mbase = musb->mregs; 523 u8 reg; 524 525 musb_dbg(musb, "HNP: stop from %s", 526 usb_otg_state_string(musb->xceiv->otg->state)); 527 528 switch (musb->xceiv->otg->state) { 529 case OTG_STATE_A_PERIPHERAL: 530 musb_g_disconnect(musb); 531 musb_dbg(musb, "HNP: back to %s", 532 usb_otg_state_string(musb->xceiv->otg->state)); 533 break; 534 case OTG_STATE_B_HOST: 535 musb_dbg(musb, "HNP: Disabling HR"); 536 if (hcd) 537 hcd->self.is_b_host = 0; 538 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 539 MUSB_DEV_MODE(musb); 540 reg = musb_readb(mbase, MUSB_POWER); 541 reg |= MUSB_POWER_SUSPENDM; 542 musb_writeb(mbase, MUSB_POWER, reg); 543 /* REVISIT: Start SESSION_REQUEST here? */ 544 break; 545 default: 546 musb_dbg(musb, "HNP: Stopping in unknown state %s", 547 usb_otg_state_string(musb->xceiv->otg->state)); 548 } 549 550 /* 551 * When returning to A state after HNP, avoid hub_port_rebounce(), 552 * which cause occasional OPT A "Did not receive reset after connect" 553 * errors. 554 */ 555 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 556 } 557 558 static void musb_recover_from_babble(struct musb *musb); 559 560 /* 561 * Interrupt Service Routine to record USB "global" interrupts. 562 * Since these do not happen often and signify things of 563 * paramount importance, it seems OK to check them individually; 564 * the order of the tests is specified in the manual 565 * 566 * @param musb instance pointer 567 * @param int_usb register contents 568 * @param devctl 569 * @param power 570 */ 571 572 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 573 u8 devctl) 574 { 575 irqreturn_t handled = IRQ_NONE; 576 577 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb); 578 579 /* in host mode, the peripheral may issue remote wakeup. 580 * in peripheral mode, the host may resume the link. 581 * spurious RESUME irqs happen too, paired with SUSPEND. 582 */ 583 if (int_usb & MUSB_INTR_RESUME) { 584 handled = IRQ_HANDLED; 585 musb_dbg(musb, "RESUME (%s)", 586 usb_otg_state_string(musb->xceiv->otg->state)); 587 588 if (devctl & MUSB_DEVCTL_HM) { 589 switch (musb->xceiv->otg->state) { 590 case OTG_STATE_A_SUSPEND: 591 /* remote wakeup? */ 592 musb->port1_status |= 593 (USB_PORT_STAT_C_SUSPEND << 16) 594 | MUSB_PORT_STAT_RESUME; 595 musb->rh_timer = jiffies 596 + msecs_to_jiffies(USB_RESUME_TIMEOUT); 597 musb->need_finish_resume = 1; 598 599 musb->xceiv->otg->state = OTG_STATE_A_HOST; 600 musb->is_active = 1; 601 musb_host_resume_root_hub(musb); 602 break; 603 case OTG_STATE_B_WAIT_ACON: 604 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 605 musb->is_active = 1; 606 MUSB_DEV_MODE(musb); 607 break; 608 default: 609 WARNING("bogus %s RESUME (%s)\n", 610 "host", 611 usb_otg_state_string(musb->xceiv->otg->state)); 612 } 613 } else { 614 switch (musb->xceiv->otg->state) { 615 case OTG_STATE_A_SUSPEND: 616 /* possibly DISCONNECT is upcoming */ 617 musb->xceiv->otg->state = OTG_STATE_A_HOST; 618 musb_host_resume_root_hub(musb); 619 break; 620 case OTG_STATE_B_WAIT_ACON: 621 case OTG_STATE_B_PERIPHERAL: 622 /* disconnect while suspended? we may 623 * not get a disconnect irq... 624 */ 625 if ((devctl & MUSB_DEVCTL_VBUS) 626 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 627 ) { 628 musb->int_usb |= MUSB_INTR_DISCONNECT; 629 musb->int_usb &= ~MUSB_INTR_SUSPEND; 630 break; 631 } 632 musb_g_resume(musb); 633 break; 634 case OTG_STATE_B_IDLE: 635 musb->int_usb &= ~MUSB_INTR_SUSPEND; 636 break; 637 default: 638 WARNING("bogus %s RESUME (%s)\n", 639 "peripheral", 640 usb_otg_state_string(musb->xceiv->otg->state)); 641 } 642 } 643 } 644 645 /* see manual for the order of the tests */ 646 if (int_usb & MUSB_INTR_SESSREQ) { 647 void __iomem *mbase = musb->mregs; 648 649 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 650 && (devctl & MUSB_DEVCTL_BDEVICE)) { 651 musb_dbg(musb, "SessReq while on B state"); 652 return IRQ_HANDLED; 653 } 654 655 musb_dbg(musb, "SESSION_REQUEST (%s)", 656 usb_otg_state_string(musb->xceiv->otg->state)); 657 658 /* IRQ arrives from ID pin sense or (later, if VBUS power 659 * is removed) SRP. responses are time critical: 660 * - turn on VBUS (with silicon-specific mechanism) 661 * - go through A_WAIT_VRISE 662 * - ... to A_WAIT_BCON. 663 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 664 */ 665 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 666 musb->ep0_stage = MUSB_EP0_START; 667 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 668 MUSB_HST_MODE(musb); 669 musb_platform_set_vbus(musb, 1); 670 671 handled = IRQ_HANDLED; 672 } 673 674 if (int_usb & MUSB_INTR_VBUSERROR) { 675 int ignore = 0; 676 677 /* During connection as an A-Device, we may see a short 678 * current spikes causing voltage drop, because of cable 679 * and peripheral capacitance combined with vbus draw. 680 * (So: less common with truly self-powered devices, where 681 * vbus doesn't act like a power supply.) 682 * 683 * Such spikes are short; usually less than ~500 usec, max 684 * of ~2 msec. That is, they're not sustained overcurrent 685 * errors, though they're reported using VBUSERROR irqs. 686 * 687 * Workarounds: (a) hardware: use self powered devices. 688 * (b) software: ignore non-repeated VBUS errors. 689 * 690 * REVISIT: do delays from lots of DEBUG_KERNEL checks 691 * make trouble here, keeping VBUS < 4.4V ? 692 */ 693 switch (musb->xceiv->otg->state) { 694 case OTG_STATE_A_HOST: 695 /* recovery is dicey once we've gotten past the 696 * initial stages of enumeration, but if VBUS 697 * stayed ok at the other end of the link, and 698 * another reset is due (at least for high speed, 699 * to redo the chirp etc), it might work OK... 700 */ 701 case OTG_STATE_A_WAIT_BCON: 702 case OTG_STATE_A_WAIT_VRISE: 703 if (musb->vbuserr_retry) { 704 void __iomem *mbase = musb->mregs; 705 706 musb->vbuserr_retry--; 707 ignore = 1; 708 devctl |= MUSB_DEVCTL_SESSION; 709 musb_writeb(mbase, MUSB_DEVCTL, devctl); 710 } else { 711 musb->port1_status |= 712 USB_PORT_STAT_OVERCURRENT 713 | (USB_PORT_STAT_C_OVERCURRENT << 16); 714 } 715 break; 716 default: 717 break; 718 } 719 720 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, 721 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 722 usb_otg_state_string(musb->xceiv->otg->state), 723 devctl, 724 ({ char *s; 725 switch (devctl & MUSB_DEVCTL_VBUS) { 726 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 727 s = "<SessEnd"; break; 728 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 729 s = "<AValid"; break; 730 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 731 s = "<VBusValid"; break; 732 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 733 default: 734 s = "VALID"; break; 735 } s; }), 736 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 737 musb->port1_status); 738 739 /* go through A_WAIT_VFALL then start a new session */ 740 if (!ignore) 741 musb_platform_set_vbus(musb, 0); 742 handled = IRQ_HANDLED; 743 } 744 745 if (int_usb & MUSB_INTR_SUSPEND) { 746 musb_dbg(musb, "SUSPEND (%s) devctl %02x", 747 usb_otg_state_string(musb->xceiv->otg->state), devctl); 748 handled = IRQ_HANDLED; 749 750 switch (musb->xceiv->otg->state) { 751 case OTG_STATE_A_PERIPHERAL: 752 /* We also come here if the cable is removed, since 753 * this silicon doesn't report ID-no-longer-grounded. 754 * 755 * We depend on T(a_wait_bcon) to shut us down, and 756 * hope users don't do anything dicey during this 757 * undesired detour through A_WAIT_BCON. 758 */ 759 musb_hnp_stop(musb); 760 musb_host_resume_root_hub(musb); 761 musb_root_disconnect(musb); 762 musb_platform_try_idle(musb, jiffies 763 + msecs_to_jiffies(musb->a_wait_bcon 764 ? : OTG_TIME_A_WAIT_BCON)); 765 766 break; 767 case OTG_STATE_B_IDLE: 768 if (!musb->is_active) 769 break; 770 case OTG_STATE_B_PERIPHERAL: 771 musb_g_suspend(musb); 772 musb->is_active = musb->g.b_hnp_enable; 773 if (musb->is_active) { 774 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON; 775 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst"); 776 mod_timer(&musb->otg_timer, jiffies 777 + msecs_to_jiffies( 778 OTG_TIME_B_ASE0_BRST)); 779 } 780 break; 781 case OTG_STATE_A_WAIT_BCON: 782 if (musb->a_wait_bcon != 0) 783 musb_platform_try_idle(musb, jiffies 784 + msecs_to_jiffies(musb->a_wait_bcon)); 785 break; 786 case OTG_STATE_A_HOST: 787 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND; 788 musb->is_active = musb->hcd->self.b_hnp_enable; 789 break; 790 case OTG_STATE_B_HOST: 791 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 792 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST"); 793 break; 794 default: 795 /* "should not happen" */ 796 musb->is_active = 0; 797 break; 798 } 799 } 800 801 if (int_usb & MUSB_INTR_CONNECT) { 802 struct usb_hcd *hcd = musb->hcd; 803 804 handled = IRQ_HANDLED; 805 musb->is_active = 1; 806 807 musb->ep0_stage = MUSB_EP0_START; 808 809 musb->intrtxe = musb->epmask; 810 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); 811 musb->intrrxe = musb->epmask & 0xfffe; 812 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); 813 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 814 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 815 |USB_PORT_STAT_HIGH_SPEED 816 |USB_PORT_STAT_ENABLE 817 ); 818 musb->port1_status |= USB_PORT_STAT_CONNECTION 819 |(USB_PORT_STAT_C_CONNECTION << 16); 820 821 /* high vs full speed is just a guess until after reset */ 822 if (devctl & MUSB_DEVCTL_LSDEV) 823 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 824 825 /* indicate new connection to OTG machine */ 826 switch (musb->xceiv->otg->state) { 827 case OTG_STATE_B_PERIPHERAL: 828 if (int_usb & MUSB_INTR_SUSPEND) { 829 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host"); 830 int_usb &= ~MUSB_INTR_SUSPEND; 831 goto b_host; 832 } else 833 musb_dbg(musb, "CONNECT as b_peripheral???"); 834 break; 835 case OTG_STATE_B_WAIT_ACON: 836 musb_dbg(musb, "HNP: CONNECT, now b_host"); 837 b_host: 838 musb->xceiv->otg->state = OTG_STATE_B_HOST; 839 if (musb->hcd) 840 musb->hcd->self.is_b_host = 1; 841 del_timer(&musb->otg_timer); 842 break; 843 default: 844 if ((devctl & MUSB_DEVCTL_VBUS) 845 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 846 musb->xceiv->otg->state = OTG_STATE_A_HOST; 847 if (hcd) 848 hcd->self.is_b_host = 0; 849 } 850 break; 851 } 852 853 musb_host_poke_root_hub(musb); 854 855 musb_dbg(musb, "CONNECT (%s) devctl %02x", 856 usb_otg_state_string(musb->xceiv->otg->state), devctl); 857 } 858 859 if (int_usb & MUSB_INTR_DISCONNECT) { 860 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x", 861 usb_otg_state_string(musb->xceiv->otg->state), 862 MUSB_MODE(musb), devctl); 863 handled = IRQ_HANDLED; 864 865 switch (musb->xceiv->otg->state) { 866 case OTG_STATE_A_HOST: 867 case OTG_STATE_A_SUSPEND: 868 musb_host_resume_root_hub(musb); 869 musb_root_disconnect(musb); 870 if (musb->a_wait_bcon != 0) 871 musb_platform_try_idle(musb, jiffies 872 + msecs_to_jiffies(musb->a_wait_bcon)); 873 break; 874 case OTG_STATE_B_HOST: 875 /* REVISIT this behaves for "real disconnect" 876 * cases; make sure the other transitions from 877 * from B_HOST act right too. The B_HOST code 878 * in hnp_stop() is currently not used... 879 */ 880 musb_root_disconnect(musb); 881 if (musb->hcd) 882 musb->hcd->self.is_b_host = 0; 883 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 884 MUSB_DEV_MODE(musb); 885 musb_g_disconnect(musb); 886 break; 887 case OTG_STATE_A_PERIPHERAL: 888 musb_hnp_stop(musb); 889 musb_root_disconnect(musb); 890 /* FALLTHROUGH */ 891 case OTG_STATE_B_WAIT_ACON: 892 /* FALLTHROUGH */ 893 case OTG_STATE_B_PERIPHERAL: 894 case OTG_STATE_B_IDLE: 895 musb_g_disconnect(musb); 896 break; 897 default: 898 WARNING("unhandled DISCONNECT transition (%s)\n", 899 usb_otg_state_string(musb->xceiv->otg->state)); 900 break; 901 } 902 } 903 904 /* mentor saves a bit: bus reset and babble share the same irq. 905 * only host sees babble; only peripheral sees bus reset. 906 */ 907 if (int_usb & MUSB_INTR_RESET) { 908 handled = IRQ_HANDLED; 909 if (devctl & MUSB_DEVCTL_HM) { 910 /* 911 * When BABBLE happens what we can depends on which 912 * platform MUSB is running, because some platforms 913 * implemented proprietary means for 'recovering' from 914 * Babble conditions. One such platform is AM335x. In 915 * most cases, however, the only thing we can do is 916 * drop the session. 917 */ 918 dev_err(musb->controller, "Babble\n"); 919 920 if (is_host_active(musb)) 921 musb_recover_from_babble(musb); 922 } else { 923 musb_dbg(musb, "BUS RESET as %s", 924 usb_otg_state_string(musb->xceiv->otg->state)); 925 switch (musb->xceiv->otg->state) { 926 case OTG_STATE_A_SUSPEND: 927 musb_g_reset(musb); 928 /* FALLTHROUGH */ 929 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 930 /* never use invalid T(a_wait_bcon) */ 931 musb_dbg(musb, "HNP: in %s, %d msec timeout", 932 usb_otg_state_string(musb->xceiv->otg->state), 933 TA_WAIT_BCON(musb)); 934 mod_timer(&musb->otg_timer, jiffies 935 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 936 break; 937 case OTG_STATE_A_PERIPHERAL: 938 del_timer(&musb->otg_timer); 939 musb_g_reset(musb); 940 break; 941 case OTG_STATE_B_WAIT_ACON: 942 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral", 943 usb_otg_state_string(musb->xceiv->otg->state)); 944 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 945 musb_g_reset(musb); 946 break; 947 case OTG_STATE_B_IDLE: 948 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 949 /* FALLTHROUGH */ 950 case OTG_STATE_B_PERIPHERAL: 951 musb_g_reset(musb); 952 break; 953 default: 954 musb_dbg(musb, "Unhandled BUS RESET as %s", 955 usb_otg_state_string(musb->xceiv->otg->state)); 956 } 957 } 958 } 959 960 #if 0 961 /* REVISIT ... this would be for multiplexing periodic endpoints, or 962 * supporting transfer phasing to prevent exceeding ISO bandwidth 963 * limits of a given frame or microframe. 964 * 965 * It's not needed for peripheral side, which dedicates endpoints; 966 * though it _might_ use SOF irqs for other purposes. 967 * 968 * And it's not currently needed for host side, which also dedicates 969 * endpoints, relies on TX/RX interval registers, and isn't claimed 970 * to support ISO transfers yet. 971 */ 972 if (int_usb & MUSB_INTR_SOF) { 973 void __iomem *mbase = musb->mregs; 974 struct musb_hw_ep *ep; 975 u8 epnum; 976 u16 frame; 977 978 dev_dbg(musb->controller, "START_OF_FRAME\n"); 979 handled = IRQ_HANDLED; 980 981 /* start any periodic Tx transfers waiting for current frame */ 982 frame = musb_readw(mbase, MUSB_FRAME); 983 ep = musb->endpoints; 984 for (epnum = 1; (epnum < musb->nr_endpoints) 985 && (musb->epmask >= (1 << epnum)); 986 epnum++, ep++) { 987 /* 988 * FIXME handle framecounter wraps (12 bits) 989 * eliminate duplicated StartUrb logic 990 */ 991 if (ep->dwWaitFrame >= frame) { 992 ep->dwWaitFrame = 0; 993 pr_debug("SOF --> periodic TX%s on %d\n", 994 ep->tx_channel ? " DMA" : "", 995 epnum); 996 if (!ep->tx_channel) 997 musb_h_tx_start(musb, epnum); 998 else 999 cppi_hostdma_start(musb, epnum); 1000 } 1001 } /* end of for loop */ 1002 } 1003 #endif 1004 1005 schedule_delayed_work(&musb->irq_work, 0); 1006 1007 return handled; 1008 } 1009 1010 /*-------------------------------------------------------------------------*/ 1011 1012 static void musb_disable_interrupts(struct musb *musb) 1013 { 1014 void __iomem *mbase = musb->mregs; 1015 u16 temp; 1016 1017 /* disable interrupts */ 1018 musb_writeb(mbase, MUSB_INTRUSBE, 0); 1019 musb->intrtxe = 0; 1020 musb_writew(mbase, MUSB_INTRTXE, 0); 1021 musb->intrrxe = 0; 1022 musb_writew(mbase, MUSB_INTRRXE, 0); 1023 1024 /* flush pending interrupts */ 1025 temp = musb_readb(mbase, MUSB_INTRUSB); 1026 temp = musb_readw(mbase, MUSB_INTRTX); 1027 temp = musb_readw(mbase, MUSB_INTRRX); 1028 } 1029 1030 static void musb_enable_interrupts(struct musb *musb) 1031 { 1032 void __iomem *regs = musb->mregs; 1033 1034 /* Set INT enable registers, enable interrupts */ 1035 musb->intrtxe = musb->epmask; 1036 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); 1037 musb->intrrxe = musb->epmask & 0xfffe; 1038 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); 1039 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 1040 1041 } 1042 1043 static void musb_generic_disable(struct musb *musb) 1044 { 1045 void __iomem *mbase = musb->mregs; 1046 1047 musb_disable_interrupts(musb); 1048 1049 /* off */ 1050 musb_writeb(mbase, MUSB_DEVCTL, 0); 1051 } 1052 1053 /* 1054 * Program the HDRC to start (enable interrupts, dma, etc.). 1055 */ 1056 void musb_start(struct musb *musb) 1057 { 1058 void __iomem *regs = musb->mregs; 1059 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 1060 u8 power; 1061 1062 musb_dbg(musb, "<== devctl %02x", devctl); 1063 1064 musb_enable_interrupts(musb); 1065 musb_writeb(regs, MUSB_TESTMODE, 0); 1066 1067 power = MUSB_POWER_ISOUPDATE; 1068 /* 1069 * treating UNKNOWN as unspecified maximum speed, in which case 1070 * we will default to high-speed. 1071 */ 1072 if (musb->config->maximum_speed == USB_SPEED_HIGH || 1073 musb->config->maximum_speed == USB_SPEED_UNKNOWN) 1074 power |= MUSB_POWER_HSENAB; 1075 musb_writeb(regs, MUSB_POWER, power); 1076 1077 musb->is_active = 0; 1078 devctl = musb_readb(regs, MUSB_DEVCTL); 1079 devctl &= ~MUSB_DEVCTL_SESSION; 1080 1081 /* session started after: 1082 * (a) ID-grounded irq, host mode; 1083 * (b) vbus present/connect IRQ, peripheral mode; 1084 * (c) peripheral initiates, using SRP 1085 */ 1086 if (musb->port_mode != MUSB_PORT_MODE_HOST && 1087 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON && 1088 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { 1089 musb->is_active = 1; 1090 } else { 1091 devctl |= MUSB_DEVCTL_SESSION; 1092 } 1093 1094 musb_platform_enable(musb); 1095 musb_writeb(regs, MUSB_DEVCTL, devctl); 1096 } 1097 1098 /* 1099 * Make the HDRC stop (disable interrupts, etc.); 1100 * reversible by musb_start 1101 * called on gadget driver unregister 1102 * with controller locked, irqs blocked 1103 * acts as a NOP unless some role activated the hardware 1104 */ 1105 void musb_stop(struct musb *musb) 1106 { 1107 /* stop IRQs, timers, ... */ 1108 musb_platform_disable(musb); 1109 musb_generic_disable(musb); 1110 musb_dbg(musb, "HDRC disabled"); 1111 1112 /* FIXME 1113 * - mark host and/or peripheral drivers unusable/inactive 1114 * - disable DMA (and enable it in HdrcStart) 1115 * - make sure we can musb_start() after musb_stop(); with 1116 * OTG mode, gadget driver module rmmod/modprobe cycles that 1117 * - ... 1118 */ 1119 musb_platform_try_idle(musb, 0); 1120 } 1121 1122 /*-------------------------------------------------------------------------*/ 1123 1124 /* 1125 * The silicon either has hard-wired endpoint configurations, or else 1126 * "dynamic fifo" sizing. The driver has support for both, though at this 1127 * writing only the dynamic sizing is very well tested. Since we switched 1128 * away from compile-time hardware parameters, we can no longer rely on 1129 * dead code elimination to leave only the relevant one in the object file. 1130 * 1131 * We don't currently use dynamic fifo setup capability to do anything 1132 * more than selecting one of a bunch of predefined configurations. 1133 */ 1134 static ushort fifo_mode; 1135 1136 /* "modprobe ... fifo_mode=1" etc */ 1137 module_param(fifo_mode, ushort, 0); 1138 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1139 1140 /* 1141 * tables defining fifo_mode values. define more if you like. 1142 * for host side, make sure both halves of ep1 are set up. 1143 */ 1144 1145 /* mode 0 - fits in 2KB */ 1146 static struct musb_fifo_cfg mode_0_cfg[] = { 1147 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1148 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1149 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1150 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1151 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1152 }; 1153 1154 /* mode 1 - fits in 4KB */ 1155 static struct musb_fifo_cfg mode_1_cfg[] = { 1156 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1157 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1158 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1159 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1160 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1161 }; 1162 1163 /* mode 2 - fits in 4KB */ 1164 static struct musb_fifo_cfg mode_2_cfg[] = { 1165 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1166 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1167 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1168 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1169 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1170 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1171 }; 1172 1173 /* mode 3 - fits in 4KB */ 1174 static struct musb_fifo_cfg mode_3_cfg[] = { 1175 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1176 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1177 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1178 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1179 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1180 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1181 }; 1182 1183 /* mode 4 - fits in 16KB */ 1184 static struct musb_fifo_cfg mode_4_cfg[] = { 1185 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1186 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1187 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1188 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1189 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1190 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1191 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1192 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1193 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1194 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1195 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1196 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1197 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1198 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1199 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1200 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1201 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1202 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1203 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1204 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1205 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1206 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1207 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1208 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1209 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1210 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1211 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1212 }; 1213 1214 /* mode 5 - fits in 8KB */ 1215 static struct musb_fifo_cfg mode_5_cfg[] = { 1216 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1217 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1218 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1219 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1220 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1221 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1222 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1223 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1224 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1225 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1226 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1227 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1228 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1229 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1230 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1231 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1232 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1233 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1234 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1235 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1236 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1237 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1238 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1239 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1240 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1241 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1242 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1243 }; 1244 1245 /* 1246 * configure a fifo; for non-shared endpoints, this may be called 1247 * once for a tx fifo and once for an rx fifo. 1248 * 1249 * returns negative errno or offset for next fifo. 1250 */ 1251 static int 1252 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1253 const struct musb_fifo_cfg *cfg, u16 offset) 1254 { 1255 void __iomem *mbase = musb->mregs; 1256 int size = 0; 1257 u16 maxpacket = cfg->maxpacket; 1258 u16 c_off = offset >> 3; 1259 u8 c_size; 1260 1261 /* expect hw_ep has already been zero-initialized */ 1262 1263 size = ffs(max(maxpacket, (u16) 8)) - 1; 1264 maxpacket = 1 << size; 1265 1266 c_size = size - 3; 1267 if (cfg->mode == BUF_DOUBLE) { 1268 if ((offset + (maxpacket << 1)) > 1269 (1 << (musb->config->ram_bits + 2))) 1270 return -EMSGSIZE; 1271 c_size |= MUSB_FIFOSZ_DPB; 1272 } else { 1273 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1274 return -EMSGSIZE; 1275 } 1276 1277 /* configure the FIFO */ 1278 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1279 1280 /* EP0 reserved endpoint for control, bidirectional; 1281 * EP1 reserved for bulk, two unidirectional halves. 1282 */ 1283 if (hw_ep->epnum == 1) 1284 musb->bulk_ep = hw_ep; 1285 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1286 switch (cfg->style) { 1287 case FIFO_TX: 1288 musb_write_txfifosz(mbase, c_size); 1289 musb_write_txfifoadd(mbase, c_off); 1290 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1291 hw_ep->max_packet_sz_tx = maxpacket; 1292 break; 1293 case FIFO_RX: 1294 musb_write_rxfifosz(mbase, c_size); 1295 musb_write_rxfifoadd(mbase, c_off); 1296 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1297 hw_ep->max_packet_sz_rx = maxpacket; 1298 break; 1299 case FIFO_RXTX: 1300 musb_write_txfifosz(mbase, c_size); 1301 musb_write_txfifoadd(mbase, c_off); 1302 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1303 hw_ep->max_packet_sz_rx = maxpacket; 1304 1305 musb_write_rxfifosz(mbase, c_size); 1306 musb_write_rxfifoadd(mbase, c_off); 1307 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1308 hw_ep->max_packet_sz_tx = maxpacket; 1309 1310 hw_ep->is_shared_fifo = true; 1311 break; 1312 } 1313 1314 /* NOTE rx and tx endpoint irqs aren't managed separately, 1315 * which happens to be ok 1316 */ 1317 musb->epmask |= (1 << hw_ep->epnum); 1318 1319 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1320 } 1321 1322 static struct musb_fifo_cfg ep0_cfg = { 1323 .style = FIFO_RXTX, .maxpacket = 64, 1324 }; 1325 1326 static int ep_config_from_table(struct musb *musb) 1327 { 1328 const struct musb_fifo_cfg *cfg; 1329 unsigned i, n; 1330 int offset; 1331 struct musb_hw_ep *hw_ep = musb->endpoints; 1332 1333 if (musb->config->fifo_cfg) { 1334 cfg = musb->config->fifo_cfg; 1335 n = musb->config->fifo_cfg_size; 1336 goto done; 1337 } 1338 1339 switch (fifo_mode) { 1340 default: 1341 fifo_mode = 0; 1342 /* FALLTHROUGH */ 1343 case 0: 1344 cfg = mode_0_cfg; 1345 n = ARRAY_SIZE(mode_0_cfg); 1346 break; 1347 case 1: 1348 cfg = mode_1_cfg; 1349 n = ARRAY_SIZE(mode_1_cfg); 1350 break; 1351 case 2: 1352 cfg = mode_2_cfg; 1353 n = ARRAY_SIZE(mode_2_cfg); 1354 break; 1355 case 3: 1356 cfg = mode_3_cfg; 1357 n = ARRAY_SIZE(mode_3_cfg); 1358 break; 1359 case 4: 1360 cfg = mode_4_cfg; 1361 n = ARRAY_SIZE(mode_4_cfg); 1362 break; 1363 case 5: 1364 cfg = mode_5_cfg; 1365 n = ARRAY_SIZE(mode_5_cfg); 1366 break; 1367 } 1368 1369 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); 1370 1371 1372 done: 1373 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1374 /* assert(offset > 0) */ 1375 1376 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1377 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1378 */ 1379 1380 for (i = 0; i < n; i++) { 1381 u8 epn = cfg->hw_ep_num; 1382 1383 if (epn >= musb->config->num_eps) { 1384 pr_debug("%s: invalid ep %d\n", 1385 musb_driver_name, epn); 1386 return -EINVAL; 1387 } 1388 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1389 if (offset < 0) { 1390 pr_debug("%s: mem overrun, ep %d\n", 1391 musb_driver_name, epn); 1392 return offset; 1393 } 1394 epn++; 1395 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1396 } 1397 1398 pr_debug("%s: %d/%d max ep, %d/%d memory\n", 1399 musb_driver_name, 1400 n + 1, musb->config->num_eps * 2 - 1, 1401 offset, (1 << (musb->config->ram_bits + 2))); 1402 1403 if (!musb->bulk_ep) { 1404 pr_debug("%s: missing bulk\n", musb_driver_name); 1405 return -EINVAL; 1406 } 1407 1408 return 0; 1409 } 1410 1411 1412 /* 1413 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1414 * @param musb the controller 1415 */ 1416 static int ep_config_from_hw(struct musb *musb) 1417 { 1418 u8 epnum = 0; 1419 struct musb_hw_ep *hw_ep; 1420 void __iomem *mbase = musb->mregs; 1421 int ret = 0; 1422 1423 musb_dbg(musb, "<== static silicon ep config"); 1424 1425 /* FIXME pick up ep0 maxpacket size */ 1426 1427 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1428 musb_ep_select(mbase, epnum); 1429 hw_ep = musb->endpoints + epnum; 1430 1431 ret = musb_read_fifosize(musb, hw_ep, epnum); 1432 if (ret < 0) 1433 break; 1434 1435 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1436 1437 /* pick an RX/TX endpoint for bulk */ 1438 if (hw_ep->max_packet_sz_tx < 512 1439 || hw_ep->max_packet_sz_rx < 512) 1440 continue; 1441 1442 /* REVISIT: this algorithm is lazy, we should at least 1443 * try to pick a double buffered endpoint. 1444 */ 1445 if (musb->bulk_ep) 1446 continue; 1447 musb->bulk_ep = hw_ep; 1448 } 1449 1450 if (!musb->bulk_ep) { 1451 pr_debug("%s: missing bulk\n", musb_driver_name); 1452 return -EINVAL; 1453 } 1454 1455 return 0; 1456 } 1457 1458 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1459 1460 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1461 * configure endpoints, or take their config from silicon 1462 */ 1463 static int musb_core_init(u16 musb_type, struct musb *musb) 1464 { 1465 u8 reg; 1466 char *type; 1467 char aInfo[90]; 1468 void __iomem *mbase = musb->mregs; 1469 int status = 0; 1470 int i; 1471 1472 /* log core options (read using indexed model) */ 1473 reg = musb_read_configdata(mbase); 1474 1475 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1476 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1477 strcat(aInfo, ", dyn FIFOs"); 1478 musb->dyn_fifo = true; 1479 } 1480 if (reg & MUSB_CONFIGDATA_MPRXE) { 1481 strcat(aInfo, ", bulk combine"); 1482 musb->bulk_combine = true; 1483 } 1484 if (reg & MUSB_CONFIGDATA_MPTXE) { 1485 strcat(aInfo, ", bulk split"); 1486 musb->bulk_split = true; 1487 } 1488 if (reg & MUSB_CONFIGDATA_HBRXE) { 1489 strcat(aInfo, ", HB-ISO Rx"); 1490 musb->hb_iso_rx = true; 1491 } 1492 if (reg & MUSB_CONFIGDATA_HBTXE) { 1493 strcat(aInfo, ", HB-ISO Tx"); 1494 musb->hb_iso_tx = true; 1495 } 1496 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1497 strcat(aInfo, ", SoftConn"); 1498 1499 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); 1500 1501 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1502 musb->is_multipoint = 1; 1503 type = "M"; 1504 } else { 1505 musb->is_multipoint = 0; 1506 type = ""; 1507 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1508 pr_err("%s: kernel must blacklist external hubs\n", 1509 musb_driver_name); 1510 #endif 1511 } 1512 1513 /* log release info */ 1514 musb->hwvers = musb_read_hwvers(mbase); 1515 pr_debug("%s: %sHDRC RTL version %d.%d%s\n", 1516 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers), 1517 MUSB_HWVERS_MINOR(musb->hwvers), 1518 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1519 1520 /* configure ep0 */ 1521 musb_configure_ep0(musb); 1522 1523 /* discover endpoint configuration */ 1524 musb->nr_endpoints = 1; 1525 musb->epmask = 1; 1526 1527 if (musb->dyn_fifo) 1528 status = ep_config_from_table(musb); 1529 else 1530 status = ep_config_from_hw(musb); 1531 1532 if (status < 0) 1533 return status; 1534 1535 /* finish init, and print endpoint config */ 1536 for (i = 0; i < musb->nr_endpoints; i++) { 1537 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1538 1539 hw_ep->fifo = musb->io.fifo_offset(i) + mbase; 1540 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) 1541 if (musb->io.quirks & MUSB_IN_TUSB) { 1542 hw_ep->fifo_async = musb->async + 0x400 + 1543 musb->io.fifo_offset(i); 1544 hw_ep->fifo_sync = musb->sync + 0x400 + 1545 musb->io.fifo_offset(i); 1546 hw_ep->fifo_sync_va = 1547 musb->sync_va + 0x400 + musb->io.fifo_offset(i); 1548 1549 if (i == 0) 1550 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1551 else 1552 hw_ep->conf = mbase + 0x400 + 1553 (((i - 1) & 0xf) << 2); 1554 } 1555 #endif 1556 1557 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase; 1558 hw_ep->rx_reinit = 1; 1559 hw_ep->tx_reinit = 1; 1560 1561 if (hw_ep->max_packet_sz_tx) { 1562 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", 1563 musb_driver_name, i, 1564 hw_ep->is_shared_fifo ? "shared" : "tx", 1565 hw_ep->tx_double_buffered 1566 ? "doublebuffer, " : "", 1567 hw_ep->max_packet_sz_tx); 1568 } 1569 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1570 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", 1571 musb_driver_name, i, 1572 "rx", 1573 hw_ep->rx_double_buffered 1574 ? "doublebuffer, " : "", 1575 hw_ep->max_packet_sz_rx); 1576 } 1577 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1578 musb_dbg(musb, "hw_ep %d not configured", i); 1579 } 1580 1581 return 0; 1582 } 1583 1584 /*-------------------------------------------------------------------------*/ 1585 1586 /* 1587 * handle all the irqs defined by the HDRC core. for now we expect: other 1588 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1589 * will be assigned, and the irq will already have been acked. 1590 * 1591 * called in irq context with spinlock held, irqs blocked 1592 */ 1593 irqreturn_t musb_interrupt(struct musb *musb) 1594 { 1595 irqreturn_t retval = IRQ_NONE; 1596 unsigned long status; 1597 unsigned long epnum; 1598 u8 devctl; 1599 1600 if (!musb->int_usb && !musb->int_tx && !musb->int_rx) 1601 return IRQ_NONE; 1602 1603 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1604 1605 trace_musb_isr(musb); 1606 1607 /** 1608 * According to Mentor Graphics' documentation, flowchart on page 98, 1609 * IRQ should be handled as follows: 1610 * 1611 * . Resume IRQ 1612 * . Session Request IRQ 1613 * . VBUS Error IRQ 1614 * . Suspend IRQ 1615 * . Connect IRQ 1616 * . Disconnect IRQ 1617 * . Reset/Babble IRQ 1618 * . SOF IRQ (we're not using this one) 1619 * . Endpoint 0 IRQ 1620 * . TX Endpoints 1621 * . RX Endpoints 1622 * 1623 * We will be following that flowchart in order to avoid any problems 1624 * that might arise with internal Finite State Machine. 1625 */ 1626 1627 if (musb->int_usb) 1628 retval |= musb_stage0_irq(musb, musb->int_usb, devctl); 1629 1630 if (musb->int_tx & 1) { 1631 if (is_host_active(musb)) 1632 retval |= musb_h_ep0_irq(musb); 1633 else 1634 retval |= musb_g_ep0_irq(musb); 1635 1636 /* we have just handled endpoint 0 IRQ, clear it */ 1637 musb->int_tx &= ~BIT(0); 1638 } 1639 1640 status = musb->int_tx; 1641 1642 for_each_set_bit(epnum, &status, 16) { 1643 retval = IRQ_HANDLED; 1644 if (is_host_active(musb)) 1645 musb_host_tx(musb, epnum); 1646 else 1647 musb_g_tx(musb, epnum); 1648 } 1649 1650 status = musb->int_rx; 1651 1652 for_each_set_bit(epnum, &status, 16) { 1653 retval = IRQ_HANDLED; 1654 if (is_host_active(musb)) 1655 musb_host_rx(musb, epnum); 1656 else 1657 musb_g_rx(musb, epnum); 1658 } 1659 1660 return retval; 1661 } 1662 EXPORT_SYMBOL_GPL(musb_interrupt); 1663 1664 #ifndef CONFIG_MUSB_PIO_ONLY 1665 static bool use_dma = 1; 1666 1667 /* "modprobe ... use_dma=0" etc */ 1668 module_param(use_dma, bool, 0644); 1669 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1670 1671 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1672 { 1673 /* called with controller lock already held */ 1674 1675 if (!epnum) { 1676 if (!is_cppi_enabled(musb)) { 1677 /* endpoint 0 */ 1678 if (is_host_active(musb)) 1679 musb_h_ep0_irq(musb); 1680 else 1681 musb_g_ep0_irq(musb); 1682 } 1683 } else { 1684 /* endpoints 1..15 */ 1685 if (transmit) { 1686 if (is_host_active(musb)) 1687 musb_host_tx(musb, epnum); 1688 else 1689 musb_g_tx(musb, epnum); 1690 } else { 1691 /* receive */ 1692 if (is_host_active(musb)) 1693 musb_host_rx(musb, epnum); 1694 else 1695 musb_g_rx(musb, epnum); 1696 } 1697 } 1698 } 1699 EXPORT_SYMBOL_GPL(musb_dma_completion); 1700 1701 #else 1702 #define use_dma 0 1703 #endif 1704 1705 static int (*musb_phy_callback)(enum musb_vbus_id_status status); 1706 1707 /* 1708 * musb_mailbox - optional phy notifier function 1709 * @status phy state change 1710 * 1711 * Optionally gets called from the USB PHY. Note that the USB PHY must be 1712 * disabled at the point the phy_callback is registered or unregistered. 1713 */ 1714 int musb_mailbox(enum musb_vbus_id_status status) 1715 { 1716 if (musb_phy_callback) 1717 return musb_phy_callback(status); 1718 1719 return -ENODEV; 1720 }; 1721 EXPORT_SYMBOL_GPL(musb_mailbox); 1722 1723 /*-------------------------------------------------------------------------*/ 1724 1725 static ssize_t 1726 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1727 { 1728 struct musb *musb = dev_to_musb(dev); 1729 unsigned long flags; 1730 int ret = -EINVAL; 1731 1732 spin_lock_irqsave(&musb->lock, flags); 1733 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state)); 1734 spin_unlock_irqrestore(&musb->lock, flags); 1735 1736 return ret; 1737 } 1738 1739 static ssize_t 1740 musb_mode_store(struct device *dev, struct device_attribute *attr, 1741 const char *buf, size_t n) 1742 { 1743 struct musb *musb = dev_to_musb(dev); 1744 unsigned long flags; 1745 int status; 1746 1747 spin_lock_irqsave(&musb->lock, flags); 1748 if (sysfs_streq(buf, "host")) 1749 status = musb_platform_set_mode(musb, MUSB_HOST); 1750 else if (sysfs_streq(buf, "peripheral")) 1751 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1752 else if (sysfs_streq(buf, "otg")) 1753 status = musb_platform_set_mode(musb, MUSB_OTG); 1754 else 1755 status = -EINVAL; 1756 spin_unlock_irqrestore(&musb->lock, flags); 1757 1758 return (status == 0) ? n : status; 1759 } 1760 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1761 1762 static ssize_t 1763 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1764 const char *buf, size_t n) 1765 { 1766 struct musb *musb = dev_to_musb(dev); 1767 unsigned long flags; 1768 unsigned long val; 1769 1770 if (sscanf(buf, "%lu", &val) < 1) { 1771 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1772 return -EINVAL; 1773 } 1774 1775 spin_lock_irqsave(&musb->lock, flags); 1776 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1777 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1778 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) 1779 musb->is_active = 0; 1780 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1781 spin_unlock_irqrestore(&musb->lock, flags); 1782 1783 return n; 1784 } 1785 1786 static ssize_t 1787 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1788 { 1789 struct musb *musb = dev_to_musb(dev); 1790 unsigned long flags; 1791 unsigned long val; 1792 int vbus; 1793 u8 devctl; 1794 1795 spin_lock_irqsave(&musb->lock, flags); 1796 val = musb->a_wait_bcon; 1797 vbus = musb_platform_get_vbus_status(musb); 1798 if (vbus < 0) { 1799 /* Use default MUSB method by means of DEVCTL register */ 1800 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1801 if ((devctl & MUSB_DEVCTL_VBUS) 1802 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) 1803 vbus = 1; 1804 else 1805 vbus = 0; 1806 } 1807 spin_unlock_irqrestore(&musb->lock, flags); 1808 1809 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1810 vbus ? "on" : "off", val); 1811 } 1812 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1813 1814 /* Gadget drivers can't know that a host is connected so they might want 1815 * to start SRP, but users can. This allows userspace to trigger SRP. 1816 */ 1817 static ssize_t 1818 musb_srp_store(struct device *dev, struct device_attribute *attr, 1819 const char *buf, size_t n) 1820 { 1821 struct musb *musb = dev_to_musb(dev); 1822 unsigned short srp; 1823 1824 if (sscanf(buf, "%hu", &srp) != 1 1825 || (srp != 1)) { 1826 dev_err(dev, "SRP: Value must be 1\n"); 1827 return -EINVAL; 1828 } 1829 1830 if (srp == 1) 1831 musb_g_wakeup(musb); 1832 1833 return n; 1834 } 1835 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1836 1837 static struct attribute *musb_attributes[] = { 1838 &dev_attr_mode.attr, 1839 &dev_attr_vbus.attr, 1840 &dev_attr_srp.attr, 1841 NULL 1842 }; 1843 1844 static const struct attribute_group musb_attr_group = { 1845 .attrs = musb_attributes, 1846 }; 1847 1848 #define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \ 1849 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \ 1850 MUSB_DEVCTL_SESSION) 1851 #define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \ 1852 MUSB_DEVCTL_SESSION) 1853 1854 /* 1855 * Check the musb devctl session bit to determine if we want to 1856 * allow PM runtime for the device. In general, we want to keep things 1857 * active when the session bit is set except after host disconnect. 1858 * 1859 * Only called from musb_irq_work. If this ever needs to get called 1860 * elsewhere, proper locking must be implemented for musb->session. 1861 */ 1862 static void musb_pm_runtime_check_session(struct musb *musb) 1863 { 1864 u8 devctl, s; 1865 int error; 1866 1867 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1868 1869 /* Handle session status quirks first */ 1870 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV | 1871 MUSB_DEVCTL_HR; 1872 switch (devctl & ~s) { 1873 case MUSB_QUIRK_B_INVALID_VBUS_91: 1874 if (musb->quirk_retries--) { 1875 musb_dbg(musb, 1876 "Poll devctl on invalid vbus, assume no session"); 1877 schedule_delayed_work(&musb->irq_work, 1878 msecs_to_jiffies(1000)); 1879 1880 return; 1881 } 1882 case MUSB_QUIRK_A_DISCONNECT_19: 1883 if (musb->quirk_retries--) { 1884 musb_dbg(musb, 1885 "Poll devctl on possible host mode disconnect"); 1886 schedule_delayed_work(&musb->irq_work, 1887 msecs_to_jiffies(1000)); 1888 1889 return; 1890 } 1891 if (!musb->session) 1892 break; 1893 musb_dbg(musb, "Allow PM on possible host mode disconnect"); 1894 pm_runtime_mark_last_busy(musb->controller); 1895 pm_runtime_put_autosuspend(musb->controller); 1896 musb->session = false; 1897 return; 1898 default: 1899 break; 1900 } 1901 1902 /* No need to do anything if session has not changed */ 1903 s = devctl & MUSB_DEVCTL_SESSION; 1904 if (s == musb->session) 1905 return; 1906 1907 /* Block PM or allow PM? */ 1908 if (s) { 1909 musb_dbg(musb, "Block PM on active session: %02x", devctl); 1910 error = pm_runtime_get_sync(musb->controller); 1911 if (error < 0) 1912 dev_err(musb->controller, "Could not enable: %i\n", 1913 error); 1914 musb->quirk_retries = 3; 1915 } else { 1916 musb_dbg(musb, "Allow PM with no session: %02x", devctl); 1917 pm_runtime_mark_last_busy(musb->controller); 1918 pm_runtime_put_autosuspend(musb->controller); 1919 } 1920 1921 musb->session = s; 1922 } 1923 1924 /* Only used to provide driver mode change events */ 1925 static void musb_irq_work(struct work_struct *data) 1926 { 1927 struct musb *musb = container_of(data, struct musb, irq_work.work); 1928 1929 musb_pm_runtime_check_session(musb); 1930 1931 if (musb->xceiv->otg->state != musb->xceiv_old_state) { 1932 musb->xceiv_old_state = musb->xceiv->otg->state; 1933 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1934 } 1935 } 1936 1937 static void musb_recover_from_babble(struct musb *musb) 1938 { 1939 int ret; 1940 u8 devctl; 1941 1942 musb_disable_interrupts(musb); 1943 1944 /* 1945 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give 1946 * it some slack and wait for 10us. 1947 */ 1948 udelay(10); 1949 1950 ret = musb_platform_recover(musb); 1951 if (ret) { 1952 musb_enable_interrupts(musb); 1953 return; 1954 } 1955 1956 /* drop session bit */ 1957 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1958 devctl &= ~MUSB_DEVCTL_SESSION; 1959 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 1960 1961 /* tell usbcore about it */ 1962 musb_root_disconnect(musb); 1963 1964 /* 1965 * When a babble condition occurs, the musb controller 1966 * removes the session bit and the endpoint config is lost. 1967 */ 1968 if (musb->dyn_fifo) 1969 ret = ep_config_from_table(musb); 1970 else 1971 ret = ep_config_from_hw(musb); 1972 1973 /* restart session */ 1974 if (ret == 0) 1975 musb_start(musb); 1976 } 1977 1978 /* -------------------------------------------------------------------------- 1979 * Init support 1980 */ 1981 1982 static struct musb *allocate_instance(struct device *dev, 1983 const struct musb_hdrc_config *config, void __iomem *mbase) 1984 { 1985 struct musb *musb; 1986 struct musb_hw_ep *ep; 1987 int epnum; 1988 int ret; 1989 1990 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); 1991 if (!musb) 1992 return NULL; 1993 1994 INIT_LIST_HEAD(&musb->control); 1995 INIT_LIST_HEAD(&musb->in_bulk); 1996 INIT_LIST_HEAD(&musb->out_bulk); 1997 INIT_LIST_HEAD(&musb->pending_list); 1998 1999 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 2000 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 2001 musb->mregs = mbase; 2002 musb->ctrl_base = mbase; 2003 musb->nIrq = -ENODEV; 2004 musb->config = config; 2005 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 2006 for (epnum = 0, ep = musb->endpoints; 2007 epnum < musb->config->num_eps; 2008 epnum++, ep++) { 2009 ep->musb = musb; 2010 ep->epnum = epnum; 2011 } 2012 2013 musb->controller = dev; 2014 2015 ret = musb_host_alloc(musb); 2016 if (ret < 0) 2017 goto err_free; 2018 2019 dev_set_drvdata(dev, musb); 2020 2021 return musb; 2022 2023 err_free: 2024 return NULL; 2025 } 2026 2027 static void musb_free(struct musb *musb) 2028 { 2029 /* this has multiple entry modes. it handles fault cleanup after 2030 * probe(), where things may be partially set up, as well as rmmod 2031 * cleanup after everything's been de-activated. 2032 */ 2033 2034 #ifdef CONFIG_SYSFS 2035 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 2036 #endif 2037 2038 if (musb->nIrq >= 0) { 2039 if (musb->irq_wake) 2040 disable_irq_wake(musb->nIrq); 2041 free_irq(musb->nIrq, musb); 2042 } 2043 2044 musb_host_free(musb); 2045 } 2046 2047 struct musb_pending_work { 2048 int (*callback)(struct musb *musb, void *data); 2049 void *data; 2050 struct list_head node; 2051 }; 2052 2053 #ifdef CONFIG_PM 2054 /* 2055 * Called from musb_runtime_resume(), musb_resume(), and 2056 * musb_queue_resume_work(). Callers must take musb->lock. 2057 */ 2058 static int musb_run_resume_work(struct musb *musb) 2059 { 2060 struct musb_pending_work *w, *_w; 2061 unsigned long flags; 2062 int error = 0; 2063 2064 spin_lock_irqsave(&musb->list_lock, flags); 2065 list_for_each_entry_safe(w, _w, &musb->pending_list, node) { 2066 if (w->callback) { 2067 error = w->callback(musb, w->data); 2068 if (error < 0) { 2069 dev_err(musb->controller, 2070 "resume callback %p failed: %i\n", 2071 w->callback, error); 2072 } 2073 } 2074 list_del(&w->node); 2075 devm_kfree(musb->controller, w); 2076 } 2077 spin_unlock_irqrestore(&musb->list_lock, flags); 2078 2079 return error; 2080 } 2081 #endif 2082 2083 /* 2084 * Called to run work if device is active or else queue the work to happen 2085 * on resume. Caller must take musb->lock and must hold an RPM reference. 2086 * 2087 * Note that we cowardly refuse queuing work after musb PM runtime 2088 * resume is done calling musb_run_resume_work() and return -EINPROGRESS 2089 * instead. 2090 */ 2091 int musb_queue_resume_work(struct musb *musb, 2092 int (*callback)(struct musb *musb, void *data), 2093 void *data) 2094 { 2095 struct musb_pending_work *w; 2096 unsigned long flags; 2097 int error; 2098 2099 if (WARN_ON(!callback)) 2100 return -EINVAL; 2101 2102 if (pm_runtime_active(musb->controller)) 2103 return callback(musb, data); 2104 2105 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC); 2106 if (!w) 2107 return -ENOMEM; 2108 2109 w->callback = callback; 2110 w->data = data; 2111 spin_lock_irqsave(&musb->list_lock, flags); 2112 if (musb->is_runtime_suspended) { 2113 list_add_tail(&w->node, &musb->pending_list); 2114 error = 0; 2115 } else { 2116 dev_err(musb->controller, "could not add resume work %p\n", 2117 callback); 2118 devm_kfree(musb->controller, w); 2119 error = -EINPROGRESS; 2120 } 2121 spin_unlock_irqrestore(&musb->list_lock, flags); 2122 2123 return error; 2124 } 2125 EXPORT_SYMBOL_GPL(musb_queue_resume_work); 2126 2127 static void musb_deassert_reset(struct work_struct *work) 2128 { 2129 struct musb *musb; 2130 unsigned long flags; 2131 2132 musb = container_of(work, struct musb, deassert_reset_work.work); 2133 2134 spin_lock_irqsave(&musb->lock, flags); 2135 2136 if (musb->port1_status & USB_PORT_STAT_RESET) 2137 musb_port_reset(musb, false); 2138 2139 spin_unlock_irqrestore(&musb->lock, flags); 2140 } 2141 2142 /* 2143 * Perform generic per-controller initialization. 2144 * 2145 * @dev: the controller (already clocked, etc) 2146 * @nIrq: IRQ number 2147 * @ctrl: virtual address of controller registers, 2148 * not yet corrected for platform-specific offsets 2149 */ 2150 static int 2151 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 2152 { 2153 int status; 2154 struct musb *musb; 2155 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 2156 2157 /* The driver might handle more features than the board; OK. 2158 * Fail when the board needs a feature that's not enabled. 2159 */ 2160 if (!plat) { 2161 dev_err(dev, "no platform_data?\n"); 2162 status = -ENODEV; 2163 goto fail0; 2164 } 2165 2166 /* allocate */ 2167 musb = allocate_instance(dev, plat->config, ctrl); 2168 if (!musb) { 2169 status = -ENOMEM; 2170 goto fail0; 2171 } 2172 2173 spin_lock_init(&musb->lock); 2174 spin_lock_init(&musb->list_lock); 2175 musb->board_set_power = plat->set_power; 2176 musb->min_power = plat->min_power; 2177 musb->ops = plat->platform_ops; 2178 musb->port_mode = plat->mode; 2179 2180 /* 2181 * Initialize the default IO functions. At least omap2430 needs 2182 * these early. We initialize the platform specific IO functions 2183 * later on. 2184 */ 2185 musb_readb = musb_default_readb; 2186 musb_writeb = musb_default_writeb; 2187 musb_readw = musb_default_readw; 2188 musb_writew = musb_default_writew; 2189 musb_readl = musb_default_readl; 2190 musb_writel = musb_default_writel; 2191 2192 /* The musb_platform_init() call: 2193 * - adjusts musb->mregs 2194 * - sets the musb->isr 2195 * - may initialize an integrated transceiver 2196 * - initializes musb->xceiv, usually by otg_get_phy() 2197 * - stops powering VBUS 2198 * 2199 * There are various transceiver configurations. Blackfin, 2200 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 2201 * external/discrete ones in various flavors (twl4030 family, 2202 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2203 */ 2204 status = musb_platform_init(musb); 2205 if (status < 0) 2206 goto fail1; 2207 2208 if (!musb->isr) { 2209 status = -ENODEV; 2210 goto fail2; 2211 } 2212 2213 if (musb->ops->quirks) 2214 musb->io.quirks = musb->ops->quirks; 2215 2216 /* Most devices use indexed offset or flat offset */ 2217 if (musb->io.quirks & MUSB_INDEXED_EP) { 2218 musb->io.ep_offset = musb_indexed_ep_offset; 2219 musb->io.ep_select = musb_indexed_ep_select; 2220 } else { 2221 musb->io.ep_offset = musb_flat_ep_offset; 2222 musb->io.ep_select = musb_flat_ep_select; 2223 } 2224 2225 /* At least tusb6010 has its own offsets */ 2226 if (musb->ops->ep_offset) 2227 musb->io.ep_offset = musb->ops->ep_offset; 2228 if (musb->ops->ep_select) 2229 musb->io.ep_select = musb->ops->ep_select; 2230 2231 if (musb->ops->fifo_mode) 2232 fifo_mode = musb->ops->fifo_mode; 2233 else 2234 fifo_mode = 4; 2235 2236 if (musb->ops->fifo_offset) 2237 musb->io.fifo_offset = musb->ops->fifo_offset; 2238 else 2239 musb->io.fifo_offset = musb_default_fifo_offset; 2240 2241 if (musb->ops->busctl_offset) 2242 musb->io.busctl_offset = musb->ops->busctl_offset; 2243 else 2244 musb->io.busctl_offset = musb_default_busctl_offset; 2245 2246 if (musb->ops->readb) 2247 musb_readb = musb->ops->readb; 2248 if (musb->ops->writeb) 2249 musb_writeb = musb->ops->writeb; 2250 if (musb->ops->readw) 2251 musb_readw = musb->ops->readw; 2252 if (musb->ops->writew) 2253 musb_writew = musb->ops->writew; 2254 if (musb->ops->readl) 2255 musb_readl = musb->ops->readl; 2256 if (musb->ops->writel) 2257 musb_writel = musb->ops->writel; 2258 2259 #ifndef CONFIG_MUSB_PIO_ONLY 2260 if (!musb->ops->dma_init || !musb->ops->dma_exit) { 2261 dev_err(dev, "DMA controller not set\n"); 2262 status = -ENODEV; 2263 goto fail2; 2264 } 2265 musb_dma_controller_create = musb->ops->dma_init; 2266 musb_dma_controller_destroy = musb->ops->dma_exit; 2267 #endif 2268 2269 if (musb->ops->read_fifo) 2270 musb->io.read_fifo = musb->ops->read_fifo; 2271 else 2272 musb->io.read_fifo = musb_default_read_fifo; 2273 2274 if (musb->ops->write_fifo) 2275 musb->io.write_fifo = musb->ops->write_fifo; 2276 else 2277 musb->io.write_fifo = musb_default_write_fifo; 2278 2279 if (!musb->xceiv->io_ops) { 2280 musb->xceiv->io_dev = musb->controller; 2281 musb->xceiv->io_priv = musb->mregs; 2282 musb->xceiv->io_ops = &musb_ulpi_access; 2283 } 2284 2285 if (musb->ops->phy_callback) 2286 musb_phy_callback = musb->ops->phy_callback; 2287 2288 /* 2289 * We need musb_read/write functions initialized for PM. 2290 * Note that at least 2430 glue needs autosuspend delay 2291 * somewhere above 300 ms for the hardware to idle properly 2292 * after disconnecting the cable in host mode. Let's use 2293 * 500 ms for some margin. 2294 */ 2295 pm_runtime_use_autosuspend(musb->controller); 2296 pm_runtime_set_autosuspend_delay(musb->controller, 500); 2297 pm_runtime_enable(musb->controller); 2298 pm_runtime_get_sync(musb->controller); 2299 2300 status = usb_phy_init(musb->xceiv); 2301 if (status < 0) 2302 goto err_usb_phy_init; 2303 2304 if (use_dma && dev->dma_mask) { 2305 musb->dma_controller = 2306 musb_dma_controller_create(musb, musb->mregs); 2307 if (IS_ERR(musb->dma_controller)) { 2308 status = PTR_ERR(musb->dma_controller); 2309 goto fail2_5; 2310 } 2311 } 2312 2313 /* be sure interrupts are disabled before connecting ISR */ 2314 musb_platform_disable(musb); 2315 musb_generic_disable(musb); 2316 2317 /* Init IRQ workqueue before request_irq */ 2318 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work); 2319 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); 2320 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); 2321 2322 /* setup musb parts of the core (especially endpoints) */ 2323 status = musb_core_init(plat->config->multipoint 2324 ? MUSB_CONTROLLER_MHDRC 2325 : MUSB_CONTROLLER_HDRC, musb); 2326 if (status < 0) 2327 goto fail3; 2328 2329 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2330 2331 /* attach to the IRQ */ 2332 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2333 dev_err(dev, "request_irq %d failed!\n", nIrq); 2334 status = -ENODEV; 2335 goto fail3; 2336 } 2337 musb->nIrq = nIrq; 2338 /* FIXME this handles wakeup irqs wrong */ 2339 if (enable_irq_wake(nIrq) == 0) { 2340 musb->irq_wake = 1; 2341 device_init_wakeup(dev, 1); 2342 } else { 2343 musb->irq_wake = 0; 2344 } 2345 2346 /* program PHY to use external vBus if required */ 2347 if (plat->extvbus) { 2348 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2349 busctl |= MUSB_ULPI_USE_EXTVBUS; 2350 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2351 } 2352 2353 if (musb->xceiv->otg->default_a) { 2354 MUSB_HST_MODE(musb); 2355 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 2356 } else { 2357 MUSB_DEV_MODE(musb); 2358 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 2359 } 2360 2361 switch (musb->port_mode) { 2362 case MUSB_PORT_MODE_HOST: 2363 status = musb_host_setup(musb, plat->power); 2364 if (status < 0) 2365 goto fail3; 2366 status = musb_platform_set_mode(musb, MUSB_HOST); 2367 break; 2368 case MUSB_PORT_MODE_GADGET: 2369 status = musb_gadget_setup(musb); 2370 if (status < 0) 2371 goto fail3; 2372 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 2373 break; 2374 case MUSB_PORT_MODE_DUAL_ROLE: 2375 status = musb_host_setup(musb, plat->power); 2376 if (status < 0) 2377 goto fail3; 2378 status = musb_gadget_setup(musb); 2379 if (status) { 2380 musb_host_cleanup(musb); 2381 goto fail3; 2382 } 2383 status = musb_platform_set_mode(musb, MUSB_OTG); 2384 break; 2385 default: 2386 dev_err(dev, "unsupported port mode %d\n", musb->port_mode); 2387 break; 2388 } 2389 2390 if (status < 0) 2391 goto fail3; 2392 2393 status = musb_init_debugfs(musb); 2394 if (status < 0) 2395 goto fail4; 2396 2397 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2398 if (status) 2399 goto fail5; 2400 2401 musb->is_initialized = 1; 2402 pm_runtime_mark_last_busy(musb->controller); 2403 pm_runtime_put_autosuspend(musb->controller); 2404 2405 return 0; 2406 2407 fail5: 2408 musb_exit_debugfs(musb); 2409 2410 fail4: 2411 musb_gadget_cleanup(musb); 2412 musb_host_cleanup(musb); 2413 2414 fail3: 2415 cancel_delayed_work_sync(&musb->irq_work); 2416 cancel_delayed_work_sync(&musb->finish_resume_work); 2417 cancel_delayed_work_sync(&musb->deassert_reset_work); 2418 if (musb->dma_controller) 2419 musb_dma_controller_destroy(musb->dma_controller); 2420 2421 fail2_5: 2422 usb_phy_shutdown(musb->xceiv); 2423 2424 err_usb_phy_init: 2425 pm_runtime_dont_use_autosuspend(musb->controller); 2426 pm_runtime_put_sync(musb->controller); 2427 pm_runtime_disable(musb->controller); 2428 2429 fail2: 2430 if (musb->irq_wake) 2431 device_init_wakeup(dev, 0); 2432 musb_platform_exit(musb); 2433 2434 fail1: 2435 if (status != -EPROBE_DEFER) 2436 dev_err(musb->controller, 2437 "%s failed with status %d\n", __func__, status); 2438 2439 musb_free(musb); 2440 2441 fail0: 2442 2443 return status; 2444 2445 } 2446 2447 /*-------------------------------------------------------------------------*/ 2448 2449 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2450 * bridge to a platform device; this driver then suffices. 2451 */ 2452 static int musb_probe(struct platform_device *pdev) 2453 { 2454 struct device *dev = &pdev->dev; 2455 int irq = platform_get_irq_byname(pdev, "mc"); 2456 struct resource *iomem; 2457 void __iomem *base; 2458 2459 if (irq <= 0) 2460 return -ENODEV; 2461 2462 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2463 base = devm_ioremap_resource(dev, iomem); 2464 if (IS_ERR(base)) 2465 return PTR_ERR(base); 2466 2467 return musb_init_controller(dev, irq, base); 2468 } 2469 2470 static int musb_remove(struct platform_device *pdev) 2471 { 2472 struct device *dev = &pdev->dev; 2473 struct musb *musb = dev_to_musb(dev); 2474 unsigned long flags; 2475 2476 /* this gets called on rmmod. 2477 * - Host mode: host may still be active 2478 * - Peripheral mode: peripheral is deactivated (or never-activated) 2479 * - OTG mode: both roles are deactivated (or never-activated) 2480 */ 2481 musb_exit_debugfs(musb); 2482 2483 cancel_delayed_work_sync(&musb->irq_work); 2484 cancel_delayed_work_sync(&musb->finish_resume_work); 2485 cancel_delayed_work_sync(&musb->deassert_reset_work); 2486 pm_runtime_get_sync(musb->controller); 2487 musb_host_cleanup(musb); 2488 musb_gadget_cleanup(musb); 2489 spin_lock_irqsave(&musb->lock, flags); 2490 musb_platform_disable(musb); 2491 musb_generic_disable(musb); 2492 spin_unlock_irqrestore(&musb->lock, flags); 2493 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2494 pm_runtime_dont_use_autosuspend(musb->controller); 2495 pm_runtime_put_sync(musb->controller); 2496 pm_runtime_disable(musb->controller); 2497 musb_platform_exit(musb); 2498 musb_phy_callback = NULL; 2499 if (musb->dma_controller) 2500 musb_dma_controller_destroy(musb->dma_controller); 2501 usb_phy_shutdown(musb->xceiv); 2502 musb_free(musb); 2503 device_init_wakeup(dev, 0); 2504 return 0; 2505 } 2506 2507 #ifdef CONFIG_PM 2508 2509 static void musb_save_context(struct musb *musb) 2510 { 2511 int i; 2512 void __iomem *musb_base = musb->mregs; 2513 void __iomem *epio; 2514 2515 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2516 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2517 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2518 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2519 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2520 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2521 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2522 2523 for (i = 0; i < musb->config->num_eps; ++i) { 2524 struct musb_hw_ep *hw_ep; 2525 2526 hw_ep = &musb->endpoints[i]; 2527 if (!hw_ep) 2528 continue; 2529 2530 epio = hw_ep->regs; 2531 if (!epio) 2532 continue; 2533 2534 musb_writeb(musb_base, MUSB_INDEX, i); 2535 musb->context.index_regs[i].txmaxp = 2536 musb_readw(epio, MUSB_TXMAXP); 2537 musb->context.index_regs[i].txcsr = 2538 musb_readw(epio, MUSB_TXCSR); 2539 musb->context.index_regs[i].rxmaxp = 2540 musb_readw(epio, MUSB_RXMAXP); 2541 musb->context.index_regs[i].rxcsr = 2542 musb_readw(epio, MUSB_RXCSR); 2543 2544 if (musb->dyn_fifo) { 2545 musb->context.index_regs[i].txfifoadd = 2546 musb_read_txfifoadd(musb_base); 2547 musb->context.index_regs[i].rxfifoadd = 2548 musb_read_rxfifoadd(musb_base); 2549 musb->context.index_regs[i].txfifosz = 2550 musb_read_txfifosz(musb_base); 2551 musb->context.index_regs[i].rxfifosz = 2552 musb_read_rxfifosz(musb_base); 2553 } 2554 2555 musb->context.index_regs[i].txtype = 2556 musb_readb(epio, MUSB_TXTYPE); 2557 musb->context.index_regs[i].txinterval = 2558 musb_readb(epio, MUSB_TXINTERVAL); 2559 musb->context.index_regs[i].rxtype = 2560 musb_readb(epio, MUSB_RXTYPE); 2561 musb->context.index_regs[i].rxinterval = 2562 musb_readb(epio, MUSB_RXINTERVAL); 2563 2564 musb->context.index_regs[i].txfunaddr = 2565 musb_read_txfunaddr(musb, i); 2566 musb->context.index_regs[i].txhubaddr = 2567 musb_read_txhubaddr(musb, i); 2568 musb->context.index_regs[i].txhubport = 2569 musb_read_txhubport(musb, i); 2570 2571 musb->context.index_regs[i].rxfunaddr = 2572 musb_read_rxfunaddr(musb, i); 2573 musb->context.index_regs[i].rxhubaddr = 2574 musb_read_rxhubaddr(musb, i); 2575 musb->context.index_regs[i].rxhubport = 2576 musb_read_rxhubport(musb, i); 2577 } 2578 } 2579 2580 static void musb_restore_context(struct musb *musb) 2581 { 2582 int i; 2583 void __iomem *musb_base = musb->mregs; 2584 void __iomem *epio; 2585 u8 power; 2586 2587 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2588 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2589 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2590 2591 /* Don't affect SUSPENDM/RESUME bits in POWER reg */ 2592 power = musb_readb(musb_base, MUSB_POWER); 2593 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; 2594 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); 2595 power |= musb->context.power; 2596 musb_writeb(musb_base, MUSB_POWER, power); 2597 2598 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); 2599 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); 2600 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2601 if (musb->context.devctl & MUSB_DEVCTL_SESSION) 2602 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2603 2604 for (i = 0; i < musb->config->num_eps; ++i) { 2605 struct musb_hw_ep *hw_ep; 2606 2607 hw_ep = &musb->endpoints[i]; 2608 if (!hw_ep) 2609 continue; 2610 2611 epio = hw_ep->regs; 2612 if (!epio) 2613 continue; 2614 2615 musb_writeb(musb_base, MUSB_INDEX, i); 2616 musb_writew(epio, MUSB_TXMAXP, 2617 musb->context.index_regs[i].txmaxp); 2618 musb_writew(epio, MUSB_TXCSR, 2619 musb->context.index_regs[i].txcsr); 2620 musb_writew(epio, MUSB_RXMAXP, 2621 musb->context.index_regs[i].rxmaxp); 2622 musb_writew(epio, MUSB_RXCSR, 2623 musb->context.index_regs[i].rxcsr); 2624 2625 if (musb->dyn_fifo) { 2626 musb_write_txfifosz(musb_base, 2627 musb->context.index_regs[i].txfifosz); 2628 musb_write_rxfifosz(musb_base, 2629 musb->context.index_regs[i].rxfifosz); 2630 musb_write_txfifoadd(musb_base, 2631 musb->context.index_regs[i].txfifoadd); 2632 musb_write_rxfifoadd(musb_base, 2633 musb->context.index_regs[i].rxfifoadd); 2634 } 2635 2636 musb_writeb(epio, MUSB_TXTYPE, 2637 musb->context.index_regs[i].txtype); 2638 musb_writeb(epio, MUSB_TXINTERVAL, 2639 musb->context.index_regs[i].txinterval); 2640 musb_writeb(epio, MUSB_RXTYPE, 2641 musb->context.index_regs[i].rxtype); 2642 musb_writeb(epio, MUSB_RXINTERVAL, 2643 2644 musb->context.index_regs[i].rxinterval); 2645 musb_write_txfunaddr(musb, i, 2646 musb->context.index_regs[i].txfunaddr); 2647 musb_write_txhubaddr(musb, i, 2648 musb->context.index_regs[i].txhubaddr); 2649 musb_write_txhubport(musb, i, 2650 musb->context.index_regs[i].txhubport); 2651 2652 musb_write_rxfunaddr(musb, i, 2653 musb->context.index_regs[i].rxfunaddr); 2654 musb_write_rxhubaddr(musb, i, 2655 musb->context.index_regs[i].rxhubaddr); 2656 musb_write_rxhubport(musb, i, 2657 musb->context.index_regs[i].rxhubport); 2658 } 2659 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2660 } 2661 2662 static int musb_suspend(struct device *dev) 2663 { 2664 struct musb *musb = dev_to_musb(dev); 2665 unsigned long flags; 2666 2667 musb_platform_disable(musb); 2668 musb_generic_disable(musb); 2669 WARN_ON(!list_empty(&musb->pending_list)); 2670 2671 spin_lock_irqsave(&musb->lock, flags); 2672 2673 if (is_peripheral_active(musb)) { 2674 /* FIXME force disconnect unless we know USB will wake 2675 * the system up quickly enough to respond ... 2676 */ 2677 } else if (is_host_active(musb)) { 2678 /* we know all the children are suspended; sometimes 2679 * they will even be wakeup-enabled. 2680 */ 2681 } 2682 2683 musb_save_context(musb); 2684 2685 spin_unlock_irqrestore(&musb->lock, flags); 2686 return 0; 2687 } 2688 2689 static int musb_resume(struct device *dev) 2690 { 2691 struct musb *musb = dev_to_musb(dev); 2692 unsigned long flags; 2693 int error; 2694 u8 devctl; 2695 u8 mask; 2696 2697 /* 2698 * For static cmos like DaVinci, register values were preserved 2699 * unless for some reason the whole soc powered down or the USB 2700 * module got reset through the PSC (vs just being disabled). 2701 * 2702 * For the DSPS glue layer though, a full register restore has to 2703 * be done. As it shouldn't harm other platforms, we do it 2704 * unconditionally. 2705 */ 2706 2707 musb_restore_context(musb); 2708 2709 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2710 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; 2711 if ((devctl & mask) != (musb->context.devctl & mask)) 2712 musb->port1_status = 0; 2713 if (musb->need_finish_resume) { 2714 musb->need_finish_resume = 0; 2715 schedule_delayed_work(&musb->finish_resume_work, 2716 msecs_to_jiffies(USB_RESUME_TIMEOUT)); 2717 } 2718 2719 /* 2720 * The USB HUB code expects the device to be in RPM_ACTIVE once it came 2721 * out of suspend 2722 */ 2723 pm_runtime_disable(dev); 2724 pm_runtime_set_active(dev); 2725 pm_runtime_enable(dev); 2726 2727 musb_start(musb); 2728 2729 spin_lock_irqsave(&musb->lock, flags); 2730 error = musb_run_resume_work(musb); 2731 if (error) 2732 dev_err(musb->controller, "resume work failed with %i\n", 2733 error); 2734 spin_unlock_irqrestore(&musb->lock, flags); 2735 2736 return 0; 2737 } 2738 2739 static int musb_runtime_suspend(struct device *dev) 2740 { 2741 struct musb *musb = dev_to_musb(dev); 2742 2743 musb_save_context(musb); 2744 musb->is_runtime_suspended = 1; 2745 2746 return 0; 2747 } 2748 2749 static int musb_runtime_resume(struct device *dev) 2750 { 2751 struct musb *musb = dev_to_musb(dev); 2752 unsigned long flags; 2753 int error; 2754 2755 /* 2756 * When pm_runtime_get_sync called for the first time in driver 2757 * init, some of the structure is still not initialized which is 2758 * used in restore function. But clock needs to be 2759 * enabled before any register access, so 2760 * pm_runtime_get_sync has to be called. 2761 * Also context restore without save does not make 2762 * any sense 2763 */ 2764 if (!musb->is_initialized) 2765 return 0; 2766 2767 musb_restore_context(musb); 2768 2769 if (musb->need_finish_resume) { 2770 musb->need_finish_resume = 0; 2771 schedule_delayed_work(&musb->finish_resume_work, 2772 msecs_to_jiffies(USB_RESUME_TIMEOUT)); 2773 } 2774 2775 spin_lock_irqsave(&musb->lock, flags); 2776 error = musb_run_resume_work(musb); 2777 if (error) 2778 dev_err(musb->controller, "resume work failed with %i\n", 2779 error); 2780 musb->is_runtime_suspended = 0; 2781 spin_unlock_irqrestore(&musb->lock, flags); 2782 2783 return 0; 2784 } 2785 2786 static const struct dev_pm_ops musb_dev_pm_ops = { 2787 .suspend = musb_suspend, 2788 .resume = musb_resume, 2789 .runtime_suspend = musb_runtime_suspend, 2790 .runtime_resume = musb_runtime_resume, 2791 }; 2792 2793 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2794 #else 2795 #define MUSB_DEV_PM_OPS NULL 2796 #endif 2797 2798 static struct platform_driver musb_driver = { 2799 .driver = { 2800 .name = (char *)musb_driver_name, 2801 .bus = &platform_bus_type, 2802 .pm = MUSB_DEV_PM_OPS, 2803 }, 2804 .probe = musb_probe, 2805 .remove = musb_remove, 2806 }; 2807 2808 module_platform_driver(musb_driver); 2809