1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/init.h> 97 #include <linux/list.h> 98 #include <linux/kobject.h> 99 #include <linux/platform_device.h> 100 #include <linux/io.h> 101 102 #ifdef CONFIG_ARM 103 #include <mach/hardware.h> 104 #include <mach/memory.h> 105 #include <asm/mach-types.h> 106 #endif 107 108 #include "musb_core.h" 109 110 111 #ifdef CONFIG_ARCH_DAVINCI 112 #include "davinci.h" 113 #endif 114 115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 116 117 118 unsigned musb_debug; 119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 121 122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 124 125 #define MUSB_VERSION "6.0" 126 127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 128 129 #define MUSB_DRIVER_NAME "musb_hdrc" 130 const char musb_driver_name[] = MUSB_DRIVER_NAME; 131 132 MODULE_DESCRIPTION(DRIVER_INFO); 133 MODULE_AUTHOR(DRIVER_AUTHOR); 134 MODULE_LICENSE("GPL"); 135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 136 137 138 /*-------------------------------------------------------------------------*/ 139 140 static inline struct musb *dev_to_musb(struct device *dev) 141 { 142 #ifdef CONFIG_USB_MUSB_HDRC_HCD 143 /* usbcore insists dev->driver_data is a "struct hcd *" */ 144 return hcd_to_musb(dev_get_drvdata(dev)); 145 #else 146 return dev_get_drvdata(dev); 147 #endif 148 } 149 150 /*-------------------------------------------------------------------------*/ 151 152 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN) 153 154 /* 155 * Load an endpoint's FIFO 156 */ 157 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 158 { 159 void __iomem *fifo = hw_ep->fifo; 160 161 prefetch((u8 *)src); 162 163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 164 'T', hw_ep->epnum, fifo, len, src); 165 166 /* we can't assume unaligned reads work */ 167 if (likely((0x01 & (unsigned long) src) == 0)) { 168 u16 index = 0; 169 170 /* best case is 32bit-aligned source address */ 171 if ((0x02 & (unsigned long) src) == 0) { 172 if (len >= 4) { 173 writesl(fifo, src + index, len >> 2); 174 index += len & ~0x03; 175 } 176 if (len & 0x02) { 177 musb_writew(fifo, 0, *(u16 *)&src[index]); 178 index += 2; 179 } 180 } else { 181 if (len >= 2) { 182 writesw(fifo, src + index, len >> 1); 183 index += len & ~0x01; 184 } 185 } 186 if (len & 0x01) 187 musb_writeb(fifo, 0, src[index]); 188 } else { 189 /* byte aligned */ 190 writesb(fifo, src, len); 191 } 192 } 193 194 /* 195 * Unload an endpoint's FIFO 196 */ 197 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 198 { 199 void __iomem *fifo = hw_ep->fifo; 200 201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 202 'R', hw_ep->epnum, fifo, len, dst); 203 204 /* we can't assume unaligned writes work */ 205 if (likely((0x01 & (unsigned long) dst) == 0)) { 206 u16 index = 0; 207 208 /* best case is 32bit-aligned destination address */ 209 if ((0x02 & (unsigned long) dst) == 0) { 210 if (len >= 4) { 211 readsl(fifo, dst, len >> 2); 212 index = len & ~0x03; 213 } 214 if (len & 0x02) { 215 *(u16 *)&dst[index] = musb_readw(fifo, 0); 216 index += 2; 217 } 218 } else { 219 if (len >= 2) { 220 readsw(fifo, dst, len >> 1); 221 index = len & ~0x01; 222 } 223 } 224 if (len & 0x01) 225 dst[index] = musb_readb(fifo, 0); 226 } else { 227 /* byte aligned */ 228 readsb(fifo, dst, len); 229 } 230 } 231 232 #endif /* normal PIO */ 233 234 235 /*-------------------------------------------------------------------------*/ 236 237 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 238 static const u8 musb_test_packet[53] = { 239 /* implicit SYNC then DATA0 to start */ 240 241 /* JKJKJKJK x9 */ 242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 243 /* JJKKJJKK x8 */ 244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 245 /* JJJJKKKK x8 */ 246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 247 /* JJJJJJJKKKKKKK x8 */ 248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 249 /* JJJJJJJK x8 */ 250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 251 /* JKKKKKKK x10, JK */ 252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 253 254 /* implicit CRC16 then EOP to end */ 255 }; 256 257 void musb_load_testpacket(struct musb *musb) 258 { 259 void __iomem *regs = musb->endpoints[0].regs; 260 261 musb_ep_select(musb->mregs, 0); 262 musb_write_fifo(musb->control_ep, 263 sizeof(musb_test_packet), musb_test_packet); 264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 265 } 266 267 /*-------------------------------------------------------------------------*/ 268 269 const char *otg_state_string(struct musb *musb) 270 { 271 switch (musb->xceiv->state) { 272 case OTG_STATE_A_IDLE: return "a_idle"; 273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 275 case OTG_STATE_A_HOST: return "a_host"; 276 case OTG_STATE_A_SUSPEND: return "a_suspend"; 277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 280 case OTG_STATE_B_IDLE: return "b_idle"; 281 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 284 case OTG_STATE_B_HOST: return "b_host"; 285 default: return "UNDEFINED"; 286 } 287 } 288 289 #ifdef CONFIG_USB_MUSB_OTG 290 291 /* 292 * Handles OTG hnp timeouts, such as b_ase0_brst 293 */ 294 void musb_otg_timer_func(unsigned long data) 295 { 296 struct musb *musb = (struct musb *)data; 297 unsigned long flags; 298 299 spin_lock_irqsave(&musb->lock, flags); 300 switch (musb->xceiv->state) { 301 case OTG_STATE_B_WAIT_ACON: 302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 303 musb_g_disconnect(musb); 304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 305 musb->is_active = 0; 306 break; 307 case OTG_STATE_A_SUSPEND: 308 case OTG_STATE_A_WAIT_BCON: 309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 310 musb_set_vbus(musb, 0); 311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 312 break; 313 default: 314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 315 } 316 musb->ignore_disconnect = 0; 317 spin_unlock_irqrestore(&musb->lock, flags); 318 } 319 320 /* 321 * Stops the HNP transition. Caller must take care of locking. 322 */ 323 void musb_hnp_stop(struct musb *musb) 324 { 325 struct usb_hcd *hcd = musb_to_hcd(musb); 326 void __iomem *mbase = musb->mregs; 327 u8 reg; 328 329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 330 331 switch (musb->xceiv->state) { 332 case OTG_STATE_A_PERIPHERAL: 333 musb_g_disconnect(musb); 334 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 335 break; 336 case OTG_STATE_B_HOST: 337 DBG(1, "HNP: Disabling HR\n"); 338 hcd->self.is_b_host = 0; 339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 340 MUSB_DEV_MODE(musb); 341 reg = musb_readb(mbase, MUSB_POWER); 342 reg |= MUSB_POWER_SUSPENDM; 343 musb_writeb(mbase, MUSB_POWER, reg); 344 /* REVISIT: Start SESSION_REQUEST here? */ 345 break; 346 default: 347 DBG(1, "HNP: Stopping in unknown state %s\n", 348 otg_state_string(musb)); 349 } 350 351 /* 352 * When returning to A state after HNP, avoid hub_port_rebounce(), 353 * which cause occasional OPT A "Did not receive reset after connect" 354 * errors. 355 */ 356 musb->port1_status &= 357 ~(1 << USB_PORT_FEAT_C_CONNECTION); 358 } 359 360 #endif 361 362 /* 363 * Interrupt Service Routine to record USB "global" interrupts. 364 * Since these do not happen often and signify things of 365 * paramount importance, it seems OK to check them individually; 366 * the order of the tests is specified in the manual 367 * 368 * @param musb instance pointer 369 * @param int_usb register contents 370 * @param devctl 371 * @param power 372 */ 373 374 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ 375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ 376 | MUSB_INTR_RESET) 377 378 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 379 u8 devctl, u8 power) 380 { 381 irqreturn_t handled = IRQ_NONE; 382 void __iomem *mbase = musb->mregs; 383 384 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 385 int_usb); 386 387 /* in host mode, the peripheral may issue remote wakeup. 388 * in peripheral mode, the host may resume the link. 389 * spurious RESUME irqs happen too, paired with SUSPEND. 390 */ 391 if (int_usb & MUSB_INTR_RESUME) { 392 handled = IRQ_HANDLED; 393 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 394 395 if (devctl & MUSB_DEVCTL_HM) { 396 #ifdef CONFIG_USB_MUSB_HDRC_HCD 397 switch (musb->xceiv->state) { 398 case OTG_STATE_A_SUSPEND: 399 /* remote wakeup? later, GetPortStatus 400 * will stop RESUME signaling 401 */ 402 403 if (power & MUSB_POWER_SUSPENDM) { 404 /* spurious */ 405 musb->int_usb &= ~MUSB_INTR_SUSPEND; 406 DBG(2, "Spurious SUSPENDM\n"); 407 break; 408 } 409 410 power &= ~MUSB_POWER_SUSPENDM; 411 musb_writeb(mbase, MUSB_POWER, 412 power | MUSB_POWER_RESUME); 413 414 musb->port1_status |= 415 (USB_PORT_STAT_C_SUSPEND << 16) 416 | MUSB_PORT_STAT_RESUME; 417 musb->rh_timer = jiffies 418 + msecs_to_jiffies(20); 419 420 musb->xceiv->state = OTG_STATE_A_HOST; 421 musb->is_active = 1; 422 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 423 break; 424 case OTG_STATE_B_WAIT_ACON: 425 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 426 musb->is_active = 1; 427 MUSB_DEV_MODE(musb); 428 break; 429 default: 430 WARNING("bogus %s RESUME (%s)\n", 431 "host", 432 otg_state_string(musb)); 433 } 434 #endif 435 } else { 436 switch (musb->xceiv->state) { 437 #ifdef CONFIG_USB_MUSB_HDRC_HCD 438 case OTG_STATE_A_SUSPEND: 439 /* possibly DISCONNECT is upcoming */ 440 musb->xceiv->state = OTG_STATE_A_HOST; 441 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 442 break; 443 #endif 444 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 445 case OTG_STATE_B_WAIT_ACON: 446 case OTG_STATE_B_PERIPHERAL: 447 /* disconnect while suspended? we may 448 * not get a disconnect irq... 449 */ 450 if ((devctl & MUSB_DEVCTL_VBUS) 451 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 452 ) { 453 musb->int_usb |= MUSB_INTR_DISCONNECT; 454 musb->int_usb &= ~MUSB_INTR_SUSPEND; 455 break; 456 } 457 musb_g_resume(musb); 458 break; 459 case OTG_STATE_B_IDLE: 460 musb->int_usb &= ~MUSB_INTR_SUSPEND; 461 break; 462 #endif 463 default: 464 WARNING("bogus %s RESUME (%s)\n", 465 "peripheral", 466 otg_state_string(musb)); 467 } 468 } 469 } 470 471 #ifdef CONFIG_USB_MUSB_HDRC_HCD 472 /* see manual for the order of the tests */ 473 if (int_usb & MUSB_INTR_SESSREQ) { 474 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 475 476 /* IRQ arrives from ID pin sense or (later, if VBUS power 477 * is removed) SRP. responses are time critical: 478 * - turn on VBUS (with silicon-specific mechanism) 479 * - go through A_WAIT_VRISE 480 * - ... to A_WAIT_BCON. 481 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 482 */ 483 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 484 musb->ep0_stage = MUSB_EP0_START; 485 musb->xceiv->state = OTG_STATE_A_IDLE; 486 MUSB_HST_MODE(musb); 487 musb_set_vbus(musb, 1); 488 489 handled = IRQ_HANDLED; 490 } 491 492 if (int_usb & MUSB_INTR_VBUSERROR) { 493 int ignore = 0; 494 495 /* During connection as an A-Device, we may see a short 496 * current spikes causing voltage drop, because of cable 497 * and peripheral capacitance combined with vbus draw. 498 * (So: less common with truly self-powered devices, where 499 * vbus doesn't act like a power supply.) 500 * 501 * Such spikes are short; usually less than ~500 usec, max 502 * of ~2 msec. That is, they're not sustained overcurrent 503 * errors, though they're reported using VBUSERROR irqs. 504 * 505 * Workarounds: (a) hardware: use self powered devices. 506 * (b) software: ignore non-repeated VBUS errors. 507 * 508 * REVISIT: do delays from lots of DEBUG_KERNEL checks 509 * make trouble here, keeping VBUS < 4.4V ? 510 */ 511 switch (musb->xceiv->state) { 512 case OTG_STATE_A_HOST: 513 /* recovery is dicey once we've gotten past the 514 * initial stages of enumeration, but if VBUS 515 * stayed ok at the other end of the link, and 516 * another reset is due (at least for high speed, 517 * to redo the chirp etc), it might work OK... 518 */ 519 case OTG_STATE_A_WAIT_BCON: 520 case OTG_STATE_A_WAIT_VRISE: 521 if (musb->vbuserr_retry) { 522 musb->vbuserr_retry--; 523 ignore = 1; 524 devctl |= MUSB_DEVCTL_SESSION; 525 musb_writeb(mbase, MUSB_DEVCTL, devctl); 526 } else { 527 musb->port1_status |= 528 (1 << USB_PORT_FEAT_OVER_CURRENT) 529 | (1 << USB_PORT_FEAT_C_OVER_CURRENT); 530 } 531 break; 532 default: 533 break; 534 } 535 536 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 537 otg_state_string(musb), 538 devctl, 539 ({ char *s; 540 switch (devctl & MUSB_DEVCTL_VBUS) { 541 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 542 s = "<SessEnd"; break; 543 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 544 s = "<AValid"; break; 545 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 546 s = "<VBusValid"; break; 547 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 548 default: 549 s = "VALID"; break; 550 }; s; }), 551 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 552 musb->port1_status); 553 554 /* go through A_WAIT_VFALL then start a new session */ 555 if (!ignore) 556 musb_set_vbus(musb, 0); 557 handled = IRQ_HANDLED; 558 } 559 560 if (int_usb & MUSB_INTR_CONNECT) { 561 struct usb_hcd *hcd = musb_to_hcd(musb); 562 563 handled = IRQ_HANDLED; 564 musb->is_active = 1; 565 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 566 567 musb->ep0_stage = MUSB_EP0_START; 568 569 #ifdef CONFIG_USB_MUSB_OTG 570 /* flush endpoints when transitioning from Device Mode */ 571 if (is_peripheral_active(musb)) { 572 /* REVISIT HNP; just force disconnect */ 573 } 574 musb_writew(mbase, MUSB_INTRTXE, musb->epmask); 575 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); 576 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); 577 #endif 578 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 579 |USB_PORT_STAT_HIGH_SPEED 580 |USB_PORT_STAT_ENABLE 581 ); 582 musb->port1_status |= USB_PORT_STAT_CONNECTION 583 |(USB_PORT_STAT_C_CONNECTION << 16); 584 585 /* high vs full speed is just a guess until after reset */ 586 if (devctl & MUSB_DEVCTL_LSDEV) 587 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 588 589 /* indicate new connection to OTG machine */ 590 switch (musb->xceiv->state) { 591 case OTG_STATE_B_PERIPHERAL: 592 if (int_usb & MUSB_INTR_SUSPEND) { 593 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 594 int_usb &= ~MUSB_INTR_SUSPEND; 595 goto b_host; 596 } else 597 DBG(1, "CONNECT as b_peripheral???\n"); 598 break; 599 case OTG_STATE_B_WAIT_ACON: 600 DBG(1, "HNP: CONNECT, now b_host\n"); 601 b_host: 602 musb->xceiv->state = OTG_STATE_B_HOST; 603 hcd->self.is_b_host = 1; 604 musb->ignore_disconnect = 0; 605 del_timer(&musb->otg_timer); 606 break; 607 default: 608 if ((devctl & MUSB_DEVCTL_VBUS) 609 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 610 musb->xceiv->state = OTG_STATE_A_HOST; 611 hcd->self.is_b_host = 0; 612 } 613 break; 614 } 615 616 /* poke the root hub */ 617 MUSB_HST_MODE(musb); 618 if (hcd->status_urb) 619 usb_hcd_poll_rh_status(hcd); 620 else 621 usb_hcd_resume_root_hub(hcd); 622 623 DBG(1, "CONNECT (%s) devctl %02x\n", 624 otg_state_string(musb), devctl); 625 } 626 #endif /* CONFIG_USB_MUSB_HDRC_HCD */ 627 628 /* mentor saves a bit: bus reset and babble share the same irq. 629 * only host sees babble; only peripheral sees bus reset. 630 */ 631 if (int_usb & MUSB_INTR_RESET) { 632 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 633 /* 634 * Looks like non-HS BABBLE can be ignored, but 635 * HS BABBLE is an error condition. For HS the solution 636 * is to avoid babble in the first place and fix what 637 * caused BABBLE. When HS BABBLE happens we can only 638 * stop the session. 639 */ 640 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 641 DBG(1, "BABBLE devctl: %02x\n", devctl); 642 else { 643 ERR("Stopping host session -- babble\n"); 644 musb_writeb(mbase, MUSB_DEVCTL, 0); 645 } 646 } else if (is_peripheral_capable()) { 647 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 648 switch (musb->xceiv->state) { 649 #ifdef CONFIG_USB_OTG 650 case OTG_STATE_A_SUSPEND: 651 /* We need to ignore disconnect on suspend 652 * otherwise tusb 2.0 won't reconnect after a 653 * power cycle, which breaks otg compliance. 654 */ 655 musb->ignore_disconnect = 1; 656 musb_g_reset(musb); 657 /* FALLTHROUGH */ 658 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 659 /* never use invalid T(a_wait_bcon) */ 660 DBG(1, "HNP: in %s, %d msec timeout\n", 661 otg_state_string(musb), 662 TA_WAIT_BCON(musb)); 663 mod_timer(&musb->otg_timer, jiffies 664 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 665 break; 666 case OTG_STATE_A_PERIPHERAL: 667 musb->ignore_disconnect = 0; 668 del_timer(&musb->otg_timer); 669 musb_g_reset(musb); 670 break; 671 case OTG_STATE_B_WAIT_ACON: 672 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 673 otg_state_string(musb)); 674 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 675 musb_g_reset(musb); 676 break; 677 #endif 678 case OTG_STATE_B_IDLE: 679 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 680 /* FALLTHROUGH */ 681 case OTG_STATE_B_PERIPHERAL: 682 musb_g_reset(musb); 683 break; 684 default: 685 DBG(1, "Unhandled BUS RESET as %s\n", 686 otg_state_string(musb)); 687 } 688 } 689 690 handled = IRQ_HANDLED; 691 } 692 schedule_work(&musb->irq_work); 693 694 return handled; 695 } 696 697 /* 698 * Interrupt Service Routine to record USB "global" interrupts. 699 * Since these do not happen often and signify things of 700 * paramount importance, it seems OK to check them individually; 701 * the order of the tests is specified in the manual 702 * 703 * @param musb instance pointer 704 * @param int_usb register contents 705 * @param devctl 706 * @param power 707 */ 708 static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb, 709 u8 devctl, u8 power) 710 { 711 irqreturn_t handled = IRQ_NONE; 712 713 #if 0 714 /* REVISIT ... this would be for multiplexing periodic endpoints, or 715 * supporting transfer phasing to prevent exceeding ISO bandwidth 716 * limits of a given frame or microframe. 717 * 718 * It's not needed for peripheral side, which dedicates endpoints; 719 * though it _might_ use SOF irqs for other purposes. 720 * 721 * And it's not currently needed for host side, which also dedicates 722 * endpoints, relies on TX/RX interval registers, and isn't claimed 723 * to support ISO transfers yet. 724 */ 725 if (int_usb & MUSB_INTR_SOF) { 726 void __iomem *mbase = musb->mregs; 727 struct musb_hw_ep *ep; 728 u8 epnum; 729 u16 frame; 730 731 DBG(6, "START_OF_FRAME\n"); 732 handled = IRQ_HANDLED; 733 734 /* start any periodic Tx transfers waiting for current frame */ 735 frame = musb_readw(mbase, MUSB_FRAME); 736 ep = musb->endpoints; 737 for (epnum = 1; (epnum < musb->nr_endpoints) 738 && (musb->epmask >= (1 << epnum)); 739 epnum++, ep++) { 740 /* 741 * FIXME handle framecounter wraps (12 bits) 742 * eliminate duplicated StartUrb logic 743 */ 744 if (ep->dwWaitFrame >= frame) { 745 ep->dwWaitFrame = 0; 746 pr_debug("SOF --> periodic TX%s on %d\n", 747 ep->tx_channel ? " DMA" : "", 748 epnum); 749 if (!ep->tx_channel) 750 musb_h_tx_start(musb, epnum); 751 else 752 cppi_hostdma_start(musb, epnum); 753 } 754 } /* end of for loop */ 755 } 756 #endif 757 758 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 759 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 760 otg_state_string(musb), 761 MUSB_MODE(musb), devctl); 762 handled = IRQ_HANDLED; 763 764 switch (musb->xceiv->state) { 765 #ifdef CONFIG_USB_MUSB_HDRC_HCD 766 case OTG_STATE_A_HOST: 767 case OTG_STATE_A_SUSPEND: 768 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 769 musb_root_disconnect(musb); 770 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 771 musb_platform_try_idle(musb, jiffies 772 + msecs_to_jiffies(musb->a_wait_bcon)); 773 break; 774 #endif /* HOST */ 775 #ifdef CONFIG_USB_MUSB_OTG 776 case OTG_STATE_B_HOST: 777 /* REVISIT this behaves for "real disconnect" 778 * cases; make sure the other transitions from 779 * from B_HOST act right too. The B_HOST code 780 * in hnp_stop() is currently not used... 781 */ 782 musb_root_disconnect(musb); 783 musb_to_hcd(musb)->self.is_b_host = 0; 784 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 785 MUSB_DEV_MODE(musb); 786 musb_g_disconnect(musb); 787 break; 788 case OTG_STATE_A_PERIPHERAL: 789 musb_hnp_stop(musb); 790 musb_root_disconnect(musb); 791 /* FALLTHROUGH */ 792 case OTG_STATE_B_WAIT_ACON: 793 /* FALLTHROUGH */ 794 #endif /* OTG */ 795 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 796 case OTG_STATE_B_PERIPHERAL: 797 case OTG_STATE_B_IDLE: 798 musb_g_disconnect(musb); 799 break; 800 #endif /* GADGET */ 801 default: 802 WARNING("unhandled DISCONNECT transition (%s)\n", 803 otg_state_string(musb)); 804 break; 805 } 806 807 schedule_work(&musb->irq_work); 808 } 809 810 if (int_usb & MUSB_INTR_SUSPEND) { 811 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 812 otg_state_string(musb), devctl, power); 813 handled = IRQ_HANDLED; 814 815 switch (musb->xceiv->state) { 816 #ifdef CONFIG_USB_MUSB_OTG 817 case OTG_STATE_A_PERIPHERAL: 818 /* We also come here if the cable is removed, since 819 * this silicon doesn't report ID-no-longer-grounded. 820 * 821 * We depend on T(a_wait_bcon) to shut us down, and 822 * hope users don't do anything dicey during this 823 * undesired detour through A_WAIT_BCON. 824 */ 825 musb_hnp_stop(musb); 826 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 827 musb_root_disconnect(musb); 828 musb_platform_try_idle(musb, jiffies 829 + msecs_to_jiffies(musb->a_wait_bcon 830 ? : OTG_TIME_A_WAIT_BCON)); 831 break; 832 #endif 833 case OTG_STATE_B_PERIPHERAL: 834 musb_g_suspend(musb); 835 musb->is_active = is_otg_enabled(musb) 836 && musb->xceiv->gadget->b_hnp_enable; 837 if (musb->is_active) { 838 #ifdef CONFIG_USB_MUSB_OTG 839 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 840 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 841 mod_timer(&musb->otg_timer, jiffies 842 + msecs_to_jiffies( 843 OTG_TIME_B_ASE0_BRST)); 844 #endif 845 } 846 break; 847 case OTG_STATE_A_WAIT_BCON: 848 if (musb->a_wait_bcon != 0) 849 musb_platform_try_idle(musb, jiffies 850 + msecs_to_jiffies(musb->a_wait_bcon)); 851 break; 852 case OTG_STATE_A_HOST: 853 musb->xceiv->state = OTG_STATE_A_SUSPEND; 854 musb->is_active = is_otg_enabled(musb) 855 && musb->xceiv->host->b_hnp_enable; 856 break; 857 case OTG_STATE_B_HOST: 858 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 859 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 860 break; 861 default: 862 /* "should not happen" */ 863 musb->is_active = 0; 864 break; 865 } 866 schedule_work(&musb->irq_work); 867 } 868 869 870 return handled; 871 } 872 873 /*-------------------------------------------------------------------------*/ 874 875 /* 876 * Program the HDRC to start (enable interrupts, dma, etc.). 877 */ 878 void musb_start(struct musb *musb) 879 { 880 void __iomem *regs = musb->mregs; 881 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 882 883 DBG(2, "<== devctl %02x\n", devctl); 884 885 /* Set INT enable registers, enable interrupts */ 886 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 887 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 888 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 889 890 musb_writeb(regs, MUSB_TESTMODE, 0); 891 892 /* put into basic highspeed mode and start session */ 893 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 894 | MUSB_POWER_SOFTCONN 895 | MUSB_POWER_HSENAB 896 /* ENSUSPEND wedges tusb */ 897 /* | MUSB_POWER_ENSUSPEND */ 898 ); 899 900 musb->is_active = 0; 901 devctl = musb_readb(regs, MUSB_DEVCTL); 902 devctl &= ~MUSB_DEVCTL_SESSION; 903 904 if (is_otg_enabled(musb)) { 905 /* session started after: 906 * (a) ID-grounded irq, host mode; 907 * (b) vbus present/connect IRQ, peripheral mode; 908 * (c) peripheral initiates, using SRP 909 */ 910 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 911 musb->is_active = 1; 912 else 913 devctl |= MUSB_DEVCTL_SESSION; 914 915 } else if (is_host_enabled(musb)) { 916 /* assume ID pin is hard-wired to ground */ 917 devctl |= MUSB_DEVCTL_SESSION; 918 919 } else /* peripheral is enabled */ { 920 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 921 musb->is_active = 1; 922 } 923 musb_platform_enable(musb); 924 musb_writeb(regs, MUSB_DEVCTL, devctl); 925 } 926 927 928 static void musb_generic_disable(struct musb *musb) 929 { 930 void __iomem *mbase = musb->mregs; 931 u16 temp; 932 933 /* disable interrupts */ 934 musb_writeb(mbase, MUSB_INTRUSBE, 0); 935 musb_writew(mbase, MUSB_INTRTXE, 0); 936 musb_writew(mbase, MUSB_INTRRXE, 0); 937 938 /* off */ 939 musb_writeb(mbase, MUSB_DEVCTL, 0); 940 941 /* flush pending interrupts */ 942 temp = musb_readb(mbase, MUSB_INTRUSB); 943 temp = musb_readw(mbase, MUSB_INTRTX); 944 temp = musb_readw(mbase, MUSB_INTRRX); 945 946 } 947 948 /* 949 * Make the HDRC stop (disable interrupts, etc.); 950 * reversible by musb_start 951 * called on gadget driver unregister 952 * with controller locked, irqs blocked 953 * acts as a NOP unless some role activated the hardware 954 */ 955 void musb_stop(struct musb *musb) 956 { 957 /* stop IRQs, timers, ... */ 958 musb_platform_disable(musb); 959 musb_generic_disable(musb); 960 DBG(3, "HDRC disabled\n"); 961 962 /* FIXME 963 * - mark host and/or peripheral drivers unusable/inactive 964 * - disable DMA (and enable it in HdrcStart) 965 * - make sure we can musb_start() after musb_stop(); with 966 * OTG mode, gadget driver module rmmod/modprobe cycles that 967 * - ... 968 */ 969 musb_platform_try_idle(musb, 0); 970 } 971 972 static void musb_shutdown(struct platform_device *pdev) 973 { 974 struct musb *musb = dev_to_musb(&pdev->dev); 975 unsigned long flags; 976 977 spin_lock_irqsave(&musb->lock, flags); 978 musb_platform_disable(musb); 979 musb_generic_disable(musb); 980 if (musb->clock) { 981 clk_put(musb->clock); 982 musb->clock = NULL; 983 } 984 spin_unlock_irqrestore(&musb->lock, flags); 985 986 /* FIXME power down */ 987 } 988 989 990 /*-------------------------------------------------------------------------*/ 991 992 /* 993 * The silicon either has hard-wired endpoint configurations, or else 994 * "dynamic fifo" sizing. The driver has support for both, though at this 995 * writing only the dynamic sizing is very well tested. Since we switched 996 * away from compile-time hardware parameters, we can no longer rely on 997 * dead code elimination to leave only the relevant one in the object file. 998 * 999 * We don't currently use dynamic fifo setup capability to do anything 1000 * more than selecting one of a bunch of predefined configurations. 1001 */ 1002 #if defined(CONFIG_USB_TUSB6010) || \ 1003 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) 1004 static ushort __initdata fifo_mode = 4; 1005 #else 1006 static ushort __initdata fifo_mode = 2; 1007 #endif 1008 1009 /* "modprobe ... fifo_mode=1" etc */ 1010 module_param(fifo_mode, ushort, 0); 1011 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1012 1013 1014 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed)); 1015 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed)); 1016 1017 struct fifo_cfg { 1018 u8 hw_ep_num; 1019 enum fifo_style style; 1020 enum buf_mode mode; 1021 u16 maxpacket; 1022 }; 1023 1024 /* 1025 * tables defining fifo_mode values. define more if you like. 1026 * for host side, make sure both halves of ep1 are set up. 1027 */ 1028 1029 /* mode 0 - fits in 2KB */ 1030 static struct fifo_cfg __initdata mode_0_cfg[] = { 1031 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1032 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1033 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1034 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1035 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1036 }; 1037 1038 /* mode 1 - fits in 4KB */ 1039 static struct fifo_cfg __initdata mode_1_cfg[] = { 1040 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1041 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1042 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1043 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1044 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1045 }; 1046 1047 /* mode 2 - fits in 4KB */ 1048 static struct fifo_cfg __initdata mode_2_cfg[] = { 1049 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1050 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1051 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1052 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1053 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1054 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1055 }; 1056 1057 /* mode 3 - fits in 4KB */ 1058 static struct fifo_cfg __initdata mode_3_cfg[] = { 1059 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1060 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1061 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1062 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1063 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1064 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1065 }; 1066 1067 /* mode 4 - fits in 16KB */ 1068 static struct fifo_cfg __initdata mode_4_cfg[] = { 1069 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1070 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1071 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1072 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1073 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1074 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1075 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1076 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1077 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1078 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1079 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1080 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1081 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1082 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1083 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1084 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1085 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1086 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1087 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1088 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1089 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1090 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1091 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1092 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1093 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1094 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1095 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1096 }; 1097 1098 1099 /* 1100 * configure a fifo; for non-shared endpoints, this may be called 1101 * once for a tx fifo and once for an rx fifo. 1102 * 1103 * returns negative errno or offset for next fifo. 1104 */ 1105 static int __init 1106 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1107 const struct fifo_cfg *cfg, u16 offset) 1108 { 1109 void __iomem *mbase = musb->mregs; 1110 int size = 0; 1111 u16 maxpacket = cfg->maxpacket; 1112 u16 c_off = offset >> 3; 1113 u8 c_size; 1114 1115 /* expect hw_ep has already been zero-initialized */ 1116 1117 size = ffs(max(maxpacket, (u16) 8)) - 1; 1118 maxpacket = 1 << size; 1119 1120 c_size = size - 3; 1121 if (cfg->mode == BUF_DOUBLE) { 1122 if ((offset + (maxpacket << 1)) > 1123 (1 << (musb->config->ram_bits + 2))) 1124 return -EMSGSIZE; 1125 c_size |= MUSB_FIFOSZ_DPB; 1126 } else { 1127 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1128 return -EMSGSIZE; 1129 } 1130 1131 /* configure the FIFO */ 1132 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1133 1134 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1135 /* EP0 reserved endpoint for control, bidirectional; 1136 * EP1 reserved for bulk, two unidirection halves. 1137 */ 1138 if (hw_ep->epnum == 1) 1139 musb->bulk_ep = hw_ep; 1140 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1141 #endif 1142 switch (cfg->style) { 1143 case FIFO_TX: 1144 musb_write_txfifosz(mbase, c_size); 1145 musb_write_txfifoadd(mbase, c_off); 1146 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1147 hw_ep->max_packet_sz_tx = maxpacket; 1148 break; 1149 case FIFO_RX: 1150 musb_write_rxfifosz(mbase, c_size); 1151 musb_write_rxfifoadd(mbase, c_off); 1152 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1153 hw_ep->max_packet_sz_rx = maxpacket; 1154 break; 1155 case FIFO_RXTX: 1156 musb_write_txfifosz(mbase, c_size); 1157 musb_write_txfifoadd(mbase, c_off); 1158 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1159 hw_ep->max_packet_sz_rx = maxpacket; 1160 1161 musb_write_rxfifosz(mbase, c_size); 1162 musb_write_rxfifoadd(mbase, c_off); 1163 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1164 hw_ep->max_packet_sz_tx = maxpacket; 1165 1166 hw_ep->is_shared_fifo = true; 1167 break; 1168 } 1169 1170 /* NOTE rx and tx endpoint irqs aren't managed separately, 1171 * which happens to be ok 1172 */ 1173 musb->epmask |= (1 << hw_ep->epnum); 1174 1175 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1176 } 1177 1178 static struct fifo_cfg __initdata ep0_cfg = { 1179 .style = FIFO_RXTX, .maxpacket = 64, 1180 }; 1181 1182 static int __init ep_config_from_table(struct musb *musb) 1183 { 1184 const struct fifo_cfg *cfg; 1185 unsigned i, n; 1186 int offset; 1187 struct musb_hw_ep *hw_ep = musb->endpoints; 1188 1189 switch (fifo_mode) { 1190 default: 1191 fifo_mode = 0; 1192 /* FALLTHROUGH */ 1193 case 0: 1194 cfg = mode_0_cfg; 1195 n = ARRAY_SIZE(mode_0_cfg); 1196 break; 1197 case 1: 1198 cfg = mode_1_cfg; 1199 n = ARRAY_SIZE(mode_1_cfg); 1200 break; 1201 case 2: 1202 cfg = mode_2_cfg; 1203 n = ARRAY_SIZE(mode_2_cfg); 1204 break; 1205 case 3: 1206 cfg = mode_3_cfg; 1207 n = ARRAY_SIZE(mode_3_cfg); 1208 break; 1209 case 4: 1210 cfg = mode_4_cfg; 1211 n = ARRAY_SIZE(mode_4_cfg); 1212 break; 1213 } 1214 1215 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1216 musb_driver_name, fifo_mode); 1217 1218 1219 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1220 /* assert(offset > 0) */ 1221 1222 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1223 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1224 */ 1225 1226 for (i = 0; i < n; i++) { 1227 u8 epn = cfg->hw_ep_num; 1228 1229 if (epn >= musb->config->num_eps) { 1230 pr_debug("%s: invalid ep %d\n", 1231 musb_driver_name, epn); 1232 return -EINVAL; 1233 } 1234 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1235 if (offset < 0) { 1236 pr_debug("%s: mem overrun, ep %d\n", 1237 musb_driver_name, epn); 1238 return -EINVAL; 1239 } 1240 epn++; 1241 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1242 } 1243 1244 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1245 musb_driver_name, 1246 n + 1, musb->config->num_eps * 2 - 1, 1247 offset, (1 << (musb->config->ram_bits + 2))); 1248 1249 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1250 if (!musb->bulk_ep) { 1251 pr_debug("%s: missing bulk\n", musb_driver_name); 1252 return -EINVAL; 1253 } 1254 #endif 1255 1256 return 0; 1257 } 1258 1259 1260 /* 1261 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1262 * @param musb the controller 1263 */ 1264 static int __init ep_config_from_hw(struct musb *musb) 1265 { 1266 u8 epnum = 0; 1267 struct musb_hw_ep *hw_ep; 1268 void *mbase = musb->mregs; 1269 int ret = 0; 1270 1271 DBG(2, "<== static silicon ep config\n"); 1272 1273 /* FIXME pick up ep0 maxpacket size */ 1274 1275 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1276 musb_ep_select(mbase, epnum); 1277 hw_ep = musb->endpoints + epnum; 1278 1279 ret = musb_read_fifosize(musb, hw_ep, epnum); 1280 if (ret < 0) 1281 break; 1282 1283 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1284 1285 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1286 /* pick an RX/TX endpoint for bulk */ 1287 if (hw_ep->max_packet_sz_tx < 512 1288 || hw_ep->max_packet_sz_rx < 512) 1289 continue; 1290 1291 /* REVISIT: this algorithm is lazy, we should at least 1292 * try to pick a double buffered endpoint. 1293 */ 1294 if (musb->bulk_ep) 1295 continue; 1296 musb->bulk_ep = hw_ep; 1297 #endif 1298 } 1299 1300 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1301 if (!musb->bulk_ep) { 1302 pr_debug("%s: missing bulk\n", musb_driver_name); 1303 return -EINVAL; 1304 } 1305 #endif 1306 1307 return 0; 1308 } 1309 1310 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1311 1312 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1313 * configure endpoints, or take their config from silicon 1314 */ 1315 static int __init musb_core_init(u16 musb_type, struct musb *musb) 1316 { 1317 #ifdef MUSB_AHB_ID 1318 u32 data; 1319 #endif 1320 u8 reg; 1321 char *type; 1322 u16 hwvers, rev_major, rev_minor; 1323 char aInfo[78], aRevision[32], aDate[12]; 1324 void __iomem *mbase = musb->mregs; 1325 int status = 0; 1326 int i; 1327 1328 /* log core options (read using indexed model) */ 1329 reg = musb_read_configdata(mbase); 1330 1331 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1332 if (reg & MUSB_CONFIGDATA_DYNFIFO) 1333 strcat(aInfo, ", dyn FIFOs"); 1334 if (reg & MUSB_CONFIGDATA_MPRXE) { 1335 strcat(aInfo, ", bulk combine"); 1336 #ifdef C_MP_RX 1337 musb->bulk_combine = true; 1338 #else 1339 strcat(aInfo, " (X)"); /* no driver support */ 1340 #endif 1341 } 1342 if (reg & MUSB_CONFIGDATA_MPTXE) { 1343 strcat(aInfo, ", bulk split"); 1344 #ifdef C_MP_TX 1345 musb->bulk_split = true; 1346 #else 1347 strcat(aInfo, " (X)"); /* no driver support */ 1348 #endif 1349 } 1350 if (reg & MUSB_CONFIGDATA_HBRXE) { 1351 strcat(aInfo, ", HB-ISO Rx"); 1352 musb->hb_iso_rx = true; 1353 } 1354 if (reg & MUSB_CONFIGDATA_HBTXE) { 1355 strcat(aInfo, ", HB-ISO Tx"); 1356 musb->hb_iso_tx = true; 1357 } 1358 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1359 strcat(aInfo, ", SoftConn"); 1360 1361 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1362 musb_driver_name, reg, aInfo); 1363 1364 #ifdef MUSB_AHB_ID 1365 data = musb_readl(mbase, 0x404); 1366 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff), 1367 (data >> 16) & 0xff, (data >> 24) & 0xff); 1368 /* FIXME ID2 and ID3 are unused */ 1369 data = musb_readl(mbase, 0x408); 1370 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data); 1371 data = musb_readl(mbase, 0x40c); 1372 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data); 1373 reg = musb_readb(mbase, 0x400); 1374 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC; 1375 #else 1376 aDate[0] = 0; 1377 #endif 1378 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1379 musb->is_multipoint = 1; 1380 type = "M"; 1381 } else { 1382 musb->is_multipoint = 0; 1383 type = ""; 1384 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1385 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1386 printk(KERN_ERR 1387 "%s: kernel must blacklist external hubs\n", 1388 musb_driver_name); 1389 #endif 1390 #endif 1391 } 1392 1393 /* log release info */ 1394 hwvers = musb_read_hwvers(mbase); 1395 rev_major = (hwvers >> 10) & 0x1f; 1396 rev_minor = hwvers & 0x3ff; 1397 snprintf(aRevision, 32, "%d.%d%s", rev_major, 1398 rev_minor, (hwvers & 0x8000) ? "RC" : ""); 1399 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1400 musb_driver_name, type, aRevision, aDate); 1401 1402 /* configure ep0 */ 1403 musb_configure_ep0(musb); 1404 1405 /* discover endpoint configuration */ 1406 musb->nr_endpoints = 1; 1407 musb->epmask = 1; 1408 1409 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1410 if (musb->config->dyn_fifo) 1411 status = ep_config_from_table(musb); 1412 else { 1413 ERR("reconfigure software for Dynamic FIFOs\n"); 1414 status = -ENODEV; 1415 } 1416 } else { 1417 if (!musb->config->dyn_fifo) 1418 status = ep_config_from_hw(musb); 1419 else { 1420 ERR("reconfigure software for static FIFOs\n"); 1421 return -ENODEV; 1422 } 1423 } 1424 1425 if (status < 0) 1426 return status; 1427 1428 /* finish init, and print endpoint config */ 1429 for (i = 0; i < musb->nr_endpoints; i++) { 1430 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1431 1432 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1433 #ifdef CONFIG_USB_TUSB6010 1434 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1435 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1436 hw_ep->fifo_sync_va = 1437 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1438 1439 if (i == 0) 1440 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1441 else 1442 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1443 #endif 1444 1445 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1446 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1447 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1448 hw_ep->rx_reinit = 1; 1449 hw_ep->tx_reinit = 1; 1450 #endif 1451 1452 if (hw_ep->max_packet_sz_tx) { 1453 printk(KERN_DEBUG 1454 "%s: hw_ep %d%s, %smax %d\n", 1455 musb_driver_name, i, 1456 hw_ep->is_shared_fifo ? "shared" : "tx", 1457 hw_ep->tx_double_buffered 1458 ? "doublebuffer, " : "", 1459 hw_ep->max_packet_sz_tx); 1460 } 1461 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1462 printk(KERN_DEBUG 1463 "%s: hw_ep %d%s, %smax %d\n", 1464 musb_driver_name, i, 1465 "rx", 1466 hw_ep->rx_double_buffered 1467 ? "doublebuffer, " : "", 1468 hw_ep->max_packet_sz_rx); 1469 } 1470 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1471 DBG(1, "hw_ep %d not configured\n", i); 1472 } 1473 1474 return 0; 1475 } 1476 1477 /*-------------------------------------------------------------------------*/ 1478 1479 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 1480 1481 static irqreturn_t generic_interrupt(int irq, void *__hci) 1482 { 1483 unsigned long flags; 1484 irqreturn_t retval = IRQ_NONE; 1485 struct musb *musb = __hci; 1486 1487 spin_lock_irqsave(&musb->lock, flags); 1488 1489 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1490 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1491 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1492 1493 if (musb->int_usb || musb->int_tx || musb->int_rx) 1494 retval = musb_interrupt(musb); 1495 1496 spin_unlock_irqrestore(&musb->lock, flags); 1497 1498 return retval; 1499 } 1500 1501 #else 1502 #define generic_interrupt NULL 1503 #endif 1504 1505 /* 1506 * handle all the irqs defined by the HDRC core. for now we expect: other 1507 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1508 * will be assigned, and the irq will already have been acked. 1509 * 1510 * called in irq context with spinlock held, irqs blocked 1511 */ 1512 irqreturn_t musb_interrupt(struct musb *musb) 1513 { 1514 irqreturn_t retval = IRQ_NONE; 1515 u8 devctl, power; 1516 int ep_num; 1517 u32 reg; 1518 1519 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1520 power = musb_readb(musb->mregs, MUSB_POWER); 1521 1522 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1523 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1524 musb->int_usb, musb->int_tx, musb->int_rx); 1525 1526 /* the core can interrupt us for multiple reasons; docs have 1527 * a generic interrupt flowchart to follow 1528 */ 1529 if (musb->int_usb & STAGE0_MASK) 1530 retval |= musb_stage0_irq(musb, musb->int_usb, 1531 devctl, power); 1532 1533 /* "stage 1" is handling endpoint irqs */ 1534 1535 /* handle endpoint 0 first */ 1536 if (musb->int_tx & 1) { 1537 if (devctl & MUSB_DEVCTL_HM) 1538 retval |= musb_h_ep0_irq(musb); 1539 else 1540 retval |= musb_g_ep0_irq(musb); 1541 } 1542 1543 /* RX on endpoints 1-15 */ 1544 reg = musb->int_rx >> 1; 1545 ep_num = 1; 1546 while (reg) { 1547 if (reg & 1) { 1548 /* musb_ep_select(musb->mregs, ep_num); */ 1549 /* REVISIT just retval = ep->rx_irq(...) */ 1550 retval = IRQ_HANDLED; 1551 if (devctl & MUSB_DEVCTL_HM) { 1552 if (is_host_capable()) 1553 musb_host_rx(musb, ep_num); 1554 } else { 1555 if (is_peripheral_capable()) 1556 musb_g_rx(musb, ep_num); 1557 } 1558 } 1559 1560 reg >>= 1; 1561 ep_num++; 1562 } 1563 1564 /* TX on endpoints 1-15 */ 1565 reg = musb->int_tx >> 1; 1566 ep_num = 1; 1567 while (reg) { 1568 if (reg & 1) { 1569 /* musb_ep_select(musb->mregs, ep_num); */ 1570 /* REVISIT just retval |= ep->tx_irq(...) */ 1571 retval = IRQ_HANDLED; 1572 if (devctl & MUSB_DEVCTL_HM) { 1573 if (is_host_capable()) 1574 musb_host_tx(musb, ep_num); 1575 } else { 1576 if (is_peripheral_capable()) 1577 musb_g_tx(musb, ep_num); 1578 } 1579 } 1580 reg >>= 1; 1581 ep_num++; 1582 } 1583 1584 /* finish handling "global" interrupts after handling fifos */ 1585 if (musb->int_usb) 1586 retval |= musb_stage2_irq(musb, 1587 musb->int_usb, devctl, power); 1588 1589 return retval; 1590 } 1591 1592 1593 #ifndef CONFIG_MUSB_PIO_ONLY 1594 static int __initdata use_dma = 1; 1595 1596 /* "modprobe ... use_dma=0" etc */ 1597 module_param(use_dma, bool, 0); 1598 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1599 1600 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1601 { 1602 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1603 1604 /* called with controller lock already held */ 1605 1606 if (!epnum) { 1607 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1608 if (!is_cppi_enabled()) { 1609 /* endpoint 0 */ 1610 if (devctl & MUSB_DEVCTL_HM) 1611 musb_h_ep0_irq(musb); 1612 else 1613 musb_g_ep0_irq(musb); 1614 } 1615 #endif 1616 } else { 1617 /* endpoints 1..15 */ 1618 if (transmit) { 1619 if (devctl & MUSB_DEVCTL_HM) { 1620 if (is_host_capable()) 1621 musb_host_tx(musb, epnum); 1622 } else { 1623 if (is_peripheral_capable()) 1624 musb_g_tx(musb, epnum); 1625 } 1626 } else { 1627 /* receive */ 1628 if (devctl & MUSB_DEVCTL_HM) { 1629 if (is_host_capable()) 1630 musb_host_rx(musb, epnum); 1631 } else { 1632 if (is_peripheral_capable()) 1633 musb_g_rx(musb, epnum); 1634 } 1635 } 1636 } 1637 } 1638 1639 #else 1640 #define use_dma 0 1641 #endif 1642 1643 /*-------------------------------------------------------------------------*/ 1644 1645 #ifdef CONFIG_SYSFS 1646 1647 static ssize_t 1648 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1649 { 1650 struct musb *musb = dev_to_musb(dev); 1651 unsigned long flags; 1652 int ret = -EINVAL; 1653 1654 spin_lock_irqsave(&musb->lock, flags); 1655 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1656 spin_unlock_irqrestore(&musb->lock, flags); 1657 1658 return ret; 1659 } 1660 1661 static ssize_t 1662 musb_mode_store(struct device *dev, struct device_attribute *attr, 1663 const char *buf, size_t n) 1664 { 1665 struct musb *musb = dev_to_musb(dev); 1666 unsigned long flags; 1667 int status; 1668 1669 spin_lock_irqsave(&musb->lock, flags); 1670 if (sysfs_streq(buf, "host")) 1671 status = musb_platform_set_mode(musb, MUSB_HOST); 1672 else if (sysfs_streq(buf, "peripheral")) 1673 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1674 else if (sysfs_streq(buf, "otg")) 1675 status = musb_platform_set_mode(musb, MUSB_OTG); 1676 else 1677 status = -EINVAL; 1678 spin_unlock_irqrestore(&musb->lock, flags); 1679 1680 return (status == 0) ? n : status; 1681 } 1682 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1683 1684 static ssize_t 1685 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1686 const char *buf, size_t n) 1687 { 1688 struct musb *musb = dev_to_musb(dev); 1689 unsigned long flags; 1690 unsigned long val; 1691 1692 if (sscanf(buf, "%lu", &val) < 1) { 1693 printk(KERN_ERR "Invalid VBUS timeout ms value\n"); 1694 return -EINVAL; 1695 } 1696 1697 spin_lock_irqsave(&musb->lock, flags); 1698 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1699 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1700 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1701 musb->is_active = 0; 1702 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1703 spin_unlock_irqrestore(&musb->lock, flags); 1704 1705 return n; 1706 } 1707 1708 static ssize_t 1709 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1710 { 1711 struct musb *musb = dev_to_musb(dev); 1712 unsigned long flags; 1713 unsigned long val; 1714 int vbus; 1715 1716 spin_lock_irqsave(&musb->lock, flags); 1717 val = musb->a_wait_bcon; 1718 /* FIXME get_vbus_status() is normally #defined as false... 1719 * and is effectively TUSB-specific. 1720 */ 1721 vbus = musb_platform_get_vbus_status(musb); 1722 spin_unlock_irqrestore(&musb->lock, flags); 1723 1724 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1725 vbus ? "on" : "off", val); 1726 } 1727 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1728 1729 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 1730 1731 /* Gadget drivers can't know that a host is connected so they might want 1732 * to start SRP, but users can. This allows userspace to trigger SRP. 1733 */ 1734 static ssize_t 1735 musb_srp_store(struct device *dev, struct device_attribute *attr, 1736 const char *buf, size_t n) 1737 { 1738 struct musb *musb = dev_to_musb(dev); 1739 unsigned short srp; 1740 1741 if (sscanf(buf, "%hu", &srp) != 1 1742 || (srp != 1)) { 1743 printk(KERN_ERR "SRP: Value must be 1\n"); 1744 return -EINVAL; 1745 } 1746 1747 if (srp == 1) 1748 musb_g_wakeup(musb); 1749 1750 return n; 1751 } 1752 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1753 1754 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1755 1756 #endif /* sysfs */ 1757 1758 /* Only used to provide driver mode change events */ 1759 static void musb_irq_work(struct work_struct *data) 1760 { 1761 struct musb *musb = container_of(data, struct musb, irq_work); 1762 static int old_state; 1763 1764 if (musb->xceiv->state != old_state) { 1765 old_state = musb->xceiv->state; 1766 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1767 } 1768 } 1769 1770 /* -------------------------------------------------------------------------- 1771 * Init support 1772 */ 1773 1774 static struct musb *__init 1775 allocate_instance(struct device *dev, 1776 struct musb_hdrc_config *config, void __iomem *mbase) 1777 { 1778 struct musb *musb; 1779 struct musb_hw_ep *ep; 1780 int epnum; 1781 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1782 struct usb_hcd *hcd; 1783 1784 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1785 if (!hcd) 1786 return NULL; 1787 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1788 1789 musb = hcd_to_musb(hcd); 1790 INIT_LIST_HEAD(&musb->control); 1791 INIT_LIST_HEAD(&musb->in_bulk); 1792 INIT_LIST_HEAD(&musb->out_bulk); 1793 1794 hcd->uses_new_polling = 1; 1795 1796 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1797 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1798 #else 1799 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1800 if (!musb) 1801 return NULL; 1802 dev_set_drvdata(dev, musb); 1803 1804 #endif 1805 1806 musb->mregs = mbase; 1807 musb->ctrl_base = mbase; 1808 musb->nIrq = -ENODEV; 1809 musb->config = config; 1810 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1811 for (epnum = 0, ep = musb->endpoints; 1812 epnum < musb->config->num_eps; 1813 epnum++, ep++) { 1814 ep->musb = musb; 1815 ep->epnum = epnum; 1816 } 1817 1818 musb->controller = dev; 1819 return musb; 1820 } 1821 1822 static void musb_free(struct musb *musb) 1823 { 1824 /* this has multiple entry modes. it handles fault cleanup after 1825 * probe(), where things may be partially set up, as well as rmmod 1826 * cleanup after everything's been de-activated. 1827 */ 1828 1829 #ifdef CONFIG_SYSFS 1830 device_remove_file(musb->controller, &dev_attr_mode); 1831 device_remove_file(musb->controller, &dev_attr_vbus); 1832 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 1833 device_remove_file(musb->controller, &dev_attr_srp); 1834 #endif 1835 #endif 1836 1837 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 1838 musb_gadget_cleanup(musb); 1839 #endif 1840 1841 if (musb->nIrq >= 0) { 1842 if (musb->irq_wake) 1843 disable_irq_wake(musb->nIrq); 1844 free_irq(musb->nIrq, musb); 1845 } 1846 if (is_dma_capable() && musb->dma_controller) { 1847 struct dma_controller *c = musb->dma_controller; 1848 1849 (void) c->stop(c); 1850 dma_controller_destroy(c); 1851 } 1852 1853 #ifdef CONFIG_USB_MUSB_OTG 1854 put_device(musb->xceiv->dev); 1855 #endif 1856 1857 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1858 musb_platform_exit(musb); 1859 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1860 1861 if (musb->clock) { 1862 clk_disable(musb->clock); 1863 clk_put(musb->clock); 1864 } 1865 1866 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1867 usb_put_hcd(musb_to_hcd(musb)); 1868 #else 1869 kfree(musb); 1870 #endif 1871 } 1872 1873 /* 1874 * Perform generic per-controller initialization. 1875 * 1876 * @pDevice: the controller (already clocked, etc) 1877 * @nIrq: irq 1878 * @mregs: virtual address of controller registers, 1879 * not yet corrected for platform-specific offsets 1880 */ 1881 static int __init 1882 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1883 { 1884 int status; 1885 struct musb *musb; 1886 struct musb_hdrc_platform_data *plat = dev->platform_data; 1887 1888 /* The driver might handle more features than the board; OK. 1889 * Fail when the board needs a feature that's not enabled. 1890 */ 1891 if (!plat) { 1892 dev_dbg(dev, "no platform_data?\n"); 1893 return -ENODEV; 1894 } 1895 switch (plat->mode) { 1896 case MUSB_HOST: 1897 #ifdef CONFIG_USB_MUSB_HDRC_HCD 1898 break; 1899 #else 1900 goto bad_config; 1901 #endif 1902 case MUSB_PERIPHERAL: 1903 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 1904 break; 1905 #else 1906 goto bad_config; 1907 #endif 1908 case MUSB_OTG: 1909 #ifdef CONFIG_USB_MUSB_OTG 1910 break; 1911 #else 1912 bad_config: 1913 #endif 1914 default: 1915 dev_err(dev, "incompatible Kconfig role setting\n"); 1916 return -EINVAL; 1917 } 1918 1919 /* allocate */ 1920 musb = allocate_instance(dev, plat->config, ctrl); 1921 if (!musb) 1922 return -ENOMEM; 1923 1924 spin_lock_init(&musb->lock); 1925 musb->board_mode = plat->mode; 1926 musb->board_set_power = plat->set_power; 1927 musb->set_clock = plat->set_clock; 1928 musb->min_power = plat->min_power; 1929 1930 /* Clock usage is chip-specific ... functional clock (DaVinci, 1931 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core 1932 * code does is make sure a clock handle is available; platform 1933 * code manages it during start/stop and suspend/resume. 1934 */ 1935 if (plat->clock) { 1936 musb->clock = clk_get(dev, plat->clock); 1937 if (IS_ERR(musb->clock)) { 1938 status = PTR_ERR(musb->clock); 1939 musb->clock = NULL; 1940 goto fail; 1941 } 1942 } 1943 1944 /* The musb_platform_init() call: 1945 * - adjusts musb->mregs and musb->isr if needed, 1946 * - may initialize an integrated tranceiver 1947 * - initializes musb->xceiv, usually by otg_get_transceiver() 1948 * - activates clocks. 1949 * - stops powering VBUS 1950 * - assigns musb->board_set_vbus if host mode is enabled 1951 * 1952 * There are various transciever configurations. Blackfin, 1953 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1954 * external/discrete ones in various flavors (twl4030 family, 1955 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1956 */ 1957 musb->isr = generic_interrupt; 1958 status = musb_platform_init(musb); 1959 1960 if (status < 0) 1961 goto fail; 1962 if (!musb->isr) { 1963 status = -ENODEV; 1964 goto fail2; 1965 } 1966 1967 #ifndef CONFIG_MUSB_PIO_ONLY 1968 if (use_dma && dev->dma_mask) { 1969 struct dma_controller *c; 1970 1971 c = dma_controller_create(musb, musb->mregs); 1972 musb->dma_controller = c; 1973 if (c) 1974 (void) c->start(c); 1975 } 1976 #endif 1977 /* ideally this would be abstracted in platform setup */ 1978 if (!is_dma_capable() || !musb->dma_controller) 1979 dev->dma_mask = NULL; 1980 1981 /* be sure interrupts are disabled before connecting ISR */ 1982 musb_platform_disable(musb); 1983 musb_generic_disable(musb); 1984 1985 /* setup musb parts of the core (especially endpoints) */ 1986 status = musb_core_init(plat->config->multipoint 1987 ? MUSB_CONTROLLER_MHDRC 1988 : MUSB_CONTROLLER_HDRC, musb); 1989 if (status < 0) 1990 goto fail2; 1991 1992 #ifdef CONFIG_USB_MUSB_OTG 1993 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1994 #endif 1995 1996 /* Init IRQ workqueue before request_irq */ 1997 INIT_WORK(&musb->irq_work, musb_irq_work); 1998 1999 /* attach to the IRQ */ 2000 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2001 dev_err(dev, "request_irq %d failed!\n", nIrq); 2002 status = -ENODEV; 2003 goto fail2; 2004 } 2005 musb->nIrq = nIrq; 2006 /* FIXME this handles wakeup irqs wrong */ 2007 if (enable_irq_wake(nIrq) == 0) { 2008 musb->irq_wake = 1; 2009 device_init_wakeup(dev, 1); 2010 } else { 2011 musb->irq_wake = 0; 2012 } 2013 2014 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n", 2015 musb_driver_name, 2016 ({char *s; 2017 switch (musb->board_mode) { 2018 case MUSB_HOST: s = "Host"; break; 2019 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2020 default: s = "OTG"; break; 2021 }; s; }), 2022 ctrl, 2023 (is_dma_capable() && musb->dma_controller) 2024 ? "DMA" : "PIO", 2025 musb->nIrq); 2026 2027 /* host side needs more setup */ 2028 if (is_host_enabled(musb)) { 2029 struct usb_hcd *hcd = musb_to_hcd(musb); 2030 2031 otg_set_host(musb->xceiv, &hcd->self); 2032 2033 if (is_otg_enabled(musb)) 2034 hcd->self.otg_port = 1; 2035 musb->xceiv->host = &hcd->self; 2036 hcd->power_budget = 2 * (plat->power ? : 250); 2037 } 2038 2039 /* For the host-only role, we can activate right away. 2040 * (We expect the ID pin to be forcibly grounded!!) 2041 * Otherwise, wait till the gadget driver hooks up. 2042 */ 2043 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2044 MUSB_HST_MODE(musb); 2045 musb->xceiv->default_a = 1; 2046 musb->xceiv->state = OTG_STATE_A_IDLE; 2047 2048 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2049 if (status) 2050 goto fail; 2051 2052 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2053 "HOST", status, 2054 musb_readb(musb->mregs, MUSB_DEVCTL), 2055 (musb_readb(musb->mregs, MUSB_DEVCTL) 2056 & MUSB_DEVCTL_BDEVICE 2057 ? 'B' : 'A')); 2058 2059 } else /* peripheral is enabled */ { 2060 MUSB_DEV_MODE(musb); 2061 musb->xceiv->default_a = 0; 2062 musb->xceiv->state = OTG_STATE_B_IDLE; 2063 2064 status = musb_gadget_setup(musb); 2065 if (status) 2066 goto fail; 2067 2068 DBG(1, "%s mode, status %d, dev%02x\n", 2069 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2070 status, 2071 musb_readb(musb->mregs, MUSB_DEVCTL)); 2072 2073 } 2074 2075 #ifdef CONFIG_SYSFS 2076 status = device_create_file(dev, &dev_attr_mode); 2077 status = device_create_file(dev, &dev_attr_vbus); 2078 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 2079 status = device_create_file(dev, &dev_attr_srp); 2080 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 2081 status = 0; 2082 #endif 2083 if (status) 2084 goto fail2; 2085 2086 return 0; 2087 2088 fail2: 2089 #ifdef CONFIG_SYSFS 2090 device_remove_file(musb->controller, &dev_attr_mode); 2091 device_remove_file(musb->controller, &dev_attr_vbus); 2092 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 2093 device_remove_file(musb->controller, &dev_attr_srp); 2094 #endif 2095 #endif 2096 musb_platform_exit(musb); 2097 fail: 2098 dev_err(musb->controller, 2099 "musb_init_controller failed with status %d\n", status); 2100 2101 if (musb->clock) 2102 clk_put(musb->clock); 2103 device_init_wakeup(dev, 0); 2104 musb_free(musb); 2105 2106 return status; 2107 2108 } 2109 2110 /*-------------------------------------------------------------------------*/ 2111 2112 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2113 * bridge to a platform device; this driver then suffices. 2114 */ 2115 2116 #ifndef CONFIG_MUSB_PIO_ONLY 2117 static u64 *orig_dma_mask; 2118 #endif 2119 2120 static int __init musb_probe(struct platform_device *pdev) 2121 { 2122 struct device *dev = &pdev->dev; 2123 int irq = platform_get_irq(pdev, 0); 2124 struct resource *iomem; 2125 void __iomem *base; 2126 2127 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2128 if (!iomem || irq == 0) 2129 return -ENODEV; 2130 2131 base = ioremap(iomem->start, iomem->end - iomem->start + 1); 2132 if (!base) { 2133 dev_err(dev, "ioremap failed\n"); 2134 return -ENOMEM; 2135 } 2136 2137 #ifndef CONFIG_MUSB_PIO_ONLY 2138 /* clobbered by use_dma=n */ 2139 orig_dma_mask = dev->dma_mask; 2140 #endif 2141 return musb_init_controller(dev, irq, base); 2142 } 2143 2144 static int __devexit musb_remove(struct platform_device *pdev) 2145 { 2146 struct musb *musb = dev_to_musb(&pdev->dev); 2147 void __iomem *ctrl_base = musb->ctrl_base; 2148 2149 /* this gets called on rmmod. 2150 * - Host mode: host may still be active 2151 * - Peripheral mode: peripheral is deactivated (or never-activated) 2152 * - OTG mode: both roles are deactivated (or never-activated) 2153 */ 2154 musb_shutdown(pdev); 2155 #ifdef CONFIG_USB_MUSB_HDRC_HCD 2156 if (musb->board_mode == MUSB_HOST) 2157 usb_remove_hcd(musb_to_hcd(musb)); 2158 #endif 2159 musb_free(musb); 2160 iounmap(ctrl_base); 2161 device_init_wakeup(&pdev->dev, 0); 2162 #ifndef CONFIG_MUSB_PIO_ONLY 2163 pdev->dev.dma_mask = orig_dma_mask; 2164 #endif 2165 return 0; 2166 } 2167 2168 #ifdef CONFIG_PM 2169 2170 static int musb_suspend(struct device *dev) 2171 { 2172 struct platform_device *pdev = to_platform_device(dev); 2173 unsigned long flags; 2174 struct musb *musb = dev_to_musb(&pdev->dev); 2175 2176 if (!musb->clock) 2177 return 0; 2178 2179 spin_lock_irqsave(&musb->lock, flags); 2180 2181 if (is_peripheral_active(musb)) { 2182 /* FIXME force disconnect unless we know USB will wake 2183 * the system up quickly enough to respond ... 2184 */ 2185 } else if (is_host_active(musb)) { 2186 /* we know all the children are suspended; sometimes 2187 * they will even be wakeup-enabled. 2188 */ 2189 } 2190 2191 if (musb->set_clock) 2192 musb->set_clock(musb->clock, 0); 2193 else 2194 clk_disable(musb->clock); 2195 spin_unlock_irqrestore(&musb->lock, flags); 2196 return 0; 2197 } 2198 2199 static int musb_resume_noirq(struct device *dev) 2200 { 2201 struct platform_device *pdev = to_platform_device(dev); 2202 struct musb *musb = dev_to_musb(&pdev->dev); 2203 2204 if (!musb->clock) 2205 return 0; 2206 2207 if (musb->set_clock) 2208 musb->set_clock(musb->clock, 1); 2209 else 2210 clk_enable(musb->clock); 2211 2212 /* for static cmos like DaVinci, register values were preserved 2213 * unless for some reason the whole soc powered down or the USB 2214 * module got reset through the PSC (vs just being disabled). 2215 */ 2216 return 0; 2217 } 2218 2219 static struct dev_pm_ops musb_dev_pm_ops = { 2220 .suspend = musb_suspend, 2221 .resume_noirq = musb_resume_noirq, 2222 }; 2223 2224 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2225 #else 2226 #define MUSB_DEV_PM_OPS NULL 2227 #endif 2228 2229 static struct platform_driver musb_driver = { 2230 .driver = { 2231 .name = (char *)musb_driver_name, 2232 .bus = &platform_bus_type, 2233 .owner = THIS_MODULE, 2234 .pm = MUSB_DEV_PM_OPS, 2235 }, 2236 .remove = __devexit_p(musb_remove), 2237 .shutdown = musb_shutdown, 2238 }; 2239 2240 /*-------------------------------------------------------------------------*/ 2241 2242 static int __init musb_init(void) 2243 { 2244 #ifdef CONFIG_USB_MUSB_HDRC_HCD 2245 if (usb_disabled()) 2246 return 0; 2247 #endif 2248 2249 pr_info("%s: version " MUSB_VERSION ", " 2250 #ifdef CONFIG_MUSB_PIO_ONLY 2251 "pio" 2252 #elif defined(CONFIG_USB_TI_CPPI_DMA) 2253 "cppi-dma" 2254 #elif defined(CONFIG_USB_INVENTRA_DMA) 2255 "musb-dma" 2256 #elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2257 "tusb-omap-dma" 2258 #else 2259 "?dma?" 2260 #endif 2261 ", " 2262 #ifdef CONFIG_USB_MUSB_OTG 2263 "otg (peripheral+host)" 2264 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2265 "peripheral" 2266 #elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2267 "host" 2268 #endif 2269 ", debug=%d\n", 2270 musb_driver_name, musb_debug); 2271 return platform_driver_probe(&musb_driver, musb_probe); 2272 } 2273 2274 /* make us init after usbcore and i2c (transceivers, regulators, etc) 2275 * and before usb gadget and host-side drivers start to register 2276 */ 2277 fs_initcall(musb_init); 2278 2279 static void __exit musb_cleanup(void) 2280 { 2281 platform_driver_unregister(&musb_driver); 2282 } 2283 module_exit(musb_cleanup); 2284