1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific information 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/list.h> 97 #include <linux/kobject.h> 98 #include <linux/prefetch.h> 99 #include <linux/platform_device.h> 100 #include <linux/io.h> 101 #include <linux/dma-mapping.h> 102 #include <linux/usb.h> 103 104 #include "musb_core.h" 105 106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 107 108 109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 111 112 #define MUSB_VERSION "6.0" 113 114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 115 116 #define MUSB_DRIVER_NAME "musb-hdrc" 117 const char musb_driver_name[] = MUSB_DRIVER_NAME; 118 119 MODULE_DESCRIPTION(DRIVER_INFO); 120 MODULE_AUTHOR(DRIVER_AUTHOR); 121 MODULE_LICENSE("GPL"); 122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 123 124 125 /*-------------------------------------------------------------------------*/ 126 127 static inline struct musb *dev_to_musb(struct device *dev) 128 { 129 return dev_get_drvdata(dev); 130 } 131 132 /*-------------------------------------------------------------------------*/ 133 134 #ifndef CONFIG_BLACKFIN 135 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 136 { 137 void __iomem *addr = phy->io_priv; 138 int i = 0; 139 u8 r; 140 u8 power; 141 int ret; 142 143 pm_runtime_get_sync(phy->io_dev); 144 145 /* Make sure the transceiver is not in low power mode */ 146 power = musb_readb(addr, MUSB_POWER); 147 power &= ~MUSB_POWER_SUSPENDM; 148 musb_writeb(addr, MUSB_POWER, power); 149 150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 152 */ 153 154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 157 158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 159 & MUSB_ULPI_REG_CMPLT)) { 160 i++; 161 if (i == 10000) { 162 ret = -ETIMEDOUT; 163 goto out; 164 } 165 166 } 167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 168 r &= ~MUSB_ULPI_REG_CMPLT; 169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 170 171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 172 173 out: 174 pm_runtime_put(phy->io_dev); 175 176 return ret; 177 } 178 179 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 180 { 181 void __iomem *addr = phy->io_priv; 182 int i = 0; 183 u8 r = 0; 184 u8 power; 185 int ret = 0; 186 187 pm_runtime_get_sync(phy->io_dev); 188 189 /* Make sure the transceiver is not in low power mode */ 190 power = musb_readb(addr, MUSB_POWER); 191 power &= ~MUSB_POWER_SUSPENDM; 192 musb_writeb(addr, MUSB_POWER, power); 193 194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 197 198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 199 & MUSB_ULPI_REG_CMPLT)) { 200 i++; 201 if (i == 10000) { 202 ret = -ETIMEDOUT; 203 goto out; 204 } 205 } 206 207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 208 r &= ~MUSB_ULPI_REG_CMPLT; 209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 210 211 out: 212 pm_runtime_put(phy->io_dev); 213 214 return ret; 215 } 216 #else 217 #define musb_ulpi_read NULL 218 #define musb_ulpi_write NULL 219 #endif 220 221 static struct usb_phy_io_ops musb_ulpi_access = { 222 .read = musb_ulpi_read, 223 .write = musb_ulpi_write, 224 }; 225 226 /*-------------------------------------------------------------------------*/ 227 228 static u32 musb_default_fifo_offset(u8 epnum) 229 { 230 return 0x20 + (epnum * 4); 231 } 232 233 /* "flat" mapping: each endpoint has its own i/o address */ 234 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum) 235 { 236 } 237 238 static u32 musb_flat_ep_offset(u8 epnum, u16 offset) 239 { 240 return 0x100 + (0x10 * epnum) + offset; 241 } 242 243 /* "indexed" mapping: INDEX register controls register bank select */ 244 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum) 245 { 246 musb_writeb(mbase, MUSB_INDEX, epnum); 247 } 248 249 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset) 250 { 251 return 0x10 + offset; 252 } 253 254 static u32 musb_default_busctl_offset(u8 epnum, u16 offset) 255 { 256 return 0x80 + (0x08 * epnum) + offset; 257 } 258 259 static u8 musb_default_readb(const void __iomem *addr, unsigned offset) 260 { 261 return __raw_readb(addr + offset); 262 } 263 264 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data) 265 { 266 __raw_writeb(data, addr + offset); 267 } 268 269 static u16 musb_default_readw(const void __iomem *addr, unsigned offset) 270 { 271 return __raw_readw(addr + offset); 272 } 273 274 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data) 275 { 276 __raw_writew(data, addr + offset); 277 } 278 279 static u32 musb_default_readl(const void __iomem *addr, unsigned offset) 280 { 281 return __raw_readl(addr + offset); 282 } 283 284 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data) 285 { 286 __raw_writel(data, addr + offset); 287 } 288 289 /* 290 * Load an endpoint's FIFO 291 */ 292 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 293 const u8 *src) 294 { 295 struct musb *musb = hw_ep->musb; 296 void __iomem *fifo = hw_ep->fifo; 297 298 if (unlikely(len == 0)) 299 return; 300 301 prefetch((u8 *)src); 302 303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 304 'T', hw_ep->epnum, fifo, len, src); 305 306 /* we can't assume unaligned reads work */ 307 if (likely((0x01 & (unsigned long) src) == 0)) { 308 u16 index = 0; 309 310 /* best case is 32bit-aligned source address */ 311 if ((0x02 & (unsigned long) src) == 0) { 312 if (len >= 4) { 313 iowrite32_rep(fifo, src + index, len >> 2); 314 index += len & ~0x03; 315 } 316 if (len & 0x02) { 317 __raw_writew(*(u16 *)&src[index], fifo); 318 index += 2; 319 } 320 } else { 321 if (len >= 2) { 322 iowrite16_rep(fifo, src + index, len >> 1); 323 index += len & ~0x01; 324 } 325 } 326 if (len & 0x01) 327 __raw_writeb(src[index], fifo); 328 } else { 329 /* byte aligned */ 330 iowrite8_rep(fifo, src, len); 331 } 332 } 333 334 /* 335 * Unload an endpoint's FIFO 336 */ 337 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 338 { 339 struct musb *musb = hw_ep->musb; 340 void __iomem *fifo = hw_ep->fifo; 341 342 if (unlikely(len == 0)) 343 return; 344 345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 346 'R', hw_ep->epnum, fifo, len, dst); 347 348 /* we can't assume unaligned writes work */ 349 if (likely((0x01 & (unsigned long) dst) == 0)) { 350 u16 index = 0; 351 352 /* best case is 32bit-aligned destination address */ 353 if ((0x02 & (unsigned long) dst) == 0) { 354 if (len >= 4) { 355 ioread32_rep(fifo, dst, len >> 2); 356 index = len & ~0x03; 357 } 358 if (len & 0x02) { 359 *(u16 *)&dst[index] = __raw_readw(fifo); 360 index += 2; 361 } 362 } else { 363 if (len >= 2) { 364 ioread16_rep(fifo, dst, len >> 1); 365 index = len & ~0x01; 366 } 367 } 368 if (len & 0x01) 369 dst[index] = __raw_readb(fifo); 370 } else { 371 /* byte aligned */ 372 ioread8_rep(fifo, dst, len); 373 } 374 } 375 376 /* 377 * Old style IO functions 378 */ 379 u8 (*musb_readb)(const void __iomem *addr, unsigned offset); 380 EXPORT_SYMBOL_GPL(musb_readb); 381 382 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data); 383 EXPORT_SYMBOL_GPL(musb_writeb); 384 385 u16 (*musb_readw)(const void __iomem *addr, unsigned offset); 386 EXPORT_SYMBOL_GPL(musb_readw); 387 388 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data); 389 EXPORT_SYMBOL_GPL(musb_writew); 390 391 u32 (*musb_readl)(const void __iomem *addr, unsigned offset); 392 EXPORT_SYMBOL_GPL(musb_readl); 393 394 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data); 395 EXPORT_SYMBOL_GPL(musb_writel); 396 397 #ifndef CONFIG_MUSB_PIO_ONLY 398 struct dma_controller * 399 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base); 400 EXPORT_SYMBOL(musb_dma_controller_create); 401 402 void (*musb_dma_controller_destroy)(struct dma_controller *c); 403 EXPORT_SYMBOL(musb_dma_controller_destroy); 404 #endif 405 406 /* 407 * New style IO functions 408 */ 409 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 410 { 411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst); 412 } 413 414 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 415 { 416 return hw_ep->musb->io.write_fifo(hw_ep, len, src); 417 } 418 419 /*-------------------------------------------------------------------------*/ 420 421 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 422 static const u8 musb_test_packet[53] = { 423 /* implicit SYNC then DATA0 to start */ 424 425 /* JKJKJKJK x9 */ 426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 427 /* JJKKJJKK x8 */ 428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 429 /* JJJJKKKK x8 */ 430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 431 /* JJJJJJJKKKKKKK x8 */ 432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 433 /* JJJJJJJK x8 */ 434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 435 /* JKKKKKKK x10, JK */ 436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 437 438 /* implicit CRC16 then EOP to end */ 439 }; 440 441 void musb_load_testpacket(struct musb *musb) 442 { 443 void __iomem *regs = musb->endpoints[0].regs; 444 445 musb_ep_select(musb->mregs, 0); 446 musb_write_fifo(musb->control_ep, 447 sizeof(musb_test_packet), musb_test_packet); 448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 449 } 450 451 /*-------------------------------------------------------------------------*/ 452 453 /* 454 * Handles OTG hnp timeouts, such as b_ase0_brst 455 */ 456 static void musb_otg_timer_func(unsigned long data) 457 { 458 struct musb *musb = (struct musb *)data; 459 unsigned long flags; 460 461 spin_lock_irqsave(&musb->lock, flags); 462 switch (musb->xceiv->otg->state) { 463 case OTG_STATE_B_WAIT_ACON: 464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 465 musb_g_disconnect(musb); 466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 467 musb->is_active = 0; 468 break; 469 case OTG_STATE_A_SUSPEND: 470 case OTG_STATE_A_WAIT_BCON: 471 dev_dbg(musb->controller, "HNP: %s timeout\n", 472 usb_otg_state_string(musb->xceiv->otg->state)); 473 musb_platform_set_vbus(musb, 0); 474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 475 break; 476 default: 477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 478 usb_otg_state_string(musb->xceiv->otg->state)); 479 } 480 spin_unlock_irqrestore(&musb->lock, flags); 481 } 482 483 /* 484 * Stops the HNP transition. Caller must take care of locking. 485 */ 486 void musb_hnp_stop(struct musb *musb) 487 { 488 struct usb_hcd *hcd = musb->hcd; 489 void __iomem *mbase = musb->mregs; 490 u8 reg; 491 492 dev_dbg(musb->controller, "HNP: stop from %s\n", 493 usb_otg_state_string(musb->xceiv->otg->state)); 494 495 switch (musb->xceiv->otg->state) { 496 case OTG_STATE_A_PERIPHERAL: 497 musb_g_disconnect(musb); 498 dev_dbg(musb->controller, "HNP: back to %s\n", 499 usb_otg_state_string(musb->xceiv->otg->state)); 500 break; 501 case OTG_STATE_B_HOST: 502 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 503 if (hcd) 504 hcd->self.is_b_host = 0; 505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 506 MUSB_DEV_MODE(musb); 507 reg = musb_readb(mbase, MUSB_POWER); 508 reg |= MUSB_POWER_SUSPENDM; 509 musb_writeb(mbase, MUSB_POWER, reg); 510 /* REVISIT: Start SESSION_REQUEST here? */ 511 break; 512 default: 513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 514 usb_otg_state_string(musb->xceiv->otg->state)); 515 } 516 517 /* 518 * When returning to A state after HNP, avoid hub_port_rebounce(), 519 * which cause occasional OPT A "Did not receive reset after connect" 520 * errors. 521 */ 522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 523 } 524 525 static void musb_recover_from_babble(struct musb *musb); 526 527 /* 528 * Interrupt Service Routine to record USB "global" interrupts. 529 * Since these do not happen often and signify things of 530 * paramount importance, it seems OK to check them individually; 531 * the order of the tests is specified in the manual 532 * 533 * @param musb instance pointer 534 * @param int_usb register contents 535 * @param devctl 536 * @param power 537 */ 538 539 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 540 u8 devctl) 541 { 542 irqreturn_t handled = IRQ_NONE; 543 544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl, 545 int_usb); 546 547 /* in host mode, the peripheral may issue remote wakeup. 548 * in peripheral mode, the host may resume the link. 549 * spurious RESUME irqs happen too, paired with SUSPEND. 550 */ 551 if (int_usb & MUSB_INTR_RESUME) { 552 handled = IRQ_HANDLED; 553 dev_dbg(musb->controller, "RESUME (%s)\n", 554 usb_otg_state_string(musb->xceiv->otg->state)); 555 556 if (devctl & MUSB_DEVCTL_HM) { 557 switch (musb->xceiv->otg->state) { 558 case OTG_STATE_A_SUSPEND: 559 /* remote wakeup? later, GetPortStatus 560 * will stop RESUME signaling 561 */ 562 563 musb->port1_status |= 564 (USB_PORT_STAT_C_SUSPEND << 16) 565 | MUSB_PORT_STAT_RESUME; 566 musb->rh_timer = jiffies 567 + msecs_to_jiffies(USB_RESUME_TIMEOUT); 568 musb->need_finish_resume = 1; 569 570 musb->xceiv->otg->state = OTG_STATE_A_HOST; 571 musb->is_active = 1; 572 musb_host_resume_root_hub(musb); 573 break; 574 case OTG_STATE_B_WAIT_ACON: 575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 576 musb->is_active = 1; 577 MUSB_DEV_MODE(musb); 578 break; 579 default: 580 WARNING("bogus %s RESUME (%s)\n", 581 "host", 582 usb_otg_state_string(musb->xceiv->otg->state)); 583 } 584 } else { 585 switch (musb->xceiv->otg->state) { 586 case OTG_STATE_A_SUSPEND: 587 /* possibly DISCONNECT is upcoming */ 588 musb->xceiv->otg->state = OTG_STATE_A_HOST; 589 musb_host_resume_root_hub(musb); 590 break; 591 case OTG_STATE_B_WAIT_ACON: 592 case OTG_STATE_B_PERIPHERAL: 593 /* disconnect while suspended? we may 594 * not get a disconnect irq... 595 */ 596 if ((devctl & MUSB_DEVCTL_VBUS) 597 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 598 ) { 599 musb->int_usb |= MUSB_INTR_DISCONNECT; 600 musb->int_usb &= ~MUSB_INTR_SUSPEND; 601 break; 602 } 603 musb_g_resume(musb); 604 break; 605 case OTG_STATE_B_IDLE: 606 musb->int_usb &= ~MUSB_INTR_SUSPEND; 607 break; 608 default: 609 WARNING("bogus %s RESUME (%s)\n", 610 "peripheral", 611 usb_otg_state_string(musb->xceiv->otg->state)); 612 } 613 } 614 } 615 616 /* see manual for the order of the tests */ 617 if (int_usb & MUSB_INTR_SESSREQ) { 618 void __iomem *mbase = musb->mregs; 619 620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 621 && (devctl & MUSB_DEVCTL_BDEVICE)) { 622 dev_dbg(musb->controller, "SessReq while on B state\n"); 623 return IRQ_HANDLED; 624 } 625 626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 627 usb_otg_state_string(musb->xceiv->otg->state)); 628 629 /* IRQ arrives from ID pin sense or (later, if VBUS power 630 * is removed) SRP. responses are time critical: 631 * - turn on VBUS (with silicon-specific mechanism) 632 * - go through A_WAIT_VRISE 633 * - ... to A_WAIT_BCON. 634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 635 */ 636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 637 musb->ep0_stage = MUSB_EP0_START; 638 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 639 MUSB_HST_MODE(musb); 640 musb_platform_set_vbus(musb, 1); 641 642 handled = IRQ_HANDLED; 643 } 644 645 if (int_usb & MUSB_INTR_VBUSERROR) { 646 int ignore = 0; 647 648 /* During connection as an A-Device, we may see a short 649 * current spikes causing voltage drop, because of cable 650 * and peripheral capacitance combined with vbus draw. 651 * (So: less common with truly self-powered devices, where 652 * vbus doesn't act like a power supply.) 653 * 654 * Such spikes are short; usually less than ~500 usec, max 655 * of ~2 msec. That is, they're not sustained overcurrent 656 * errors, though they're reported using VBUSERROR irqs. 657 * 658 * Workarounds: (a) hardware: use self powered devices. 659 * (b) software: ignore non-repeated VBUS errors. 660 * 661 * REVISIT: do delays from lots of DEBUG_KERNEL checks 662 * make trouble here, keeping VBUS < 4.4V ? 663 */ 664 switch (musb->xceiv->otg->state) { 665 case OTG_STATE_A_HOST: 666 /* recovery is dicey once we've gotten past the 667 * initial stages of enumeration, but if VBUS 668 * stayed ok at the other end of the link, and 669 * another reset is due (at least for high speed, 670 * to redo the chirp etc), it might work OK... 671 */ 672 case OTG_STATE_A_WAIT_BCON: 673 case OTG_STATE_A_WAIT_VRISE: 674 if (musb->vbuserr_retry) { 675 void __iomem *mbase = musb->mregs; 676 677 musb->vbuserr_retry--; 678 ignore = 1; 679 devctl |= MUSB_DEVCTL_SESSION; 680 musb_writeb(mbase, MUSB_DEVCTL, devctl); 681 } else { 682 musb->port1_status |= 683 USB_PORT_STAT_OVERCURRENT 684 | (USB_PORT_STAT_C_OVERCURRENT << 16); 685 } 686 break; 687 default: 688 break; 689 } 690 691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, 692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 693 usb_otg_state_string(musb->xceiv->otg->state), 694 devctl, 695 ({ char *s; 696 switch (devctl & MUSB_DEVCTL_VBUS) { 697 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 698 s = "<SessEnd"; break; 699 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 700 s = "<AValid"; break; 701 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 702 s = "<VBusValid"; break; 703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 704 default: 705 s = "VALID"; break; 706 } s; }), 707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 708 musb->port1_status); 709 710 /* go through A_WAIT_VFALL then start a new session */ 711 if (!ignore) 712 musb_platform_set_vbus(musb, 0); 713 handled = IRQ_HANDLED; 714 } 715 716 if (int_usb & MUSB_INTR_SUSPEND) { 717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n", 718 usb_otg_state_string(musb->xceiv->otg->state), devctl); 719 handled = IRQ_HANDLED; 720 721 switch (musb->xceiv->otg->state) { 722 case OTG_STATE_A_PERIPHERAL: 723 /* We also come here if the cable is removed, since 724 * this silicon doesn't report ID-no-longer-grounded. 725 * 726 * We depend on T(a_wait_bcon) to shut us down, and 727 * hope users don't do anything dicey during this 728 * undesired detour through A_WAIT_BCON. 729 */ 730 musb_hnp_stop(musb); 731 musb_host_resume_root_hub(musb); 732 musb_root_disconnect(musb); 733 musb_platform_try_idle(musb, jiffies 734 + msecs_to_jiffies(musb->a_wait_bcon 735 ? : OTG_TIME_A_WAIT_BCON)); 736 737 break; 738 case OTG_STATE_B_IDLE: 739 if (!musb->is_active) 740 break; 741 case OTG_STATE_B_PERIPHERAL: 742 musb_g_suspend(musb); 743 musb->is_active = musb->g.b_hnp_enable; 744 if (musb->is_active) { 745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON; 746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 747 mod_timer(&musb->otg_timer, jiffies 748 + msecs_to_jiffies( 749 OTG_TIME_B_ASE0_BRST)); 750 } 751 break; 752 case OTG_STATE_A_WAIT_BCON: 753 if (musb->a_wait_bcon != 0) 754 musb_platform_try_idle(musb, jiffies 755 + msecs_to_jiffies(musb->a_wait_bcon)); 756 break; 757 case OTG_STATE_A_HOST: 758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND; 759 musb->is_active = musb->hcd->self.b_hnp_enable; 760 break; 761 case OTG_STATE_B_HOST: 762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 764 break; 765 default: 766 /* "should not happen" */ 767 musb->is_active = 0; 768 break; 769 } 770 } 771 772 if (int_usb & MUSB_INTR_CONNECT) { 773 struct usb_hcd *hcd = musb->hcd; 774 775 handled = IRQ_HANDLED; 776 musb->is_active = 1; 777 778 musb->ep0_stage = MUSB_EP0_START; 779 780 musb->intrtxe = musb->epmask; 781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); 782 musb->intrrxe = musb->epmask & 0xfffe; 783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); 784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 786 |USB_PORT_STAT_HIGH_SPEED 787 |USB_PORT_STAT_ENABLE 788 ); 789 musb->port1_status |= USB_PORT_STAT_CONNECTION 790 |(USB_PORT_STAT_C_CONNECTION << 16); 791 792 /* high vs full speed is just a guess until after reset */ 793 if (devctl & MUSB_DEVCTL_LSDEV) 794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 795 796 /* indicate new connection to OTG machine */ 797 switch (musb->xceiv->otg->state) { 798 case OTG_STATE_B_PERIPHERAL: 799 if (int_usb & MUSB_INTR_SUSPEND) { 800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 801 int_usb &= ~MUSB_INTR_SUSPEND; 802 goto b_host; 803 } else 804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 805 break; 806 case OTG_STATE_B_WAIT_ACON: 807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 808 b_host: 809 musb->xceiv->otg->state = OTG_STATE_B_HOST; 810 if (musb->hcd) 811 musb->hcd->self.is_b_host = 1; 812 del_timer(&musb->otg_timer); 813 break; 814 default: 815 if ((devctl & MUSB_DEVCTL_VBUS) 816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 817 musb->xceiv->otg->state = OTG_STATE_A_HOST; 818 if (hcd) 819 hcd->self.is_b_host = 0; 820 } 821 break; 822 } 823 824 musb_host_poke_root_hub(musb); 825 826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 827 usb_otg_state_string(musb->xceiv->otg->state), devctl); 828 } 829 830 if (int_usb & MUSB_INTR_DISCONNECT) { 831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 832 usb_otg_state_string(musb->xceiv->otg->state), 833 MUSB_MODE(musb), devctl); 834 handled = IRQ_HANDLED; 835 836 switch (musb->xceiv->otg->state) { 837 case OTG_STATE_A_HOST: 838 case OTG_STATE_A_SUSPEND: 839 musb_host_resume_root_hub(musb); 840 musb_root_disconnect(musb); 841 if (musb->a_wait_bcon != 0) 842 musb_platform_try_idle(musb, jiffies 843 + msecs_to_jiffies(musb->a_wait_bcon)); 844 break; 845 case OTG_STATE_B_HOST: 846 /* REVISIT this behaves for "real disconnect" 847 * cases; make sure the other transitions from 848 * from B_HOST act right too. The B_HOST code 849 * in hnp_stop() is currently not used... 850 */ 851 musb_root_disconnect(musb); 852 if (musb->hcd) 853 musb->hcd->self.is_b_host = 0; 854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 855 MUSB_DEV_MODE(musb); 856 musb_g_disconnect(musb); 857 break; 858 case OTG_STATE_A_PERIPHERAL: 859 musb_hnp_stop(musb); 860 musb_root_disconnect(musb); 861 /* FALLTHROUGH */ 862 case OTG_STATE_B_WAIT_ACON: 863 /* FALLTHROUGH */ 864 case OTG_STATE_B_PERIPHERAL: 865 case OTG_STATE_B_IDLE: 866 musb_g_disconnect(musb); 867 break; 868 default: 869 WARNING("unhandled DISCONNECT transition (%s)\n", 870 usb_otg_state_string(musb->xceiv->otg->state)); 871 break; 872 } 873 } 874 875 /* mentor saves a bit: bus reset and babble share the same irq. 876 * only host sees babble; only peripheral sees bus reset. 877 */ 878 if (int_usb & MUSB_INTR_RESET) { 879 handled = IRQ_HANDLED; 880 if (devctl & MUSB_DEVCTL_HM) { 881 /* 882 * When BABBLE happens what we can depends on which 883 * platform MUSB is running, because some platforms 884 * implemented proprietary means for 'recovering' from 885 * Babble conditions. One such platform is AM335x. In 886 * most cases, however, the only thing we can do is 887 * drop the session. 888 */ 889 dev_err(musb->controller, "Babble\n"); 890 891 if (is_host_active(musb)) 892 musb_recover_from_babble(musb); 893 } else { 894 dev_dbg(musb->controller, "BUS RESET as %s\n", 895 usb_otg_state_string(musb->xceiv->otg->state)); 896 switch (musb->xceiv->otg->state) { 897 case OTG_STATE_A_SUSPEND: 898 musb_g_reset(musb); 899 /* FALLTHROUGH */ 900 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 901 /* never use invalid T(a_wait_bcon) */ 902 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 903 usb_otg_state_string(musb->xceiv->otg->state), 904 TA_WAIT_BCON(musb)); 905 mod_timer(&musb->otg_timer, jiffies 906 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 907 break; 908 case OTG_STATE_A_PERIPHERAL: 909 del_timer(&musb->otg_timer); 910 musb_g_reset(musb); 911 break; 912 case OTG_STATE_B_WAIT_ACON: 913 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 914 usb_otg_state_string(musb->xceiv->otg->state)); 915 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 916 musb_g_reset(musb); 917 break; 918 case OTG_STATE_B_IDLE: 919 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 920 /* FALLTHROUGH */ 921 case OTG_STATE_B_PERIPHERAL: 922 musb_g_reset(musb); 923 break; 924 default: 925 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 926 usb_otg_state_string(musb->xceiv->otg->state)); 927 } 928 } 929 } 930 931 #if 0 932 /* REVISIT ... this would be for multiplexing periodic endpoints, or 933 * supporting transfer phasing to prevent exceeding ISO bandwidth 934 * limits of a given frame or microframe. 935 * 936 * It's not needed for peripheral side, which dedicates endpoints; 937 * though it _might_ use SOF irqs for other purposes. 938 * 939 * And it's not currently needed for host side, which also dedicates 940 * endpoints, relies on TX/RX interval registers, and isn't claimed 941 * to support ISO transfers yet. 942 */ 943 if (int_usb & MUSB_INTR_SOF) { 944 void __iomem *mbase = musb->mregs; 945 struct musb_hw_ep *ep; 946 u8 epnum; 947 u16 frame; 948 949 dev_dbg(musb->controller, "START_OF_FRAME\n"); 950 handled = IRQ_HANDLED; 951 952 /* start any periodic Tx transfers waiting for current frame */ 953 frame = musb_readw(mbase, MUSB_FRAME); 954 ep = musb->endpoints; 955 for (epnum = 1; (epnum < musb->nr_endpoints) 956 && (musb->epmask >= (1 << epnum)); 957 epnum++, ep++) { 958 /* 959 * FIXME handle framecounter wraps (12 bits) 960 * eliminate duplicated StartUrb logic 961 */ 962 if (ep->dwWaitFrame >= frame) { 963 ep->dwWaitFrame = 0; 964 pr_debug("SOF --> periodic TX%s on %d\n", 965 ep->tx_channel ? " DMA" : "", 966 epnum); 967 if (!ep->tx_channel) 968 musb_h_tx_start(musb, epnum); 969 else 970 cppi_hostdma_start(musb, epnum); 971 } 972 } /* end of for loop */ 973 } 974 #endif 975 976 schedule_work(&musb->irq_work); 977 978 return handled; 979 } 980 981 /*-------------------------------------------------------------------------*/ 982 983 static void musb_disable_interrupts(struct musb *musb) 984 { 985 void __iomem *mbase = musb->mregs; 986 u16 temp; 987 988 /* disable interrupts */ 989 musb_writeb(mbase, MUSB_INTRUSBE, 0); 990 musb->intrtxe = 0; 991 musb_writew(mbase, MUSB_INTRTXE, 0); 992 musb->intrrxe = 0; 993 musb_writew(mbase, MUSB_INTRRXE, 0); 994 995 /* flush pending interrupts */ 996 temp = musb_readb(mbase, MUSB_INTRUSB); 997 temp = musb_readw(mbase, MUSB_INTRTX); 998 temp = musb_readw(mbase, MUSB_INTRRX); 999 } 1000 1001 static void musb_enable_interrupts(struct musb *musb) 1002 { 1003 void __iomem *regs = musb->mregs; 1004 1005 /* Set INT enable registers, enable interrupts */ 1006 musb->intrtxe = musb->epmask; 1007 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); 1008 musb->intrrxe = musb->epmask & 0xfffe; 1009 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); 1010 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 1011 1012 } 1013 1014 static void musb_generic_disable(struct musb *musb) 1015 { 1016 void __iomem *mbase = musb->mregs; 1017 1018 musb_disable_interrupts(musb); 1019 1020 /* off */ 1021 musb_writeb(mbase, MUSB_DEVCTL, 0); 1022 } 1023 1024 /* 1025 * Program the HDRC to start (enable interrupts, dma, etc.). 1026 */ 1027 void musb_start(struct musb *musb) 1028 { 1029 void __iomem *regs = musb->mregs; 1030 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 1031 1032 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 1033 1034 musb_enable_interrupts(musb); 1035 musb_writeb(regs, MUSB_TESTMODE, 0); 1036 1037 /* put into basic highspeed mode and start session */ 1038 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 1039 | MUSB_POWER_HSENAB 1040 /* ENSUSPEND wedges tusb */ 1041 /* | MUSB_POWER_ENSUSPEND */ 1042 ); 1043 1044 musb->is_active = 0; 1045 devctl = musb_readb(regs, MUSB_DEVCTL); 1046 devctl &= ~MUSB_DEVCTL_SESSION; 1047 1048 /* session started after: 1049 * (a) ID-grounded irq, host mode; 1050 * (b) vbus present/connect IRQ, peripheral mode; 1051 * (c) peripheral initiates, using SRP 1052 */ 1053 if (musb->port_mode != MUSB_PORT_MODE_HOST && 1054 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { 1055 musb->is_active = 1; 1056 } else { 1057 devctl |= MUSB_DEVCTL_SESSION; 1058 } 1059 1060 musb_platform_enable(musb); 1061 musb_writeb(regs, MUSB_DEVCTL, devctl); 1062 } 1063 1064 /* 1065 * Make the HDRC stop (disable interrupts, etc.); 1066 * reversible by musb_start 1067 * called on gadget driver unregister 1068 * with controller locked, irqs blocked 1069 * acts as a NOP unless some role activated the hardware 1070 */ 1071 void musb_stop(struct musb *musb) 1072 { 1073 /* stop IRQs, timers, ... */ 1074 musb_platform_disable(musb); 1075 musb_generic_disable(musb); 1076 dev_dbg(musb->controller, "HDRC disabled\n"); 1077 1078 /* FIXME 1079 * - mark host and/or peripheral drivers unusable/inactive 1080 * - disable DMA (and enable it in HdrcStart) 1081 * - make sure we can musb_start() after musb_stop(); with 1082 * OTG mode, gadget driver module rmmod/modprobe cycles that 1083 * - ... 1084 */ 1085 musb_platform_try_idle(musb, 0); 1086 } 1087 1088 static void musb_shutdown(struct platform_device *pdev) 1089 { 1090 struct musb *musb = dev_to_musb(&pdev->dev); 1091 unsigned long flags; 1092 1093 pm_runtime_get_sync(musb->controller); 1094 1095 musb_host_cleanup(musb); 1096 musb_gadget_cleanup(musb); 1097 1098 spin_lock_irqsave(&musb->lock, flags); 1099 musb_platform_disable(musb); 1100 musb_generic_disable(musb); 1101 spin_unlock_irqrestore(&musb->lock, flags); 1102 1103 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1104 musb_platform_exit(musb); 1105 1106 pm_runtime_put(musb->controller); 1107 /* FIXME power down */ 1108 } 1109 1110 1111 /*-------------------------------------------------------------------------*/ 1112 1113 /* 1114 * The silicon either has hard-wired endpoint configurations, or else 1115 * "dynamic fifo" sizing. The driver has support for both, though at this 1116 * writing only the dynamic sizing is very well tested. Since we switched 1117 * away from compile-time hardware parameters, we can no longer rely on 1118 * dead code elimination to leave only the relevant one in the object file. 1119 * 1120 * We don't currently use dynamic fifo setup capability to do anything 1121 * more than selecting one of a bunch of predefined configurations. 1122 */ 1123 static ushort fifo_mode; 1124 1125 /* "modprobe ... fifo_mode=1" etc */ 1126 module_param(fifo_mode, ushort, 0); 1127 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1128 1129 /* 1130 * tables defining fifo_mode values. define more if you like. 1131 * for host side, make sure both halves of ep1 are set up. 1132 */ 1133 1134 /* mode 0 - fits in 2KB */ 1135 static struct musb_fifo_cfg mode_0_cfg[] = { 1136 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1137 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1138 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1139 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1140 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1141 }; 1142 1143 /* mode 1 - fits in 4KB */ 1144 static struct musb_fifo_cfg mode_1_cfg[] = { 1145 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1146 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1147 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1148 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1149 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1150 }; 1151 1152 /* mode 2 - fits in 4KB */ 1153 static struct musb_fifo_cfg mode_2_cfg[] = { 1154 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1155 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1156 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1157 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1158 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1159 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1160 }; 1161 1162 /* mode 3 - fits in 4KB */ 1163 static struct musb_fifo_cfg mode_3_cfg[] = { 1164 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1165 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1166 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1167 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1168 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1169 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1170 }; 1171 1172 /* mode 4 - fits in 16KB */ 1173 static struct musb_fifo_cfg mode_4_cfg[] = { 1174 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1175 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1176 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1177 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1178 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1179 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1180 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1181 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1182 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1183 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1184 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1185 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1186 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1187 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1188 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1189 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1190 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1191 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1192 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1193 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1194 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1195 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1196 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1197 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1198 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1199 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1200 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1201 }; 1202 1203 /* mode 5 - fits in 8KB */ 1204 static struct musb_fifo_cfg mode_5_cfg[] = { 1205 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1206 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1207 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1208 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1209 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1210 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1211 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1212 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1213 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1214 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1215 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1216 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1217 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1218 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1219 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1220 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1221 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1222 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1223 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1224 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1225 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1226 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1227 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1228 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1229 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1230 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1231 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1232 }; 1233 1234 /* 1235 * configure a fifo; for non-shared endpoints, this may be called 1236 * once for a tx fifo and once for an rx fifo. 1237 * 1238 * returns negative errno or offset for next fifo. 1239 */ 1240 static int 1241 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1242 const struct musb_fifo_cfg *cfg, u16 offset) 1243 { 1244 void __iomem *mbase = musb->mregs; 1245 int size = 0; 1246 u16 maxpacket = cfg->maxpacket; 1247 u16 c_off = offset >> 3; 1248 u8 c_size; 1249 1250 /* expect hw_ep has already been zero-initialized */ 1251 1252 size = ffs(max(maxpacket, (u16) 8)) - 1; 1253 maxpacket = 1 << size; 1254 1255 c_size = size - 3; 1256 if (cfg->mode == BUF_DOUBLE) { 1257 if ((offset + (maxpacket << 1)) > 1258 (1 << (musb->config->ram_bits + 2))) 1259 return -EMSGSIZE; 1260 c_size |= MUSB_FIFOSZ_DPB; 1261 } else { 1262 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1263 return -EMSGSIZE; 1264 } 1265 1266 /* configure the FIFO */ 1267 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1268 1269 /* EP0 reserved endpoint for control, bidirectional; 1270 * EP1 reserved for bulk, two unidirectional halves. 1271 */ 1272 if (hw_ep->epnum == 1) 1273 musb->bulk_ep = hw_ep; 1274 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1275 switch (cfg->style) { 1276 case FIFO_TX: 1277 musb_write_txfifosz(mbase, c_size); 1278 musb_write_txfifoadd(mbase, c_off); 1279 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1280 hw_ep->max_packet_sz_tx = maxpacket; 1281 break; 1282 case FIFO_RX: 1283 musb_write_rxfifosz(mbase, c_size); 1284 musb_write_rxfifoadd(mbase, c_off); 1285 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1286 hw_ep->max_packet_sz_rx = maxpacket; 1287 break; 1288 case FIFO_RXTX: 1289 musb_write_txfifosz(mbase, c_size); 1290 musb_write_txfifoadd(mbase, c_off); 1291 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1292 hw_ep->max_packet_sz_rx = maxpacket; 1293 1294 musb_write_rxfifosz(mbase, c_size); 1295 musb_write_rxfifoadd(mbase, c_off); 1296 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1297 hw_ep->max_packet_sz_tx = maxpacket; 1298 1299 hw_ep->is_shared_fifo = true; 1300 break; 1301 } 1302 1303 /* NOTE rx and tx endpoint irqs aren't managed separately, 1304 * which happens to be ok 1305 */ 1306 musb->epmask |= (1 << hw_ep->epnum); 1307 1308 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1309 } 1310 1311 static struct musb_fifo_cfg ep0_cfg = { 1312 .style = FIFO_RXTX, .maxpacket = 64, 1313 }; 1314 1315 static int ep_config_from_table(struct musb *musb) 1316 { 1317 const struct musb_fifo_cfg *cfg; 1318 unsigned i, n; 1319 int offset; 1320 struct musb_hw_ep *hw_ep = musb->endpoints; 1321 1322 if (musb->config->fifo_cfg) { 1323 cfg = musb->config->fifo_cfg; 1324 n = musb->config->fifo_cfg_size; 1325 goto done; 1326 } 1327 1328 switch (fifo_mode) { 1329 default: 1330 fifo_mode = 0; 1331 /* FALLTHROUGH */ 1332 case 0: 1333 cfg = mode_0_cfg; 1334 n = ARRAY_SIZE(mode_0_cfg); 1335 break; 1336 case 1: 1337 cfg = mode_1_cfg; 1338 n = ARRAY_SIZE(mode_1_cfg); 1339 break; 1340 case 2: 1341 cfg = mode_2_cfg; 1342 n = ARRAY_SIZE(mode_2_cfg); 1343 break; 1344 case 3: 1345 cfg = mode_3_cfg; 1346 n = ARRAY_SIZE(mode_3_cfg); 1347 break; 1348 case 4: 1349 cfg = mode_4_cfg; 1350 n = ARRAY_SIZE(mode_4_cfg); 1351 break; 1352 case 5: 1353 cfg = mode_5_cfg; 1354 n = ARRAY_SIZE(mode_5_cfg); 1355 break; 1356 } 1357 1358 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1359 musb_driver_name, fifo_mode); 1360 1361 1362 done: 1363 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1364 /* assert(offset > 0) */ 1365 1366 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1367 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1368 */ 1369 1370 for (i = 0; i < n; i++) { 1371 u8 epn = cfg->hw_ep_num; 1372 1373 if (epn >= musb->config->num_eps) { 1374 pr_debug("%s: invalid ep %d\n", 1375 musb_driver_name, epn); 1376 return -EINVAL; 1377 } 1378 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1379 if (offset < 0) { 1380 pr_debug("%s: mem overrun, ep %d\n", 1381 musb_driver_name, epn); 1382 return offset; 1383 } 1384 epn++; 1385 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1386 } 1387 1388 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1389 musb_driver_name, 1390 n + 1, musb->config->num_eps * 2 - 1, 1391 offset, (1 << (musb->config->ram_bits + 2))); 1392 1393 if (!musb->bulk_ep) { 1394 pr_debug("%s: missing bulk\n", musb_driver_name); 1395 return -EINVAL; 1396 } 1397 1398 return 0; 1399 } 1400 1401 1402 /* 1403 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1404 * @param musb the controller 1405 */ 1406 static int ep_config_from_hw(struct musb *musb) 1407 { 1408 u8 epnum = 0; 1409 struct musb_hw_ep *hw_ep; 1410 void __iomem *mbase = musb->mregs; 1411 int ret = 0; 1412 1413 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1414 1415 /* FIXME pick up ep0 maxpacket size */ 1416 1417 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1418 musb_ep_select(mbase, epnum); 1419 hw_ep = musb->endpoints + epnum; 1420 1421 ret = musb_read_fifosize(musb, hw_ep, epnum); 1422 if (ret < 0) 1423 break; 1424 1425 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1426 1427 /* pick an RX/TX endpoint for bulk */ 1428 if (hw_ep->max_packet_sz_tx < 512 1429 || hw_ep->max_packet_sz_rx < 512) 1430 continue; 1431 1432 /* REVISIT: this algorithm is lazy, we should at least 1433 * try to pick a double buffered endpoint. 1434 */ 1435 if (musb->bulk_ep) 1436 continue; 1437 musb->bulk_ep = hw_ep; 1438 } 1439 1440 if (!musb->bulk_ep) { 1441 pr_debug("%s: missing bulk\n", musb_driver_name); 1442 return -EINVAL; 1443 } 1444 1445 return 0; 1446 } 1447 1448 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1449 1450 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1451 * configure endpoints, or take their config from silicon 1452 */ 1453 static int musb_core_init(u16 musb_type, struct musb *musb) 1454 { 1455 u8 reg; 1456 char *type; 1457 char aInfo[90], aRevision[32], aDate[12]; 1458 void __iomem *mbase = musb->mregs; 1459 int status = 0; 1460 int i; 1461 1462 /* log core options (read using indexed model) */ 1463 reg = musb_read_configdata(mbase); 1464 1465 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1466 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1467 strcat(aInfo, ", dyn FIFOs"); 1468 musb->dyn_fifo = true; 1469 } 1470 if (reg & MUSB_CONFIGDATA_MPRXE) { 1471 strcat(aInfo, ", bulk combine"); 1472 musb->bulk_combine = true; 1473 } 1474 if (reg & MUSB_CONFIGDATA_MPTXE) { 1475 strcat(aInfo, ", bulk split"); 1476 musb->bulk_split = true; 1477 } 1478 if (reg & MUSB_CONFIGDATA_HBRXE) { 1479 strcat(aInfo, ", HB-ISO Rx"); 1480 musb->hb_iso_rx = true; 1481 } 1482 if (reg & MUSB_CONFIGDATA_HBTXE) { 1483 strcat(aInfo, ", HB-ISO Tx"); 1484 musb->hb_iso_tx = true; 1485 } 1486 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1487 strcat(aInfo, ", SoftConn"); 1488 1489 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1490 musb_driver_name, reg, aInfo); 1491 1492 aDate[0] = 0; 1493 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1494 musb->is_multipoint = 1; 1495 type = "M"; 1496 } else { 1497 musb->is_multipoint = 0; 1498 type = ""; 1499 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1500 printk(KERN_ERR 1501 "%s: kernel must blacklist external hubs\n", 1502 musb_driver_name); 1503 #endif 1504 } 1505 1506 /* log release info */ 1507 musb->hwvers = musb_read_hwvers(mbase); 1508 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1509 MUSB_HWVERS_MINOR(musb->hwvers), 1510 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1511 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1512 musb_driver_name, type, aRevision, aDate); 1513 1514 /* configure ep0 */ 1515 musb_configure_ep0(musb); 1516 1517 /* discover endpoint configuration */ 1518 musb->nr_endpoints = 1; 1519 musb->epmask = 1; 1520 1521 if (musb->dyn_fifo) 1522 status = ep_config_from_table(musb); 1523 else 1524 status = ep_config_from_hw(musb); 1525 1526 if (status < 0) 1527 return status; 1528 1529 /* finish init, and print endpoint config */ 1530 for (i = 0; i < musb->nr_endpoints; i++) { 1531 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1532 1533 hw_ep->fifo = musb->io.fifo_offset(i) + mbase; 1534 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) 1535 if (musb->io.quirks & MUSB_IN_TUSB) { 1536 hw_ep->fifo_async = musb->async + 0x400 + 1537 musb->io.fifo_offset(i); 1538 hw_ep->fifo_sync = musb->sync + 0x400 + 1539 musb->io.fifo_offset(i); 1540 hw_ep->fifo_sync_va = 1541 musb->sync_va + 0x400 + musb->io.fifo_offset(i); 1542 1543 if (i == 0) 1544 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1545 else 1546 hw_ep->conf = mbase + 0x400 + 1547 (((i - 1) & 0xf) << 2); 1548 } 1549 #endif 1550 1551 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase; 1552 hw_ep->rx_reinit = 1; 1553 hw_ep->tx_reinit = 1; 1554 1555 if (hw_ep->max_packet_sz_tx) { 1556 dev_dbg(musb->controller, 1557 "%s: hw_ep %d%s, %smax %d\n", 1558 musb_driver_name, i, 1559 hw_ep->is_shared_fifo ? "shared" : "tx", 1560 hw_ep->tx_double_buffered 1561 ? "doublebuffer, " : "", 1562 hw_ep->max_packet_sz_tx); 1563 } 1564 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1565 dev_dbg(musb->controller, 1566 "%s: hw_ep %d%s, %smax %d\n", 1567 musb_driver_name, i, 1568 "rx", 1569 hw_ep->rx_double_buffered 1570 ? "doublebuffer, " : "", 1571 hw_ep->max_packet_sz_rx); 1572 } 1573 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1574 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1575 } 1576 1577 return 0; 1578 } 1579 1580 /*-------------------------------------------------------------------------*/ 1581 1582 /* 1583 * handle all the irqs defined by the HDRC core. for now we expect: other 1584 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1585 * will be assigned, and the irq will already have been acked. 1586 * 1587 * called in irq context with spinlock held, irqs blocked 1588 */ 1589 irqreturn_t musb_interrupt(struct musb *musb) 1590 { 1591 irqreturn_t retval = IRQ_NONE; 1592 unsigned long status; 1593 unsigned long epnum; 1594 u8 devctl; 1595 1596 if (!musb->int_usb && !musb->int_tx && !musb->int_rx) 1597 return IRQ_NONE; 1598 1599 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1600 1601 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1602 is_host_active(musb) ? "host" : "peripheral", 1603 musb->int_usb, musb->int_tx, musb->int_rx); 1604 1605 /** 1606 * According to Mentor Graphics' documentation, flowchart on page 98, 1607 * IRQ should be handled as follows: 1608 * 1609 * . Resume IRQ 1610 * . Session Request IRQ 1611 * . VBUS Error IRQ 1612 * . Suspend IRQ 1613 * . Connect IRQ 1614 * . Disconnect IRQ 1615 * . Reset/Babble IRQ 1616 * . SOF IRQ (we're not using this one) 1617 * . Endpoint 0 IRQ 1618 * . TX Endpoints 1619 * . RX Endpoints 1620 * 1621 * We will be following that flowchart in order to avoid any problems 1622 * that might arise with internal Finite State Machine. 1623 */ 1624 1625 if (musb->int_usb) 1626 retval |= musb_stage0_irq(musb, musb->int_usb, devctl); 1627 1628 if (musb->int_tx & 1) { 1629 if (is_host_active(musb)) 1630 retval |= musb_h_ep0_irq(musb); 1631 else 1632 retval |= musb_g_ep0_irq(musb); 1633 1634 /* we have just handled endpoint 0 IRQ, clear it */ 1635 musb->int_tx &= ~BIT(0); 1636 } 1637 1638 status = musb->int_tx; 1639 1640 for_each_set_bit(epnum, &status, 16) { 1641 retval = IRQ_HANDLED; 1642 if (is_host_active(musb)) 1643 musb_host_tx(musb, epnum); 1644 else 1645 musb_g_tx(musb, epnum); 1646 } 1647 1648 status = musb->int_rx; 1649 1650 for_each_set_bit(epnum, &status, 16) { 1651 retval = IRQ_HANDLED; 1652 if (is_host_active(musb)) 1653 musb_host_rx(musb, epnum); 1654 else 1655 musb_g_rx(musb, epnum); 1656 } 1657 1658 return retval; 1659 } 1660 EXPORT_SYMBOL_GPL(musb_interrupt); 1661 1662 #ifndef CONFIG_MUSB_PIO_ONLY 1663 static bool use_dma = 1; 1664 1665 /* "modprobe ... use_dma=0" etc */ 1666 module_param(use_dma, bool, 0); 1667 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1668 1669 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1670 { 1671 /* called with controller lock already held */ 1672 1673 if (!epnum) { 1674 if (!is_cppi_enabled(musb)) { 1675 /* endpoint 0 */ 1676 if (is_host_active(musb)) 1677 musb_h_ep0_irq(musb); 1678 else 1679 musb_g_ep0_irq(musb); 1680 } 1681 } else { 1682 /* endpoints 1..15 */ 1683 if (transmit) { 1684 if (is_host_active(musb)) 1685 musb_host_tx(musb, epnum); 1686 else 1687 musb_g_tx(musb, epnum); 1688 } else { 1689 /* receive */ 1690 if (is_host_active(musb)) 1691 musb_host_rx(musb, epnum); 1692 else 1693 musb_g_rx(musb, epnum); 1694 } 1695 } 1696 } 1697 EXPORT_SYMBOL_GPL(musb_dma_completion); 1698 1699 #else 1700 #define use_dma 0 1701 #endif 1702 1703 /*-------------------------------------------------------------------------*/ 1704 1705 static ssize_t 1706 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1707 { 1708 struct musb *musb = dev_to_musb(dev); 1709 unsigned long flags; 1710 int ret = -EINVAL; 1711 1712 spin_lock_irqsave(&musb->lock, flags); 1713 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state)); 1714 spin_unlock_irqrestore(&musb->lock, flags); 1715 1716 return ret; 1717 } 1718 1719 static ssize_t 1720 musb_mode_store(struct device *dev, struct device_attribute *attr, 1721 const char *buf, size_t n) 1722 { 1723 struct musb *musb = dev_to_musb(dev); 1724 unsigned long flags; 1725 int status; 1726 1727 spin_lock_irqsave(&musb->lock, flags); 1728 if (sysfs_streq(buf, "host")) 1729 status = musb_platform_set_mode(musb, MUSB_HOST); 1730 else if (sysfs_streq(buf, "peripheral")) 1731 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1732 else if (sysfs_streq(buf, "otg")) 1733 status = musb_platform_set_mode(musb, MUSB_OTG); 1734 else 1735 status = -EINVAL; 1736 spin_unlock_irqrestore(&musb->lock, flags); 1737 1738 return (status == 0) ? n : status; 1739 } 1740 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1741 1742 static ssize_t 1743 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1744 const char *buf, size_t n) 1745 { 1746 struct musb *musb = dev_to_musb(dev); 1747 unsigned long flags; 1748 unsigned long val; 1749 1750 if (sscanf(buf, "%lu", &val) < 1) { 1751 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1752 return -EINVAL; 1753 } 1754 1755 spin_lock_irqsave(&musb->lock, flags); 1756 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1757 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1758 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) 1759 musb->is_active = 0; 1760 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1761 spin_unlock_irqrestore(&musb->lock, flags); 1762 1763 return n; 1764 } 1765 1766 static ssize_t 1767 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1768 { 1769 struct musb *musb = dev_to_musb(dev); 1770 unsigned long flags; 1771 unsigned long val; 1772 int vbus; 1773 1774 spin_lock_irqsave(&musb->lock, flags); 1775 val = musb->a_wait_bcon; 1776 /* FIXME get_vbus_status() is normally #defined as false... 1777 * and is effectively TUSB-specific. 1778 */ 1779 vbus = musb_platform_get_vbus_status(musb); 1780 spin_unlock_irqrestore(&musb->lock, flags); 1781 1782 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1783 vbus ? "on" : "off", val); 1784 } 1785 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1786 1787 /* Gadget drivers can't know that a host is connected so they might want 1788 * to start SRP, but users can. This allows userspace to trigger SRP. 1789 */ 1790 static ssize_t 1791 musb_srp_store(struct device *dev, struct device_attribute *attr, 1792 const char *buf, size_t n) 1793 { 1794 struct musb *musb = dev_to_musb(dev); 1795 unsigned short srp; 1796 1797 if (sscanf(buf, "%hu", &srp) != 1 1798 || (srp != 1)) { 1799 dev_err(dev, "SRP: Value must be 1\n"); 1800 return -EINVAL; 1801 } 1802 1803 if (srp == 1) 1804 musb_g_wakeup(musb); 1805 1806 return n; 1807 } 1808 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1809 1810 static struct attribute *musb_attributes[] = { 1811 &dev_attr_mode.attr, 1812 &dev_attr_vbus.attr, 1813 &dev_attr_srp.attr, 1814 NULL 1815 }; 1816 1817 static const struct attribute_group musb_attr_group = { 1818 .attrs = musb_attributes, 1819 }; 1820 1821 /* Only used to provide driver mode change events */ 1822 static void musb_irq_work(struct work_struct *data) 1823 { 1824 struct musb *musb = container_of(data, struct musb, irq_work); 1825 1826 if (musb->xceiv->otg->state != musb->xceiv_old_state) { 1827 musb->xceiv_old_state = musb->xceiv->otg->state; 1828 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1829 } 1830 } 1831 1832 static void musb_recover_from_babble(struct musb *musb) 1833 { 1834 int ret; 1835 u8 devctl; 1836 1837 musb_disable_interrupts(musb); 1838 1839 /* 1840 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give 1841 * it some slack and wait for 10us. 1842 */ 1843 udelay(10); 1844 1845 ret = musb_platform_recover(musb); 1846 if (ret) { 1847 musb_enable_interrupts(musb); 1848 return; 1849 } 1850 1851 /* drop session bit */ 1852 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1853 devctl &= ~MUSB_DEVCTL_SESSION; 1854 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 1855 1856 /* tell usbcore about it */ 1857 musb_root_disconnect(musb); 1858 1859 /* 1860 * When a babble condition occurs, the musb controller 1861 * removes the session bit and the endpoint config is lost. 1862 */ 1863 if (musb->dyn_fifo) 1864 ret = ep_config_from_table(musb); 1865 else 1866 ret = ep_config_from_hw(musb); 1867 1868 /* restart session */ 1869 if (ret == 0) 1870 musb_start(musb); 1871 } 1872 1873 /* -------------------------------------------------------------------------- 1874 * Init support 1875 */ 1876 1877 static struct musb *allocate_instance(struct device *dev, 1878 struct musb_hdrc_config *config, void __iomem *mbase) 1879 { 1880 struct musb *musb; 1881 struct musb_hw_ep *ep; 1882 int epnum; 1883 int ret; 1884 1885 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); 1886 if (!musb) 1887 return NULL; 1888 1889 INIT_LIST_HEAD(&musb->control); 1890 INIT_LIST_HEAD(&musb->in_bulk); 1891 INIT_LIST_HEAD(&musb->out_bulk); 1892 1893 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1894 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1895 musb->mregs = mbase; 1896 musb->ctrl_base = mbase; 1897 musb->nIrq = -ENODEV; 1898 musb->config = config; 1899 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1900 for (epnum = 0, ep = musb->endpoints; 1901 epnum < musb->config->num_eps; 1902 epnum++, ep++) { 1903 ep->musb = musb; 1904 ep->epnum = epnum; 1905 } 1906 1907 musb->controller = dev; 1908 1909 ret = musb_host_alloc(musb); 1910 if (ret < 0) 1911 goto err_free; 1912 1913 dev_set_drvdata(dev, musb); 1914 1915 return musb; 1916 1917 err_free: 1918 return NULL; 1919 } 1920 1921 static void musb_free(struct musb *musb) 1922 { 1923 /* this has multiple entry modes. it handles fault cleanup after 1924 * probe(), where things may be partially set up, as well as rmmod 1925 * cleanup after everything's been de-activated. 1926 */ 1927 1928 #ifdef CONFIG_SYSFS 1929 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1930 #endif 1931 1932 if (musb->nIrq >= 0) { 1933 if (musb->irq_wake) 1934 disable_irq_wake(musb->nIrq); 1935 free_irq(musb->nIrq, musb); 1936 } 1937 1938 musb_host_free(musb); 1939 } 1940 1941 static void musb_deassert_reset(struct work_struct *work) 1942 { 1943 struct musb *musb; 1944 unsigned long flags; 1945 1946 musb = container_of(work, struct musb, deassert_reset_work.work); 1947 1948 spin_lock_irqsave(&musb->lock, flags); 1949 1950 if (musb->port1_status & USB_PORT_STAT_RESET) 1951 musb_port_reset(musb, false); 1952 1953 spin_unlock_irqrestore(&musb->lock, flags); 1954 } 1955 1956 /* 1957 * Perform generic per-controller initialization. 1958 * 1959 * @dev: the controller (already clocked, etc) 1960 * @nIrq: IRQ number 1961 * @ctrl: virtual address of controller registers, 1962 * not yet corrected for platform-specific offsets 1963 */ 1964 static int 1965 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1966 { 1967 int status; 1968 struct musb *musb; 1969 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 1970 1971 /* The driver might handle more features than the board; OK. 1972 * Fail when the board needs a feature that's not enabled. 1973 */ 1974 if (!plat) { 1975 dev_dbg(dev, "no platform_data?\n"); 1976 status = -ENODEV; 1977 goto fail0; 1978 } 1979 1980 /* allocate */ 1981 musb = allocate_instance(dev, plat->config, ctrl); 1982 if (!musb) { 1983 status = -ENOMEM; 1984 goto fail0; 1985 } 1986 1987 spin_lock_init(&musb->lock); 1988 musb->board_set_power = plat->set_power; 1989 musb->min_power = plat->min_power; 1990 musb->ops = plat->platform_ops; 1991 musb->port_mode = plat->mode; 1992 1993 /* 1994 * Initialize the default IO functions. At least omap2430 needs 1995 * these early. We initialize the platform specific IO functions 1996 * later on. 1997 */ 1998 musb_readb = musb_default_readb; 1999 musb_writeb = musb_default_writeb; 2000 musb_readw = musb_default_readw; 2001 musb_writew = musb_default_writew; 2002 musb_readl = musb_default_readl; 2003 musb_writel = musb_default_writel; 2004 2005 /* We need musb_read/write functions initialized for PM */ 2006 pm_runtime_use_autosuspend(musb->controller); 2007 pm_runtime_set_autosuspend_delay(musb->controller, 200); 2008 pm_runtime_irq_safe(musb->controller); 2009 pm_runtime_enable(musb->controller); 2010 2011 /* The musb_platform_init() call: 2012 * - adjusts musb->mregs 2013 * - sets the musb->isr 2014 * - may initialize an integrated transceiver 2015 * - initializes musb->xceiv, usually by otg_get_phy() 2016 * - stops powering VBUS 2017 * 2018 * There are various transceiver configurations. Blackfin, 2019 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 2020 * external/discrete ones in various flavors (twl4030 family, 2021 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2022 */ 2023 status = musb_platform_init(musb); 2024 if (status < 0) 2025 goto fail1; 2026 2027 if (!musb->isr) { 2028 status = -ENODEV; 2029 goto fail2; 2030 } 2031 2032 if (musb->ops->quirks) 2033 musb->io.quirks = musb->ops->quirks; 2034 2035 /* Most devices use indexed offset or flat offset */ 2036 if (musb->io.quirks & MUSB_INDEXED_EP) { 2037 musb->io.ep_offset = musb_indexed_ep_offset; 2038 musb->io.ep_select = musb_indexed_ep_select; 2039 } else { 2040 musb->io.ep_offset = musb_flat_ep_offset; 2041 musb->io.ep_select = musb_flat_ep_select; 2042 } 2043 /* And override them with platform specific ops if specified. */ 2044 if (musb->ops->ep_offset) 2045 musb->io.ep_offset = musb->ops->ep_offset; 2046 if (musb->ops->ep_select) 2047 musb->io.ep_select = musb->ops->ep_select; 2048 2049 /* At least tusb6010 has its own offsets */ 2050 if (musb->ops->ep_offset) 2051 musb->io.ep_offset = musb->ops->ep_offset; 2052 if (musb->ops->ep_select) 2053 musb->io.ep_select = musb->ops->ep_select; 2054 2055 if (musb->ops->fifo_mode) 2056 fifo_mode = musb->ops->fifo_mode; 2057 else 2058 fifo_mode = 4; 2059 2060 if (musb->ops->fifo_offset) 2061 musb->io.fifo_offset = musb->ops->fifo_offset; 2062 else 2063 musb->io.fifo_offset = musb_default_fifo_offset; 2064 2065 if (musb->ops->busctl_offset) 2066 musb->io.busctl_offset = musb->ops->busctl_offset; 2067 else 2068 musb->io.busctl_offset = musb_default_busctl_offset; 2069 2070 if (musb->ops->readb) 2071 musb_readb = musb->ops->readb; 2072 if (musb->ops->writeb) 2073 musb_writeb = musb->ops->writeb; 2074 if (musb->ops->readw) 2075 musb_readw = musb->ops->readw; 2076 if (musb->ops->writew) 2077 musb_writew = musb->ops->writew; 2078 if (musb->ops->readl) 2079 musb_readl = musb->ops->readl; 2080 if (musb->ops->writel) 2081 musb_writel = musb->ops->writel; 2082 2083 #ifndef CONFIG_MUSB_PIO_ONLY 2084 if (!musb->ops->dma_init || !musb->ops->dma_exit) { 2085 dev_err(dev, "DMA controller not set\n"); 2086 goto fail2; 2087 } 2088 musb_dma_controller_create = musb->ops->dma_init; 2089 musb_dma_controller_destroy = musb->ops->dma_exit; 2090 #endif 2091 2092 if (musb->ops->read_fifo) 2093 musb->io.read_fifo = musb->ops->read_fifo; 2094 else 2095 musb->io.read_fifo = musb_default_read_fifo; 2096 2097 if (musb->ops->write_fifo) 2098 musb->io.write_fifo = musb->ops->write_fifo; 2099 else 2100 musb->io.write_fifo = musb_default_write_fifo; 2101 2102 if (!musb->xceiv->io_ops) { 2103 musb->xceiv->io_dev = musb->controller; 2104 musb->xceiv->io_priv = musb->mregs; 2105 musb->xceiv->io_ops = &musb_ulpi_access; 2106 } 2107 2108 pm_runtime_get_sync(musb->controller); 2109 2110 if (use_dma && dev->dma_mask) { 2111 musb->dma_controller = 2112 musb_dma_controller_create(musb, musb->mregs); 2113 if (IS_ERR(musb->dma_controller)) { 2114 status = PTR_ERR(musb->dma_controller); 2115 goto fail2_5; 2116 } 2117 } 2118 2119 /* be sure interrupts are disabled before connecting ISR */ 2120 musb_platform_disable(musb); 2121 musb_generic_disable(musb); 2122 2123 /* Init IRQ workqueue before request_irq */ 2124 INIT_WORK(&musb->irq_work, musb_irq_work); 2125 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); 2126 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); 2127 2128 /* setup musb parts of the core (especially endpoints) */ 2129 status = musb_core_init(plat->config->multipoint 2130 ? MUSB_CONTROLLER_MHDRC 2131 : MUSB_CONTROLLER_HDRC, musb); 2132 if (status < 0) 2133 goto fail3; 2134 2135 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2136 2137 /* attach to the IRQ */ 2138 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2139 dev_err(dev, "request_irq %d failed!\n", nIrq); 2140 status = -ENODEV; 2141 goto fail3; 2142 } 2143 musb->nIrq = nIrq; 2144 /* FIXME this handles wakeup irqs wrong */ 2145 if (enable_irq_wake(nIrq) == 0) { 2146 musb->irq_wake = 1; 2147 device_init_wakeup(dev, 1); 2148 } else { 2149 musb->irq_wake = 0; 2150 } 2151 2152 /* program PHY to use external vBus if required */ 2153 if (plat->extvbus) { 2154 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2155 busctl |= MUSB_ULPI_USE_EXTVBUS; 2156 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2157 } 2158 2159 if (musb->xceiv->otg->default_a) { 2160 MUSB_HST_MODE(musb); 2161 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 2162 } else { 2163 MUSB_DEV_MODE(musb); 2164 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 2165 } 2166 2167 switch (musb->port_mode) { 2168 case MUSB_PORT_MODE_HOST: 2169 status = musb_host_setup(musb, plat->power); 2170 if (status < 0) 2171 goto fail3; 2172 status = musb_platform_set_mode(musb, MUSB_HOST); 2173 break; 2174 case MUSB_PORT_MODE_GADGET: 2175 status = musb_gadget_setup(musb); 2176 if (status < 0) 2177 goto fail3; 2178 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 2179 break; 2180 case MUSB_PORT_MODE_DUAL_ROLE: 2181 status = musb_host_setup(musb, plat->power); 2182 if (status < 0) 2183 goto fail3; 2184 status = musb_gadget_setup(musb); 2185 if (status) { 2186 musb_host_cleanup(musb); 2187 goto fail3; 2188 } 2189 status = musb_platform_set_mode(musb, MUSB_OTG); 2190 break; 2191 default: 2192 dev_err(dev, "unsupported port mode %d\n", musb->port_mode); 2193 break; 2194 } 2195 2196 if (status < 0) 2197 goto fail3; 2198 2199 status = musb_init_debugfs(musb); 2200 if (status < 0) 2201 goto fail4; 2202 2203 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2204 if (status) 2205 goto fail5; 2206 2207 pm_runtime_put(musb->controller); 2208 2209 return 0; 2210 2211 fail5: 2212 musb_exit_debugfs(musb); 2213 2214 fail4: 2215 musb_gadget_cleanup(musb); 2216 musb_host_cleanup(musb); 2217 2218 fail3: 2219 cancel_work_sync(&musb->irq_work); 2220 cancel_delayed_work_sync(&musb->finish_resume_work); 2221 cancel_delayed_work_sync(&musb->deassert_reset_work); 2222 if (musb->dma_controller) 2223 musb_dma_controller_destroy(musb->dma_controller); 2224 fail2_5: 2225 pm_runtime_put_sync(musb->controller); 2226 2227 fail2: 2228 if (musb->irq_wake) 2229 device_init_wakeup(dev, 0); 2230 musb_platform_exit(musb); 2231 2232 fail1: 2233 pm_runtime_disable(musb->controller); 2234 dev_err(musb->controller, 2235 "musb_init_controller failed with status %d\n", status); 2236 2237 musb_free(musb); 2238 2239 fail0: 2240 2241 return status; 2242 2243 } 2244 2245 /*-------------------------------------------------------------------------*/ 2246 2247 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2248 * bridge to a platform device; this driver then suffices. 2249 */ 2250 static int musb_probe(struct platform_device *pdev) 2251 { 2252 struct device *dev = &pdev->dev; 2253 int irq = platform_get_irq_byname(pdev, "mc"); 2254 struct resource *iomem; 2255 void __iomem *base; 2256 2257 if (irq <= 0) 2258 return -ENODEV; 2259 2260 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2261 base = devm_ioremap_resource(dev, iomem); 2262 if (IS_ERR(base)) 2263 return PTR_ERR(base); 2264 2265 return musb_init_controller(dev, irq, base); 2266 } 2267 2268 static int musb_remove(struct platform_device *pdev) 2269 { 2270 struct device *dev = &pdev->dev; 2271 struct musb *musb = dev_to_musb(dev); 2272 2273 /* this gets called on rmmod. 2274 * - Host mode: host may still be active 2275 * - Peripheral mode: peripheral is deactivated (or never-activated) 2276 * - OTG mode: both roles are deactivated (or never-activated) 2277 */ 2278 musb_exit_debugfs(musb); 2279 musb_shutdown(pdev); 2280 2281 if (musb->dma_controller) 2282 musb_dma_controller_destroy(musb->dma_controller); 2283 2284 cancel_work_sync(&musb->irq_work); 2285 cancel_delayed_work_sync(&musb->finish_resume_work); 2286 cancel_delayed_work_sync(&musb->deassert_reset_work); 2287 musb_free(musb); 2288 device_init_wakeup(dev, 0); 2289 return 0; 2290 } 2291 2292 #ifdef CONFIG_PM 2293 2294 static void musb_save_context(struct musb *musb) 2295 { 2296 int i; 2297 void __iomem *musb_base = musb->mregs; 2298 void __iomem *epio; 2299 2300 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2301 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2302 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2303 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2304 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2305 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2306 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2307 2308 for (i = 0; i < musb->config->num_eps; ++i) { 2309 struct musb_hw_ep *hw_ep; 2310 2311 hw_ep = &musb->endpoints[i]; 2312 if (!hw_ep) 2313 continue; 2314 2315 epio = hw_ep->regs; 2316 if (!epio) 2317 continue; 2318 2319 musb_writeb(musb_base, MUSB_INDEX, i); 2320 musb->context.index_regs[i].txmaxp = 2321 musb_readw(epio, MUSB_TXMAXP); 2322 musb->context.index_regs[i].txcsr = 2323 musb_readw(epio, MUSB_TXCSR); 2324 musb->context.index_regs[i].rxmaxp = 2325 musb_readw(epio, MUSB_RXMAXP); 2326 musb->context.index_regs[i].rxcsr = 2327 musb_readw(epio, MUSB_RXCSR); 2328 2329 if (musb->dyn_fifo) { 2330 musb->context.index_regs[i].txfifoadd = 2331 musb_read_txfifoadd(musb_base); 2332 musb->context.index_regs[i].rxfifoadd = 2333 musb_read_rxfifoadd(musb_base); 2334 musb->context.index_regs[i].txfifosz = 2335 musb_read_txfifosz(musb_base); 2336 musb->context.index_regs[i].rxfifosz = 2337 musb_read_rxfifosz(musb_base); 2338 } 2339 2340 musb->context.index_regs[i].txtype = 2341 musb_readb(epio, MUSB_TXTYPE); 2342 musb->context.index_regs[i].txinterval = 2343 musb_readb(epio, MUSB_TXINTERVAL); 2344 musb->context.index_regs[i].rxtype = 2345 musb_readb(epio, MUSB_RXTYPE); 2346 musb->context.index_regs[i].rxinterval = 2347 musb_readb(epio, MUSB_RXINTERVAL); 2348 2349 musb->context.index_regs[i].txfunaddr = 2350 musb_read_txfunaddr(musb, i); 2351 musb->context.index_regs[i].txhubaddr = 2352 musb_read_txhubaddr(musb, i); 2353 musb->context.index_regs[i].txhubport = 2354 musb_read_txhubport(musb, i); 2355 2356 musb->context.index_regs[i].rxfunaddr = 2357 musb_read_rxfunaddr(musb, i); 2358 musb->context.index_regs[i].rxhubaddr = 2359 musb_read_rxhubaddr(musb, i); 2360 musb->context.index_regs[i].rxhubport = 2361 musb_read_rxhubport(musb, i); 2362 } 2363 } 2364 2365 static void musb_restore_context(struct musb *musb) 2366 { 2367 int i; 2368 void __iomem *musb_base = musb->mregs; 2369 void __iomem *epio; 2370 u8 power; 2371 2372 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2373 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2374 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2375 2376 /* Don't affect SUSPENDM/RESUME bits in POWER reg */ 2377 power = musb_readb(musb_base, MUSB_POWER); 2378 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; 2379 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); 2380 power |= musb->context.power; 2381 musb_writeb(musb_base, MUSB_POWER, power); 2382 2383 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); 2384 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); 2385 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2386 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2387 2388 for (i = 0; i < musb->config->num_eps; ++i) { 2389 struct musb_hw_ep *hw_ep; 2390 2391 hw_ep = &musb->endpoints[i]; 2392 if (!hw_ep) 2393 continue; 2394 2395 epio = hw_ep->regs; 2396 if (!epio) 2397 continue; 2398 2399 musb_writeb(musb_base, MUSB_INDEX, i); 2400 musb_writew(epio, MUSB_TXMAXP, 2401 musb->context.index_regs[i].txmaxp); 2402 musb_writew(epio, MUSB_TXCSR, 2403 musb->context.index_regs[i].txcsr); 2404 musb_writew(epio, MUSB_RXMAXP, 2405 musb->context.index_regs[i].rxmaxp); 2406 musb_writew(epio, MUSB_RXCSR, 2407 musb->context.index_regs[i].rxcsr); 2408 2409 if (musb->dyn_fifo) { 2410 musb_write_txfifosz(musb_base, 2411 musb->context.index_regs[i].txfifosz); 2412 musb_write_rxfifosz(musb_base, 2413 musb->context.index_regs[i].rxfifosz); 2414 musb_write_txfifoadd(musb_base, 2415 musb->context.index_regs[i].txfifoadd); 2416 musb_write_rxfifoadd(musb_base, 2417 musb->context.index_regs[i].rxfifoadd); 2418 } 2419 2420 musb_writeb(epio, MUSB_TXTYPE, 2421 musb->context.index_regs[i].txtype); 2422 musb_writeb(epio, MUSB_TXINTERVAL, 2423 musb->context.index_regs[i].txinterval); 2424 musb_writeb(epio, MUSB_RXTYPE, 2425 musb->context.index_regs[i].rxtype); 2426 musb_writeb(epio, MUSB_RXINTERVAL, 2427 2428 musb->context.index_regs[i].rxinterval); 2429 musb_write_txfunaddr(musb, i, 2430 musb->context.index_regs[i].txfunaddr); 2431 musb_write_txhubaddr(musb, i, 2432 musb->context.index_regs[i].txhubaddr); 2433 musb_write_txhubport(musb, i, 2434 musb->context.index_regs[i].txhubport); 2435 2436 musb_write_rxfunaddr(musb, i, 2437 musb->context.index_regs[i].rxfunaddr); 2438 musb_write_rxhubaddr(musb, i, 2439 musb->context.index_regs[i].rxhubaddr); 2440 musb_write_rxhubport(musb, i, 2441 musb->context.index_regs[i].rxhubport); 2442 } 2443 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2444 } 2445 2446 static int musb_suspend(struct device *dev) 2447 { 2448 struct musb *musb = dev_to_musb(dev); 2449 unsigned long flags; 2450 2451 spin_lock_irqsave(&musb->lock, flags); 2452 2453 if (is_peripheral_active(musb)) { 2454 /* FIXME force disconnect unless we know USB will wake 2455 * the system up quickly enough to respond ... 2456 */ 2457 } else if (is_host_active(musb)) { 2458 /* we know all the children are suspended; sometimes 2459 * they will even be wakeup-enabled. 2460 */ 2461 } 2462 2463 musb_save_context(musb); 2464 2465 spin_unlock_irqrestore(&musb->lock, flags); 2466 return 0; 2467 } 2468 2469 static int musb_resume(struct device *dev) 2470 { 2471 struct musb *musb = dev_to_musb(dev); 2472 u8 devctl; 2473 u8 mask; 2474 2475 /* 2476 * For static cmos like DaVinci, register values were preserved 2477 * unless for some reason the whole soc powered down or the USB 2478 * module got reset through the PSC (vs just being disabled). 2479 * 2480 * For the DSPS glue layer though, a full register restore has to 2481 * be done. As it shouldn't harm other platforms, we do it 2482 * unconditionally. 2483 */ 2484 2485 musb_restore_context(musb); 2486 2487 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2488 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; 2489 if ((devctl & mask) != (musb->context.devctl & mask)) 2490 musb->port1_status = 0; 2491 if (musb->need_finish_resume) { 2492 musb->need_finish_resume = 0; 2493 schedule_delayed_work(&musb->finish_resume_work, 2494 msecs_to_jiffies(USB_RESUME_TIMEOUT)); 2495 } 2496 2497 /* 2498 * The USB HUB code expects the device to be in RPM_ACTIVE once it came 2499 * out of suspend 2500 */ 2501 pm_runtime_disable(dev); 2502 pm_runtime_set_active(dev); 2503 pm_runtime_enable(dev); 2504 return 0; 2505 } 2506 2507 static int musb_runtime_suspend(struct device *dev) 2508 { 2509 struct musb *musb = dev_to_musb(dev); 2510 2511 musb_save_context(musb); 2512 2513 return 0; 2514 } 2515 2516 static int musb_runtime_resume(struct device *dev) 2517 { 2518 struct musb *musb = dev_to_musb(dev); 2519 static int first = 1; 2520 2521 /* 2522 * When pm_runtime_get_sync called for the first time in driver 2523 * init, some of the structure is still not initialized which is 2524 * used in restore function. But clock needs to be 2525 * enabled before any register access, so 2526 * pm_runtime_get_sync has to be called. 2527 * Also context restore without save does not make 2528 * any sense 2529 */ 2530 if (!first) 2531 musb_restore_context(musb); 2532 first = 0; 2533 2534 if (musb->need_finish_resume) { 2535 musb->need_finish_resume = 0; 2536 schedule_delayed_work(&musb->finish_resume_work, 2537 msecs_to_jiffies(USB_RESUME_TIMEOUT)); 2538 } 2539 2540 return 0; 2541 } 2542 2543 static const struct dev_pm_ops musb_dev_pm_ops = { 2544 .suspend = musb_suspend, 2545 .resume = musb_resume, 2546 .runtime_suspend = musb_runtime_suspend, 2547 .runtime_resume = musb_runtime_resume, 2548 }; 2549 2550 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2551 #else 2552 #define MUSB_DEV_PM_OPS NULL 2553 #endif 2554 2555 static struct platform_driver musb_driver = { 2556 .driver = { 2557 .name = (char *)musb_driver_name, 2558 .bus = &platform_bus_type, 2559 .pm = MUSB_DEV_PM_OPS, 2560 }, 2561 .probe = musb_probe, 2562 .remove = musb_remove, 2563 .shutdown = musb_shutdown, 2564 }; 2565 2566 module_platform_driver(musb_driver); 2567