xref: /openbmc/linux/drivers/usb/musb/musb_core.c (revision b6dcefde)
1 /*
2  * MUSB OTG driver core code
3  *
4  * Copyright 2005 Mentor Graphics Corporation
5  * Copyright (C) 2005-2006 by Texas Instruments
6  * Copyright (C) 2006-2007 Nokia Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  */
34 
35 /*
36  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37  *
38  * This consists of a Host Controller Driver (HCD) and a peripheral
39  * controller driver implementing the "Gadget" API; OTG support is
40  * in the works.  These are normal Linux-USB controller drivers which
41  * use IRQs and have no dedicated thread.
42  *
43  * This version of the driver has only been used with products from
44  * Texas Instruments.  Those products integrate the Inventra logic
45  * with other DMA, IRQ, and bus modules, as well as other logic that
46  * needs to be reflected in this driver.
47  *
48  *
49  * NOTE:  the original Mentor code here was pretty much a collection
50  * of mechanisms that don't seem to have been fully integrated/working
51  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
52  * Key open issues include:
53  *
54  *  - Lack of host-side transaction scheduling, for all transfer types.
55  *    The hardware doesn't do it; instead, software must.
56  *
57  *    This is not an issue for OTG devices that don't support external
58  *    hubs, but for more "normal" USB hosts it's a user issue that the
59  *    "multipoint" support doesn't scale in the expected ways.  That
60  *    includes DaVinci EVM in a common non-OTG mode.
61  *
62  *      * Control and bulk use dedicated endpoints, and there's as
63  *        yet no mechanism to either (a) reclaim the hardware when
64  *        peripherals are NAKing, which gets complicated with bulk
65  *        endpoints, or (b) use more than a single bulk endpoint in
66  *        each direction.
67  *
68  *        RESULT:  one device may be perceived as blocking another one.
69  *
70  *      * Interrupt and isochronous will dynamically allocate endpoint
71  *        hardware, but (a) there's no record keeping for bandwidth;
72  *        (b) in the common case that few endpoints are available, there
73  *        is no mechanism to reuse endpoints to talk to multiple devices.
74  *
75  *        RESULT:  At one extreme, bandwidth can be overcommitted in
76  *        some hardware configurations, no faults will be reported.
77  *        At the other extreme, the bandwidth capabilities which do
78  *        exist tend to be severely undercommitted.  You can't yet hook
79  *        up both a keyboard and a mouse to an external USB hub.
80  */
81 
82 /*
83  * This gets many kinds of configuration information:
84  *	- Kconfig for everything user-configurable
85  *	- platform_device for addressing, irq, and platform_data
86  *	- platform_data is mostly for board-specific informarion
87  *	  (plus recentrly, SOC or family details)
88  *
89  * Most of the conditional compilation will (someday) vanish.
90  */
91 
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 
102 #ifdef	CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107 
108 #include "musb_core.h"
109 
110 
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114 
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
116 
117 
118 unsigned musb_debug;
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121 
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124 
125 #define MUSB_VERSION "6.0"
126 
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128 
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131 
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136 
137 
138 /*-------------------------------------------------------------------------*/
139 
140 static inline struct musb *dev_to_musb(struct device *dev)
141 {
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 	/* usbcore insists dev->driver_data is a "struct hcd *" */
144 	return hcd_to_musb(dev_get_drvdata(dev));
145 #else
146 	return dev_get_drvdata(dev);
147 #endif
148 }
149 
150 /*-------------------------------------------------------------------------*/
151 
152 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
153 
154 /*
155  * Load an endpoint's FIFO
156  */
157 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
158 {
159 	void __iomem *fifo = hw_ep->fifo;
160 
161 	prefetch((u8 *)src);
162 
163 	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
164 			'T', hw_ep->epnum, fifo, len, src);
165 
166 	/* we can't assume unaligned reads work */
167 	if (likely((0x01 & (unsigned long) src) == 0)) {
168 		u16	index = 0;
169 
170 		/* best case is 32bit-aligned source address */
171 		if ((0x02 & (unsigned long) src) == 0) {
172 			if (len >= 4) {
173 				writesl(fifo, src + index, len >> 2);
174 				index += len & ~0x03;
175 			}
176 			if (len & 0x02) {
177 				musb_writew(fifo, 0, *(u16 *)&src[index]);
178 				index += 2;
179 			}
180 		} else {
181 			if (len >= 2) {
182 				writesw(fifo, src + index, len >> 1);
183 				index += len & ~0x01;
184 			}
185 		}
186 		if (len & 0x01)
187 			musb_writeb(fifo, 0, src[index]);
188 	} else  {
189 		/* byte aligned */
190 		writesb(fifo, src, len);
191 	}
192 }
193 
194 /*
195  * Unload an endpoint's FIFO
196  */
197 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
198 {
199 	void __iomem *fifo = hw_ep->fifo;
200 
201 	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
202 			'R', hw_ep->epnum, fifo, len, dst);
203 
204 	/* we can't assume unaligned writes work */
205 	if (likely((0x01 & (unsigned long) dst) == 0)) {
206 		u16	index = 0;
207 
208 		/* best case is 32bit-aligned destination address */
209 		if ((0x02 & (unsigned long) dst) == 0) {
210 			if (len >= 4) {
211 				readsl(fifo, dst, len >> 2);
212 				index = len & ~0x03;
213 			}
214 			if (len & 0x02) {
215 				*(u16 *)&dst[index] = musb_readw(fifo, 0);
216 				index += 2;
217 			}
218 		} else {
219 			if (len >= 2) {
220 				readsw(fifo, dst, len >> 1);
221 				index = len & ~0x01;
222 			}
223 		}
224 		if (len & 0x01)
225 			dst[index] = musb_readb(fifo, 0);
226 	} else  {
227 		/* byte aligned */
228 		readsb(fifo, dst, len);
229 	}
230 }
231 
232 #endif	/* normal PIO */
233 
234 
235 /*-------------------------------------------------------------------------*/
236 
237 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
238 static const u8 musb_test_packet[53] = {
239 	/* implicit SYNC then DATA0 to start */
240 
241 	/* JKJKJKJK x9 */
242 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 	/* JJKKJJKK x8 */
244 	0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
245 	/* JJJJKKKK x8 */
246 	0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
247 	/* JJJJJJJKKKKKKK x8 */
248 	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
249 	/* JJJJJJJK x8 */
250 	0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
251 	/* JKKKKKKK x10, JK */
252 	0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
253 
254 	/* implicit CRC16 then EOP to end */
255 };
256 
257 void musb_load_testpacket(struct musb *musb)
258 {
259 	void __iomem	*regs = musb->endpoints[0].regs;
260 
261 	musb_ep_select(musb->mregs, 0);
262 	musb_write_fifo(musb->control_ep,
263 			sizeof(musb_test_packet), musb_test_packet);
264 	musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
265 }
266 
267 /*-------------------------------------------------------------------------*/
268 
269 const char *otg_state_string(struct musb *musb)
270 {
271 	switch (musb->xceiv->state) {
272 	case OTG_STATE_A_IDLE:		return "a_idle";
273 	case OTG_STATE_A_WAIT_VRISE:	return "a_wait_vrise";
274 	case OTG_STATE_A_WAIT_BCON:	return "a_wait_bcon";
275 	case OTG_STATE_A_HOST:		return "a_host";
276 	case OTG_STATE_A_SUSPEND:	return "a_suspend";
277 	case OTG_STATE_A_PERIPHERAL:	return "a_peripheral";
278 	case OTG_STATE_A_WAIT_VFALL:	return "a_wait_vfall";
279 	case OTG_STATE_A_VBUS_ERR:	return "a_vbus_err";
280 	case OTG_STATE_B_IDLE:		return "b_idle";
281 	case OTG_STATE_B_SRP_INIT:	return "b_srp_init";
282 	case OTG_STATE_B_PERIPHERAL:	return "b_peripheral";
283 	case OTG_STATE_B_WAIT_ACON:	return "b_wait_acon";
284 	case OTG_STATE_B_HOST:		return "b_host";
285 	default:			return "UNDEFINED";
286 	}
287 }
288 
289 #ifdef	CONFIG_USB_MUSB_OTG
290 
291 /*
292  * Handles OTG hnp timeouts, such as b_ase0_brst
293  */
294 void musb_otg_timer_func(unsigned long data)
295 {
296 	struct musb	*musb = (struct musb *)data;
297 	unsigned long	flags;
298 
299 	spin_lock_irqsave(&musb->lock, flags);
300 	switch (musb->xceiv->state) {
301 	case OTG_STATE_B_WAIT_ACON:
302 		DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
303 		musb_g_disconnect(musb);
304 		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
305 		musb->is_active = 0;
306 		break;
307 	case OTG_STATE_A_SUSPEND:
308 	case OTG_STATE_A_WAIT_BCON:
309 		DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
310 		musb_set_vbus(musb, 0);
311 		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
312 		break;
313 	default:
314 		DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
315 	}
316 	musb->ignore_disconnect = 0;
317 	spin_unlock_irqrestore(&musb->lock, flags);
318 }
319 
320 /*
321  * Stops the HNP transition. Caller must take care of locking.
322  */
323 void musb_hnp_stop(struct musb *musb)
324 {
325 	struct usb_hcd	*hcd = musb_to_hcd(musb);
326 	void __iomem	*mbase = musb->mregs;
327 	u8	reg;
328 
329 	DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
330 
331 	switch (musb->xceiv->state) {
332 	case OTG_STATE_A_PERIPHERAL:
333 		musb_g_disconnect(musb);
334 		DBG(1, "HNP: back to %s\n", otg_state_string(musb));
335 		break;
336 	case OTG_STATE_B_HOST:
337 		DBG(1, "HNP: Disabling HR\n");
338 		hcd->self.is_b_host = 0;
339 		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
340 		MUSB_DEV_MODE(musb);
341 		reg = musb_readb(mbase, MUSB_POWER);
342 		reg |= MUSB_POWER_SUSPENDM;
343 		musb_writeb(mbase, MUSB_POWER, reg);
344 		/* REVISIT: Start SESSION_REQUEST here? */
345 		break;
346 	default:
347 		DBG(1, "HNP: Stopping in unknown state %s\n",
348 			otg_state_string(musb));
349 	}
350 
351 	/*
352 	 * When returning to A state after HNP, avoid hub_port_rebounce(),
353 	 * which cause occasional OPT A "Did not receive reset after connect"
354 	 * errors.
355 	 */
356 	musb->port1_status &=
357 		~(1 << USB_PORT_FEAT_C_CONNECTION);
358 }
359 
360 #endif
361 
362 /*
363  * Interrupt Service Routine to record USB "global" interrupts.
364  * Since these do not happen often and signify things of
365  * paramount importance, it seems OK to check them individually;
366  * the order of the tests is specified in the manual
367  *
368  * @param musb instance pointer
369  * @param int_usb register contents
370  * @param devctl
371  * @param power
372  */
373 
374 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
375 		| MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
376 		| MUSB_INTR_RESET)
377 
378 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
379 				u8 devctl, u8 power)
380 {
381 	irqreturn_t handled = IRQ_NONE;
382 	void __iomem *mbase = musb->mregs;
383 
384 	DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
385 		int_usb);
386 
387 	/* in host mode, the peripheral may issue remote wakeup.
388 	 * in peripheral mode, the host may resume the link.
389 	 * spurious RESUME irqs happen too, paired with SUSPEND.
390 	 */
391 	if (int_usb & MUSB_INTR_RESUME) {
392 		handled = IRQ_HANDLED;
393 		DBG(3, "RESUME (%s)\n", otg_state_string(musb));
394 
395 		if (devctl & MUSB_DEVCTL_HM) {
396 #ifdef CONFIG_USB_MUSB_HDRC_HCD
397 			switch (musb->xceiv->state) {
398 			case OTG_STATE_A_SUSPEND:
399 				/* remote wakeup?  later, GetPortStatus
400 				 * will stop RESUME signaling
401 				 */
402 
403 				if (power & MUSB_POWER_SUSPENDM) {
404 					/* spurious */
405 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
406 					DBG(2, "Spurious SUSPENDM\n");
407 					break;
408 				}
409 
410 				power &= ~MUSB_POWER_SUSPENDM;
411 				musb_writeb(mbase, MUSB_POWER,
412 						power | MUSB_POWER_RESUME);
413 
414 				musb->port1_status |=
415 						(USB_PORT_STAT_C_SUSPEND << 16)
416 						| MUSB_PORT_STAT_RESUME;
417 				musb->rh_timer = jiffies
418 						+ msecs_to_jiffies(20);
419 
420 				musb->xceiv->state = OTG_STATE_A_HOST;
421 				musb->is_active = 1;
422 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
423 				break;
424 			case OTG_STATE_B_WAIT_ACON:
425 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
426 				musb->is_active = 1;
427 				MUSB_DEV_MODE(musb);
428 				break;
429 			default:
430 				WARNING("bogus %s RESUME (%s)\n",
431 					"host",
432 					otg_state_string(musb));
433 			}
434 #endif
435 		} else {
436 			switch (musb->xceiv->state) {
437 #ifdef CONFIG_USB_MUSB_HDRC_HCD
438 			case OTG_STATE_A_SUSPEND:
439 				/* possibly DISCONNECT is upcoming */
440 				musb->xceiv->state = OTG_STATE_A_HOST;
441 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
442 				break;
443 #endif
444 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
445 			case OTG_STATE_B_WAIT_ACON:
446 			case OTG_STATE_B_PERIPHERAL:
447 				/* disconnect while suspended?  we may
448 				 * not get a disconnect irq...
449 				 */
450 				if ((devctl & MUSB_DEVCTL_VBUS)
451 						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
452 						) {
453 					musb->int_usb |= MUSB_INTR_DISCONNECT;
454 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
455 					break;
456 				}
457 				musb_g_resume(musb);
458 				break;
459 			case OTG_STATE_B_IDLE:
460 				musb->int_usb &= ~MUSB_INTR_SUSPEND;
461 				break;
462 #endif
463 			default:
464 				WARNING("bogus %s RESUME (%s)\n",
465 					"peripheral",
466 					otg_state_string(musb));
467 			}
468 		}
469 	}
470 
471 #ifdef CONFIG_USB_MUSB_HDRC_HCD
472 	/* see manual for the order of the tests */
473 	if (int_usb & MUSB_INTR_SESSREQ) {
474 		DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
475 
476 		/* IRQ arrives from ID pin sense or (later, if VBUS power
477 		 * is removed) SRP.  responses are time critical:
478 		 *  - turn on VBUS (with silicon-specific mechanism)
479 		 *  - go through A_WAIT_VRISE
480 		 *  - ... to A_WAIT_BCON.
481 		 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
482 		 */
483 		musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
484 		musb->ep0_stage = MUSB_EP0_START;
485 		musb->xceiv->state = OTG_STATE_A_IDLE;
486 		MUSB_HST_MODE(musb);
487 		musb_set_vbus(musb, 1);
488 
489 		handled = IRQ_HANDLED;
490 	}
491 
492 	if (int_usb & MUSB_INTR_VBUSERROR) {
493 		int	ignore = 0;
494 
495 		/* During connection as an A-Device, we may see a short
496 		 * current spikes causing voltage drop, because of cable
497 		 * and peripheral capacitance combined with vbus draw.
498 		 * (So: less common with truly self-powered devices, where
499 		 * vbus doesn't act like a power supply.)
500 		 *
501 		 * Such spikes are short; usually less than ~500 usec, max
502 		 * of ~2 msec.  That is, they're not sustained overcurrent
503 		 * errors, though they're reported using VBUSERROR irqs.
504 		 *
505 		 * Workarounds:  (a) hardware: use self powered devices.
506 		 * (b) software:  ignore non-repeated VBUS errors.
507 		 *
508 		 * REVISIT:  do delays from lots of DEBUG_KERNEL checks
509 		 * make trouble here, keeping VBUS < 4.4V ?
510 		 */
511 		switch (musb->xceiv->state) {
512 		case OTG_STATE_A_HOST:
513 			/* recovery is dicey once we've gotten past the
514 			 * initial stages of enumeration, but if VBUS
515 			 * stayed ok at the other end of the link, and
516 			 * another reset is due (at least for high speed,
517 			 * to redo the chirp etc), it might work OK...
518 			 */
519 		case OTG_STATE_A_WAIT_BCON:
520 		case OTG_STATE_A_WAIT_VRISE:
521 			if (musb->vbuserr_retry) {
522 				musb->vbuserr_retry--;
523 				ignore = 1;
524 				devctl |= MUSB_DEVCTL_SESSION;
525 				musb_writeb(mbase, MUSB_DEVCTL, devctl);
526 			} else {
527 				musb->port1_status |=
528 					  (1 << USB_PORT_FEAT_OVER_CURRENT)
529 					| (1 << USB_PORT_FEAT_C_OVER_CURRENT);
530 			}
531 			break;
532 		default:
533 			break;
534 		}
535 
536 		DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
537 				otg_state_string(musb),
538 				devctl,
539 				({ char *s;
540 				switch (devctl & MUSB_DEVCTL_VBUS) {
541 				case 0 << MUSB_DEVCTL_VBUS_SHIFT:
542 					s = "<SessEnd"; break;
543 				case 1 << MUSB_DEVCTL_VBUS_SHIFT:
544 					s = "<AValid"; break;
545 				case 2 << MUSB_DEVCTL_VBUS_SHIFT:
546 					s = "<VBusValid"; break;
547 				/* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
548 				default:
549 					s = "VALID"; break;
550 				}; s; }),
551 				VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
552 				musb->port1_status);
553 
554 		/* go through A_WAIT_VFALL then start a new session */
555 		if (!ignore)
556 			musb_set_vbus(musb, 0);
557 		handled = IRQ_HANDLED;
558 	}
559 
560 	if (int_usb & MUSB_INTR_CONNECT) {
561 		struct usb_hcd *hcd = musb_to_hcd(musb);
562 
563 		handled = IRQ_HANDLED;
564 		musb->is_active = 1;
565 		set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
566 
567 		musb->ep0_stage = MUSB_EP0_START;
568 
569 #ifdef CONFIG_USB_MUSB_OTG
570 		/* flush endpoints when transitioning from Device Mode */
571 		if (is_peripheral_active(musb)) {
572 			/* REVISIT HNP; just force disconnect */
573 		}
574 		musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
575 		musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
576 		musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
577 #endif
578 		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
579 					|USB_PORT_STAT_HIGH_SPEED
580 					|USB_PORT_STAT_ENABLE
581 					);
582 		musb->port1_status |= USB_PORT_STAT_CONNECTION
583 					|(USB_PORT_STAT_C_CONNECTION << 16);
584 
585 		/* high vs full speed is just a guess until after reset */
586 		if (devctl & MUSB_DEVCTL_LSDEV)
587 			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
588 
589 		/* indicate new connection to OTG machine */
590 		switch (musb->xceiv->state) {
591 		case OTG_STATE_B_PERIPHERAL:
592 			if (int_usb & MUSB_INTR_SUSPEND) {
593 				DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
594 				int_usb &= ~MUSB_INTR_SUSPEND;
595 				goto b_host;
596 			} else
597 				DBG(1, "CONNECT as b_peripheral???\n");
598 			break;
599 		case OTG_STATE_B_WAIT_ACON:
600 			DBG(1, "HNP: CONNECT, now b_host\n");
601 b_host:
602 			musb->xceiv->state = OTG_STATE_B_HOST;
603 			hcd->self.is_b_host = 1;
604 			musb->ignore_disconnect = 0;
605 			del_timer(&musb->otg_timer);
606 			break;
607 		default:
608 			if ((devctl & MUSB_DEVCTL_VBUS)
609 					== (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
610 				musb->xceiv->state = OTG_STATE_A_HOST;
611 				hcd->self.is_b_host = 0;
612 			}
613 			break;
614 		}
615 
616 		/* poke the root hub */
617 		MUSB_HST_MODE(musb);
618 		if (hcd->status_urb)
619 			usb_hcd_poll_rh_status(hcd);
620 		else
621 			usb_hcd_resume_root_hub(hcd);
622 
623 		DBG(1, "CONNECT (%s) devctl %02x\n",
624 				otg_state_string(musb), devctl);
625 	}
626 #endif	/* CONFIG_USB_MUSB_HDRC_HCD */
627 
628 	/* mentor saves a bit: bus reset and babble share the same irq.
629 	 * only host sees babble; only peripheral sees bus reset.
630 	 */
631 	if (int_usb & MUSB_INTR_RESET) {
632 		if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
633 			/*
634 			 * Looks like non-HS BABBLE can be ignored, but
635 			 * HS BABBLE is an error condition. For HS the solution
636 			 * is to avoid babble in the first place and fix what
637 			 * caused BABBLE. When HS BABBLE happens we can only
638 			 * stop the session.
639 			 */
640 			if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
641 				DBG(1, "BABBLE devctl: %02x\n", devctl);
642 			else {
643 				ERR("Stopping host session -- babble\n");
644 				musb_writeb(mbase, MUSB_DEVCTL, 0);
645 			}
646 		} else if (is_peripheral_capable()) {
647 			DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
648 			switch (musb->xceiv->state) {
649 #ifdef CONFIG_USB_OTG
650 			case OTG_STATE_A_SUSPEND:
651 				/* We need to ignore disconnect on suspend
652 				 * otherwise tusb 2.0 won't reconnect after a
653 				 * power cycle, which breaks otg compliance.
654 				 */
655 				musb->ignore_disconnect = 1;
656 				musb_g_reset(musb);
657 				/* FALLTHROUGH */
658 			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
659 				/* never use invalid T(a_wait_bcon) */
660 				DBG(1, "HNP: in %s, %d msec timeout\n",
661 						otg_state_string(musb),
662 						TA_WAIT_BCON(musb));
663 				mod_timer(&musb->otg_timer, jiffies
664 					+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
665 				break;
666 			case OTG_STATE_A_PERIPHERAL:
667 				musb->ignore_disconnect = 0;
668 				del_timer(&musb->otg_timer);
669 				musb_g_reset(musb);
670 				break;
671 			case OTG_STATE_B_WAIT_ACON:
672 				DBG(1, "HNP: RESET (%s), to b_peripheral\n",
673 					otg_state_string(musb));
674 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
675 				musb_g_reset(musb);
676 				break;
677 #endif
678 			case OTG_STATE_B_IDLE:
679 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
680 				/* FALLTHROUGH */
681 			case OTG_STATE_B_PERIPHERAL:
682 				musb_g_reset(musb);
683 				break;
684 			default:
685 				DBG(1, "Unhandled BUS RESET as %s\n",
686 					otg_state_string(musb));
687 			}
688 		}
689 
690 		handled = IRQ_HANDLED;
691 	}
692 	schedule_work(&musb->irq_work);
693 
694 	return handled;
695 }
696 
697 /*
698  * Interrupt Service Routine to record USB "global" interrupts.
699  * Since these do not happen often and signify things of
700  * paramount importance, it seems OK to check them individually;
701  * the order of the tests is specified in the manual
702  *
703  * @param musb instance pointer
704  * @param int_usb register contents
705  * @param devctl
706  * @param power
707  */
708 static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
709 				u8 devctl, u8 power)
710 {
711 	irqreturn_t handled = IRQ_NONE;
712 
713 #if 0
714 /* REVISIT ... this would be for multiplexing periodic endpoints, or
715  * supporting transfer phasing to prevent exceeding ISO bandwidth
716  * limits of a given frame or microframe.
717  *
718  * It's not needed for peripheral side, which dedicates endpoints;
719  * though it _might_ use SOF irqs for other purposes.
720  *
721  * And it's not currently needed for host side, which also dedicates
722  * endpoints, relies on TX/RX interval registers, and isn't claimed
723  * to support ISO transfers yet.
724  */
725 	if (int_usb & MUSB_INTR_SOF) {
726 		void __iomem *mbase = musb->mregs;
727 		struct musb_hw_ep	*ep;
728 		u8 epnum;
729 		u16 frame;
730 
731 		DBG(6, "START_OF_FRAME\n");
732 		handled = IRQ_HANDLED;
733 
734 		/* start any periodic Tx transfers waiting for current frame */
735 		frame = musb_readw(mbase, MUSB_FRAME);
736 		ep = musb->endpoints;
737 		for (epnum = 1; (epnum < musb->nr_endpoints)
738 					&& (musb->epmask >= (1 << epnum));
739 				epnum++, ep++) {
740 			/*
741 			 * FIXME handle framecounter wraps (12 bits)
742 			 * eliminate duplicated StartUrb logic
743 			 */
744 			if (ep->dwWaitFrame >= frame) {
745 				ep->dwWaitFrame = 0;
746 				pr_debug("SOF --> periodic TX%s on %d\n",
747 					ep->tx_channel ? " DMA" : "",
748 					epnum);
749 				if (!ep->tx_channel)
750 					musb_h_tx_start(musb, epnum);
751 				else
752 					cppi_hostdma_start(musb, epnum);
753 			}
754 		}		/* end of for loop */
755 	}
756 #endif
757 
758 	if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
759 		DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
760 				otg_state_string(musb),
761 				MUSB_MODE(musb), devctl);
762 		handled = IRQ_HANDLED;
763 
764 		switch (musb->xceiv->state) {
765 #ifdef CONFIG_USB_MUSB_HDRC_HCD
766 		case OTG_STATE_A_HOST:
767 		case OTG_STATE_A_SUSPEND:
768 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
769 			musb_root_disconnect(musb);
770 			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
771 				musb_platform_try_idle(musb, jiffies
772 					+ msecs_to_jiffies(musb->a_wait_bcon));
773 			break;
774 #endif	/* HOST */
775 #ifdef CONFIG_USB_MUSB_OTG
776 		case OTG_STATE_B_HOST:
777 			/* REVISIT this behaves for "real disconnect"
778 			 * cases; make sure the other transitions from
779 			 * from B_HOST act right too.  The B_HOST code
780 			 * in hnp_stop() is currently not used...
781 			 */
782 			musb_root_disconnect(musb);
783 			musb_to_hcd(musb)->self.is_b_host = 0;
784 			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
785 			MUSB_DEV_MODE(musb);
786 			musb_g_disconnect(musb);
787 			break;
788 		case OTG_STATE_A_PERIPHERAL:
789 			musb_hnp_stop(musb);
790 			musb_root_disconnect(musb);
791 			/* FALLTHROUGH */
792 		case OTG_STATE_B_WAIT_ACON:
793 			/* FALLTHROUGH */
794 #endif	/* OTG */
795 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
796 		case OTG_STATE_B_PERIPHERAL:
797 		case OTG_STATE_B_IDLE:
798 			musb_g_disconnect(musb);
799 			break;
800 #endif	/* GADGET */
801 		default:
802 			WARNING("unhandled DISCONNECT transition (%s)\n",
803 				otg_state_string(musb));
804 			break;
805 		}
806 
807 		schedule_work(&musb->irq_work);
808 	}
809 
810 	if (int_usb & MUSB_INTR_SUSPEND) {
811 		DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
812 				otg_state_string(musb), devctl, power);
813 		handled = IRQ_HANDLED;
814 
815 		switch (musb->xceiv->state) {
816 #ifdef	CONFIG_USB_MUSB_OTG
817 		case OTG_STATE_A_PERIPHERAL:
818 			/* We also come here if the cable is removed, since
819 			 * this silicon doesn't report ID-no-longer-grounded.
820 			 *
821 			 * We depend on T(a_wait_bcon) to shut us down, and
822 			 * hope users don't do anything dicey during this
823 			 * undesired detour through A_WAIT_BCON.
824 			 */
825 			musb_hnp_stop(musb);
826 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
827 			musb_root_disconnect(musb);
828 			musb_platform_try_idle(musb, jiffies
829 					+ msecs_to_jiffies(musb->a_wait_bcon
830 						? : OTG_TIME_A_WAIT_BCON));
831 			break;
832 #endif
833 		case OTG_STATE_B_PERIPHERAL:
834 			musb_g_suspend(musb);
835 			musb->is_active = is_otg_enabled(musb)
836 					&& musb->xceiv->gadget->b_hnp_enable;
837 			if (musb->is_active) {
838 #ifdef	CONFIG_USB_MUSB_OTG
839 				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
840 				DBG(1, "HNP: Setting timer for b_ase0_brst\n");
841 				mod_timer(&musb->otg_timer, jiffies
842 					+ msecs_to_jiffies(
843 							OTG_TIME_B_ASE0_BRST));
844 #endif
845 			}
846 			break;
847 		case OTG_STATE_A_WAIT_BCON:
848 			if (musb->a_wait_bcon != 0)
849 				musb_platform_try_idle(musb, jiffies
850 					+ msecs_to_jiffies(musb->a_wait_bcon));
851 			break;
852 		case OTG_STATE_A_HOST:
853 			musb->xceiv->state = OTG_STATE_A_SUSPEND;
854 			musb->is_active = is_otg_enabled(musb)
855 					&& musb->xceiv->host->b_hnp_enable;
856 			break;
857 		case OTG_STATE_B_HOST:
858 			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
859 			DBG(1, "REVISIT: SUSPEND as B_HOST\n");
860 			break;
861 		default:
862 			/* "should not happen" */
863 			musb->is_active = 0;
864 			break;
865 		}
866 		schedule_work(&musb->irq_work);
867 	}
868 
869 
870 	return handled;
871 }
872 
873 /*-------------------------------------------------------------------------*/
874 
875 /*
876 * Program the HDRC to start (enable interrupts, dma, etc.).
877 */
878 void musb_start(struct musb *musb)
879 {
880 	void __iomem	*regs = musb->mregs;
881 	u8		devctl = musb_readb(regs, MUSB_DEVCTL);
882 
883 	DBG(2, "<== devctl %02x\n", devctl);
884 
885 	/*  Set INT enable registers, enable interrupts */
886 	musb_writew(regs, MUSB_INTRTXE, musb->epmask);
887 	musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
888 	musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
889 
890 	musb_writeb(regs, MUSB_TESTMODE, 0);
891 
892 	/* put into basic highspeed mode and start session */
893 	musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
894 						| MUSB_POWER_SOFTCONN
895 						| MUSB_POWER_HSENAB
896 						/* ENSUSPEND wedges tusb */
897 						/* | MUSB_POWER_ENSUSPEND */
898 						);
899 
900 	musb->is_active = 0;
901 	devctl = musb_readb(regs, MUSB_DEVCTL);
902 	devctl &= ~MUSB_DEVCTL_SESSION;
903 
904 	if (is_otg_enabled(musb)) {
905 		/* session started after:
906 		 * (a) ID-grounded irq, host mode;
907 		 * (b) vbus present/connect IRQ, peripheral mode;
908 		 * (c) peripheral initiates, using SRP
909 		 */
910 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
911 			musb->is_active = 1;
912 		else
913 			devctl |= MUSB_DEVCTL_SESSION;
914 
915 	} else if (is_host_enabled(musb)) {
916 		/* assume ID pin is hard-wired to ground */
917 		devctl |= MUSB_DEVCTL_SESSION;
918 
919 	} else /* peripheral is enabled */ {
920 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
921 			musb->is_active = 1;
922 	}
923 	musb_platform_enable(musb);
924 	musb_writeb(regs, MUSB_DEVCTL, devctl);
925 }
926 
927 
928 static void musb_generic_disable(struct musb *musb)
929 {
930 	void __iomem	*mbase = musb->mregs;
931 	u16	temp;
932 
933 	/* disable interrupts */
934 	musb_writeb(mbase, MUSB_INTRUSBE, 0);
935 	musb_writew(mbase, MUSB_INTRTXE, 0);
936 	musb_writew(mbase, MUSB_INTRRXE, 0);
937 
938 	/* off */
939 	musb_writeb(mbase, MUSB_DEVCTL, 0);
940 
941 	/*  flush pending interrupts */
942 	temp = musb_readb(mbase, MUSB_INTRUSB);
943 	temp = musb_readw(mbase, MUSB_INTRTX);
944 	temp = musb_readw(mbase, MUSB_INTRRX);
945 
946 }
947 
948 /*
949  * Make the HDRC stop (disable interrupts, etc.);
950  * reversible by musb_start
951  * called on gadget driver unregister
952  * with controller locked, irqs blocked
953  * acts as a NOP unless some role activated the hardware
954  */
955 void musb_stop(struct musb *musb)
956 {
957 	/* stop IRQs, timers, ... */
958 	musb_platform_disable(musb);
959 	musb_generic_disable(musb);
960 	DBG(3, "HDRC disabled\n");
961 
962 	/* FIXME
963 	 *  - mark host and/or peripheral drivers unusable/inactive
964 	 *  - disable DMA (and enable it in HdrcStart)
965 	 *  - make sure we can musb_start() after musb_stop(); with
966 	 *    OTG mode, gadget driver module rmmod/modprobe cycles that
967 	 *  - ...
968 	 */
969 	musb_platform_try_idle(musb, 0);
970 }
971 
972 static void musb_shutdown(struct platform_device *pdev)
973 {
974 	struct musb	*musb = dev_to_musb(&pdev->dev);
975 	unsigned long	flags;
976 
977 	spin_lock_irqsave(&musb->lock, flags);
978 	musb_platform_disable(musb);
979 	musb_generic_disable(musb);
980 	if (musb->clock) {
981 		clk_put(musb->clock);
982 		musb->clock = NULL;
983 	}
984 	spin_unlock_irqrestore(&musb->lock, flags);
985 
986 	/* FIXME power down */
987 }
988 
989 
990 /*-------------------------------------------------------------------------*/
991 
992 /*
993  * The silicon either has hard-wired endpoint configurations, or else
994  * "dynamic fifo" sizing.  The driver has support for both, though at this
995  * writing only the dynamic sizing is very well tested.   Since we switched
996  * away from compile-time hardware parameters, we can no longer rely on
997  * dead code elimination to leave only the relevant one in the object file.
998  *
999  * We don't currently use dynamic fifo setup capability to do anything
1000  * more than selecting one of a bunch of predefined configurations.
1001  */
1002 #if defined(CONFIG_USB_TUSB6010) || \
1003 	defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1004 static ushort __initdata fifo_mode = 4;
1005 #else
1006 static ushort __initdata fifo_mode = 2;
1007 #endif
1008 
1009 /* "modprobe ... fifo_mode=1" etc */
1010 module_param(fifo_mode, ushort, 0);
1011 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1012 
1013 
1014 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1015 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1016 
1017 struct fifo_cfg {
1018 	u8		hw_ep_num;
1019 	enum fifo_style	style;
1020 	enum buf_mode	mode;
1021 	u16		maxpacket;
1022 };
1023 
1024 /*
1025  * tables defining fifo_mode values.  define more if you like.
1026  * for host side, make sure both halves of ep1 are set up.
1027  */
1028 
1029 /* mode 0 - fits in 2KB */
1030 static struct fifo_cfg __initdata mode_0_cfg[] = {
1031 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1032 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1033 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1034 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1035 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1036 };
1037 
1038 /* mode 1 - fits in 4KB */
1039 static struct fifo_cfg __initdata mode_1_cfg[] = {
1040 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1041 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1042 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1043 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1044 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1045 };
1046 
1047 /* mode 2 - fits in 4KB */
1048 static struct fifo_cfg __initdata mode_2_cfg[] = {
1049 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1050 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1051 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1052 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1053 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1054 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1055 };
1056 
1057 /* mode 3 - fits in 4KB */
1058 static struct fifo_cfg __initdata mode_3_cfg[] = {
1059 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1060 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1061 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1062 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1063 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1064 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1065 };
1066 
1067 /* mode 4 - fits in 16KB */
1068 static struct fifo_cfg __initdata mode_4_cfg[] = {
1069 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1070 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1071 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1072 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1073 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1074 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1075 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1076 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1077 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1078 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1079 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1080 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1081 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1082 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1083 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1084 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1085 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1086 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1087 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1088 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1089 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1090 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1091 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1092 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1093 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1094 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1095 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1096 };
1097 
1098 
1099 /*
1100  * configure a fifo; for non-shared endpoints, this may be called
1101  * once for a tx fifo and once for an rx fifo.
1102  *
1103  * returns negative errno or offset for next fifo.
1104  */
1105 static int __init
1106 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1107 		const struct fifo_cfg *cfg, u16 offset)
1108 {
1109 	void __iomem	*mbase = musb->mregs;
1110 	int	size = 0;
1111 	u16	maxpacket = cfg->maxpacket;
1112 	u16	c_off = offset >> 3;
1113 	u8	c_size;
1114 
1115 	/* expect hw_ep has already been zero-initialized */
1116 
1117 	size = ffs(max(maxpacket, (u16) 8)) - 1;
1118 	maxpacket = 1 << size;
1119 
1120 	c_size = size - 3;
1121 	if (cfg->mode == BUF_DOUBLE) {
1122 		if ((offset + (maxpacket << 1)) >
1123 				(1 << (musb->config->ram_bits + 2)))
1124 			return -EMSGSIZE;
1125 		c_size |= MUSB_FIFOSZ_DPB;
1126 	} else {
1127 		if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1128 			return -EMSGSIZE;
1129 	}
1130 
1131 	/* configure the FIFO */
1132 	musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1133 
1134 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1135 	/* EP0 reserved endpoint for control, bidirectional;
1136 	 * EP1 reserved for bulk, two unidirection halves.
1137 	 */
1138 	if (hw_ep->epnum == 1)
1139 		musb->bulk_ep = hw_ep;
1140 	/* REVISIT error check:  be sure ep0 can both rx and tx ... */
1141 #endif
1142 	switch (cfg->style) {
1143 	case FIFO_TX:
1144 		musb_write_txfifosz(mbase, c_size);
1145 		musb_write_txfifoadd(mbase, c_off);
1146 		hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1147 		hw_ep->max_packet_sz_tx = maxpacket;
1148 		break;
1149 	case FIFO_RX:
1150 		musb_write_rxfifosz(mbase, c_size);
1151 		musb_write_rxfifoadd(mbase, c_off);
1152 		hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1153 		hw_ep->max_packet_sz_rx = maxpacket;
1154 		break;
1155 	case FIFO_RXTX:
1156 		musb_write_txfifosz(mbase, c_size);
1157 		musb_write_txfifoadd(mbase, c_off);
1158 		hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1159 		hw_ep->max_packet_sz_rx = maxpacket;
1160 
1161 		musb_write_rxfifosz(mbase, c_size);
1162 		musb_write_rxfifoadd(mbase, c_off);
1163 		hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1164 		hw_ep->max_packet_sz_tx = maxpacket;
1165 
1166 		hw_ep->is_shared_fifo = true;
1167 		break;
1168 	}
1169 
1170 	/* NOTE rx and tx endpoint irqs aren't managed separately,
1171 	 * which happens to be ok
1172 	 */
1173 	musb->epmask |= (1 << hw_ep->epnum);
1174 
1175 	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1176 }
1177 
1178 static struct fifo_cfg __initdata ep0_cfg = {
1179 	.style = FIFO_RXTX, .maxpacket = 64,
1180 };
1181 
1182 static int __init ep_config_from_table(struct musb *musb)
1183 {
1184 	const struct fifo_cfg	*cfg;
1185 	unsigned		i, n;
1186 	int			offset;
1187 	struct musb_hw_ep	*hw_ep = musb->endpoints;
1188 
1189 	switch (fifo_mode) {
1190 	default:
1191 		fifo_mode = 0;
1192 		/* FALLTHROUGH */
1193 	case 0:
1194 		cfg = mode_0_cfg;
1195 		n = ARRAY_SIZE(mode_0_cfg);
1196 		break;
1197 	case 1:
1198 		cfg = mode_1_cfg;
1199 		n = ARRAY_SIZE(mode_1_cfg);
1200 		break;
1201 	case 2:
1202 		cfg = mode_2_cfg;
1203 		n = ARRAY_SIZE(mode_2_cfg);
1204 		break;
1205 	case 3:
1206 		cfg = mode_3_cfg;
1207 		n = ARRAY_SIZE(mode_3_cfg);
1208 		break;
1209 	case 4:
1210 		cfg = mode_4_cfg;
1211 		n = ARRAY_SIZE(mode_4_cfg);
1212 		break;
1213 	}
1214 
1215 	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1216 			musb_driver_name, fifo_mode);
1217 
1218 
1219 	offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1220 	/* assert(offset > 0) */
1221 
1222 	/* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1223 	 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1224 	 */
1225 
1226 	for (i = 0; i < n; i++) {
1227 		u8	epn = cfg->hw_ep_num;
1228 
1229 		if (epn >= musb->config->num_eps) {
1230 			pr_debug("%s: invalid ep %d\n",
1231 					musb_driver_name, epn);
1232 			return -EINVAL;
1233 		}
1234 		offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1235 		if (offset < 0) {
1236 			pr_debug("%s: mem overrun, ep %d\n",
1237 					musb_driver_name, epn);
1238 			return -EINVAL;
1239 		}
1240 		epn++;
1241 		musb->nr_endpoints = max(epn, musb->nr_endpoints);
1242 	}
1243 
1244 	printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1245 			musb_driver_name,
1246 			n + 1, musb->config->num_eps * 2 - 1,
1247 			offset, (1 << (musb->config->ram_bits + 2)));
1248 
1249 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1250 	if (!musb->bulk_ep) {
1251 		pr_debug("%s: missing bulk\n", musb_driver_name);
1252 		return -EINVAL;
1253 	}
1254 #endif
1255 
1256 	return 0;
1257 }
1258 
1259 
1260 /*
1261  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1262  * @param musb the controller
1263  */
1264 static int __init ep_config_from_hw(struct musb *musb)
1265 {
1266 	u8 epnum = 0;
1267 	struct musb_hw_ep *hw_ep;
1268 	void *mbase = musb->mregs;
1269 	int ret = 0;
1270 
1271 	DBG(2, "<== static silicon ep config\n");
1272 
1273 	/* FIXME pick up ep0 maxpacket size */
1274 
1275 	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1276 		musb_ep_select(mbase, epnum);
1277 		hw_ep = musb->endpoints + epnum;
1278 
1279 		ret = musb_read_fifosize(musb, hw_ep, epnum);
1280 		if (ret < 0)
1281 			break;
1282 
1283 		/* FIXME set up hw_ep->{rx,tx}_double_buffered */
1284 
1285 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1286 		/* pick an RX/TX endpoint for bulk */
1287 		if (hw_ep->max_packet_sz_tx < 512
1288 				|| hw_ep->max_packet_sz_rx < 512)
1289 			continue;
1290 
1291 		/* REVISIT:  this algorithm is lazy, we should at least
1292 		 * try to pick a double buffered endpoint.
1293 		 */
1294 		if (musb->bulk_ep)
1295 			continue;
1296 		musb->bulk_ep = hw_ep;
1297 #endif
1298 	}
1299 
1300 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1301 	if (!musb->bulk_ep) {
1302 		pr_debug("%s: missing bulk\n", musb_driver_name);
1303 		return -EINVAL;
1304 	}
1305 #endif
1306 
1307 	return 0;
1308 }
1309 
1310 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1311 
1312 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1313  * configure endpoints, or take their config from silicon
1314  */
1315 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1316 {
1317 #ifdef MUSB_AHB_ID
1318 	u32 data;
1319 #endif
1320 	u8 reg;
1321 	char *type;
1322 	char aInfo[90], aRevision[32], aDate[12];
1323 	void __iomem	*mbase = musb->mregs;
1324 	int		status = 0;
1325 	int		i;
1326 
1327 	/* log core options (read using indexed model) */
1328 	reg = musb_read_configdata(mbase);
1329 
1330 	strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1331 	if (reg & MUSB_CONFIGDATA_DYNFIFO)
1332 		strcat(aInfo, ", dyn FIFOs");
1333 	if (reg & MUSB_CONFIGDATA_MPRXE) {
1334 		strcat(aInfo, ", bulk combine");
1335 #ifdef C_MP_RX
1336 		musb->bulk_combine = true;
1337 #else
1338 		strcat(aInfo, " (X)");		/* no driver support */
1339 #endif
1340 	}
1341 	if (reg & MUSB_CONFIGDATA_MPTXE) {
1342 		strcat(aInfo, ", bulk split");
1343 #ifdef C_MP_TX
1344 		musb->bulk_split = true;
1345 #else
1346 		strcat(aInfo, " (X)");		/* no driver support */
1347 #endif
1348 	}
1349 	if (reg & MUSB_CONFIGDATA_HBRXE) {
1350 		strcat(aInfo, ", HB-ISO Rx");
1351 		musb->hb_iso_rx = true;
1352 	}
1353 	if (reg & MUSB_CONFIGDATA_HBTXE) {
1354 		strcat(aInfo, ", HB-ISO Tx");
1355 		musb->hb_iso_tx = true;
1356 	}
1357 	if (reg & MUSB_CONFIGDATA_SOFTCONE)
1358 		strcat(aInfo, ", SoftConn");
1359 
1360 	printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1361 			musb_driver_name, reg, aInfo);
1362 
1363 #ifdef MUSB_AHB_ID
1364 	data = musb_readl(mbase, 0x404);
1365 	sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1366 		(data >> 16) & 0xff, (data >> 24) & 0xff);
1367 	/* FIXME ID2 and ID3 are unused */
1368 	data = musb_readl(mbase, 0x408);
1369 	printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1370 	data = musb_readl(mbase, 0x40c);
1371 	printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1372 	reg = musb_readb(mbase, 0x400);
1373 	musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1374 #else
1375 	aDate[0] = 0;
1376 #endif
1377 	if (MUSB_CONTROLLER_MHDRC == musb_type) {
1378 		musb->is_multipoint = 1;
1379 		type = "M";
1380 	} else {
1381 		musb->is_multipoint = 0;
1382 		type = "";
1383 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1384 #ifndef	CONFIG_USB_OTG_BLACKLIST_HUB
1385 		printk(KERN_ERR
1386 			"%s: kernel must blacklist external hubs\n",
1387 			musb_driver_name);
1388 #endif
1389 #endif
1390 	}
1391 
1392 	/* log release info */
1393 	musb->hwvers = musb_read_hwvers(mbase);
1394 	snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1395 		MUSB_HWVERS_MINOR(musb->hwvers),
1396 		(musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1397 	printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1398 			musb_driver_name, type, aRevision, aDate);
1399 
1400 	/* configure ep0 */
1401 	musb_configure_ep0(musb);
1402 
1403 	/* discover endpoint configuration */
1404 	musb->nr_endpoints = 1;
1405 	musb->epmask = 1;
1406 
1407 	if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1408 		if (musb->config->dyn_fifo)
1409 			status = ep_config_from_table(musb);
1410 		else {
1411 			ERR("reconfigure software for Dynamic FIFOs\n");
1412 			status = -ENODEV;
1413 		}
1414 	} else {
1415 		if (!musb->config->dyn_fifo)
1416 			status = ep_config_from_hw(musb);
1417 		else {
1418 			ERR("reconfigure software for static FIFOs\n");
1419 			return -ENODEV;
1420 		}
1421 	}
1422 
1423 	if (status < 0)
1424 		return status;
1425 
1426 	/* finish init, and print endpoint config */
1427 	for (i = 0; i < musb->nr_endpoints; i++) {
1428 		struct musb_hw_ep	*hw_ep = musb->endpoints + i;
1429 
1430 		hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1431 #ifdef CONFIG_USB_TUSB6010
1432 		hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1433 		hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1434 		hw_ep->fifo_sync_va =
1435 			musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1436 
1437 		if (i == 0)
1438 			hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1439 		else
1440 			hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1441 #endif
1442 
1443 		hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1444 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1445 		hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1446 		hw_ep->rx_reinit = 1;
1447 		hw_ep->tx_reinit = 1;
1448 #endif
1449 
1450 		if (hw_ep->max_packet_sz_tx) {
1451 			DBG(1,
1452 				"%s: hw_ep %d%s, %smax %d\n",
1453 				musb_driver_name, i,
1454 				hw_ep->is_shared_fifo ? "shared" : "tx",
1455 				hw_ep->tx_double_buffered
1456 					? "doublebuffer, " : "",
1457 				hw_ep->max_packet_sz_tx);
1458 		}
1459 		if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1460 			DBG(1,
1461 				"%s: hw_ep %d%s, %smax %d\n",
1462 				musb_driver_name, i,
1463 				"rx",
1464 				hw_ep->rx_double_buffered
1465 					? "doublebuffer, " : "",
1466 				hw_ep->max_packet_sz_rx);
1467 		}
1468 		if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1469 			DBG(1, "hw_ep %d not configured\n", i);
1470 	}
1471 
1472 	return 0;
1473 }
1474 
1475 /*-------------------------------------------------------------------------*/
1476 
1477 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1478 
1479 static irqreturn_t generic_interrupt(int irq, void *__hci)
1480 {
1481 	unsigned long	flags;
1482 	irqreturn_t	retval = IRQ_NONE;
1483 	struct musb	*musb = __hci;
1484 
1485 	spin_lock_irqsave(&musb->lock, flags);
1486 
1487 	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1488 	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1489 	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1490 
1491 	if (musb->int_usb || musb->int_tx || musb->int_rx)
1492 		retval = musb_interrupt(musb);
1493 
1494 	spin_unlock_irqrestore(&musb->lock, flags);
1495 
1496 	return retval;
1497 }
1498 
1499 #else
1500 #define generic_interrupt	NULL
1501 #endif
1502 
1503 /*
1504  * handle all the irqs defined by the HDRC core. for now we expect:  other
1505  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1506  * will be assigned, and the irq will already have been acked.
1507  *
1508  * called in irq context with spinlock held, irqs blocked
1509  */
1510 irqreturn_t musb_interrupt(struct musb *musb)
1511 {
1512 	irqreturn_t	retval = IRQ_NONE;
1513 	u8		devctl, power;
1514 	int		ep_num;
1515 	u32		reg;
1516 
1517 	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1518 	power = musb_readb(musb->mregs, MUSB_POWER);
1519 
1520 	DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1521 		(devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1522 		musb->int_usb, musb->int_tx, musb->int_rx);
1523 
1524 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1525 	if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1526 		if (!musb->gadget_driver) {
1527 			DBG(5, "No gadget driver loaded\n");
1528 			return IRQ_HANDLED;
1529 		}
1530 #endif
1531 
1532 	/* the core can interrupt us for multiple reasons; docs have
1533 	 * a generic interrupt flowchart to follow
1534 	 */
1535 	if (musb->int_usb & STAGE0_MASK)
1536 		retval |= musb_stage0_irq(musb, musb->int_usb,
1537 				devctl, power);
1538 
1539 	/* "stage 1" is handling endpoint irqs */
1540 
1541 	/* handle endpoint 0 first */
1542 	if (musb->int_tx & 1) {
1543 		if (devctl & MUSB_DEVCTL_HM)
1544 			retval |= musb_h_ep0_irq(musb);
1545 		else
1546 			retval |= musb_g_ep0_irq(musb);
1547 	}
1548 
1549 	/* RX on endpoints 1-15 */
1550 	reg = musb->int_rx >> 1;
1551 	ep_num = 1;
1552 	while (reg) {
1553 		if (reg & 1) {
1554 			/* musb_ep_select(musb->mregs, ep_num); */
1555 			/* REVISIT just retval = ep->rx_irq(...) */
1556 			retval = IRQ_HANDLED;
1557 			if (devctl & MUSB_DEVCTL_HM) {
1558 				if (is_host_capable())
1559 					musb_host_rx(musb, ep_num);
1560 			} else {
1561 				if (is_peripheral_capable())
1562 					musb_g_rx(musb, ep_num);
1563 			}
1564 		}
1565 
1566 		reg >>= 1;
1567 		ep_num++;
1568 	}
1569 
1570 	/* TX on endpoints 1-15 */
1571 	reg = musb->int_tx >> 1;
1572 	ep_num = 1;
1573 	while (reg) {
1574 		if (reg & 1) {
1575 			/* musb_ep_select(musb->mregs, ep_num); */
1576 			/* REVISIT just retval |= ep->tx_irq(...) */
1577 			retval = IRQ_HANDLED;
1578 			if (devctl & MUSB_DEVCTL_HM) {
1579 				if (is_host_capable())
1580 					musb_host_tx(musb, ep_num);
1581 			} else {
1582 				if (is_peripheral_capable())
1583 					musb_g_tx(musb, ep_num);
1584 			}
1585 		}
1586 		reg >>= 1;
1587 		ep_num++;
1588 	}
1589 
1590 	/* finish handling "global" interrupts after handling fifos */
1591 	if (musb->int_usb)
1592 		retval |= musb_stage2_irq(musb,
1593 				musb->int_usb, devctl, power);
1594 
1595 	return retval;
1596 }
1597 
1598 
1599 #ifndef CONFIG_MUSB_PIO_ONLY
1600 static int __initdata use_dma = 1;
1601 
1602 /* "modprobe ... use_dma=0" etc */
1603 module_param(use_dma, bool, 0);
1604 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1605 
1606 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1607 {
1608 	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1609 
1610 	/* called with controller lock already held */
1611 
1612 	if (!epnum) {
1613 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1614 		if (!is_cppi_enabled()) {
1615 			/* endpoint 0 */
1616 			if (devctl & MUSB_DEVCTL_HM)
1617 				musb_h_ep0_irq(musb);
1618 			else
1619 				musb_g_ep0_irq(musb);
1620 		}
1621 #endif
1622 	} else {
1623 		/* endpoints 1..15 */
1624 		if (transmit) {
1625 			if (devctl & MUSB_DEVCTL_HM) {
1626 				if (is_host_capable())
1627 					musb_host_tx(musb, epnum);
1628 			} else {
1629 				if (is_peripheral_capable())
1630 					musb_g_tx(musb, epnum);
1631 			}
1632 		} else {
1633 			/* receive */
1634 			if (devctl & MUSB_DEVCTL_HM) {
1635 				if (is_host_capable())
1636 					musb_host_rx(musb, epnum);
1637 			} else {
1638 				if (is_peripheral_capable())
1639 					musb_g_rx(musb, epnum);
1640 			}
1641 		}
1642 	}
1643 }
1644 
1645 #else
1646 #define use_dma			0
1647 #endif
1648 
1649 /*-------------------------------------------------------------------------*/
1650 
1651 #ifdef CONFIG_SYSFS
1652 
1653 static ssize_t
1654 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1655 {
1656 	struct musb *musb = dev_to_musb(dev);
1657 	unsigned long flags;
1658 	int ret = -EINVAL;
1659 
1660 	spin_lock_irqsave(&musb->lock, flags);
1661 	ret = sprintf(buf, "%s\n", otg_state_string(musb));
1662 	spin_unlock_irqrestore(&musb->lock, flags);
1663 
1664 	return ret;
1665 }
1666 
1667 static ssize_t
1668 musb_mode_store(struct device *dev, struct device_attribute *attr,
1669 		const char *buf, size_t n)
1670 {
1671 	struct musb	*musb = dev_to_musb(dev);
1672 	unsigned long	flags;
1673 	int		status;
1674 
1675 	spin_lock_irqsave(&musb->lock, flags);
1676 	if (sysfs_streq(buf, "host"))
1677 		status = musb_platform_set_mode(musb, MUSB_HOST);
1678 	else if (sysfs_streq(buf, "peripheral"))
1679 		status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1680 	else if (sysfs_streq(buf, "otg"))
1681 		status = musb_platform_set_mode(musb, MUSB_OTG);
1682 	else
1683 		status = -EINVAL;
1684 	spin_unlock_irqrestore(&musb->lock, flags);
1685 
1686 	return (status == 0) ? n : status;
1687 }
1688 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1689 
1690 static ssize_t
1691 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1692 		const char *buf, size_t n)
1693 {
1694 	struct musb	*musb = dev_to_musb(dev);
1695 	unsigned long	flags;
1696 	unsigned long	val;
1697 
1698 	if (sscanf(buf, "%lu", &val) < 1) {
1699 		printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1700 		return -EINVAL;
1701 	}
1702 
1703 	spin_lock_irqsave(&musb->lock, flags);
1704 	/* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1705 	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1706 	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1707 		musb->is_active = 0;
1708 	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1709 	spin_unlock_irqrestore(&musb->lock, flags);
1710 
1711 	return n;
1712 }
1713 
1714 static ssize_t
1715 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1716 {
1717 	struct musb	*musb = dev_to_musb(dev);
1718 	unsigned long	flags;
1719 	unsigned long	val;
1720 	int		vbus;
1721 
1722 	spin_lock_irqsave(&musb->lock, flags);
1723 	val = musb->a_wait_bcon;
1724 	/* FIXME get_vbus_status() is normally #defined as false...
1725 	 * and is effectively TUSB-specific.
1726 	 */
1727 	vbus = musb_platform_get_vbus_status(musb);
1728 	spin_unlock_irqrestore(&musb->lock, flags);
1729 
1730 	return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1731 			vbus ? "on" : "off", val);
1732 }
1733 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1734 
1735 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1736 
1737 /* Gadget drivers can't know that a host is connected so they might want
1738  * to start SRP, but users can.  This allows userspace to trigger SRP.
1739  */
1740 static ssize_t
1741 musb_srp_store(struct device *dev, struct device_attribute *attr,
1742 		const char *buf, size_t n)
1743 {
1744 	struct musb	*musb = dev_to_musb(dev);
1745 	unsigned short	srp;
1746 
1747 	if (sscanf(buf, "%hu", &srp) != 1
1748 			|| (srp != 1)) {
1749 		printk(KERN_ERR "SRP: Value must be 1\n");
1750 		return -EINVAL;
1751 	}
1752 
1753 	if (srp == 1)
1754 		musb_g_wakeup(musb);
1755 
1756 	return n;
1757 }
1758 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1759 
1760 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1761 
1762 #endif	/* sysfs */
1763 
1764 /* Only used to provide driver mode change events */
1765 static void musb_irq_work(struct work_struct *data)
1766 {
1767 	struct musb *musb = container_of(data, struct musb, irq_work);
1768 	static int old_state;
1769 
1770 	if (musb->xceiv->state != old_state) {
1771 		old_state = musb->xceiv->state;
1772 		sysfs_notify(&musb->controller->kobj, NULL, "mode");
1773 	}
1774 }
1775 
1776 /* --------------------------------------------------------------------------
1777  * Init support
1778  */
1779 
1780 static struct musb *__init
1781 allocate_instance(struct device *dev,
1782 		struct musb_hdrc_config *config, void __iomem *mbase)
1783 {
1784 	struct musb		*musb;
1785 	struct musb_hw_ep	*ep;
1786 	int			epnum;
1787 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1788 	struct usb_hcd	*hcd;
1789 
1790 	hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1791 	if (!hcd)
1792 		return NULL;
1793 	/* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1794 
1795 	musb = hcd_to_musb(hcd);
1796 	INIT_LIST_HEAD(&musb->control);
1797 	INIT_LIST_HEAD(&musb->in_bulk);
1798 	INIT_LIST_HEAD(&musb->out_bulk);
1799 
1800 	hcd->uses_new_polling = 1;
1801 
1802 	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1803 	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1804 #else
1805 	musb = kzalloc(sizeof *musb, GFP_KERNEL);
1806 	if (!musb)
1807 		return NULL;
1808 	dev_set_drvdata(dev, musb);
1809 
1810 #endif
1811 
1812 	musb->mregs = mbase;
1813 	musb->ctrl_base = mbase;
1814 	musb->nIrq = -ENODEV;
1815 	musb->config = config;
1816 	BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1817 	for (epnum = 0, ep = musb->endpoints;
1818 			epnum < musb->config->num_eps;
1819 			epnum++, ep++) {
1820 		ep->musb = musb;
1821 		ep->epnum = epnum;
1822 	}
1823 
1824 	musb->controller = dev;
1825 	return musb;
1826 }
1827 
1828 static void musb_free(struct musb *musb)
1829 {
1830 	/* this has multiple entry modes. it handles fault cleanup after
1831 	 * probe(), where things may be partially set up, as well as rmmod
1832 	 * cleanup after everything's been de-activated.
1833 	 */
1834 
1835 #ifdef CONFIG_SYSFS
1836 	device_remove_file(musb->controller, &dev_attr_mode);
1837 	device_remove_file(musb->controller, &dev_attr_vbus);
1838 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1839 	device_remove_file(musb->controller, &dev_attr_srp);
1840 #endif
1841 #endif
1842 
1843 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1844 	musb_gadget_cleanup(musb);
1845 #endif
1846 
1847 	if (musb->nIrq >= 0) {
1848 		if (musb->irq_wake)
1849 			disable_irq_wake(musb->nIrq);
1850 		free_irq(musb->nIrq, musb);
1851 	}
1852 	if (is_dma_capable() && musb->dma_controller) {
1853 		struct dma_controller	*c = musb->dma_controller;
1854 
1855 		(void) c->stop(c);
1856 		dma_controller_destroy(c);
1857 	}
1858 
1859 #ifdef CONFIG_USB_MUSB_OTG
1860 	put_device(musb->xceiv->dev);
1861 #endif
1862 
1863 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1864 	musb_platform_exit(musb);
1865 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1866 
1867 	if (musb->clock) {
1868 		clk_disable(musb->clock);
1869 		clk_put(musb->clock);
1870 	}
1871 
1872 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1873 	usb_put_hcd(musb_to_hcd(musb));
1874 #else
1875 	kfree(musb);
1876 #endif
1877 }
1878 
1879 /*
1880  * Perform generic per-controller initialization.
1881  *
1882  * @pDevice: the controller (already clocked, etc)
1883  * @nIrq: irq
1884  * @mregs: virtual address of controller registers,
1885  *	not yet corrected for platform-specific offsets
1886  */
1887 static int __init
1888 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1889 {
1890 	int			status;
1891 	struct musb		*musb;
1892 	struct musb_hdrc_platform_data *plat = dev->platform_data;
1893 
1894 	/* The driver might handle more features than the board; OK.
1895 	 * Fail when the board needs a feature that's not enabled.
1896 	 */
1897 	if (!plat) {
1898 		dev_dbg(dev, "no platform_data?\n");
1899 		return -ENODEV;
1900 	}
1901 	switch (plat->mode) {
1902 	case MUSB_HOST:
1903 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1904 		break;
1905 #else
1906 		goto bad_config;
1907 #endif
1908 	case MUSB_PERIPHERAL:
1909 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1910 		break;
1911 #else
1912 		goto bad_config;
1913 #endif
1914 	case MUSB_OTG:
1915 #ifdef CONFIG_USB_MUSB_OTG
1916 		break;
1917 #else
1918 bad_config:
1919 #endif
1920 	default:
1921 		dev_err(dev, "incompatible Kconfig role setting\n");
1922 		return -EINVAL;
1923 	}
1924 
1925 	/* allocate */
1926 	musb = allocate_instance(dev, plat->config, ctrl);
1927 	if (!musb)
1928 		return -ENOMEM;
1929 
1930 	spin_lock_init(&musb->lock);
1931 	musb->board_mode = plat->mode;
1932 	musb->board_set_power = plat->set_power;
1933 	musb->set_clock = plat->set_clock;
1934 	musb->min_power = plat->min_power;
1935 
1936 	/* Clock usage is chip-specific ... functional clock (DaVinci,
1937 	 * OMAP2430), or PHY ref (some TUSB6010 boards).  All this core
1938 	 * code does is make sure a clock handle is available; platform
1939 	 * code manages it during start/stop and suspend/resume.
1940 	 */
1941 	if (plat->clock) {
1942 		musb->clock = clk_get(dev, plat->clock);
1943 		if (IS_ERR(musb->clock)) {
1944 			status = PTR_ERR(musb->clock);
1945 			musb->clock = NULL;
1946 			goto fail;
1947 		}
1948 	}
1949 
1950 	/* The musb_platform_init() call:
1951 	 *   - adjusts musb->mregs and musb->isr if needed,
1952 	 *   - may initialize an integrated tranceiver
1953 	 *   - initializes musb->xceiv, usually by otg_get_transceiver()
1954 	 *   - activates clocks.
1955 	 *   - stops powering VBUS
1956 	 *   - assigns musb->board_set_vbus if host mode is enabled
1957 	 *
1958 	 * There are various transciever configurations.  Blackfin,
1959 	 * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
1960 	 * external/discrete ones in various flavors (twl4030 family,
1961 	 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1962 	 */
1963 	musb->isr = generic_interrupt;
1964 	status = musb_platform_init(musb);
1965 
1966 	if (status < 0)
1967 		goto fail;
1968 	if (!musb->isr) {
1969 		status = -ENODEV;
1970 		goto fail2;
1971 	}
1972 
1973 #ifndef CONFIG_MUSB_PIO_ONLY
1974 	if (use_dma && dev->dma_mask) {
1975 		struct dma_controller	*c;
1976 
1977 		c = dma_controller_create(musb, musb->mregs);
1978 		musb->dma_controller = c;
1979 		if (c)
1980 			(void) c->start(c);
1981 	}
1982 #endif
1983 	/* ideally this would be abstracted in platform setup */
1984 	if (!is_dma_capable() || !musb->dma_controller)
1985 		dev->dma_mask = NULL;
1986 
1987 	/* be sure interrupts are disabled before connecting ISR */
1988 	musb_platform_disable(musb);
1989 	musb_generic_disable(musb);
1990 
1991 	/* setup musb parts of the core (especially endpoints) */
1992 	status = musb_core_init(plat->config->multipoint
1993 			? MUSB_CONTROLLER_MHDRC
1994 			: MUSB_CONTROLLER_HDRC, musb);
1995 	if (status < 0)
1996 		goto fail2;
1997 
1998 #ifdef CONFIG_USB_MUSB_OTG
1999 	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2000 #endif
2001 
2002 	/* Init IRQ workqueue before request_irq */
2003 	INIT_WORK(&musb->irq_work, musb_irq_work);
2004 
2005 	/* attach to the IRQ */
2006 	if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2007 		dev_err(dev, "request_irq %d failed!\n", nIrq);
2008 		status = -ENODEV;
2009 		goto fail2;
2010 	}
2011 	musb->nIrq = nIrq;
2012 /* FIXME this handles wakeup irqs wrong */
2013 	if (enable_irq_wake(nIrq) == 0) {
2014 		musb->irq_wake = 1;
2015 		device_init_wakeup(dev, 1);
2016 	} else {
2017 		musb->irq_wake = 0;
2018 	}
2019 
2020 	pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2021 			musb_driver_name,
2022 			({char *s;
2023 			switch (musb->board_mode) {
2024 			case MUSB_HOST:		s = "Host"; break;
2025 			case MUSB_PERIPHERAL:	s = "Peripheral"; break;
2026 			default:		s = "OTG"; break;
2027 			}; s; }),
2028 			ctrl,
2029 			(is_dma_capable() && musb->dma_controller)
2030 				? "DMA" : "PIO",
2031 			musb->nIrq);
2032 
2033 	/* host side needs more setup */
2034 	if (is_host_enabled(musb)) {
2035 		struct usb_hcd	*hcd = musb_to_hcd(musb);
2036 
2037 		otg_set_host(musb->xceiv, &hcd->self);
2038 
2039 		if (is_otg_enabled(musb))
2040 			hcd->self.otg_port = 1;
2041 		musb->xceiv->host = &hcd->self;
2042 		hcd->power_budget = 2 * (plat->power ? : 250);
2043 	}
2044 
2045 	/* For the host-only role, we can activate right away.
2046 	 * (We expect the ID pin to be forcibly grounded!!)
2047 	 * Otherwise, wait till the gadget driver hooks up.
2048 	 */
2049 	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2050 		MUSB_HST_MODE(musb);
2051 		musb->xceiv->default_a = 1;
2052 		musb->xceiv->state = OTG_STATE_A_IDLE;
2053 
2054 		status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2055 		if (status)
2056 			goto fail;
2057 
2058 		DBG(1, "%s mode, status %d, devctl %02x %c\n",
2059 			"HOST", status,
2060 			musb_readb(musb->mregs, MUSB_DEVCTL),
2061 			(musb_readb(musb->mregs, MUSB_DEVCTL)
2062 					& MUSB_DEVCTL_BDEVICE
2063 				? 'B' : 'A'));
2064 
2065 	} else /* peripheral is enabled */ {
2066 		MUSB_DEV_MODE(musb);
2067 		musb->xceiv->default_a = 0;
2068 		musb->xceiv->state = OTG_STATE_B_IDLE;
2069 
2070 		status = musb_gadget_setup(musb);
2071 		if (status)
2072 			goto fail;
2073 
2074 		DBG(1, "%s mode, status %d, dev%02x\n",
2075 			is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2076 			status,
2077 			musb_readb(musb->mregs, MUSB_DEVCTL));
2078 
2079 	}
2080 
2081 #ifdef CONFIG_SYSFS
2082 	status = device_create_file(dev, &dev_attr_mode);
2083 	status = device_create_file(dev, &dev_attr_vbus);
2084 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2085 	status = device_create_file(dev, &dev_attr_srp);
2086 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2087 	status = 0;
2088 #endif
2089 	if (status)
2090 		goto fail2;
2091 
2092 	return 0;
2093 
2094 fail2:
2095 #ifdef CONFIG_SYSFS
2096 	device_remove_file(musb->controller, &dev_attr_mode);
2097 	device_remove_file(musb->controller, &dev_attr_vbus);
2098 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2099 	device_remove_file(musb->controller, &dev_attr_srp);
2100 #endif
2101 #endif
2102 	musb_platform_exit(musb);
2103 fail:
2104 	dev_err(musb->controller,
2105 		"musb_init_controller failed with status %d\n", status);
2106 
2107 	if (musb->clock)
2108 		clk_put(musb->clock);
2109 	device_init_wakeup(dev, 0);
2110 	musb_free(musb);
2111 
2112 	return status;
2113 
2114 }
2115 
2116 /*-------------------------------------------------------------------------*/
2117 
2118 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2119  * bridge to a platform device; this driver then suffices.
2120  */
2121 
2122 #ifndef CONFIG_MUSB_PIO_ONLY
2123 static u64	*orig_dma_mask;
2124 #endif
2125 
2126 static int __init musb_probe(struct platform_device *pdev)
2127 {
2128 	struct device	*dev = &pdev->dev;
2129 	int		irq = platform_get_irq(pdev, 0);
2130 	struct resource	*iomem;
2131 	void __iomem	*base;
2132 
2133 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2134 	if (!iomem || irq == 0)
2135 		return -ENODEV;
2136 
2137 	base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2138 	if (!base) {
2139 		dev_err(dev, "ioremap failed\n");
2140 		return -ENOMEM;
2141 	}
2142 
2143 #ifndef CONFIG_MUSB_PIO_ONLY
2144 	/* clobbered by use_dma=n */
2145 	orig_dma_mask = dev->dma_mask;
2146 #endif
2147 	return musb_init_controller(dev, irq, base);
2148 }
2149 
2150 static int __exit musb_remove(struct platform_device *pdev)
2151 {
2152 	struct musb	*musb = dev_to_musb(&pdev->dev);
2153 	void __iomem	*ctrl_base = musb->ctrl_base;
2154 
2155 	/* this gets called on rmmod.
2156 	 *  - Host mode: host may still be active
2157 	 *  - Peripheral mode: peripheral is deactivated (or never-activated)
2158 	 *  - OTG mode: both roles are deactivated (or never-activated)
2159 	 */
2160 	musb_shutdown(pdev);
2161 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2162 	if (musb->board_mode == MUSB_HOST)
2163 		usb_remove_hcd(musb_to_hcd(musb));
2164 #endif
2165 	musb_free(musb);
2166 	iounmap(ctrl_base);
2167 	device_init_wakeup(&pdev->dev, 0);
2168 #ifndef CONFIG_MUSB_PIO_ONLY
2169 	pdev->dev.dma_mask = orig_dma_mask;
2170 #endif
2171 	return 0;
2172 }
2173 
2174 #ifdef	CONFIG_PM
2175 
2176 static int musb_suspend(struct device *dev)
2177 {
2178 	struct platform_device *pdev = to_platform_device(dev);
2179 	unsigned long	flags;
2180 	struct musb	*musb = dev_to_musb(&pdev->dev);
2181 
2182 	if (!musb->clock)
2183 		return 0;
2184 
2185 	spin_lock_irqsave(&musb->lock, flags);
2186 
2187 	if (is_peripheral_active(musb)) {
2188 		/* FIXME force disconnect unless we know USB will wake
2189 		 * the system up quickly enough to respond ...
2190 		 */
2191 	} else if (is_host_active(musb)) {
2192 		/* we know all the children are suspended; sometimes
2193 		 * they will even be wakeup-enabled.
2194 		 */
2195 	}
2196 
2197 	if (musb->set_clock)
2198 		musb->set_clock(musb->clock, 0);
2199 	else
2200 		clk_disable(musb->clock);
2201 	spin_unlock_irqrestore(&musb->lock, flags);
2202 	return 0;
2203 }
2204 
2205 static int musb_resume_noirq(struct device *dev)
2206 {
2207 	struct platform_device *pdev = to_platform_device(dev);
2208 	struct musb	*musb = dev_to_musb(&pdev->dev);
2209 
2210 	if (!musb->clock)
2211 		return 0;
2212 
2213 	if (musb->set_clock)
2214 		musb->set_clock(musb->clock, 1);
2215 	else
2216 		clk_enable(musb->clock);
2217 
2218 	/* for static cmos like DaVinci, register values were preserved
2219 	 * unless for some reason the whole soc powered down or the USB
2220 	 * module got reset through the PSC (vs just being disabled).
2221 	 */
2222 	return 0;
2223 }
2224 
2225 static const struct dev_pm_ops musb_dev_pm_ops = {
2226 	.suspend	= musb_suspend,
2227 	.resume_noirq	= musb_resume_noirq,
2228 };
2229 
2230 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2231 #else
2232 #define	MUSB_DEV_PM_OPS	NULL
2233 #endif
2234 
2235 static struct platform_driver musb_driver = {
2236 	.driver = {
2237 		.name		= (char *)musb_driver_name,
2238 		.bus		= &platform_bus_type,
2239 		.owner		= THIS_MODULE,
2240 		.pm		= MUSB_DEV_PM_OPS,
2241 	},
2242 	.remove		= __exit_p(musb_remove),
2243 	.shutdown	= musb_shutdown,
2244 };
2245 
2246 /*-------------------------------------------------------------------------*/
2247 
2248 static int __init musb_init(void)
2249 {
2250 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2251 	if (usb_disabled())
2252 		return 0;
2253 #endif
2254 
2255 	pr_info("%s: version " MUSB_VERSION ", "
2256 #ifdef CONFIG_MUSB_PIO_ONLY
2257 		"pio"
2258 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2259 		"cppi-dma"
2260 #elif defined(CONFIG_USB_INVENTRA_DMA)
2261 		"musb-dma"
2262 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2263 		"tusb-omap-dma"
2264 #else
2265 		"?dma?"
2266 #endif
2267 		", "
2268 #ifdef CONFIG_USB_MUSB_OTG
2269 		"otg (peripheral+host)"
2270 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2271 		"peripheral"
2272 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2273 		"host"
2274 #endif
2275 		", debug=%d\n",
2276 		musb_driver_name, musb_debug);
2277 	return platform_driver_probe(&musb_driver, musb_probe);
2278 }
2279 
2280 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2281  * and before usb gadget and host-side drivers start to register
2282  */
2283 fs_initcall(musb_init);
2284 
2285 static void __exit musb_cleanup(void)
2286 {
2287 	platform_driver_unregister(&musb_driver);
2288 }
2289 module_exit(musb_cleanup);
2290