1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/init.h> 97 #include <linux/list.h> 98 #include <linux/kobject.h> 99 #include <linux/prefetch.h> 100 #include <linux/platform_device.h> 101 #include <linux/io.h> 102 #include <linux/dma-mapping.h> 103 104 #include "musb_core.h" 105 106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 107 108 109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 111 112 #define MUSB_VERSION "6.0" 113 114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 115 116 #define MUSB_DRIVER_NAME "musb-hdrc" 117 const char musb_driver_name[] = MUSB_DRIVER_NAME; 118 119 MODULE_DESCRIPTION(DRIVER_INFO); 120 MODULE_AUTHOR(DRIVER_AUTHOR); 121 MODULE_LICENSE("GPL"); 122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 123 124 125 /*-------------------------------------------------------------------------*/ 126 127 static inline struct musb *dev_to_musb(struct device *dev) 128 { 129 return dev_get_drvdata(dev); 130 } 131 132 /*-------------------------------------------------------------------------*/ 133 134 #ifndef CONFIG_BLACKFIN 135 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 136 { 137 void __iomem *addr = phy->io_priv; 138 int i = 0; 139 u8 r; 140 u8 power; 141 int ret; 142 143 pm_runtime_get_sync(phy->io_dev); 144 145 /* Make sure the transceiver is not in low power mode */ 146 power = musb_readb(addr, MUSB_POWER); 147 power &= ~MUSB_POWER_SUSPENDM; 148 musb_writeb(addr, MUSB_POWER, power); 149 150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 152 */ 153 154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 157 158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 159 & MUSB_ULPI_REG_CMPLT)) { 160 i++; 161 if (i == 10000) { 162 ret = -ETIMEDOUT; 163 goto out; 164 } 165 166 } 167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 168 r &= ~MUSB_ULPI_REG_CMPLT; 169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 170 171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 172 173 out: 174 pm_runtime_put(phy->io_dev); 175 176 return ret; 177 } 178 179 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 180 { 181 void __iomem *addr = phy->io_priv; 182 int i = 0; 183 u8 r = 0; 184 u8 power; 185 int ret = 0; 186 187 pm_runtime_get_sync(phy->io_dev); 188 189 /* Make sure the transceiver is not in low power mode */ 190 power = musb_readb(addr, MUSB_POWER); 191 power &= ~MUSB_POWER_SUSPENDM; 192 musb_writeb(addr, MUSB_POWER, power); 193 194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 197 198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 199 & MUSB_ULPI_REG_CMPLT)) { 200 i++; 201 if (i == 10000) { 202 ret = -ETIMEDOUT; 203 goto out; 204 } 205 } 206 207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 208 r &= ~MUSB_ULPI_REG_CMPLT; 209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 210 211 out: 212 pm_runtime_put(phy->io_dev); 213 214 return ret; 215 } 216 #else 217 #define musb_ulpi_read NULL 218 #define musb_ulpi_write NULL 219 #endif 220 221 static struct usb_phy_io_ops musb_ulpi_access = { 222 .read = musb_ulpi_read, 223 .write = musb_ulpi_write, 224 }; 225 226 /*-------------------------------------------------------------------------*/ 227 228 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 229 230 /* 231 * Load an endpoint's FIFO 232 */ 233 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 234 { 235 struct musb *musb = hw_ep->musb; 236 void __iomem *fifo = hw_ep->fifo; 237 238 if (unlikely(len == 0)) 239 return; 240 241 prefetch((u8 *)src); 242 243 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 244 'T', hw_ep->epnum, fifo, len, src); 245 246 /* we can't assume unaligned reads work */ 247 if (likely((0x01 & (unsigned long) src) == 0)) { 248 u16 index = 0; 249 250 /* best case is 32bit-aligned source address */ 251 if ((0x02 & (unsigned long) src) == 0) { 252 if (len >= 4) { 253 iowrite32_rep(fifo, src + index, len >> 2); 254 index += len & ~0x03; 255 } 256 if (len & 0x02) { 257 musb_writew(fifo, 0, *(u16 *)&src[index]); 258 index += 2; 259 } 260 } else { 261 if (len >= 2) { 262 iowrite16_rep(fifo, src + index, len >> 1); 263 index += len & ~0x01; 264 } 265 } 266 if (len & 0x01) 267 musb_writeb(fifo, 0, src[index]); 268 } else { 269 /* byte aligned */ 270 iowrite8_rep(fifo, src, len); 271 } 272 } 273 274 #if !defined(CONFIG_USB_MUSB_AM35X) 275 /* 276 * Unload an endpoint's FIFO 277 */ 278 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 279 { 280 struct musb *musb = hw_ep->musb; 281 void __iomem *fifo = hw_ep->fifo; 282 283 if (unlikely(len == 0)) 284 return; 285 286 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 287 'R', hw_ep->epnum, fifo, len, dst); 288 289 /* we can't assume unaligned writes work */ 290 if (likely((0x01 & (unsigned long) dst) == 0)) { 291 u16 index = 0; 292 293 /* best case is 32bit-aligned destination address */ 294 if ((0x02 & (unsigned long) dst) == 0) { 295 if (len >= 4) { 296 ioread32_rep(fifo, dst, len >> 2); 297 index = len & ~0x03; 298 } 299 if (len & 0x02) { 300 *(u16 *)&dst[index] = musb_readw(fifo, 0); 301 index += 2; 302 } 303 } else { 304 if (len >= 2) { 305 ioread16_rep(fifo, dst, len >> 1); 306 index = len & ~0x01; 307 } 308 } 309 if (len & 0x01) 310 dst[index] = musb_readb(fifo, 0); 311 } else { 312 /* byte aligned */ 313 ioread8_rep(fifo, dst, len); 314 } 315 } 316 #endif 317 318 #endif /* normal PIO */ 319 320 321 /*-------------------------------------------------------------------------*/ 322 323 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 324 static const u8 musb_test_packet[53] = { 325 /* implicit SYNC then DATA0 to start */ 326 327 /* JKJKJKJK x9 */ 328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 329 /* JJKKJJKK x8 */ 330 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 331 /* JJJJKKKK x8 */ 332 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 333 /* JJJJJJJKKKKKKK x8 */ 334 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 335 /* JJJJJJJK x8 */ 336 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 337 /* JKKKKKKK x10, JK */ 338 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 339 340 /* implicit CRC16 then EOP to end */ 341 }; 342 343 void musb_load_testpacket(struct musb *musb) 344 { 345 void __iomem *regs = musb->endpoints[0].regs; 346 347 musb_ep_select(musb->mregs, 0); 348 musb_write_fifo(musb->control_ep, 349 sizeof(musb_test_packet), musb_test_packet); 350 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 351 } 352 353 /*-------------------------------------------------------------------------*/ 354 355 /* 356 * Handles OTG hnp timeouts, such as b_ase0_brst 357 */ 358 static void musb_otg_timer_func(unsigned long data) 359 { 360 struct musb *musb = (struct musb *)data; 361 unsigned long flags; 362 363 spin_lock_irqsave(&musb->lock, flags); 364 switch (musb->xceiv->state) { 365 case OTG_STATE_B_WAIT_ACON: 366 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 367 musb_g_disconnect(musb); 368 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 369 musb->is_active = 0; 370 break; 371 case OTG_STATE_A_SUSPEND: 372 case OTG_STATE_A_WAIT_BCON: 373 dev_dbg(musb->controller, "HNP: %s timeout\n", 374 usb_otg_state_string(musb->xceiv->state)); 375 musb_platform_set_vbus(musb, 0); 376 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 377 break; 378 default: 379 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 380 usb_otg_state_string(musb->xceiv->state)); 381 } 382 spin_unlock_irqrestore(&musb->lock, flags); 383 } 384 385 /* 386 * Stops the HNP transition. Caller must take care of locking. 387 */ 388 void musb_hnp_stop(struct musb *musb) 389 { 390 struct usb_hcd *hcd = musb->hcd; 391 void __iomem *mbase = musb->mregs; 392 u8 reg; 393 394 dev_dbg(musb->controller, "HNP: stop from %s\n", 395 usb_otg_state_string(musb->xceiv->state)); 396 397 switch (musb->xceiv->state) { 398 case OTG_STATE_A_PERIPHERAL: 399 musb_g_disconnect(musb); 400 dev_dbg(musb->controller, "HNP: back to %s\n", 401 usb_otg_state_string(musb->xceiv->state)); 402 break; 403 case OTG_STATE_B_HOST: 404 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 405 if (hcd) 406 hcd->self.is_b_host = 0; 407 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 408 MUSB_DEV_MODE(musb); 409 reg = musb_readb(mbase, MUSB_POWER); 410 reg |= MUSB_POWER_SUSPENDM; 411 musb_writeb(mbase, MUSB_POWER, reg); 412 /* REVISIT: Start SESSION_REQUEST here? */ 413 break; 414 default: 415 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 416 usb_otg_state_string(musb->xceiv->state)); 417 } 418 419 /* 420 * When returning to A state after HNP, avoid hub_port_rebounce(), 421 * which cause occasional OPT A "Did not receive reset after connect" 422 * errors. 423 */ 424 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 425 } 426 427 /* 428 * Interrupt Service Routine to record USB "global" interrupts. 429 * Since these do not happen often and signify things of 430 * paramount importance, it seems OK to check them individually; 431 * the order of the tests is specified in the manual 432 * 433 * @param musb instance pointer 434 * @param int_usb register contents 435 * @param devctl 436 * @param power 437 */ 438 439 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 440 u8 devctl) 441 { 442 struct usb_otg *otg = musb->xceiv->otg; 443 irqreturn_t handled = IRQ_NONE; 444 445 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl, 446 int_usb); 447 448 /* in host mode, the peripheral may issue remote wakeup. 449 * in peripheral mode, the host may resume the link. 450 * spurious RESUME irqs happen too, paired with SUSPEND. 451 */ 452 if (int_usb & MUSB_INTR_RESUME) { 453 handled = IRQ_HANDLED; 454 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state)); 455 456 if (devctl & MUSB_DEVCTL_HM) { 457 void __iomem *mbase = musb->mregs; 458 u8 power; 459 460 switch (musb->xceiv->state) { 461 case OTG_STATE_A_SUSPEND: 462 /* remote wakeup? later, GetPortStatus 463 * will stop RESUME signaling 464 */ 465 466 power = musb_readb(musb->mregs, MUSB_POWER); 467 if (power & MUSB_POWER_SUSPENDM) { 468 /* spurious */ 469 musb->int_usb &= ~MUSB_INTR_SUSPEND; 470 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 471 break; 472 } 473 474 power &= ~MUSB_POWER_SUSPENDM; 475 musb_writeb(mbase, MUSB_POWER, 476 power | MUSB_POWER_RESUME); 477 478 musb->port1_status |= 479 (USB_PORT_STAT_C_SUSPEND << 16) 480 | MUSB_PORT_STAT_RESUME; 481 musb->rh_timer = jiffies 482 + msecs_to_jiffies(20); 483 484 musb->xceiv->state = OTG_STATE_A_HOST; 485 musb->is_active = 1; 486 musb_host_resume_root_hub(musb); 487 break; 488 case OTG_STATE_B_WAIT_ACON: 489 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 490 musb->is_active = 1; 491 MUSB_DEV_MODE(musb); 492 break; 493 default: 494 WARNING("bogus %s RESUME (%s)\n", 495 "host", 496 usb_otg_state_string(musb->xceiv->state)); 497 } 498 } else { 499 switch (musb->xceiv->state) { 500 case OTG_STATE_A_SUSPEND: 501 /* possibly DISCONNECT is upcoming */ 502 musb->xceiv->state = OTG_STATE_A_HOST; 503 musb_host_resume_root_hub(musb); 504 break; 505 case OTG_STATE_B_WAIT_ACON: 506 case OTG_STATE_B_PERIPHERAL: 507 /* disconnect while suspended? we may 508 * not get a disconnect irq... 509 */ 510 if ((devctl & MUSB_DEVCTL_VBUS) 511 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 512 ) { 513 musb->int_usb |= MUSB_INTR_DISCONNECT; 514 musb->int_usb &= ~MUSB_INTR_SUSPEND; 515 break; 516 } 517 musb_g_resume(musb); 518 break; 519 case OTG_STATE_B_IDLE: 520 musb->int_usb &= ~MUSB_INTR_SUSPEND; 521 break; 522 default: 523 WARNING("bogus %s RESUME (%s)\n", 524 "peripheral", 525 usb_otg_state_string(musb->xceiv->state)); 526 } 527 } 528 } 529 530 /* see manual for the order of the tests */ 531 if (int_usb & MUSB_INTR_SESSREQ) { 532 void __iomem *mbase = musb->mregs; 533 534 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 535 && (devctl & MUSB_DEVCTL_BDEVICE)) { 536 dev_dbg(musb->controller, "SessReq while on B state\n"); 537 return IRQ_HANDLED; 538 } 539 540 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 541 usb_otg_state_string(musb->xceiv->state)); 542 543 /* IRQ arrives from ID pin sense or (later, if VBUS power 544 * is removed) SRP. responses are time critical: 545 * - turn on VBUS (with silicon-specific mechanism) 546 * - go through A_WAIT_VRISE 547 * - ... to A_WAIT_BCON. 548 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 549 */ 550 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 551 musb->ep0_stage = MUSB_EP0_START; 552 musb->xceiv->state = OTG_STATE_A_IDLE; 553 MUSB_HST_MODE(musb); 554 musb_platform_set_vbus(musb, 1); 555 556 handled = IRQ_HANDLED; 557 } 558 559 if (int_usb & MUSB_INTR_VBUSERROR) { 560 int ignore = 0; 561 562 /* During connection as an A-Device, we may see a short 563 * current spikes causing voltage drop, because of cable 564 * and peripheral capacitance combined with vbus draw. 565 * (So: less common with truly self-powered devices, where 566 * vbus doesn't act like a power supply.) 567 * 568 * Such spikes are short; usually less than ~500 usec, max 569 * of ~2 msec. That is, they're not sustained overcurrent 570 * errors, though they're reported using VBUSERROR irqs. 571 * 572 * Workarounds: (a) hardware: use self powered devices. 573 * (b) software: ignore non-repeated VBUS errors. 574 * 575 * REVISIT: do delays from lots of DEBUG_KERNEL checks 576 * make trouble here, keeping VBUS < 4.4V ? 577 */ 578 switch (musb->xceiv->state) { 579 case OTG_STATE_A_HOST: 580 /* recovery is dicey once we've gotten past the 581 * initial stages of enumeration, but if VBUS 582 * stayed ok at the other end of the link, and 583 * another reset is due (at least for high speed, 584 * to redo the chirp etc), it might work OK... 585 */ 586 case OTG_STATE_A_WAIT_BCON: 587 case OTG_STATE_A_WAIT_VRISE: 588 if (musb->vbuserr_retry) { 589 void __iomem *mbase = musb->mregs; 590 591 musb->vbuserr_retry--; 592 ignore = 1; 593 devctl |= MUSB_DEVCTL_SESSION; 594 musb_writeb(mbase, MUSB_DEVCTL, devctl); 595 } else { 596 musb->port1_status |= 597 USB_PORT_STAT_OVERCURRENT 598 | (USB_PORT_STAT_C_OVERCURRENT << 16); 599 } 600 break; 601 default: 602 break; 603 } 604 605 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, 606 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 607 usb_otg_state_string(musb->xceiv->state), 608 devctl, 609 ({ char *s; 610 switch (devctl & MUSB_DEVCTL_VBUS) { 611 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 612 s = "<SessEnd"; break; 613 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 614 s = "<AValid"; break; 615 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 616 s = "<VBusValid"; break; 617 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 618 default: 619 s = "VALID"; break; 620 }; s; }), 621 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 622 musb->port1_status); 623 624 /* go through A_WAIT_VFALL then start a new session */ 625 if (!ignore) 626 musb_platform_set_vbus(musb, 0); 627 handled = IRQ_HANDLED; 628 } 629 630 if (int_usb & MUSB_INTR_SUSPEND) { 631 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n", 632 usb_otg_state_string(musb->xceiv->state), devctl); 633 handled = IRQ_HANDLED; 634 635 switch (musb->xceiv->state) { 636 case OTG_STATE_A_PERIPHERAL: 637 /* We also come here if the cable is removed, since 638 * this silicon doesn't report ID-no-longer-grounded. 639 * 640 * We depend on T(a_wait_bcon) to shut us down, and 641 * hope users don't do anything dicey during this 642 * undesired detour through A_WAIT_BCON. 643 */ 644 musb_hnp_stop(musb); 645 musb_host_resume_root_hub(musb); 646 musb_root_disconnect(musb); 647 musb_platform_try_idle(musb, jiffies 648 + msecs_to_jiffies(musb->a_wait_bcon 649 ? : OTG_TIME_A_WAIT_BCON)); 650 651 break; 652 case OTG_STATE_B_IDLE: 653 if (!musb->is_active) 654 break; 655 case OTG_STATE_B_PERIPHERAL: 656 musb_g_suspend(musb); 657 musb->is_active = otg->gadget->b_hnp_enable; 658 if (musb->is_active) { 659 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 660 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 661 mod_timer(&musb->otg_timer, jiffies 662 + msecs_to_jiffies( 663 OTG_TIME_B_ASE0_BRST)); 664 } 665 break; 666 case OTG_STATE_A_WAIT_BCON: 667 if (musb->a_wait_bcon != 0) 668 musb_platform_try_idle(musb, jiffies 669 + msecs_to_jiffies(musb->a_wait_bcon)); 670 break; 671 case OTG_STATE_A_HOST: 672 musb->xceiv->state = OTG_STATE_A_SUSPEND; 673 musb->is_active = otg->host->b_hnp_enable; 674 break; 675 case OTG_STATE_B_HOST: 676 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 677 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 678 break; 679 default: 680 /* "should not happen" */ 681 musb->is_active = 0; 682 break; 683 } 684 } 685 686 if (int_usb & MUSB_INTR_CONNECT) { 687 struct usb_hcd *hcd = musb->hcd; 688 689 handled = IRQ_HANDLED; 690 musb->is_active = 1; 691 692 musb->ep0_stage = MUSB_EP0_START; 693 694 /* flush endpoints when transitioning from Device Mode */ 695 if (is_peripheral_active(musb)) { 696 /* REVISIT HNP; just force disconnect */ 697 } 698 musb->intrtxe = musb->epmask; 699 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); 700 musb->intrrxe = musb->epmask & 0xfffe; 701 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); 702 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 703 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 704 |USB_PORT_STAT_HIGH_SPEED 705 |USB_PORT_STAT_ENABLE 706 ); 707 musb->port1_status |= USB_PORT_STAT_CONNECTION 708 |(USB_PORT_STAT_C_CONNECTION << 16); 709 710 /* high vs full speed is just a guess until after reset */ 711 if (devctl & MUSB_DEVCTL_LSDEV) 712 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 713 714 /* indicate new connection to OTG machine */ 715 switch (musb->xceiv->state) { 716 case OTG_STATE_B_PERIPHERAL: 717 if (int_usb & MUSB_INTR_SUSPEND) { 718 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 719 int_usb &= ~MUSB_INTR_SUSPEND; 720 goto b_host; 721 } else 722 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 723 break; 724 case OTG_STATE_B_WAIT_ACON: 725 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 726 b_host: 727 musb->xceiv->state = OTG_STATE_B_HOST; 728 if (musb->hcd) 729 musb->hcd->self.is_b_host = 1; 730 del_timer(&musb->otg_timer); 731 break; 732 default: 733 if ((devctl & MUSB_DEVCTL_VBUS) 734 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 735 musb->xceiv->state = OTG_STATE_A_HOST; 736 if (hcd) 737 hcd->self.is_b_host = 0; 738 } 739 break; 740 } 741 742 musb_host_poke_root_hub(musb); 743 744 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 745 usb_otg_state_string(musb->xceiv->state), devctl); 746 } 747 748 if (int_usb & MUSB_INTR_DISCONNECT) { 749 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 750 usb_otg_state_string(musb->xceiv->state), 751 MUSB_MODE(musb), devctl); 752 handled = IRQ_HANDLED; 753 754 switch (musb->xceiv->state) { 755 case OTG_STATE_A_HOST: 756 case OTG_STATE_A_SUSPEND: 757 musb_host_resume_root_hub(musb); 758 musb_root_disconnect(musb); 759 if (musb->a_wait_bcon != 0) 760 musb_platform_try_idle(musb, jiffies 761 + msecs_to_jiffies(musb->a_wait_bcon)); 762 break; 763 case OTG_STATE_B_HOST: 764 /* REVISIT this behaves for "real disconnect" 765 * cases; make sure the other transitions from 766 * from B_HOST act right too. The B_HOST code 767 * in hnp_stop() is currently not used... 768 */ 769 musb_root_disconnect(musb); 770 if (musb->hcd) 771 musb->hcd->self.is_b_host = 0; 772 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 773 MUSB_DEV_MODE(musb); 774 musb_g_disconnect(musb); 775 break; 776 case OTG_STATE_A_PERIPHERAL: 777 musb_hnp_stop(musb); 778 musb_root_disconnect(musb); 779 /* FALLTHROUGH */ 780 case OTG_STATE_B_WAIT_ACON: 781 /* FALLTHROUGH */ 782 case OTG_STATE_B_PERIPHERAL: 783 case OTG_STATE_B_IDLE: 784 musb_g_disconnect(musb); 785 break; 786 default: 787 WARNING("unhandled DISCONNECT transition (%s)\n", 788 usb_otg_state_string(musb->xceiv->state)); 789 break; 790 } 791 } 792 793 /* mentor saves a bit: bus reset and babble share the same irq. 794 * only host sees babble; only peripheral sees bus reset. 795 */ 796 if (int_usb & MUSB_INTR_RESET) { 797 handled = IRQ_HANDLED; 798 if ((devctl & MUSB_DEVCTL_HM) != 0) { 799 /* 800 * Looks like non-HS BABBLE can be ignored, but 801 * HS BABBLE is an error condition. For HS the solution 802 * is to avoid babble in the first place and fix what 803 * caused BABBLE. When HS BABBLE happens we can only 804 * stop the session. 805 */ 806 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 807 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 808 else { 809 ERR("Stopping host session -- babble\n"); 810 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 811 } 812 } else { 813 dev_dbg(musb->controller, "BUS RESET as %s\n", 814 usb_otg_state_string(musb->xceiv->state)); 815 switch (musb->xceiv->state) { 816 case OTG_STATE_A_SUSPEND: 817 musb_g_reset(musb); 818 /* FALLTHROUGH */ 819 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 820 /* never use invalid T(a_wait_bcon) */ 821 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 822 usb_otg_state_string(musb->xceiv->state), 823 TA_WAIT_BCON(musb)); 824 mod_timer(&musb->otg_timer, jiffies 825 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 826 break; 827 case OTG_STATE_A_PERIPHERAL: 828 del_timer(&musb->otg_timer); 829 musb_g_reset(musb); 830 break; 831 case OTG_STATE_B_WAIT_ACON: 832 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 833 usb_otg_state_string(musb->xceiv->state)); 834 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 835 musb_g_reset(musb); 836 break; 837 case OTG_STATE_B_IDLE: 838 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 839 /* FALLTHROUGH */ 840 case OTG_STATE_B_PERIPHERAL: 841 musb_g_reset(musb); 842 break; 843 default: 844 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 845 usb_otg_state_string(musb->xceiv->state)); 846 } 847 } 848 } 849 850 #if 0 851 /* REVISIT ... this would be for multiplexing periodic endpoints, or 852 * supporting transfer phasing to prevent exceeding ISO bandwidth 853 * limits of a given frame or microframe. 854 * 855 * It's not needed for peripheral side, which dedicates endpoints; 856 * though it _might_ use SOF irqs for other purposes. 857 * 858 * And it's not currently needed for host side, which also dedicates 859 * endpoints, relies on TX/RX interval registers, and isn't claimed 860 * to support ISO transfers yet. 861 */ 862 if (int_usb & MUSB_INTR_SOF) { 863 void __iomem *mbase = musb->mregs; 864 struct musb_hw_ep *ep; 865 u8 epnum; 866 u16 frame; 867 868 dev_dbg(musb->controller, "START_OF_FRAME\n"); 869 handled = IRQ_HANDLED; 870 871 /* start any periodic Tx transfers waiting for current frame */ 872 frame = musb_readw(mbase, MUSB_FRAME); 873 ep = musb->endpoints; 874 for (epnum = 1; (epnum < musb->nr_endpoints) 875 && (musb->epmask >= (1 << epnum)); 876 epnum++, ep++) { 877 /* 878 * FIXME handle framecounter wraps (12 bits) 879 * eliminate duplicated StartUrb logic 880 */ 881 if (ep->dwWaitFrame >= frame) { 882 ep->dwWaitFrame = 0; 883 pr_debug("SOF --> periodic TX%s on %d\n", 884 ep->tx_channel ? " DMA" : "", 885 epnum); 886 if (!ep->tx_channel) 887 musb_h_tx_start(musb, epnum); 888 else 889 cppi_hostdma_start(musb, epnum); 890 } 891 } /* end of for loop */ 892 } 893 #endif 894 895 schedule_work(&musb->irq_work); 896 897 return handled; 898 } 899 900 /*-------------------------------------------------------------------------*/ 901 902 static void musb_generic_disable(struct musb *musb) 903 { 904 void __iomem *mbase = musb->mregs; 905 u16 temp; 906 907 /* disable interrupts */ 908 musb_writeb(mbase, MUSB_INTRUSBE, 0); 909 musb->intrtxe = 0; 910 musb_writew(mbase, MUSB_INTRTXE, 0); 911 musb->intrrxe = 0; 912 musb_writew(mbase, MUSB_INTRRXE, 0); 913 914 /* off */ 915 musb_writeb(mbase, MUSB_DEVCTL, 0); 916 917 /* flush pending interrupts */ 918 temp = musb_readb(mbase, MUSB_INTRUSB); 919 temp = musb_readw(mbase, MUSB_INTRTX); 920 temp = musb_readw(mbase, MUSB_INTRRX); 921 922 } 923 924 /* 925 * Make the HDRC stop (disable interrupts, etc.); 926 * reversible by musb_start 927 * called on gadget driver unregister 928 * with controller locked, irqs blocked 929 * acts as a NOP unless some role activated the hardware 930 */ 931 void musb_stop(struct musb *musb) 932 { 933 /* stop IRQs, timers, ... */ 934 musb_platform_disable(musb); 935 musb_generic_disable(musb); 936 dev_dbg(musb->controller, "HDRC disabled\n"); 937 938 /* FIXME 939 * - mark host and/or peripheral drivers unusable/inactive 940 * - disable DMA (and enable it in HdrcStart) 941 * - make sure we can musb_start() after musb_stop(); with 942 * OTG mode, gadget driver module rmmod/modprobe cycles that 943 * - ... 944 */ 945 musb_platform_try_idle(musb, 0); 946 } 947 948 static void musb_shutdown(struct platform_device *pdev) 949 { 950 struct musb *musb = dev_to_musb(&pdev->dev); 951 unsigned long flags; 952 953 pm_runtime_get_sync(musb->controller); 954 955 musb_host_cleanup(musb); 956 musb_gadget_cleanup(musb); 957 958 spin_lock_irqsave(&musb->lock, flags); 959 musb_platform_disable(musb); 960 musb_generic_disable(musb); 961 spin_unlock_irqrestore(&musb->lock, flags); 962 963 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 964 musb_platform_exit(musb); 965 966 pm_runtime_put(musb->controller); 967 /* FIXME power down */ 968 } 969 970 971 /*-------------------------------------------------------------------------*/ 972 973 /* 974 * The silicon either has hard-wired endpoint configurations, or else 975 * "dynamic fifo" sizing. The driver has support for both, though at this 976 * writing only the dynamic sizing is very well tested. Since we switched 977 * away from compile-time hardware parameters, we can no longer rely on 978 * dead code elimination to leave only the relevant one in the object file. 979 * 980 * We don't currently use dynamic fifo setup capability to do anything 981 * more than selecting one of a bunch of predefined configurations. 982 */ 983 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 984 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 985 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 986 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 987 || defined(CONFIG_USB_MUSB_AM35X) \ 988 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 989 || defined(CONFIG_USB_MUSB_DSPS) \ 990 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 991 static ushort fifo_mode = 4; 992 #elif defined(CONFIG_USB_MUSB_UX500) \ 993 || defined(CONFIG_USB_MUSB_UX500_MODULE) 994 static ushort fifo_mode = 5; 995 #else 996 static ushort fifo_mode = 2; 997 #endif 998 999 /* "modprobe ... fifo_mode=1" etc */ 1000 module_param(fifo_mode, ushort, 0); 1001 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1002 1003 /* 1004 * tables defining fifo_mode values. define more if you like. 1005 * for host side, make sure both halves of ep1 are set up. 1006 */ 1007 1008 /* mode 0 - fits in 2KB */ 1009 static struct musb_fifo_cfg mode_0_cfg[] = { 1010 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1011 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1012 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1013 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1014 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1015 }; 1016 1017 /* mode 1 - fits in 4KB */ 1018 static struct musb_fifo_cfg mode_1_cfg[] = { 1019 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1020 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1021 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1022 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1023 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1024 }; 1025 1026 /* mode 2 - fits in 4KB */ 1027 static struct musb_fifo_cfg mode_2_cfg[] = { 1028 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1029 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1030 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1031 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1032 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1033 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1034 }; 1035 1036 /* mode 3 - fits in 4KB */ 1037 static struct musb_fifo_cfg mode_3_cfg[] = { 1038 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1039 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1040 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1041 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1042 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1043 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1044 }; 1045 1046 /* mode 4 - fits in 16KB */ 1047 static struct musb_fifo_cfg mode_4_cfg[] = { 1048 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1049 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1050 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1051 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1052 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1053 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1054 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1055 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1056 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1057 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1058 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1059 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1060 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1061 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1062 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1063 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1064 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1065 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1066 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1067 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1068 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1069 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1070 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1071 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1072 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1073 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1074 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1075 }; 1076 1077 /* mode 5 - fits in 8KB */ 1078 static struct musb_fifo_cfg mode_5_cfg[] = { 1079 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1080 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1081 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1082 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1083 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1084 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1085 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1086 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1087 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1088 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1089 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1090 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1091 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1092 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1093 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1094 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1095 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1096 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1097 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1098 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1099 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1100 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1101 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1102 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1103 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1104 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1105 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1106 }; 1107 1108 /* 1109 * configure a fifo; for non-shared endpoints, this may be called 1110 * once for a tx fifo and once for an rx fifo. 1111 * 1112 * returns negative errno or offset for next fifo. 1113 */ 1114 static int 1115 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1116 const struct musb_fifo_cfg *cfg, u16 offset) 1117 { 1118 void __iomem *mbase = musb->mregs; 1119 int size = 0; 1120 u16 maxpacket = cfg->maxpacket; 1121 u16 c_off = offset >> 3; 1122 u8 c_size; 1123 1124 /* expect hw_ep has already been zero-initialized */ 1125 1126 size = ffs(max(maxpacket, (u16) 8)) - 1; 1127 maxpacket = 1 << size; 1128 1129 c_size = size - 3; 1130 if (cfg->mode == BUF_DOUBLE) { 1131 if ((offset + (maxpacket << 1)) > 1132 (1 << (musb->config->ram_bits + 2))) 1133 return -EMSGSIZE; 1134 c_size |= MUSB_FIFOSZ_DPB; 1135 } else { 1136 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1137 return -EMSGSIZE; 1138 } 1139 1140 /* configure the FIFO */ 1141 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1142 1143 /* EP0 reserved endpoint for control, bidirectional; 1144 * EP1 reserved for bulk, two unidirection halves. 1145 */ 1146 if (hw_ep->epnum == 1) 1147 musb->bulk_ep = hw_ep; 1148 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1149 switch (cfg->style) { 1150 case FIFO_TX: 1151 musb_write_txfifosz(mbase, c_size); 1152 musb_write_txfifoadd(mbase, c_off); 1153 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1154 hw_ep->max_packet_sz_tx = maxpacket; 1155 break; 1156 case FIFO_RX: 1157 musb_write_rxfifosz(mbase, c_size); 1158 musb_write_rxfifoadd(mbase, c_off); 1159 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1160 hw_ep->max_packet_sz_rx = maxpacket; 1161 break; 1162 case FIFO_RXTX: 1163 musb_write_txfifosz(mbase, c_size); 1164 musb_write_txfifoadd(mbase, c_off); 1165 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1166 hw_ep->max_packet_sz_rx = maxpacket; 1167 1168 musb_write_rxfifosz(mbase, c_size); 1169 musb_write_rxfifoadd(mbase, c_off); 1170 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1171 hw_ep->max_packet_sz_tx = maxpacket; 1172 1173 hw_ep->is_shared_fifo = true; 1174 break; 1175 } 1176 1177 /* NOTE rx and tx endpoint irqs aren't managed separately, 1178 * which happens to be ok 1179 */ 1180 musb->epmask |= (1 << hw_ep->epnum); 1181 1182 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1183 } 1184 1185 static struct musb_fifo_cfg ep0_cfg = { 1186 .style = FIFO_RXTX, .maxpacket = 64, 1187 }; 1188 1189 static int ep_config_from_table(struct musb *musb) 1190 { 1191 const struct musb_fifo_cfg *cfg; 1192 unsigned i, n; 1193 int offset; 1194 struct musb_hw_ep *hw_ep = musb->endpoints; 1195 1196 if (musb->config->fifo_cfg) { 1197 cfg = musb->config->fifo_cfg; 1198 n = musb->config->fifo_cfg_size; 1199 goto done; 1200 } 1201 1202 switch (fifo_mode) { 1203 default: 1204 fifo_mode = 0; 1205 /* FALLTHROUGH */ 1206 case 0: 1207 cfg = mode_0_cfg; 1208 n = ARRAY_SIZE(mode_0_cfg); 1209 break; 1210 case 1: 1211 cfg = mode_1_cfg; 1212 n = ARRAY_SIZE(mode_1_cfg); 1213 break; 1214 case 2: 1215 cfg = mode_2_cfg; 1216 n = ARRAY_SIZE(mode_2_cfg); 1217 break; 1218 case 3: 1219 cfg = mode_3_cfg; 1220 n = ARRAY_SIZE(mode_3_cfg); 1221 break; 1222 case 4: 1223 cfg = mode_4_cfg; 1224 n = ARRAY_SIZE(mode_4_cfg); 1225 break; 1226 case 5: 1227 cfg = mode_5_cfg; 1228 n = ARRAY_SIZE(mode_5_cfg); 1229 break; 1230 } 1231 1232 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1233 musb_driver_name, fifo_mode); 1234 1235 1236 done: 1237 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1238 /* assert(offset > 0) */ 1239 1240 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1241 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1242 */ 1243 1244 for (i = 0; i < n; i++) { 1245 u8 epn = cfg->hw_ep_num; 1246 1247 if (epn >= musb->config->num_eps) { 1248 pr_debug("%s: invalid ep %d\n", 1249 musb_driver_name, epn); 1250 return -EINVAL; 1251 } 1252 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1253 if (offset < 0) { 1254 pr_debug("%s: mem overrun, ep %d\n", 1255 musb_driver_name, epn); 1256 return offset; 1257 } 1258 epn++; 1259 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1260 } 1261 1262 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1263 musb_driver_name, 1264 n + 1, musb->config->num_eps * 2 - 1, 1265 offset, (1 << (musb->config->ram_bits + 2))); 1266 1267 if (!musb->bulk_ep) { 1268 pr_debug("%s: missing bulk\n", musb_driver_name); 1269 return -EINVAL; 1270 } 1271 1272 return 0; 1273 } 1274 1275 1276 /* 1277 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1278 * @param musb the controller 1279 */ 1280 static int ep_config_from_hw(struct musb *musb) 1281 { 1282 u8 epnum = 0; 1283 struct musb_hw_ep *hw_ep; 1284 void __iomem *mbase = musb->mregs; 1285 int ret = 0; 1286 1287 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1288 1289 /* FIXME pick up ep0 maxpacket size */ 1290 1291 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1292 musb_ep_select(mbase, epnum); 1293 hw_ep = musb->endpoints + epnum; 1294 1295 ret = musb_read_fifosize(musb, hw_ep, epnum); 1296 if (ret < 0) 1297 break; 1298 1299 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1300 1301 /* pick an RX/TX endpoint for bulk */ 1302 if (hw_ep->max_packet_sz_tx < 512 1303 || hw_ep->max_packet_sz_rx < 512) 1304 continue; 1305 1306 /* REVISIT: this algorithm is lazy, we should at least 1307 * try to pick a double buffered endpoint. 1308 */ 1309 if (musb->bulk_ep) 1310 continue; 1311 musb->bulk_ep = hw_ep; 1312 } 1313 1314 if (!musb->bulk_ep) { 1315 pr_debug("%s: missing bulk\n", musb_driver_name); 1316 return -EINVAL; 1317 } 1318 1319 return 0; 1320 } 1321 1322 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1323 1324 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1325 * configure endpoints, or take their config from silicon 1326 */ 1327 static int musb_core_init(u16 musb_type, struct musb *musb) 1328 { 1329 u8 reg; 1330 char *type; 1331 char aInfo[90], aRevision[32], aDate[12]; 1332 void __iomem *mbase = musb->mregs; 1333 int status = 0; 1334 int i; 1335 1336 /* log core options (read using indexed model) */ 1337 reg = musb_read_configdata(mbase); 1338 1339 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1340 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1341 strcat(aInfo, ", dyn FIFOs"); 1342 musb->dyn_fifo = true; 1343 } 1344 if (reg & MUSB_CONFIGDATA_MPRXE) { 1345 strcat(aInfo, ", bulk combine"); 1346 musb->bulk_combine = true; 1347 } 1348 if (reg & MUSB_CONFIGDATA_MPTXE) { 1349 strcat(aInfo, ", bulk split"); 1350 musb->bulk_split = true; 1351 } 1352 if (reg & MUSB_CONFIGDATA_HBRXE) { 1353 strcat(aInfo, ", HB-ISO Rx"); 1354 musb->hb_iso_rx = true; 1355 } 1356 if (reg & MUSB_CONFIGDATA_HBTXE) { 1357 strcat(aInfo, ", HB-ISO Tx"); 1358 musb->hb_iso_tx = true; 1359 } 1360 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1361 strcat(aInfo, ", SoftConn"); 1362 1363 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1364 musb_driver_name, reg, aInfo); 1365 1366 aDate[0] = 0; 1367 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1368 musb->is_multipoint = 1; 1369 type = "M"; 1370 } else { 1371 musb->is_multipoint = 0; 1372 type = ""; 1373 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1374 printk(KERN_ERR 1375 "%s: kernel must blacklist external hubs\n", 1376 musb_driver_name); 1377 #endif 1378 } 1379 1380 /* log release info */ 1381 musb->hwvers = musb_read_hwvers(mbase); 1382 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1383 MUSB_HWVERS_MINOR(musb->hwvers), 1384 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1385 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1386 musb_driver_name, type, aRevision, aDate); 1387 1388 /* configure ep0 */ 1389 musb_configure_ep0(musb); 1390 1391 /* discover endpoint configuration */ 1392 musb->nr_endpoints = 1; 1393 musb->epmask = 1; 1394 1395 if (musb->dyn_fifo) 1396 status = ep_config_from_table(musb); 1397 else 1398 status = ep_config_from_hw(musb); 1399 1400 if (status < 0) 1401 return status; 1402 1403 /* finish init, and print endpoint config */ 1404 for (i = 0; i < musb->nr_endpoints; i++) { 1405 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1406 1407 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1408 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1409 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1410 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1411 hw_ep->fifo_sync_va = 1412 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1413 1414 if (i == 0) 1415 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1416 else 1417 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1418 #endif 1419 1420 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1421 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1422 hw_ep->rx_reinit = 1; 1423 hw_ep->tx_reinit = 1; 1424 1425 if (hw_ep->max_packet_sz_tx) { 1426 dev_dbg(musb->controller, 1427 "%s: hw_ep %d%s, %smax %d\n", 1428 musb_driver_name, i, 1429 hw_ep->is_shared_fifo ? "shared" : "tx", 1430 hw_ep->tx_double_buffered 1431 ? "doublebuffer, " : "", 1432 hw_ep->max_packet_sz_tx); 1433 } 1434 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1435 dev_dbg(musb->controller, 1436 "%s: hw_ep %d%s, %smax %d\n", 1437 musb_driver_name, i, 1438 "rx", 1439 hw_ep->rx_double_buffered 1440 ? "doublebuffer, " : "", 1441 hw_ep->max_packet_sz_rx); 1442 } 1443 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1444 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1445 } 1446 1447 return 0; 1448 } 1449 1450 /*-------------------------------------------------------------------------*/ 1451 1452 /* 1453 * handle all the irqs defined by the HDRC core. for now we expect: other 1454 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1455 * will be assigned, and the irq will already have been acked. 1456 * 1457 * called in irq context with spinlock held, irqs blocked 1458 */ 1459 irqreturn_t musb_interrupt(struct musb *musb) 1460 { 1461 irqreturn_t retval = IRQ_NONE; 1462 u8 devctl; 1463 int ep_num; 1464 u32 reg; 1465 1466 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1467 1468 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1469 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1470 musb->int_usb, musb->int_tx, musb->int_rx); 1471 1472 /* the core can interrupt us for multiple reasons; docs have 1473 * a generic interrupt flowchart to follow 1474 */ 1475 if (musb->int_usb) 1476 retval |= musb_stage0_irq(musb, musb->int_usb, 1477 devctl); 1478 1479 /* "stage 1" is handling endpoint irqs */ 1480 1481 /* handle endpoint 0 first */ 1482 if (musb->int_tx & 1) { 1483 if (devctl & MUSB_DEVCTL_HM) 1484 retval |= musb_h_ep0_irq(musb); 1485 else 1486 retval |= musb_g_ep0_irq(musb); 1487 } 1488 1489 /* RX on endpoints 1-15 */ 1490 reg = musb->int_rx >> 1; 1491 ep_num = 1; 1492 while (reg) { 1493 if (reg & 1) { 1494 /* musb_ep_select(musb->mregs, ep_num); */ 1495 /* REVISIT just retval = ep->rx_irq(...) */ 1496 retval = IRQ_HANDLED; 1497 if (devctl & MUSB_DEVCTL_HM) 1498 musb_host_rx(musb, ep_num); 1499 else 1500 musb_g_rx(musb, ep_num); 1501 } 1502 1503 reg >>= 1; 1504 ep_num++; 1505 } 1506 1507 /* TX on endpoints 1-15 */ 1508 reg = musb->int_tx >> 1; 1509 ep_num = 1; 1510 while (reg) { 1511 if (reg & 1) { 1512 /* musb_ep_select(musb->mregs, ep_num); */ 1513 /* REVISIT just retval |= ep->tx_irq(...) */ 1514 retval = IRQ_HANDLED; 1515 if (devctl & MUSB_DEVCTL_HM) 1516 musb_host_tx(musb, ep_num); 1517 else 1518 musb_g_tx(musb, ep_num); 1519 } 1520 reg >>= 1; 1521 ep_num++; 1522 } 1523 1524 return retval; 1525 } 1526 EXPORT_SYMBOL_GPL(musb_interrupt); 1527 1528 #ifndef CONFIG_MUSB_PIO_ONLY 1529 static bool use_dma = 1; 1530 1531 /* "modprobe ... use_dma=0" etc */ 1532 module_param(use_dma, bool, 0); 1533 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1534 1535 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1536 { 1537 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1538 1539 /* called with controller lock already held */ 1540 1541 if (!epnum) { 1542 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1543 if (!is_cppi_enabled()) { 1544 /* endpoint 0 */ 1545 if (devctl & MUSB_DEVCTL_HM) 1546 musb_h_ep0_irq(musb); 1547 else 1548 musb_g_ep0_irq(musb); 1549 } 1550 #endif 1551 } else { 1552 /* endpoints 1..15 */ 1553 if (transmit) { 1554 if (devctl & MUSB_DEVCTL_HM) 1555 musb_host_tx(musb, epnum); 1556 else 1557 musb_g_tx(musb, epnum); 1558 } else { 1559 /* receive */ 1560 if (devctl & MUSB_DEVCTL_HM) 1561 musb_host_rx(musb, epnum); 1562 else 1563 musb_g_rx(musb, epnum); 1564 } 1565 } 1566 } 1567 EXPORT_SYMBOL_GPL(musb_dma_completion); 1568 1569 #else 1570 #define use_dma 0 1571 #endif 1572 1573 /*-------------------------------------------------------------------------*/ 1574 1575 static ssize_t 1576 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1577 { 1578 struct musb *musb = dev_to_musb(dev); 1579 unsigned long flags; 1580 int ret = -EINVAL; 1581 1582 spin_lock_irqsave(&musb->lock, flags); 1583 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state)); 1584 spin_unlock_irqrestore(&musb->lock, flags); 1585 1586 return ret; 1587 } 1588 1589 static ssize_t 1590 musb_mode_store(struct device *dev, struct device_attribute *attr, 1591 const char *buf, size_t n) 1592 { 1593 struct musb *musb = dev_to_musb(dev); 1594 unsigned long flags; 1595 int status; 1596 1597 spin_lock_irqsave(&musb->lock, flags); 1598 if (sysfs_streq(buf, "host")) 1599 status = musb_platform_set_mode(musb, MUSB_HOST); 1600 else if (sysfs_streq(buf, "peripheral")) 1601 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1602 else if (sysfs_streq(buf, "otg")) 1603 status = musb_platform_set_mode(musb, MUSB_OTG); 1604 else 1605 status = -EINVAL; 1606 spin_unlock_irqrestore(&musb->lock, flags); 1607 1608 return (status == 0) ? n : status; 1609 } 1610 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1611 1612 static ssize_t 1613 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1614 const char *buf, size_t n) 1615 { 1616 struct musb *musb = dev_to_musb(dev); 1617 unsigned long flags; 1618 unsigned long val; 1619 1620 if (sscanf(buf, "%lu", &val) < 1) { 1621 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1622 return -EINVAL; 1623 } 1624 1625 spin_lock_irqsave(&musb->lock, flags); 1626 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1627 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1628 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1629 musb->is_active = 0; 1630 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1631 spin_unlock_irqrestore(&musb->lock, flags); 1632 1633 return n; 1634 } 1635 1636 static ssize_t 1637 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1638 { 1639 struct musb *musb = dev_to_musb(dev); 1640 unsigned long flags; 1641 unsigned long val; 1642 int vbus; 1643 1644 spin_lock_irqsave(&musb->lock, flags); 1645 val = musb->a_wait_bcon; 1646 /* FIXME get_vbus_status() is normally #defined as false... 1647 * and is effectively TUSB-specific. 1648 */ 1649 vbus = musb_platform_get_vbus_status(musb); 1650 spin_unlock_irqrestore(&musb->lock, flags); 1651 1652 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1653 vbus ? "on" : "off", val); 1654 } 1655 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1656 1657 /* Gadget drivers can't know that a host is connected so they might want 1658 * to start SRP, but users can. This allows userspace to trigger SRP. 1659 */ 1660 static ssize_t 1661 musb_srp_store(struct device *dev, struct device_attribute *attr, 1662 const char *buf, size_t n) 1663 { 1664 struct musb *musb = dev_to_musb(dev); 1665 unsigned short srp; 1666 1667 if (sscanf(buf, "%hu", &srp) != 1 1668 || (srp != 1)) { 1669 dev_err(dev, "SRP: Value must be 1\n"); 1670 return -EINVAL; 1671 } 1672 1673 if (srp == 1) 1674 musb_g_wakeup(musb); 1675 1676 return n; 1677 } 1678 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1679 1680 static struct attribute *musb_attributes[] = { 1681 &dev_attr_mode.attr, 1682 &dev_attr_vbus.attr, 1683 &dev_attr_srp.attr, 1684 NULL 1685 }; 1686 1687 static const struct attribute_group musb_attr_group = { 1688 .attrs = musb_attributes, 1689 }; 1690 1691 /* Only used to provide driver mode change events */ 1692 static void musb_irq_work(struct work_struct *data) 1693 { 1694 struct musb *musb = container_of(data, struct musb, irq_work); 1695 1696 if (musb->xceiv->state != musb->xceiv_old_state) { 1697 musb->xceiv_old_state = musb->xceiv->state; 1698 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1699 } 1700 } 1701 1702 /* -------------------------------------------------------------------------- 1703 * Init support 1704 */ 1705 1706 static struct musb *allocate_instance(struct device *dev, 1707 struct musb_hdrc_config *config, void __iomem *mbase) 1708 { 1709 struct musb *musb; 1710 struct musb_hw_ep *ep; 1711 int epnum; 1712 int ret; 1713 1714 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); 1715 if (!musb) 1716 return NULL; 1717 1718 INIT_LIST_HEAD(&musb->control); 1719 INIT_LIST_HEAD(&musb->in_bulk); 1720 INIT_LIST_HEAD(&musb->out_bulk); 1721 1722 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1723 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1724 musb->mregs = mbase; 1725 musb->ctrl_base = mbase; 1726 musb->nIrq = -ENODEV; 1727 musb->config = config; 1728 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1729 for (epnum = 0, ep = musb->endpoints; 1730 epnum < musb->config->num_eps; 1731 epnum++, ep++) { 1732 ep->musb = musb; 1733 ep->epnum = epnum; 1734 } 1735 1736 musb->controller = dev; 1737 1738 ret = musb_host_alloc(musb); 1739 if (ret < 0) 1740 goto err_free; 1741 1742 dev_set_drvdata(dev, musb); 1743 1744 return musb; 1745 1746 err_free: 1747 return NULL; 1748 } 1749 1750 static void musb_free(struct musb *musb) 1751 { 1752 /* this has multiple entry modes. it handles fault cleanup after 1753 * probe(), where things may be partially set up, as well as rmmod 1754 * cleanup after everything's been de-activated. 1755 */ 1756 1757 #ifdef CONFIG_SYSFS 1758 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1759 #endif 1760 1761 if (musb->nIrq >= 0) { 1762 if (musb->irq_wake) 1763 disable_irq_wake(musb->nIrq); 1764 free_irq(musb->nIrq, musb); 1765 } 1766 if (musb->dma_controller) 1767 dma_controller_destroy(musb->dma_controller); 1768 1769 musb_host_free(musb); 1770 } 1771 1772 /* 1773 * Perform generic per-controller initialization. 1774 * 1775 * @dev: the controller (already clocked, etc) 1776 * @nIrq: IRQ number 1777 * @ctrl: virtual address of controller registers, 1778 * not yet corrected for platform-specific offsets 1779 */ 1780 static int 1781 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1782 { 1783 int status; 1784 struct musb *musb; 1785 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 1786 1787 /* The driver might handle more features than the board; OK. 1788 * Fail when the board needs a feature that's not enabled. 1789 */ 1790 if (!plat) { 1791 dev_dbg(dev, "no platform_data?\n"); 1792 status = -ENODEV; 1793 goto fail0; 1794 } 1795 1796 /* allocate */ 1797 musb = allocate_instance(dev, plat->config, ctrl); 1798 if (!musb) { 1799 status = -ENOMEM; 1800 goto fail0; 1801 } 1802 1803 pm_runtime_use_autosuspend(musb->controller); 1804 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1805 pm_runtime_enable(musb->controller); 1806 1807 spin_lock_init(&musb->lock); 1808 musb->board_set_power = plat->set_power; 1809 musb->min_power = plat->min_power; 1810 musb->ops = plat->platform_ops; 1811 musb->port_mode = plat->mode; 1812 1813 /* The musb_platform_init() call: 1814 * - adjusts musb->mregs 1815 * - sets the musb->isr 1816 * - may initialize an integrated tranceiver 1817 * - initializes musb->xceiv, usually by otg_get_phy() 1818 * - stops powering VBUS 1819 * 1820 * There are various transceiver configurations. Blackfin, 1821 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1822 * external/discrete ones in various flavors (twl4030 family, 1823 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1824 */ 1825 status = musb_platform_init(musb); 1826 if (status < 0) 1827 goto fail1; 1828 1829 if (!musb->isr) { 1830 status = -ENODEV; 1831 goto fail2; 1832 } 1833 1834 if (!musb->xceiv->io_ops) { 1835 musb->xceiv->io_dev = musb->controller; 1836 musb->xceiv->io_priv = musb->mregs; 1837 musb->xceiv->io_ops = &musb_ulpi_access; 1838 } 1839 1840 pm_runtime_get_sync(musb->controller); 1841 1842 if (use_dma && dev->dma_mask) 1843 musb->dma_controller = dma_controller_create(musb, musb->mregs); 1844 1845 /* be sure interrupts are disabled before connecting ISR */ 1846 musb_platform_disable(musb); 1847 musb_generic_disable(musb); 1848 1849 /* setup musb parts of the core (especially endpoints) */ 1850 status = musb_core_init(plat->config->multipoint 1851 ? MUSB_CONTROLLER_MHDRC 1852 : MUSB_CONTROLLER_HDRC, musb); 1853 if (status < 0) 1854 goto fail3; 1855 1856 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1857 1858 /* Init IRQ workqueue before request_irq */ 1859 INIT_WORK(&musb->irq_work, musb_irq_work); 1860 1861 /* attach to the IRQ */ 1862 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1863 dev_err(dev, "request_irq %d failed!\n", nIrq); 1864 status = -ENODEV; 1865 goto fail3; 1866 } 1867 musb->nIrq = nIrq; 1868 /* FIXME this handles wakeup irqs wrong */ 1869 if (enable_irq_wake(nIrq) == 0) { 1870 musb->irq_wake = 1; 1871 device_init_wakeup(dev, 1); 1872 } else { 1873 musb->irq_wake = 0; 1874 } 1875 1876 /* program PHY to use external vBus if required */ 1877 if (plat->extvbus) { 1878 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 1879 busctl |= MUSB_ULPI_USE_EXTVBUS; 1880 musb_write_ulpi_buscontrol(musb->mregs, busctl); 1881 } 1882 1883 if (musb->xceiv->otg->default_a) { 1884 MUSB_HST_MODE(musb); 1885 musb->xceiv->state = OTG_STATE_A_IDLE; 1886 } else { 1887 MUSB_DEV_MODE(musb); 1888 musb->xceiv->state = OTG_STATE_B_IDLE; 1889 } 1890 1891 switch (musb->port_mode) { 1892 case MUSB_PORT_MODE_HOST: 1893 status = musb_host_setup(musb, plat->power); 1894 break; 1895 case MUSB_PORT_MODE_GADGET: 1896 status = musb_gadget_setup(musb); 1897 break; 1898 case MUSB_PORT_MODE_DUAL_ROLE: 1899 status = musb_host_setup(musb, plat->power); 1900 if (status < 0) 1901 goto fail3; 1902 status = musb_gadget_setup(musb); 1903 break; 1904 default: 1905 dev_err(dev, "unsupported port mode %d\n", musb->port_mode); 1906 break; 1907 } 1908 1909 if (status < 0) 1910 goto fail3; 1911 1912 status = musb_init_debugfs(musb); 1913 if (status < 0) 1914 goto fail4; 1915 1916 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 1917 if (status) 1918 goto fail5; 1919 1920 pm_runtime_put(musb->controller); 1921 1922 return 0; 1923 1924 fail5: 1925 musb_exit_debugfs(musb); 1926 1927 fail4: 1928 musb_gadget_cleanup(musb); 1929 1930 fail3: 1931 if (musb->dma_controller) 1932 dma_controller_destroy(musb->dma_controller); 1933 pm_runtime_put_sync(musb->controller); 1934 1935 fail2: 1936 if (musb->irq_wake) 1937 device_init_wakeup(dev, 0); 1938 musb_platform_exit(musb); 1939 1940 fail1: 1941 pm_runtime_disable(musb->controller); 1942 dev_err(musb->controller, 1943 "musb_init_controller failed with status %d\n", status); 1944 1945 musb_free(musb); 1946 1947 fail0: 1948 1949 return status; 1950 1951 } 1952 1953 /*-------------------------------------------------------------------------*/ 1954 1955 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 1956 * bridge to a platform device; this driver then suffices. 1957 */ 1958 static int musb_probe(struct platform_device *pdev) 1959 { 1960 struct device *dev = &pdev->dev; 1961 int irq = platform_get_irq_byname(pdev, "mc"); 1962 struct resource *iomem; 1963 void __iomem *base; 1964 1965 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1966 if (!iomem || irq <= 0) 1967 return -ENODEV; 1968 1969 base = devm_ioremap_resource(dev, iomem); 1970 if (IS_ERR(base)) 1971 return PTR_ERR(base); 1972 1973 return musb_init_controller(dev, irq, base); 1974 } 1975 1976 static int musb_remove(struct platform_device *pdev) 1977 { 1978 struct device *dev = &pdev->dev; 1979 struct musb *musb = dev_to_musb(dev); 1980 1981 /* this gets called on rmmod. 1982 * - Host mode: host may still be active 1983 * - Peripheral mode: peripheral is deactivated (or never-activated) 1984 * - OTG mode: both roles are deactivated (or never-activated) 1985 */ 1986 musb_exit_debugfs(musb); 1987 musb_shutdown(pdev); 1988 1989 musb_free(musb); 1990 device_init_wakeup(dev, 0); 1991 return 0; 1992 } 1993 1994 #ifdef CONFIG_PM 1995 1996 static void musb_save_context(struct musb *musb) 1997 { 1998 int i; 1999 void __iomem *musb_base = musb->mregs; 2000 void __iomem *epio; 2001 2002 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2003 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2004 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2005 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2006 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2007 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2008 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2009 2010 for (i = 0; i < musb->config->num_eps; ++i) { 2011 struct musb_hw_ep *hw_ep; 2012 2013 hw_ep = &musb->endpoints[i]; 2014 if (!hw_ep) 2015 continue; 2016 2017 epio = hw_ep->regs; 2018 if (!epio) 2019 continue; 2020 2021 musb_writeb(musb_base, MUSB_INDEX, i); 2022 musb->context.index_regs[i].txmaxp = 2023 musb_readw(epio, MUSB_TXMAXP); 2024 musb->context.index_regs[i].txcsr = 2025 musb_readw(epio, MUSB_TXCSR); 2026 musb->context.index_regs[i].rxmaxp = 2027 musb_readw(epio, MUSB_RXMAXP); 2028 musb->context.index_regs[i].rxcsr = 2029 musb_readw(epio, MUSB_RXCSR); 2030 2031 if (musb->dyn_fifo) { 2032 musb->context.index_regs[i].txfifoadd = 2033 musb_read_txfifoadd(musb_base); 2034 musb->context.index_regs[i].rxfifoadd = 2035 musb_read_rxfifoadd(musb_base); 2036 musb->context.index_regs[i].txfifosz = 2037 musb_read_txfifosz(musb_base); 2038 musb->context.index_regs[i].rxfifosz = 2039 musb_read_rxfifosz(musb_base); 2040 } 2041 2042 musb->context.index_regs[i].txtype = 2043 musb_readb(epio, MUSB_TXTYPE); 2044 musb->context.index_regs[i].txinterval = 2045 musb_readb(epio, MUSB_TXINTERVAL); 2046 musb->context.index_regs[i].rxtype = 2047 musb_readb(epio, MUSB_RXTYPE); 2048 musb->context.index_regs[i].rxinterval = 2049 musb_readb(epio, MUSB_RXINTERVAL); 2050 2051 musb->context.index_regs[i].txfunaddr = 2052 musb_read_txfunaddr(musb_base, i); 2053 musb->context.index_regs[i].txhubaddr = 2054 musb_read_txhubaddr(musb_base, i); 2055 musb->context.index_regs[i].txhubport = 2056 musb_read_txhubport(musb_base, i); 2057 2058 musb->context.index_regs[i].rxfunaddr = 2059 musb_read_rxfunaddr(musb_base, i); 2060 musb->context.index_regs[i].rxhubaddr = 2061 musb_read_rxhubaddr(musb_base, i); 2062 musb->context.index_regs[i].rxhubport = 2063 musb_read_rxhubport(musb_base, i); 2064 } 2065 } 2066 2067 static void musb_restore_context(struct musb *musb) 2068 { 2069 int i; 2070 void __iomem *musb_base = musb->mregs; 2071 void __iomem *ep_target_regs; 2072 void __iomem *epio; 2073 2074 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2075 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2076 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2077 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2078 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); 2079 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); 2080 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2081 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2082 2083 for (i = 0; i < musb->config->num_eps; ++i) { 2084 struct musb_hw_ep *hw_ep; 2085 2086 hw_ep = &musb->endpoints[i]; 2087 if (!hw_ep) 2088 continue; 2089 2090 epio = hw_ep->regs; 2091 if (!epio) 2092 continue; 2093 2094 musb_writeb(musb_base, MUSB_INDEX, i); 2095 musb_writew(epio, MUSB_TXMAXP, 2096 musb->context.index_regs[i].txmaxp); 2097 musb_writew(epio, MUSB_TXCSR, 2098 musb->context.index_regs[i].txcsr); 2099 musb_writew(epio, MUSB_RXMAXP, 2100 musb->context.index_regs[i].rxmaxp); 2101 musb_writew(epio, MUSB_RXCSR, 2102 musb->context.index_regs[i].rxcsr); 2103 2104 if (musb->dyn_fifo) { 2105 musb_write_txfifosz(musb_base, 2106 musb->context.index_regs[i].txfifosz); 2107 musb_write_rxfifosz(musb_base, 2108 musb->context.index_regs[i].rxfifosz); 2109 musb_write_txfifoadd(musb_base, 2110 musb->context.index_regs[i].txfifoadd); 2111 musb_write_rxfifoadd(musb_base, 2112 musb->context.index_regs[i].rxfifoadd); 2113 } 2114 2115 musb_writeb(epio, MUSB_TXTYPE, 2116 musb->context.index_regs[i].txtype); 2117 musb_writeb(epio, MUSB_TXINTERVAL, 2118 musb->context.index_regs[i].txinterval); 2119 musb_writeb(epio, MUSB_RXTYPE, 2120 musb->context.index_regs[i].rxtype); 2121 musb_writeb(epio, MUSB_RXINTERVAL, 2122 2123 musb->context.index_regs[i].rxinterval); 2124 musb_write_txfunaddr(musb_base, i, 2125 musb->context.index_regs[i].txfunaddr); 2126 musb_write_txhubaddr(musb_base, i, 2127 musb->context.index_regs[i].txhubaddr); 2128 musb_write_txhubport(musb_base, i, 2129 musb->context.index_regs[i].txhubport); 2130 2131 ep_target_regs = 2132 musb_read_target_reg_base(i, musb_base); 2133 2134 musb_write_rxfunaddr(ep_target_regs, 2135 musb->context.index_regs[i].rxfunaddr); 2136 musb_write_rxhubaddr(ep_target_regs, 2137 musb->context.index_regs[i].rxhubaddr); 2138 musb_write_rxhubport(ep_target_regs, 2139 musb->context.index_regs[i].rxhubport); 2140 } 2141 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2142 } 2143 2144 static int musb_suspend(struct device *dev) 2145 { 2146 struct musb *musb = dev_to_musb(dev); 2147 unsigned long flags; 2148 2149 spin_lock_irqsave(&musb->lock, flags); 2150 2151 if (is_peripheral_active(musb)) { 2152 /* FIXME force disconnect unless we know USB will wake 2153 * the system up quickly enough to respond ... 2154 */ 2155 } else if (is_host_active(musb)) { 2156 /* we know all the children are suspended; sometimes 2157 * they will even be wakeup-enabled. 2158 */ 2159 } 2160 2161 spin_unlock_irqrestore(&musb->lock, flags); 2162 return 0; 2163 } 2164 2165 static int musb_resume_noirq(struct device *dev) 2166 { 2167 /* for static cmos like DaVinci, register values were preserved 2168 * unless for some reason the whole soc powered down or the USB 2169 * module got reset through the PSC (vs just being disabled). 2170 */ 2171 return 0; 2172 } 2173 2174 static int musb_runtime_suspend(struct device *dev) 2175 { 2176 struct musb *musb = dev_to_musb(dev); 2177 2178 musb_save_context(musb); 2179 2180 return 0; 2181 } 2182 2183 static int musb_runtime_resume(struct device *dev) 2184 { 2185 struct musb *musb = dev_to_musb(dev); 2186 static int first = 1; 2187 2188 /* 2189 * When pm_runtime_get_sync called for the first time in driver 2190 * init, some of the structure is still not initialized which is 2191 * used in restore function. But clock needs to be 2192 * enabled before any register access, so 2193 * pm_runtime_get_sync has to be called. 2194 * Also context restore without save does not make 2195 * any sense 2196 */ 2197 if (!first) 2198 musb_restore_context(musb); 2199 first = 0; 2200 2201 return 0; 2202 } 2203 2204 static const struct dev_pm_ops musb_dev_pm_ops = { 2205 .suspend = musb_suspend, 2206 .resume_noirq = musb_resume_noirq, 2207 .runtime_suspend = musb_runtime_suspend, 2208 .runtime_resume = musb_runtime_resume, 2209 }; 2210 2211 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2212 #else 2213 #define MUSB_DEV_PM_OPS NULL 2214 #endif 2215 2216 static struct platform_driver musb_driver = { 2217 .driver = { 2218 .name = (char *)musb_driver_name, 2219 .bus = &platform_bus_type, 2220 .owner = THIS_MODULE, 2221 .pm = MUSB_DEV_PM_OPS, 2222 }, 2223 .probe = musb_probe, 2224 .remove = musb_remove, 2225 .shutdown = musb_shutdown, 2226 }; 2227 2228 /*-------------------------------------------------------------------------*/ 2229 2230 static int __init musb_init(void) 2231 { 2232 if (usb_disabled()) 2233 return 0; 2234 2235 return platform_driver_register(&musb_driver); 2236 } 2237 module_init(musb_init); 2238 2239 static void __exit musb_cleanup(void) 2240 { 2241 platform_driver_unregister(&musb_driver); 2242 } 2243 module_exit(musb_cleanup); 2244