1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/init.h> 97 #include <linux/list.h> 98 #include <linux/kobject.h> 99 #include <linux/prefetch.h> 100 #include <linux/platform_device.h> 101 #include <linux/io.h> 102 103 #include "musb_core.h" 104 105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 106 107 108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 110 111 #define MUSB_VERSION "6.0" 112 113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 114 115 #define MUSB_DRIVER_NAME "musb-hdrc" 116 const char musb_driver_name[] = MUSB_DRIVER_NAME; 117 118 MODULE_DESCRIPTION(DRIVER_INFO); 119 MODULE_AUTHOR(DRIVER_AUTHOR); 120 MODULE_LICENSE("GPL"); 121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 122 123 124 /*-------------------------------------------------------------------------*/ 125 126 static inline struct musb *dev_to_musb(struct device *dev) 127 { 128 return dev_get_drvdata(dev); 129 } 130 131 /*-------------------------------------------------------------------------*/ 132 133 #ifndef CONFIG_BLACKFIN 134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset) 135 { 136 void __iomem *addr = otg->io_priv; 137 int i = 0; 138 u8 r; 139 u8 power; 140 141 /* Make sure the transceiver is not in low power mode */ 142 power = musb_readb(addr, MUSB_POWER); 143 power &= ~MUSB_POWER_SUSPENDM; 144 musb_writeb(addr, MUSB_POWER, power); 145 146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 148 */ 149 150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 153 154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 155 & MUSB_ULPI_REG_CMPLT)) { 156 i++; 157 if (i == 10000) 158 return -ETIMEDOUT; 159 160 } 161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 162 r &= ~MUSB_ULPI_REG_CMPLT; 163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 164 165 return musb_readb(addr, MUSB_ULPI_REG_DATA); 166 } 167 168 static int musb_ulpi_write(struct otg_transceiver *otg, 169 u32 offset, u32 data) 170 { 171 void __iomem *addr = otg->io_priv; 172 int i = 0; 173 u8 r = 0; 174 u8 power; 175 176 /* Make sure the transceiver is not in low power mode */ 177 power = musb_readb(addr, MUSB_POWER); 178 power &= ~MUSB_POWER_SUSPENDM; 179 musb_writeb(addr, MUSB_POWER, power); 180 181 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 182 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 184 185 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 186 & MUSB_ULPI_REG_CMPLT)) { 187 i++; 188 if (i == 10000) 189 return -ETIMEDOUT; 190 } 191 192 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 193 r &= ~MUSB_ULPI_REG_CMPLT; 194 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 195 196 return 0; 197 } 198 #else 199 #define musb_ulpi_read NULL 200 #define musb_ulpi_write NULL 201 #endif 202 203 static struct otg_io_access_ops musb_ulpi_access = { 204 .read = musb_ulpi_read, 205 .write = musb_ulpi_write, 206 }; 207 208 /*-------------------------------------------------------------------------*/ 209 210 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 211 212 /* 213 * Load an endpoint's FIFO 214 */ 215 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 216 { 217 struct musb *musb = hw_ep->musb; 218 void __iomem *fifo = hw_ep->fifo; 219 220 prefetch((u8 *)src); 221 222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 223 'T', hw_ep->epnum, fifo, len, src); 224 225 /* we can't assume unaligned reads work */ 226 if (likely((0x01 & (unsigned long) src) == 0)) { 227 u16 index = 0; 228 229 /* best case is 32bit-aligned source address */ 230 if ((0x02 & (unsigned long) src) == 0) { 231 if (len >= 4) { 232 writesl(fifo, src + index, len >> 2); 233 index += len & ~0x03; 234 } 235 if (len & 0x02) { 236 musb_writew(fifo, 0, *(u16 *)&src[index]); 237 index += 2; 238 } 239 } else { 240 if (len >= 2) { 241 writesw(fifo, src + index, len >> 1); 242 index += len & ~0x01; 243 } 244 } 245 if (len & 0x01) 246 musb_writeb(fifo, 0, src[index]); 247 } else { 248 /* byte aligned */ 249 writesb(fifo, src, len); 250 } 251 } 252 253 #if !defined(CONFIG_USB_MUSB_AM35X) 254 /* 255 * Unload an endpoint's FIFO 256 */ 257 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 258 { 259 struct musb *musb = hw_ep->musb; 260 void __iomem *fifo = hw_ep->fifo; 261 262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 263 'R', hw_ep->epnum, fifo, len, dst); 264 265 /* we can't assume unaligned writes work */ 266 if (likely((0x01 & (unsigned long) dst) == 0)) { 267 u16 index = 0; 268 269 /* best case is 32bit-aligned destination address */ 270 if ((0x02 & (unsigned long) dst) == 0) { 271 if (len >= 4) { 272 readsl(fifo, dst, len >> 2); 273 index = len & ~0x03; 274 } 275 if (len & 0x02) { 276 *(u16 *)&dst[index] = musb_readw(fifo, 0); 277 index += 2; 278 } 279 } else { 280 if (len >= 2) { 281 readsw(fifo, dst, len >> 1); 282 index = len & ~0x01; 283 } 284 } 285 if (len & 0x01) 286 dst[index] = musb_readb(fifo, 0); 287 } else { 288 /* byte aligned */ 289 readsb(fifo, dst, len); 290 } 291 } 292 #endif 293 294 #endif /* normal PIO */ 295 296 297 /*-------------------------------------------------------------------------*/ 298 299 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 300 static const u8 musb_test_packet[53] = { 301 /* implicit SYNC then DATA0 to start */ 302 303 /* JKJKJKJK x9 */ 304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 305 /* JJKKJJKK x8 */ 306 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 307 /* JJJJKKKK x8 */ 308 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 309 /* JJJJJJJKKKKKKK x8 */ 310 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 311 /* JJJJJJJK x8 */ 312 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 313 /* JKKKKKKK x10, JK */ 314 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 315 316 /* implicit CRC16 then EOP to end */ 317 }; 318 319 void musb_load_testpacket(struct musb *musb) 320 { 321 void __iomem *regs = musb->endpoints[0].regs; 322 323 musb_ep_select(musb->mregs, 0); 324 musb_write_fifo(musb->control_ep, 325 sizeof(musb_test_packet), musb_test_packet); 326 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 327 } 328 329 /*-------------------------------------------------------------------------*/ 330 331 /* 332 * Handles OTG hnp timeouts, such as b_ase0_brst 333 */ 334 void musb_otg_timer_func(unsigned long data) 335 { 336 struct musb *musb = (struct musb *)data; 337 unsigned long flags; 338 339 spin_lock_irqsave(&musb->lock, flags); 340 switch (musb->xceiv->state) { 341 case OTG_STATE_B_WAIT_ACON: 342 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 343 musb_g_disconnect(musb); 344 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 345 musb->is_active = 0; 346 break; 347 case OTG_STATE_A_SUSPEND: 348 case OTG_STATE_A_WAIT_BCON: 349 dev_dbg(musb->controller, "HNP: %s timeout\n", 350 otg_state_string(musb->xceiv->state)); 351 musb_platform_set_vbus(musb, 0); 352 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 353 break; 354 default: 355 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 356 otg_state_string(musb->xceiv->state)); 357 } 358 musb->ignore_disconnect = 0; 359 spin_unlock_irqrestore(&musb->lock, flags); 360 } 361 362 /* 363 * Stops the HNP transition. Caller must take care of locking. 364 */ 365 void musb_hnp_stop(struct musb *musb) 366 { 367 struct usb_hcd *hcd = musb_to_hcd(musb); 368 void __iomem *mbase = musb->mregs; 369 u8 reg; 370 371 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 372 373 switch (musb->xceiv->state) { 374 case OTG_STATE_A_PERIPHERAL: 375 musb_g_disconnect(musb); 376 dev_dbg(musb->controller, "HNP: back to %s\n", 377 otg_state_string(musb->xceiv->state)); 378 break; 379 case OTG_STATE_B_HOST: 380 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 381 hcd->self.is_b_host = 0; 382 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 383 MUSB_DEV_MODE(musb); 384 reg = musb_readb(mbase, MUSB_POWER); 385 reg |= MUSB_POWER_SUSPENDM; 386 musb_writeb(mbase, MUSB_POWER, reg); 387 /* REVISIT: Start SESSION_REQUEST here? */ 388 break; 389 default: 390 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 391 otg_state_string(musb->xceiv->state)); 392 } 393 394 /* 395 * When returning to A state after HNP, avoid hub_port_rebounce(), 396 * which cause occasional OPT A "Did not receive reset after connect" 397 * errors. 398 */ 399 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 400 } 401 402 /* 403 * Interrupt Service Routine to record USB "global" interrupts. 404 * Since these do not happen often and signify things of 405 * paramount importance, it seems OK to check them individually; 406 * the order of the tests is specified in the manual 407 * 408 * @param musb instance pointer 409 * @param int_usb register contents 410 * @param devctl 411 * @param power 412 */ 413 414 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 415 u8 devctl, u8 power) 416 { 417 irqreturn_t handled = IRQ_NONE; 418 419 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 420 int_usb); 421 422 /* in host mode, the peripheral may issue remote wakeup. 423 * in peripheral mode, the host may resume the link. 424 * spurious RESUME irqs happen too, paired with SUSPEND. 425 */ 426 if (int_usb & MUSB_INTR_RESUME) { 427 handled = IRQ_HANDLED; 428 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 429 430 if (devctl & MUSB_DEVCTL_HM) { 431 void __iomem *mbase = musb->mregs; 432 433 switch (musb->xceiv->state) { 434 case OTG_STATE_A_SUSPEND: 435 /* remote wakeup? later, GetPortStatus 436 * will stop RESUME signaling 437 */ 438 439 if (power & MUSB_POWER_SUSPENDM) { 440 /* spurious */ 441 musb->int_usb &= ~MUSB_INTR_SUSPEND; 442 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 443 break; 444 } 445 446 power &= ~MUSB_POWER_SUSPENDM; 447 musb_writeb(mbase, MUSB_POWER, 448 power | MUSB_POWER_RESUME); 449 450 musb->port1_status |= 451 (USB_PORT_STAT_C_SUSPEND << 16) 452 | MUSB_PORT_STAT_RESUME; 453 musb->rh_timer = jiffies 454 + msecs_to_jiffies(20); 455 456 musb->xceiv->state = OTG_STATE_A_HOST; 457 musb->is_active = 1; 458 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 459 break; 460 case OTG_STATE_B_WAIT_ACON: 461 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 462 musb->is_active = 1; 463 MUSB_DEV_MODE(musb); 464 break; 465 default: 466 WARNING("bogus %s RESUME (%s)\n", 467 "host", 468 otg_state_string(musb->xceiv->state)); 469 } 470 } else { 471 switch (musb->xceiv->state) { 472 case OTG_STATE_A_SUSPEND: 473 /* possibly DISCONNECT is upcoming */ 474 musb->xceiv->state = OTG_STATE_A_HOST; 475 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 476 break; 477 case OTG_STATE_B_WAIT_ACON: 478 case OTG_STATE_B_PERIPHERAL: 479 /* disconnect while suspended? we may 480 * not get a disconnect irq... 481 */ 482 if ((devctl & MUSB_DEVCTL_VBUS) 483 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 484 ) { 485 musb->int_usb |= MUSB_INTR_DISCONNECT; 486 musb->int_usb &= ~MUSB_INTR_SUSPEND; 487 break; 488 } 489 musb_g_resume(musb); 490 break; 491 case OTG_STATE_B_IDLE: 492 musb->int_usb &= ~MUSB_INTR_SUSPEND; 493 break; 494 default: 495 WARNING("bogus %s RESUME (%s)\n", 496 "peripheral", 497 otg_state_string(musb->xceiv->state)); 498 } 499 } 500 } 501 502 /* see manual for the order of the tests */ 503 if (int_usb & MUSB_INTR_SESSREQ) { 504 void __iomem *mbase = musb->mregs; 505 506 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 507 && (devctl & MUSB_DEVCTL_BDEVICE)) { 508 dev_dbg(musb->controller, "SessReq while on B state\n"); 509 return IRQ_HANDLED; 510 } 511 512 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 513 otg_state_string(musb->xceiv->state)); 514 515 /* IRQ arrives from ID pin sense or (later, if VBUS power 516 * is removed) SRP. responses are time critical: 517 * - turn on VBUS (with silicon-specific mechanism) 518 * - go through A_WAIT_VRISE 519 * - ... to A_WAIT_BCON. 520 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 521 */ 522 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 523 musb->ep0_stage = MUSB_EP0_START; 524 musb->xceiv->state = OTG_STATE_A_IDLE; 525 MUSB_HST_MODE(musb); 526 musb_platform_set_vbus(musb, 1); 527 528 handled = IRQ_HANDLED; 529 } 530 531 if (int_usb & MUSB_INTR_VBUSERROR) { 532 int ignore = 0; 533 534 /* During connection as an A-Device, we may see a short 535 * current spikes causing voltage drop, because of cable 536 * and peripheral capacitance combined with vbus draw. 537 * (So: less common with truly self-powered devices, where 538 * vbus doesn't act like a power supply.) 539 * 540 * Such spikes are short; usually less than ~500 usec, max 541 * of ~2 msec. That is, they're not sustained overcurrent 542 * errors, though they're reported using VBUSERROR irqs. 543 * 544 * Workarounds: (a) hardware: use self powered devices. 545 * (b) software: ignore non-repeated VBUS errors. 546 * 547 * REVISIT: do delays from lots of DEBUG_KERNEL checks 548 * make trouble here, keeping VBUS < 4.4V ? 549 */ 550 switch (musb->xceiv->state) { 551 case OTG_STATE_A_HOST: 552 /* recovery is dicey once we've gotten past the 553 * initial stages of enumeration, but if VBUS 554 * stayed ok at the other end of the link, and 555 * another reset is due (at least for high speed, 556 * to redo the chirp etc), it might work OK... 557 */ 558 case OTG_STATE_A_WAIT_BCON: 559 case OTG_STATE_A_WAIT_VRISE: 560 if (musb->vbuserr_retry) { 561 void __iomem *mbase = musb->mregs; 562 563 musb->vbuserr_retry--; 564 ignore = 1; 565 devctl |= MUSB_DEVCTL_SESSION; 566 musb_writeb(mbase, MUSB_DEVCTL, devctl); 567 } else { 568 musb->port1_status |= 569 USB_PORT_STAT_OVERCURRENT 570 | (USB_PORT_STAT_C_OVERCURRENT << 16); 571 } 572 break; 573 default: 574 break; 575 } 576 577 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 578 otg_state_string(musb->xceiv->state), 579 devctl, 580 ({ char *s; 581 switch (devctl & MUSB_DEVCTL_VBUS) { 582 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 583 s = "<SessEnd"; break; 584 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 585 s = "<AValid"; break; 586 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 587 s = "<VBusValid"; break; 588 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 589 default: 590 s = "VALID"; break; 591 }; s; }), 592 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 593 musb->port1_status); 594 595 /* go through A_WAIT_VFALL then start a new session */ 596 if (!ignore) 597 musb_platform_set_vbus(musb, 0); 598 handled = IRQ_HANDLED; 599 } 600 601 if (int_usb & MUSB_INTR_SUSPEND) { 602 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 603 otg_state_string(musb->xceiv->state), devctl, power); 604 handled = IRQ_HANDLED; 605 606 switch (musb->xceiv->state) { 607 case OTG_STATE_A_PERIPHERAL: 608 /* We also come here if the cable is removed, since 609 * this silicon doesn't report ID-no-longer-grounded. 610 * 611 * We depend on T(a_wait_bcon) to shut us down, and 612 * hope users don't do anything dicey during this 613 * undesired detour through A_WAIT_BCON. 614 */ 615 musb_hnp_stop(musb); 616 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 617 musb_root_disconnect(musb); 618 musb_platform_try_idle(musb, jiffies 619 + msecs_to_jiffies(musb->a_wait_bcon 620 ? : OTG_TIME_A_WAIT_BCON)); 621 622 break; 623 case OTG_STATE_B_IDLE: 624 if (!musb->is_active) 625 break; 626 case OTG_STATE_B_PERIPHERAL: 627 musb_g_suspend(musb); 628 musb->is_active = is_otg_enabled(musb) 629 && musb->xceiv->gadget->b_hnp_enable; 630 if (musb->is_active) { 631 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 632 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 633 mod_timer(&musb->otg_timer, jiffies 634 + msecs_to_jiffies( 635 OTG_TIME_B_ASE0_BRST)); 636 } 637 break; 638 case OTG_STATE_A_WAIT_BCON: 639 if (musb->a_wait_bcon != 0) 640 musb_platform_try_idle(musb, jiffies 641 + msecs_to_jiffies(musb->a_wait_bcon)); 642 break; 643 case OTG_STATE_A_HOST: 644 musb->xceiv->state = OTG_STATE_A_SUSPEND; 645 musb->is_active = is_otg_enabled(musb) 646 && musb->xceiv->host->b_hnp_enable; 647 break; 648 case OTG_STATE_B_HOST: 649 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 650 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 651 break; 652 default: 653 /* "should not happen" */ 654 musb->is_active = 0; 655 break; 656 } 657 } 658 659 if (int_usb & MUSB_INTR_CONNECT) { 660 struct usb_hcd *hcd = musb_to_hcd(musb); 661 662 handled = IRQ_HANDLED; 663 musb->is_active = 1; 664 665 musb->ep0_stage = MUSB_EP0_START; 666 667 /* flush endpoints when transitioning from Device Mode */ 668 if (is_peripheral_active(musb)) { 669 /* REVISIT HNP; just force disconnect */ 670 } 671 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 672 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 673 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 674 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 675 |USB_PORT_STAT_HIGH_SPEED 676 |USB_PORT_STAT_ENABLE 677 ); 678 musb->port1_status |= USB_PORT_STAT_CONNECTION 679 |(USB_PORT_STAT_C_CONNECTION << 16); 680 681 /* high vs full speed is just a guess until after reset */ 682 if (devctl & MUSB_DEVCTL_LSDEV) 683 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 684 685 /* indicate new connection to OTG machine */ 686 switch (musb->xceiv->state) { 687 case OTG_STATE_B_PERIPHERAL: 688 if (int_usb & MUSB_INTR_SUSPEND) { 689 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 690 int_usb &= ~MUSB_INTR_SUSPEND; 691 goto b_host; 692 } else 693 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 694 break; 695 case OTG_STATE_B_WAIT_ACON: 696 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 697 b_host: 698 musb->xceiv->state = OTG_STATE_B_HOST; 699 hcd->self.is_b_host = 1; 700 musb->ignore_disconnect = 0; 701 del_timer(&musb->otg_timer); 702 break; 703 default: 704 if ((devctl & MUSB_DEVCTL_VBUS) 705 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 706 musb->xceiv->state = OTG_STATE_A_HOST; 707 hcd->self.is_b_host = 0; 708 } 709 break; 710 } 711 712 /* poke the root hub */ 713 MUSB_HST_MODE(musb); 714 if (hcd->status_urb) 715 usb_hcd_poll_rh_status(hcd); 716 else 717 usb_hcd_resume_root_hub(hcd); 718 719 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 720 otg_state_string(musb->xceiv->state), devctl); 721 } 722 723 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 724 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 725 otg_state_string(musb->xceiv->state), 726 MUSB_MODE(musb), devctl); 727 handled = IRQ_HANDLED; 728 729 switch (musb->xceiv->state) { 730 case OTG_STATE_A_HOST: 731 case OTG_STATE_A_SUSPEND: 732 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 733 musb_root_disconnect(musb); 734 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 735 musb_platform_try_idle(musb, jiffies 736 + msecs_to_jiffies(musb->a_wait_bcon)); 737 break; 738 case OTG_STATE_B_HOST: 739 /* REVISIT this behaves for "real disconnect" 740 * cases; make sure the other transitions from 741 * from B_HOST act right too. The B_HOST code 742 * in hnp_stop() is currently not used... 743 */ 744 musb_root_disconnect(musb); 745 musb_to_hcd(musb)->self.is_b_host = 0; 746 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 747 MUSB_DEV_MODE(musb); 748 musb_g_disconnect(musb); 749 break; 750 case OTG_STATE_A_PERIPHERAL: 751 musb_hnp_stop(musb); 752 musb_root_disconnect(musb); 753 /* FALLTHROUGH */ 754 case OTG_STATE_B_WAIT_ACON: 755 /* FALLTHROUGH */ 756 case OTG_STATE_B_PERIPHERAL: 757 case OTG_STATE_B_IDLE: 758 musb_g_disconnect(musb); 759 break; 760 default: 761 WARNING("unhandled DISCONNECT transition (%s)\n", 762 otg_state_string(musb->xceiv->state)); 763 break; 764 } 765 } 766 767 /* mentor saves a bit: bus reset and babble share the same irq. 768 * only host sees babble; only peripheral sees bus reset. 769 */ 770 if (int_usb & MUSB_INTR_RESET) { 771 handled = IRQ_HANDLED; 772 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 773 /* 774 * Looks like non-HS BABBLE can be ignored, but 775 * HS BABBLE is an error condition. For HS the solution 776 * is to avoid babble in the first place and fix what 777 * caused BABBLE. When HS BABBLE happens we can only 778 * stop the session. 779 */ 780 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 781 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 782 else { 783 ERR("Stopping host session -- babble\n"); 784 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 785 } 786 } else if (is_peripheral_capable()) { 787 dev_dbg(musb->controller, "BUS RESET as %s\n", 788 otg_state_string(musb->xceiv->state)); 789 switch (musb->xceiv->state) { 790 case OTG_STATE_A_SUSPEND: 791 /* We need to ignore disconnect on suspend 792 * otherwise tusb 2.0 won't reconnect after a 793 * power cycle, which breaks otg compliance. 794 */ 795 musb->ignore_disconnect = 1; 796 musb_g_reset(musb); 797 /* FALLTHROUGH */ 798 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 799 /* never use invalid T(a_wait_bcon) */ 800 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 801 otg_state_string(musb->xceiv->state), 802 TA_WAIT_BCON(musb)); 803 mod_timer(&musb->otg_timer, jiffies 804 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 805 break; 806 case OTG_STATE_A_PERIPHERAL: 807 musb->ignore_disconnect = 0; 808 del_timer(&musb->otg_timer); 809 musb_g_reset(musb); 810 break; 811 case OTG_STATE_B_WAIT_ACON: 812 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 813 otg_state_string(musb->xceiv->state)); 814 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 815 musb_g_reset(musb); 816 break; 817 case OTG_STATE_B_IDLE: 818 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 819 /* FALLTHROUGH */ 820 case OTG_STATE_B_PERIPHERAL: 821 musb_g_reset(musb); 822 break; 823 default: 824 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 825 otg_state_string(musb->xceiv->state)); 826 } 827 } 828 } 829 830 #if 0 831 /* REVISIT ... this would be for multiplexing periodic endpoints, or 832 * supporting transfer phasing to prevent exceeding ISO bandwidth 833 * limits of a given frame or microframe. 834 * 835 * It's not needed for peripheral side, which dedicates endpoints; 836 * though it _might_ use SOF irqs for other purposes. 837 * 838 * And it's not currently needed for host side, which also dedicates 839 * endpoints, relies on TX/RX interval registers, and isn't claimed 840 * to support ISO transfers yet. 841 */ 842 if (int_usb & MUSB_INTR_SOF) { 843 void __iomem *mbase = musb->mregs; 844 struct musb_hw_ep *ep; 845 u8 epnum; 846 u16 frame; 847 848 dev_dbg(musb->controller, "START_OF_FRAME\n"); 849 handled = IRQ_HANDLED; 850 851 /* start any periodic Tx transfers waiting for current frame */ 852 frame = musb_readw(mbase, MUSB_FRAME); 853 ep = musb->endpoints; 854 for (epnum = 1; (epnum < musb->nr_endpoints) 855 && (musb->epmask >= (1 << epnum)); 856 epnum++, ep++) { 857 /* 858 * FIXME handle framecounter wraps (12 bits) 859 * eliminate duplicated StartUrb logic 860 */ 861 if (ep->dwWaitFrame >= frame) { 862 ep->dwWaitFrame = 0; 863 pr_debug("SOF --> periodic TX%s on %d\n", 864 ep->tx_channel ? " DMA" : "", 865 epnum); 866 if (!ep->tx_channel) 867 musb_h_tx_start(musb, epnum); 868 else 869 cppi_hostdma_start(musb, epnum); 870 } 871 } /* end of for loop */ 872 } 873 #endif 874 875 schedule_work(&musb->irq_work); 876 877 return handled; 878 } 879 880 /*-------------------------------------------------------------------------*/ 881 882 /* 883 * Program the HDRC to start (enable interrupts, dma, etc.). 884 */ 885 void musb_start(struct musb *musb) 886 { 887 void __iomem *regs = musb->mregs; 888 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 889 890 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 891 892 /* Set INT enable registers, enable interrupts */ 893 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 894 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 895 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 896 897 musb_writeb(regs, MUSB_TESTMODE, 0); 898 899 /* put into basic highspeed mode and start session */ 900 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 901 | MUSB_POWER_HSENAB 902 /* ENSUSPEND wedges tusb */ 903 /* | MUSB_POWER_ENSUSPEND */ 904 ); 905 906 musb->is_active = 0; 907 devctl = musb_readb(regs, MUSB_DEVCTL); 908 devctl &= ~MUSB_DEVCTL_SESSION; 909 910 if (is_otg_enabled(musb)) { 911 /* session started after: 912 * (a) ID-grounded irq, host mode; 913 * (b) vbus present/connect IRQ, peripheral mode; 914 * (c) peripheral initiates, using SRP 915 */ 916 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 917 musb->is_active = 1; 918 else 919 devctl |= MUSB_DEVCTL_SESSION; 920 921 } else if (is_host_enabled(musb)) { 922 /* assume ID pin is hard-wired to ground */ 923 devctl |= MUSB_DEVCTL_SESSION; 924 925 } else /* peripheral is enabled */ { 926 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 927 musb->is_active = 1; 928 } 929 musb_platform_enable(musb); 930 musb_writeb(regs, MUSB_DEVCTL, devctl); 931 } 932 933 934 static void musb_generic_disable(struct musb *musb) 935 { 936 void __iomem *mbase = musb->mregs; 937 u16 temp; 938 939 /* disable interrupts */ 940 musb_writeb(mbase, MUSB_INTRUSBE, 0); 941 musb_writew(mbase, MUSB_INTRTXE, 0); 942 musb_writew(mbase, MUSB_INTRRXE, 0); 943 944 /* off */ 945 musb_writeb(mbase, MUSB_DEVCTL, 0); 946 947 /* flush pending interrupts */ 948 temp = musb_readb(mbase, MUSB_INTRUSB); 949 temp = musb_readw(mbase, MUSB_INTRTX); 950 temp = musb_readw(mbase, MUSB_INTRRX); 951 952 } 953 954 /* 955 * Make the HDRC stop (disable interrupts, etc.); 956 * reversible by musb_start 957 * called on gadget driver unregister 958 * with controller locked, irqs blocked 959 * acts as a NOP unless some role activated the hardware 960 */ 961 void musb_stop(struct musb *musb) 962 { 963 /* stop IRQs, timers, ... */ 964 musb_platform_disable(musb); 965 musb_generic_disable(musb); 966 dev_dbg(musb->controller, "HDRC disabled\n"); 967 968 /* FIXME 969 * - mark host and/or peripheral drivers unusable/inactive 970 * - disable DMA (and enable it in HdrcStart) 971 * - make sure we can musb_start() after musb_stop(); with 972 * OTG mode, gadget driver module rmmod/modprobe cycles that 973 * - ... 974 */ 975 musb_platform_try_idle(musb, 0); 976 } 977 978 static void musb_shutdown(struct platform_device *pdev) 979 { 980 struct musb *musb = dev_to_musb(&pdev->dev); 981 unsigned long flags; 982 983 pm_runtime_get_sync(musb->controller); 984 985 musb_gadget_cleanup(musb); 986 987 spin_lock_irqsave(&musb->lock, flags); 988 musb_platform_disable(musb); 989 musb_generic_disable(musb); 990 spin_unlock_irqrestore(&musb->lock, flags); 991 992 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 993 usb_remove_hcd(musb_to_hcd(musb)); 994 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 995 musb_platform_exit(musb); 996 997 pm_runtime_put(musb->controller); 998 /* FIXME power down */ 999 } 1000 1001 1002 /*-------------------------------------------------------------------------*/ 1003 1004 /* 1005 * The silicon either has hard-wired endpoint configurations, or else 1006 * "dynamic fifo" sizing. The driver has support for both, though at this 1007 * writing only the dynamic sizing is very well tested. Since we switched 1008 * away from compile-time hardware parameters, we can no longer rely on 1009 * dead code elimination to leave only the relevant one in the object file. 1010 * 1011 * We don't currently use dynamic fifo setup capability to do anything 1012 * more than selecting one of a bunch of predefined configurations. 1013 */ 1014 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1015 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1016 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1017 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1018 || defined(CONFIG_USB_MUSB_AM35X) \ 1019 || defined(CONFIG_USB_MUSB_AM35X_MODULE) 1020 static ushort __initdata fifo_mode = 4; 1021 #elif defined(CONFIG_USB_MUSB_UX500) \ 1022 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1023 static ushort __initdata fifo_mode = 5; 1024 #else 1025 static ushort __initdata fifo_mode = 2; 1026 #endif 1027 1028 /* "modprobe ... fifo_mode=1" etc */ 1029 module_param(fifo_mode, ushort, 0); 1030 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1031 1032 /* 1033 * tables defining fifo_mode values. define more if you like. 1034 * for host side, make sure both halves of ep1 are set up. 1035 */ 1036 1037 /* mode 0 - fits in 2KB */ 1038 static struct musb_fifo_cfg __initdata mode_0_cfg[] = { 1039 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1040 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1041 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1042 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1043 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1044 }; 1045 1046 /* mode 1 - fits in 4KB */ 1047 static struct musb_fifo_cfg __initdata mode_1_cfg[] = { 1048 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1049 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1050 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1051 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1052 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1053 }; 1054 1055 /* mode 2 - fits in 4KB */ 1056 static struct musb_fifo_cfg __initdata mode_2_cfg[] = { 1057 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1058 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1059 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1060 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1061 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1062 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1063 }; 1064 1065 /* mode 3 - fits in 4KB */ 1066 static struct musb_fifo_cfg __initdata mode_3_cfg[] = { 1067 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1068 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1069 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1070 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1071 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1072 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1073 }; 1074 1075 /* mode 4 - fits in 16KB */ 1076 static struct musb_fifo_cfg __initdata mode_4_cfg[] = { 1077 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1078 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1079 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1080 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1081 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1082 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1083 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1084 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1085 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1086 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1087 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1088 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1089 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1090 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1091 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1092 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1093 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1094 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1095 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1096 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1097 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1098 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1099 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1100 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1101 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1102 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1103 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1104 }; 1105 1106 /* mode 5 - fits in 8KB */ 1107 static struct musb_fifo_cfg __initdata mode_5_cfg[] = { 1108 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1109 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1110 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1111 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1112 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1113 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1114 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1115 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1116 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1117 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1118 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1119 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1120 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1121 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1122 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1123 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1124 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1125 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1126 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1127 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1128 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1129 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1130 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1131 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1132 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1133 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1134 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1135 }; 1136 1137 /* 1138 * configure a fifo; for non-shared endpoints, this may be called 1139 * once for a tx fifo and once for an rx fifo. 1140 * 1141 * returns negative errno or offset for next fifo. 1142 */ 1143 static int __init 1144 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1145 const struct musb_fifo_cfg *cfg, u16 offset) 1146 { 1147 void __iomem *mbase = musb->mregs; 1148 int size = 0; 1149 u16 maxpacket = cfg->maxpacket; 1150 u16 c_off = offset >> 3; 1151 u8 c_size; 1152 1153 /* expect hw_ep has already been zero-initialized */ 1154 1155 size = ffs(max(maxpacket, (u16) 8)) - 1; 1156 maxpacket = 1 << size; 1157 1158 c_size = size - 3; 1159 if (cfg->mode == BUF_DOUBLE) { 1160 if ((offset + (maxpacket << 1)) > 1161 (1 << (musb->config->ram_bits + 2))) 1162 return -EMSGSIZE; 1163 c_size |= MUSB_FIFOSZ_DPB; 1164 } else { 1165 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1166 return -EMSGSIZE; 1167 } 1168 1169 /* configure the FIFO */ 1170 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1171 1172 /* EP0 reserved endpoint for control, bidirectional; 1173 * EP1 reserved for bulk, two unidirection halves. 1174 */ 1175 if (hw_ep->epnum == 1) 1176 musb->bulk_ep = hw_ep; 1177 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1178 switch (cfg->style) { 1179 case FIFO_TX: 1180 musb_write_txfifosz(mbase, c_size); 1181 musb_write_txfifoadd(mbase, c_off); 1182 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1183 hw_ep->max_packet_sz_tx = maxpacket; 1184 break; 1185 case FIFO_RX: 1186 musb_write_rxfifosz(mbase, c_size); 1187 musb_write_rxfifoadd(mbase, c_off); 1188 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1189 hw_ep->max_packet_sz_rx = maxpacket; 1190 break; 1191 case FIFO_RXTX: 1192 musb_write_txfifosz(mbase, c_size); 1193 musb_write_txfifoadd(mbase, c_off); 1194 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1195 hw_ep->max_packet_sz_rx = maxpacket; 1196 1197 musb_write_rxfifosz(mbase, c_size); 1198 musb_write_rxfifoadd(mbase, c_off); 1199 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1200 hw_ep->max_packet_sz_tx = maxpacket; 1201 1202 hw_ep->is_shared_fifo = true; 1203 break; 1204 } 1205 1206 /* NOTE rx and tx endpoint irqs aren't managed separately, 1207 * which happens to be ok 1208 */ 1209 musb->epmask |= (1 << hw_ep->epnum); 1210 1211 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1212 } 1213 1214 static struct musb_fifo_cfg __initdata ep0_cfg = { 1215 .style = FIFO_RXTX, .maxpacket = 64, 1216 }; 1217 1218 static int __init ep_config_from_table(struct musb *musb) 1219 { 1220 const struct musb_fifo_cfg *cfg; 1221 unsigned i, n; 1222 int offset; 1223 struct musb_hw_ep *hw_ep = musb->endpoints; 1224 1225 if (musb->config->fifo_cfg) { 1226 cfg = musb->config->fifo_cfg; 1227 n = musb->config->fifo_cfg_size; 1228 goto done; 1229 } 1230 1231 switch (fifo_mode) { 1232 default: 1233 fifo_mode = 0; 1234 /* FALLTHROUGH */ 1235 case 0: 1236 cfg = mode_0_cfg; 1237 n = ARRAY_SIZE(mode_0_cfg); 1238 break; 1239 case 1: 1240 cfg = mode_1_cfg; 1241 n = ARRAY_SIZE(mode_1_cfg); 1242 break; 1243 case 2: 1244 cfg = mode_2_cfg; 1245 n = ARRAY_SIZE(mode_2_cfg); 1246 break; 1247 case 3: 1248 cfg = mode_3_cfg; 1249 n = ARRAY_SIZE(mode_3_cfg); 1250 break; 1251 case 4: 1252 cfg = mode_4_cfg; 1253 n = ARRAY_SIZE(mode_4_cfg); 1254 break; 1255 case 5: 1256 cfg = mode_5_cfg; 1257 n = ARRAY_SIZE(mode_5_cfg); 1258 break; 1259 } 1260 1261 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1262 musb_driver_name, fifo_mode); 1263 1264 1265 done: 1266 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1267 /* assert(offset > 0) */ 1268 1269 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1270 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1271 */ 1272 1273 for (i = 0; i < n; i++) { 1274 u8 epn = cfg->hw_ep_num; 1275 1276 if (epn >= musb->config->num_eps) { 1277 pr_debug("%s: invalid ep %d\n", 1278 musb_driver_name, epn); 1279 return -EINVAL; 1280 } 1281 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1282 if (offset < 0) { 1283 pr_debug("%s: mem overrun, ep %d\n", 1284 musb_driver_name, epn); 1285 return -EINVAL; 1286 } 1287 epn++; 1288 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1289 } 1290 1291 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1292 musb_driver_name, 1293 n + 1, musb->config->num_eps * 2 - 1, 1294 offset, (1 << (musb->config->ram_bits + 2))); 1295 1296 if (!musb->bulk_ep) { 1297 pr_debug("%s: missing bulk\n", musb_driver_name); 1298 return -EINVAL; 1299 } 1300 1301 return 0; 1302 } 1303 1304 1305 /* 1306 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1307 * @param musb the controller 1308 */ 1309 static int __init ep_config_from_hw(struct musb *musb) 1310 { 1311 u8 epnum = 0; 1312 struct musb_hw_ep *hw_ep; 1313 void *mbase = musb->mregs; 1314 int ret = 0; 1315 1316 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1317 1318 /* FIXME pick up ep0 maxpacket size */ 1319 1320 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1321 musb_ep_select(mbase, epnum); 1322 hw_ep = musb->endpoints + epnum; 1323 1324 ret = musb_read_fifosize(musb, hw_ep, epnum); 1325 if (ret < 0) 1326 break; 1327 1328 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1329 1330 /* pick an RX/TX endpoint for bulk */ 1331 if (hw_ep->max_packet_sz_tx < 512 1332 || hw_ep->max_packet_sz_rx < 512) 1333 continue; 1334 1335 /* REVISIT: this algorithm is lazy, we should at least 1336 * try to pick a double buffered endpoint. 1337 */ 1338 if (musb->bulk_ep) 1339 continue; 1340 musb->bulk_ep = hw_ep; 1341 } 1342 1343 if (!musb->bulk_ep) { 1344 pr_debug("%s: missing bulk\n", musb_driver_name); 1345 return -EINVAL; 1346 } 1347 1348 return 0; 1349 } 1350 1351 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1352 1353 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1354 * configure endpoints, or take their config from silicon 1355 */ 1356 static int __init musb_core_init(u16 musb_type, struct musb *musb) 1357 { 1358 u8 reg; 1359 char *type; 1360 char aInfo[90], aRevision[32], aDate[12]; 1361 void __iomem *mbase = musb->mregs; 1362 int status = 0; 1363 int i; 1364 1365 /* log core options (read using indexed model) */ 1366 reg = musb_read_configdata(mbase); 1367 1368 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1369 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1370 strcat(aInfo, ", dyn FIFOs"); 1371 musb->dyn_fifo = true; 1372 } 1373 if (reg & MUSB_CONFIGDATA_MPRXE) { 1374 strcat(aInfo, ", bulk combine"); 1375 musb->bulk_combine = true; 1376 } 1377 if (reg & MUSB_CONFIGDATA_MPTXE) { 1378 strcat(aInfo, ", bulk split"); 1379 musb->bulk_split = true; 1380 } 1381 if (reg & MUSB_CONFIGDATA_HBRXE) { 1382 strcat(aInfo, ", HB-ISO Rx"); 1383 musb->hb_iso_rx = true; 1384 } 1385 if (reg & MUSB_CONFIGDATA_HBTXE) { 1386 strcat(aInfo, ", HB-ISO Tx"); 1387 musb->hb_iso_tx = true; 1388 } 1389 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1390 strcat(aInfo, ", SoftConn"); 1391 1392 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1393 musb_driver_name, reg, aInfo); 1394 1395 aDate[0] = 0; 1396 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1397 musb->is_multipoint = 1; 1398 type = "M"; 1399 } else { 1400 musb->is_multipoint = 0; 1401 type = ""; 1402 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1403 printk(KERN_ERR 1404 "%s: kernel must blacklist external hubs\n", 1405 musb_driver_name); 1406 #endif 1407 } 1408 1409 /* log release info */ 1410 musb->hwvers = musb_read_hwvers(mbase); 1411 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1412 MUSB_HWVERS_MINOR(musb->hwvers), 1413 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1414 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1415 musb_driver_name, type, aRevision, aDate); 1416 1417 /* configure ep0 */ 1418 musb_configure_ep0(musb); 1419 1420 /* discover endpoint configuration */ 1421 musb->nr_endpoints = 1; 1422 musb->epmask = 1; 1423 1424 if (musb->dyn_fifo) 1425 status = ep_config_from_table(musb); 1426 else 1427 status = ep_config_from_hw(musb); 1428 1429 if (status < 0) 1430 return status; 1431 1432 /* finish init, and print endpoint config */ 1433 for (i = 0; i < musb->nr_endpoints; i++) { 1434 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1435 1436 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1437 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1438 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1439 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1440 hw_ep->fifo_sync_va = 1441 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1442 1443 if (i == 0) 1444 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1445 else 1446 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1447 #endif 1448 1449 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1450 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1451 hw_ep->rx_reinit = 1; 1452 hw_ep->tx_reinit = 1; 1453 1454 if (hw_ep->max_packet_sz_tx) { 1455 dev_dbg(musb->controller, 1456 "%s: hw_ep %d%s, %smax %d\n", 1457 musb_driver_name, i, 1458 hw_ep->is_shared_fifo ? "shared" : "tx", 1459 hw_ep->tx_double_buffered 1460 ? "doublebuffer, " : "", 1461 hw_ep->max_packet_sz_tx); 1462 } 1463 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1464 dev_dbg(musb->controller, 1465 "%s: hw_ep %d%s, %smax %d\n", 1466 musb_driver_name, i, 1467 "rx", 1468 hw_ep->rx_double_buffered 1469 ? "doublebuffer, " : "", 1470 hw_ep->max_packet_sz_rx); 1471 } 1472 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1473 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1474 } 1475 1476 return 0; 1477 } 1478 1479 /*-------------------------------------------------------------------------*/ 1480 1481 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1482 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) 1483 1484 static irqreturn_t generic_interrupt(int irq, void *__hci) 1485 { 1486 unsigned long flags; 1487 irqreturn_t retval = IRQ_NONE; 1488 struct musb *musb = __hci; 1489 1490 spin_lock_irqsave(&musb->lock, flags); 1491 1492 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1493 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1494 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1495 1496 if (musb->int_usb || musb->int_tx || musb->int_rx) 1497 retval = musb_interrupt(musb); 1498 1499 spin_unlock_irqrestore(&musb->lock, flags); 1500 1501 return retval; 1502 } 1503 1504 #else 1505 #define generic_interrupt NULL 1506 #endif 1507 1508 /* 1509 * handle all the irqs defined by the HDRC core. for now we expect: other 1510 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1511 * will be assigned, and the irq will already have been acked. 1512 * 1513 * called in irq context with spinlock held, irqs blocked 1514 */ 1515 irqreturn_t musb_interrupt(struct musb *musb) 1516 { 1517 irqreturn_t retval = IRQ_NONE; 1518 u8 devctl, power; 1519 int ep_num; 1520 u32 reg; 1521 1522 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1523 power = musb_readb(musb->mregs, MUSB_POWER); 1524 1525 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1526 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1527 musb->int_usb, musb->int_tx, musb->int_rx); 1528 1529 /* the core can interrupt us for multiple reasons; docs have 1530 * a generic interrupt flowchart to follow 1531 */ 1532 if (musb->int_usb) 1533 retval |= musb_stage0_irq(musb, musb->int_usb, 1534 devctl, power); 1535 1536 /* "stage 1" is handling endpoint irqs */ 1537 1538 /* handle endpoint 0 first */ 1539 if (musb->int_tx & 1) { 1540 if (devctl & MUSB_DEVCTL_HM) 1541 retval |= musb_h_ep0_irq(musb); 1542 else 1543 retval |= musb_g_ep0_irq(musb); 1544 } 1545 1546 /* RX on endpoints 1-15 */ 1547 reg = musb->int_rx >> 1; 1548 ep_num = 1; 1549 while (reg) { 1550 if (reg & 1) { 1551 /* musb_ep_select(musb->mregs, ep_num); */ 1552 /* REVISIT just retval = ep->rx_irq(...) */ 1553 retval = IRQ_HANDLED; 1554 if (devctl & MUSB_DEVCTL_HM) { 1555 if (is_host_capable()) 1556 musb_host_rx(musb, ep_num); 1557 } else { 1558 if (is_peripheral_capable()) 1559 musb_g_rx(musb, ep_num); 1560 } 1561 } 1562 1563 reg >>= 1; 1564 ep_num++; 1565 } 1566 1567 /* TX on endpoints 1-15 */ 1568 reg = musb->int_tx >> 1; 1569 ep_num = 1; 1570 while (reg) { 1571 if (reg & 1) { 1572 /* musb_ep_select(musb->mregs, ep_num); */ 1573 /* REVISIT just retval |= ep->tx_irq(...) */ 1574 retval = IRQ_HANDLED; 1575 if (devctl & MUSB_DEVCTL_HM) { 1576 if (is_host_capable()) 1577 musb_host_tx(musb, ep_num); 1578 } else { 1579 if (is_peripheral_capable()) 1580 musb_g_tx(musb, ep_num); 1581 } 1582 } 1583 reg >>= 1; 1584 ep_num++; 1585 } 1586 1587 return retval; 1588 } 1589 EXPORT_SYMBOL_GPL(musb_interrupt); 1590 1591 #ifndef CONFIG_MUSB_PIO_ONLY 1592 static bool __initdata use_dma = 1; 1593 1594 /* "modprobe ... use_dma=0" etc */ 1595 module_param(use_dma, bool, 0); 1596 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1597 1598 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1599 { 1600 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1601 1602 /* called with controller lock already held */ 1603 1604 if (!epnum) { 1605 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1606 if (!is_cppi_enabled()) { 1607 /* endpoint 0 */ 1608 if (devctl & MUSB_DEVCTL_HM) 1609 musb_h_ep0_irq(musb); 1610 else 1611 musb_g_ep0_irq(musb); 1612 } 1613 #endif 1614 } else { 1615 /* endpoints 1..15 */ 1616 if (transmit) { 1617 if (devctl & MUSB_DEVCTL_HM) { 1618 if (is_host_capable()) 1619 musb_host_tx(musb, epnum); 1620 } else { 1621 if (is_peripheral_capable()) 1622 musb_g_tx(musb, epnum); 1623 } 1624 } else { 1625 /* receive */ 1626 if (devctl & MUSB_DEVCTL_HM) { 1627 if (is_host_capable()) 1628 musb_host_rx(musb, epnum); 1629 } else { 1630 if (is_peripheral_capable()) 1631 musb_g_rx(musb, epnum); 1632 } 1633 } 1634 } 1635 } 1636 EXPORT_SYMBOL_GPL(musb_dma_completion); 1637 1638 #else 1639 #define use_dma 0 1640 #endif 1641 1642 /*-------------------------------------------------------------------------*/ 1643 1644 #ifdef CONFIG_SYSFS 1645 1646 static ssize_t 1647 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1648 { 1649 struct musb *musb = dev_to_musb(dev); 1650 unsigned long flags; 1651 int ret = -EINVAL; 1652 1653 spin_lock_irqsave(&musb->lock, flags); 1654 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1655 spin_unlock_irqrestore(&musb->lock, flags); 1656 1657 return ret; 1658 } 1659 1660 static ssize_t 1661 musb_mode_store(struct device *dev, struct device_attribute *attr, 1662 const char *buf, size_t n) 1663 { 1664 struct musb *musb = dev_to_musb(dev); 1665 unsigned long flags; 1666 int status; 1667 1668 spin_lock_irqsave(&musb->lock, flags); 1669 if (sysfs_streq(buf, "host")) 1670 status = musb_platform_set_mode(musb, MUSB_HOST); 1671 else if (sysfs_streq(buf, "peripheral")) 1672 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1673 else if (sysfs_streq(buf, "otg")) 1674 status = musb_platform_set_mode(musb, MUSB_OTG); 1675 else 1676 status = -EINVAL; 1677 spin_unlock_irqrestore(&musb->lock, flags); 1678 1679 return (status == 0) ? n : status; 1680 } 1681 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1682 1683 static ssize_t 1684 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1685 const char *buf, size_t n) 1686 { 1687 struct musb *musb = dev_to_musb(dev); 1688 unsigned long flags; 1689 unsigned long val; 1690 1691 if (sscanf(buf, "%lu", &val) < 1) { 1692 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1693 return -EINVAL; 1694 } 1695 1696 spin_lock_irqsave(&musb->lock, flags); 1697 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1698 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1699 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1700 musb->is_active = 0; 1701 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1702 spin_unlock_irqrestore(&musb->lock, flags); 1703 1704 return n; 1705 } 1706 1707 static ssize_t 1708 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1709 { 1710 struct musb *musb = dev_to_musb(dev); 1711 unsigned long flags; 1712 unsigned long val; 1713 int vbus; 1714 1715 spin_lock_irqsave(&musb->lock, flags); 1716 val = musb->a_wait_bcon; 1717 /* FIXME get_vbus_status() is normally #defined as false... 1718 * and is effectively TUSB-specific. 1719 */ 1720 vbus = musb_platform_get_vbus_status(musb); 1721 spin_unlock_irqrestore(&musb->lock, flags); 1722 1723 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1724 vbus ? "on" : "off", val); 1725 } 1726 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1727 1728 /* Gadget drivers can't know that a host is connected so they might want 1729 * to start SRP, but users can. This allows userspace to trigger SRP. 1730 */ 1731 static ssize_t 1732 musb_srp_store(struct device *dev, struct device_attribute *attr, 1733 const char *buf, size_t n) 1734 { 1735 struct musb *musb = dev_to_musb(dev); 1736 unsigned short srp; 1737 1738 if (sscanf(buf, "%hu", &srp) != 1 1739 || (srp != 1)) { 1740 dev_err(dev, "SRP: Value must be 1\n"); 1741 return -EINVAL; 1742 } 1743 1744 if (srp == 1) 1745 musb_g_wakeup(musb); 1746 1747 return n; 1748 } 1749 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1750 1751 static struct attribute *musb_attributes[] = { 1752 &dev_attr_mode.attr, 1753 &dev_attr_vbus.attr, 1754 &dev_attr_srp.attr, 1755 NULL 1756 }; 1757 1758 static const struct attribute_group musb_attr_group = { 1759 .attrs = musb_attributes, 1760 }; 1761 1762 #endif /* sysfs */ 1763 1764 /* Only used to provide driver mode change events */ 1765 static void musb_irq_work(struct work_struct *data) 1766 { 1767 struct musb *musb = container_of(data, struct musb, irq_work); 1768 static int old_state; 1769 1770 if (musb->xceiv->state != old_state) { 1771 old_state = musb->xceiv->state; 1772 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1773 } 1774 } 1775 1776 /* -------------------------------------------------------------------------- 1777 * Init support 1778 */ 1779 1780 static struct musb *__init 1781 allocate_instance(struct device *dev, 1782 struct musb_hdrc_config *config, void __iomem *mbase) 1783 { 1784 struct musb *musb; 1785 struct musb_hw_ep *ep; 1786 int epnum; 1787 struct usb_hcd *hcd; 1788 1789 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1790 if (!hcd) 1791 return NULL; 1792 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1793 1794 musb = hcd_to_musb(hcd); 1795 INIT_LIST_HEAD(&musb->control); 1796 INIT_LIST_HEAD(&musb->in_bulk); 1797 INIT_LIST_HEAD(&musb->out_bulk); 1798 1799 hcd->uses_new_polling = 1; 1800 hcd->has_tt = 1; 1801 1802 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1803 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1804 dev_set_drvdata(dev, musb); 1805 musb->mregs = mbase; 1806 musb->ctrl_base = mbase; 1807 musb->nIrq = -ENODEV; 1808 musb->config = config; 1809 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1810 for (epnum = 0, ep = musb->endpoints; 1811 epnum < musb->config->num_eps; 1812 epnum++, ep++) { 1813 ep->musb = musb; 1814 ep->epnum = epnum; 1815 } 1816 1817 musb->controller = dev; 1818 1819 return musb; 1820 } 1821 1822 static void musb_free(struct musb *musb) 1823 { 1824 /* this has multiple entry modes. it handles fault cleanup after 1825 * probe(), where things may be partially set up, as well as rmmod 1826 * cleanup after everything's been de-activated. 1827 */ 1828 1829 #ifdef CONFIG_SYSFS 1830 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1831 #endif 1832 1833 if (musb->nIrq >= 0) { 1834 if (musb->irq_wake) 1835 disable_irq_wake(musb->nIrq); 1836 free_irq(musb->nIrq, musb); 1837 } 1838 if (is_dma_capable() && musb->dma_controller) { 1839 struct dma_controller *c = musb->dma_controller; 1840 1841 (void) c->stop(c); 1842 dma_controller_destroy(c); 1843 } 1844 1845 kfree(musb); 1846 } 1847 1848 /* 1849 * Perform generic per-controller initialization. 1850 * 1851 * @pDevice: the controller (already clocked, etc) 1852 * @nIrq: irq 1853 * @mregs: virtual address of controller registers, 1854 * not yet corrected for platform-specific offsets 1855 */ 1856 static int __init 1857 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1858 { 1859 int status; 1860 struct musb *musb; 1861 struct musb_hdrc_platform_data *plat = dev->platform_data; 1862 1863 /* The driver might handle more features than the board; OK. 1864 * Fail when the board needs a feature that's not enabled. 1865 */ 1866 if (!plat) { 1867 dev_dbg(dev, "no platform_data?\n"); 1868 status = -ENODEV; 1869 goto fail0; 1870 } 1871 1872 /* allocate */ 1873 musb = allocate_instance(dev, plat->config, ctrl); 1874 if (!musb) { 1875 status = -ENOMEM; 1876 goto fail0; 1877 } 1878 1879 pm_runtime_use_autosuspend(musb->controller); 1880 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1881 pm_runtime_enable(musb->controller); 1882 1883 spin_lock_init(&musb->lock); 1884 musb->board_mode = plat->mode; 1885 musb->board_set_power = plat->set_power; 1886 musb->min_power = plat->min_power; 1887 musb->ops = plat->platform_ops; 1888 1889 /* The musb_platform_init() call: 1890 * - adjusts musb->mregs and musb->isr if needed, 1891 * - may initialize an integrated tranceiver 1892 * - initializes musb->xceiv, usually by otg_get_transceiver() 1893 * - stops powering VBUS 1894 * 1895 * There are various transceiver configurations. Blackfin, 1896 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1897 * external/discrete ones in various flavors (twl4030 family, 1898 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1899 */ 1900 musb->isr = generic_interrupt; 1901 status = musb_platform_init(musb); 1902 if (status < 0) 1903 goto fail1; 1904 1905 if (!musb->isr) { 1906 status = -ENODEV; 1907 goto fail3; 1908 } 1909 1910 if (!musb->xceiv->io_ops) { 1911 musb->xceiv->io_priv = musb->mregs; 1912 musb->xceiv->io_ops = &musb_ulpi_access; 1913 } 1914 1915 #ifndef CONFIG_MUSB_PIO_ONLY 1916 if (use_dma && dev->dma_mask) { 1917 struct dma_controller *c; 1918 1919 c = dma_controller_create(musb, musb->mregs); 1920 musb->dma_controller = c; 1921 if (c) 1922 (void) c->start(c); 1923 } 1924 #endif 1925 /* ideally this would be abstracted in platform setup */ 1926 if (!is_dma_capable() || !musb->dma_controller) 1927 dev->dma_mask = NULL; 1928 1929 /* be sure interrupts are disabled before connecting ISR */ 1930 musb_platform_disable(musb); 1931 musb_generic_disable(musb); 1932 1933 /* setup musb parts of the core (especially endpoints) */ 1934 status = musb_core_init(plat->config->multipoint 1935 ? MUSB_CONTROLLER_MHDRC 1936 : MUSB_CONTROLLER_HDRC, musb); 1937 if (status < 0) 1938 goto fail3; 1939 1940 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1941 1942 /* Init IRQ workqueue before request_irq */ 1943 INIT_WORK(&musb->irq_work, musb_irq_work); 1944 1945 /* attach to the IRQ */ 1946 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1947 dev_err(dev, "request_irq %d failed!\n", nIrq); 1948 status = -ENODEV; 1949 goto fail3; 1950 } 1951 musb->nIrq = nIrq; 1952 /* FIXME this handles wakeup irqs wrong */ 1953 if (enable_irq_wake(nIrq) == 0) { 1954 musb->irq_wake = 1; 1955 device_init_wakeup(dev, 1); 1956 } else { 1957 musb->irq_wake = 0; 1958 } 1959 1960 /* host side needs more setup */ 1961 if (is_host_enabled(musb)) { 1962 struct usb_hcd *hcd = musb_to_hcd(musb); 1963 1964 otg_set_host(musb->xceiv, &hcd->self); 1965 1966 if (is_otg_enabled(musb)) 1967 hcd->self.otg_port = 1; 1968 musb->xceiv->host = &hcd->self; 1969 hcd->power_budget = 2 * (plat->power ? : 250); 1970 1971 /* program PHY to use external vBus if required */ 1972 if (plat->extvbus) { 1973 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 1974 busctl |= MUSB_ULPI_USE_EXTVBUS; 1975 musb_write_ulpi_buscontrol(musb->mregs, busctl); 1976 } 1977 } 1978 1979 /* For the host-only role, we can activate right away. 1980 * (We expect the ID pin to be forcibly grounded!!) 1981 * Otherwise, wait till the gadget driver hooks up. 1982 */ 1983 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 1984 struct usb_hcd *hcd = musb_to_hcd(musb); 1985 1986 MUSB_HST_MODE(musb); 1987 musb->xceiv->default_a = 1; 1988 musb->xceiv->state = OTG_STATE_A_IDLE; 1989 1990 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 1991 1992 hcd->self.uses_pio_for_control = 1; 1993 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", 1994 "HOST", status, 1995 musb_readb(musb->mregs, MUSB_DEVCTL), 1996 (musb_readb(musb->mregs, MUSB_DEVCTL) 1997 & MUSB_DEVCTL_BDEVICE 1998 ? 'B' : 'A')); 1999 2000 } else /* peripheral is enabled */ { 2001 MUSB_DEV_MODE(musb); 2002 musb->xceiv->default_a = 0; 2003 musb->xceiv->state = OTG_STATE_B_IDLE; 2004 2005 status = musb_gadget_setup(musb); 2006 2007 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", 2008 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2009 status, 2010 musb_readb(musb->mregs, MUSB_DEVCTL)); 2011 2012 } 2013 if (status < 0) 2014 goto fail3; 2015 2016 status = musb_init_debugfs(musb); 2017 if (status < 0) 2018 goto fail4; 2019 2020 #ifdef CONFIG_SYSFS 2021 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2022 if (status) 2023 goto fail5; 2024 #endif 2025 2026 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2027 ({char *s; 2028 switch (musb->board_mode) { 2029 case MUSB_HOST: s = "Host"; break; 2030 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2031 default: s = "OTG"; break; 2032 }; s; }), 2033 ctrl, 2034 (is_dma_capable() && musb->dma_controller) 2035 ? "DMA" : "PIO", 2036 musb->nIrq); 2037 2038 return 0; 2039 2040 fail5: 2041 musb_exit_debugfs(musb); 2042 2043 fail4: 2044 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2045 usb_remove_hcd(musb_to_hcd(musb)); 2046 else 2047 musb_gadget_cleanup(musb); 2048 2049 fail3: 2050 if (musb->irq_wake) 2051 device_init_wakeup(dev, 0); 2052 musb_platform_exit(musb); 2053 2054 fail1: 2055 dev_err(musb->controller, 2056 "musb_init_controller failed with status %d\n", status); 2057 2058 musb_free(musb); 2059 2060 fail0: 2061 2062 return status; 2063 2064 } 2065 2066 /*-------------------------------------------------------------------------*/ 2067 2068 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2069 * bridge to a platform device; this driver then suffices. 2070 */ 2071 2072 #ifndef CONFIG_MUSB_PIO_ONLY 2073 static u64 *orig_dma_mask; 2074 #endif 2075 2076 static int __init musb_probe(struct platform_device *pdev) 2077 { 2078 struct device *dev = &pdev->dev; 2079 int irq = platform_get_irq_byname(pdev, "mc"); 2080 int status; 2081 struct resource *iomem; 2082 void __iomem *base; 2083 2084 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2085 if (!iomem || irq <= 0) 2086 return -ENODEV; 2087 2088 base = ioremap(iomem->start, resource_size(iomem)); 2089 if (!base) { 2090 dev_err(dev, "ioremap failed\n"); 2091 return -ENOMEM; 2092 } 2093 2094 #ifndef CONFIG_MUSB_PIO_ONLY 2095 /* clobbered by use_dma=n */ 2096 orig_dma_mask = dev->dma_mask; 2097 #endif 2098 status = musb_init_controller(dev, irq, base); 2099 if (status < 0) 2100 iounmap(base); 2101 2102 return status; 2103 } 2104 2105 static int __exit musb_remove(struct platform_device *pdev) 2106 { 2107 struct musb *musb = dev_to_musb(&pdev->dev); 2108 void __iomem *ctrl_base = musb->ctrl_base; 2109 2110 /* this gets called on rmmod. 2111 * - Host mode: host may still be active 2112 * - Peripheral mode: peripheral is deactivated (or never-activated) 2113 * - OTG mode: both roles are deactivated (or never-activated) 2114 */ 2115 pm_runtime_get_sync(musb->controller); 2116 musb_exit_debugfs(musb); 2117 musb_shutdown(pdev); 2118 2119 pm_runtime_put(musb->controller); 2120 musb_free(musb); 2121 iounmap(ctrl_base); 2122 device_init_wakeup(&pdev->dev, 0); 2123 #ifndef CONFIG_MUSB_PIO_ONLY 2124 pdev->dev.dma_mask = orig_dma_mask; 2125 #endif 2126 return 0; 2127 } 2128 2129 #ifdef CONFIG_PM 2130 2131 static void musb_save_context(struct musb *musb) 2132 { 2133 int i; 2134 void __iomem *musb_base = musb->mregs; 2135 void __iomem *epio; 2136 2137 if (is_host_enabled(musb)) { 2138 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2139 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2140 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2141 } 2142 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2143 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2144 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2145 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2146 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2147 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2148 2149 for (i = 0; i < musb->config->num_eps; ++i) { 2150 struct musb_hw_ep *hw_ep; 2151 2152 hw_ep = &musb->endpoints[i]; 2153 if (!hw_ep) 2154 continue; 2155 2156 epio = hw_ep->regs; 2157 if (!epio) 2158 continue; 2159 2160 musb_writeb(musb_base, MUSB_INDEX, i); 2161 musb->context.index_regs[i].txmaxp = 2162 musb_readw(epio, MUSB_TXMAXP); 2163 musb->context.index_regs[i].txcsr = 2164 musb_readw(epio, MUSB_TXCSR); 2165 musb->context.index_regs[i].rxmaxp = 2166 musb_readw(epio, MUSB_RXMAXP); 2167 musb->context.index_regs[i].rxcsr = 2168 musb_readw(epio, MUSB_RXCSR); 2169 2170 if (musb->dyn_fifo) { 2171 musb->context.index_regs[i].txfifoadd = 2172 musb_read_txfifoadd(musb_base); 2173 musb->context.index_regs[i].rxfifoadd = 2174 musb_read_rxfifoadd(musb_base); 2175 musb->context.index_regs[i].txfifosz = 2176 musb_read_txfifosz(musb_base); 2177 musb->context.index_regs[i].rxfifosz = 2178 musb_read_rxfifosz(musb_base); 2179 } 2180 if (is_host_enabled(musb)) { 2181 musb->context.index_regs[i].txtype = 2182 musb_readb(epio, MUSB_TXTYPE); 2183 musb->context.index_regs[i].txinterval = 2184 musb_readb(epio, MUSB_TXINTERVAL); 2185 musb->context.index_regs[i].rxtype = 2186 musb_readb(epio, MUSB_RXTYPE); 2187 musb->context.index_regs[i].rxinterval = 2188 musb_readb(epio, MUSB_RXINTERVAL); 2189 2190 musb->context.index_regs[i].txfunaddr = 2191 musb_read_txfunaddr(musb_base, i); 2192 musb->context.index_regs[i].txhubaddr = 2193 musb_read_txhubaddr(musb_base, i); 2194 musb->context.index_regs[i].txhubport = 2195 musb_read_txhubport(musb_base, i); 2196 2197 musb->context.index_regs[i].rxfunaddr = 2198 musb_read_rxfunaddr(musb_base, i); 2199 musb->context.index_regs[i].rxhubaddr = 2200 musb_read_rxhubaddr(musb_base, i); 2201 musb->context.index_regs[i].rxhubport = 2202 musb_read_rxhubport(musb_base, i); 2203 } 2204 } 2205 } 2206 2207 static void musb_restore_context(struct musb *musb) 2208 { 2209 int i; 2210 void __iomem *musb_base = musb->mregs; 2211 void __iomem *ep_target_regs; 2212 void __iomem *epio; 2213 2214 if (is_host_enabled(musb)) { 2215 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2216 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2217 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2218 } 2219 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2220 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2221 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2222 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2223 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2224 2225 for (i = 0; i < musb->config->num_eps; ++i) { 2226 struct musb_hw_ep *hw_ep; 2227 2228 hw_ep = &musb->endpoints[i]; 2229 if (!hw_ep) 2230 continue; 2231 2232 epio = hw_ep->regs; 2233 if (!epio) 2234 continue; 2235 2236 musb_writeb(musb_base, MUSB_INDEX, i); 2237 musb_writew(epio, MUSB_TXMAXP, 2238 musb->context.index_regs[i].txmaxp); 2239 musb_writew(epio, MUSB_TXCSR, 2240 musb->context.index_regs[i].txcsr); 2241 musb_writew(epio, MUSB_RXMAXP, 2242 musb->context.index_regs[i].rxmaxp); 2243 musb_writew(epio, MUSB_RXCSR, 2244 musb->context.index_regs[i].rxcsr); 2245 2246 if (musb->dyn_fifo) { 2247 musb_write_txfifosz(musb_base, 2248 musb->context.index_regs[i].txfifosz); 2249 musb_write_rxfifosz(musb_base, 2250 musb->context.index_regs[i].rxfifosz); 2251 musb_write_txfifoadd(musb_base, 2252 musb->context.index_regs[i].txfifoadd); 2253 musb_write_rxfifoadd(musb_base, 2254 musb->context.index_regs[i].rxfifoadd); 2255 } 2256 2257 if (is_host_enabled(musb)) { 2258 musb_writeb(epio, MUSB_TXTYPE, 2259 musb->context.index_regs[i].txtype); 2260 musb_writeb(epio, MUSB_TXINTERVAL, 2261 musb->context.index_regs[i].txinterval); 2262 musb_writeb(epio, MUSB_RXTYPE, 2263 musb->context.index_regs[i].rxtype); 2264 musb_writeb(epio, MUSB_RXINTERVAL, 2265 2266 musb->context.index_regs[i].rxinterval); 2267 musb_write_txfunaddr(musb_base, i, 2268 musb->context.index_regs[i].txfunaddr); 2269 musb_write_txhubaddr(musb_base, i, 2270 musb->context.index_regs[i].txhubaddr); 2271 musb_write_txhubport(musb_base, i, 2272 musb->context.index_regs[i].txhubport); 2273 2274 ep_target_regs = 2275 musb_read_target_reg_base(i, musb_base); 2276 2277 musb_write_rxfunaddr(ep_target_regs, 2278 musb->context.index_regs[i].rxfunaddr); 2279 musb_write_rxhubaddr(ep_target_regs, 2280 musb->context.index_regs[i].rxhubaddr); 2281 musb_write_rxhubport(ep_target_regs, 2282 musb->context.index_regs[i].rxhubport); 2283 } 2284 } 2285 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2286 } 2287 2288 static int musb_suspend(struct device *dev) 2289 { 2290 struct musb *musb = dev_to_musb(dev); 2291 unsigned long flags; 2292 2293 spin_lock_irqsave(&musb->lock, flags); 2294 2295 if (is_peripheral_active(musb)) { 2296 /* FIXME force disconnect unless we know USB will wake 2297 * the system up quickly enough to respond ... 2298 */ 2299 } else if (is_host_active(musb)) { 2300 /* we know all the children are suspended; sometimes 2301 * they will even be wakeup-enabled. 2302 */ 2303 } 2304 2305 spin_unlock_irqrestore(&musb->lock, flags); 2306 return 0; 2307 } 2308 2309 static int musb_resume_noirq(struct device *dev) 2310 { 2311 /* for static cmos like DaVinci, register values were preserved 2312 * unless for some reason the whole soc powered down or the USB 2313 * module got reset through the PSC (vs just being disabled). 2314 */ 2315 return 0; 2316 } 2317 2318 static int musb_runtime_suspend(struct device *dev) 2319 { 2320 struct musb *musb = dev_to_musb(dev); 2321 2322 musb_save_context(musb); 2323 2324 return 0; 2325 } 2326 2327 static int musb_runtime_resume(struct device *dev) 2328 { 2329 struct musb *musb = dev_to_musb(dev); 2330 static int first = 1; 2331 2332 /* 2333 * When pm_runtime_get_sync called for the first time in driver 2334 * init, some of the structure is still not initialized which is 2335 * used in restore function. But clock needs to be 2336 * enabled before any register access, so 2337 * pm_runtime_get_sync has to be called. 2338 * Also context restore without save does not make 2339 * any sense 2340 */ 2341 if (!first) 2342 musb_restore_context(musb); 2343 first = 0; 2344 2345 return 0; 2346 } 2347 2348 static const struct dev_pm_ops musb_dev_pm_ops = { 2349 .suspend = musb_suspend, 2350 .resume_noirq = musb_resume_noirq, 2351 .runtime_suspend = musb_runtime_suspend, 2352 .runtime_resume = musb_runtime_resume, 2353 }; 2354 2355 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2356 #else 2357 #define MUSB_DEV_PM_OPS NULL 2358 #endif 2359 2360 static struct platform_driver musb_driver = { 2361 .driver = { 2362 .name = (char *)musb_driver_name, 2363 .bus = &platform_bus_type, 2364 .owner = THIS_MODULE, 2365 .pm = MUSB_DEV_PM_OPS, 2366 }, 2367 .remove = __exit_p(musb_remove), 2368 .shutdown = musb_shutdown, 2369 }; 2370 2371 /*-------------------------------------------------------------------------*/ 2372 2373 static int __init musb_init(void) 2374 { 2375 if (usb_disabled()) 2376 return 0; 2377 2378 pr_info("%s: version " MUSB_VERSION ", " 2379 "?dma?" 2380 ", " 2381 "otg (peripheral+host)", 2382 musb_driver_name); 2383 return platform_driver_probe(&musb_driver, musb_probe); 2384 } 2385 2386 /* make us init after usbcore and i2c (transceivers, regulators, etc) 2387 * and before usb gadget and host-side drivers start to register 2388 */ 2389 fs_initcall(musb_init); 2390 2391 static void __exit musb_cleanup(void) 2392 { 2393 platform_driver_unregister(&musb_driver); 2394 } 2395 module_exit(musb_cleanup); 2396