1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific information 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #include <linux/module.h> 93 #include <linux/kernel.h> 94 #include <linux/sched.h> 95 #include <linux/slab.h> 96 #include <linux/list.h> 97 #include <linux/kobject.h> 98 #include <linux/prefetch.h> 99 #include <linux/platform_device.h> 100 #include <linux/io.h> 101 #include <linux/dma-mapping.h> 102 103 #include "musb_core.h" 104 105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 106 107 108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 110 111 #define MUSB_VERSION "6.0" 112 113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 114 115 #define MUSB_DRIVER_NAME "musb-hdrc" 116 const char musb_driver_name[] = MUSB_DRIVER_NAME; 117 118 MODULE_DESCRIPTION(DRIVER_INFO); 119 MODULE_AUTHOR(DRIVER_AUTHOR); 120 MODULE_LICENSE("GPL"); 121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 122 123 124 /*-------------------------------------------------------------------------*/ 125 126 static inline struct musb *dev_to_musb(struct device *dev) 127 { 128 return dev_get_drvdata(dev); 129 } 130 131 /*-------------------------------------------------------------------------*/ 132 133 #ifndef CONFIG_BLACKFIN 134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 135 { 136 void __iomem *addr = phy->io_priv; 137 int i = 0; 138 u8 r; 139 u8 power; 140 int ret; 141 142 pm_runtime_get_sync(phy->io_dev); 143 144 /* Make sure the transceiver is not in low power mode */ 145 power = musb_readb(addr, MUSB_POWER); 146 power &= ~MUSB_POWER_SUSPENDM; 147 musb_writeb(addr, MUSB_POWER, power); 148 149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 151 */ 152 153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 156 157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 158 & MUSB_ULPI_REG_CMPLT)) { 159 i++; 160 if (i == 10000) { 161 ret = -ETIMEDOUT; 162 goto out; 163 } 164 165 } 166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 167 r &= ~MUSB_ULPI_REG_CMPLT; 168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 169 170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 171 172 out: 173 pm_runtime_put(phy->io_dev); 174 175 return ret; 176 } 177 178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 179 { 180 void __iomem *addr = phy->io_priv; 181 int i = 0; 182 u8 r = 0; 183 u8 power; 184 int ret = 0; 185 186 pm_runtime_get_sync(phy->io_dev); 187 188 /* Make sure the transceiver is not in low power mode */ 189 power = musb_readb(addr, MUSB_POWER); 190 power &= ~MUSB_POWER_SUSPENDM; 191 musb_writeb(addr, MUSB_POWER, power); 192 193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 196 197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 198 & MUSB_ULPI_REG_CMPLT)) { 199 i++; 200 if (i == 10000) { 201 ret = -ETIMEDOUT; 202 goto out; 203 } 204 } 205 206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 207 r &= ~MUSB_ULPI_REG_CMPLT; 208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 209 210 out: 211 pm_runtime_put(phy->io_dev); 212 213 return ret; 214 } 215 #else 216 #define musb_ulpi_read NULL 217 #define musb_ulpi_write NULL 218 #endif 219 220 static struct usb_phy_io_ops musb_ulpi_access = { 221 .read = musb_ulpi_read, 222 .write = musb_ulpi_write, 223 }; 224 225 /*-------------------------------------------------------------------------*/ 226 227 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 228 229 /* 230 * Load an endpoint's FIFO 231 */ 232 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 233 { 234 struct musb *musb = hw_ep->musb; 235 void __iomem *fifo = hw_ep->fifo; 236 237 if (unlikely(len == 0)) 238 return; 239 240 prefetch((u8 *)src); 241 242 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 243 'T', hw_ep->epnum, fifo, len, src); 244 245 /* we can't assume unaligned reads work */ 246 if (likely((0x01 & (unsigned long) src) == 0)) { 247 u16 index = 0; 248 249 /* best case is 32bit-aligned source address */ 250 if ((0x02 & (unsigned long) src) == 0) { 251 if (len >= 4) { 252 iowrite32_rep(fifo, src + index, len >> 2); 253 index += len & ~0x03; 254 } 255 if (len & 0x02) { 256 musb_writew(fifo, 0, *(u16 *)&src[index]); 257 index += 2; 258 } 259 } else { 260 if (len >= 2) { 261 iowrite16_rep(fifo, src + index, len >> 1); 262 index += len & ~0x01; 263 } 264 } 265 if (len & 0x01) 266 musb_writeb(fifo, 0, src[index]); 267 } else { 268 /* byte aligned */ 269 iowrite8_rep(fifo, src, len); 270 } 271 } 272 273 #if !defined(CONFIG_USB_MUSB_AM35X) 274 /* 275 * Unload an endpoint's FIFO 276 */ 277 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 278 { 279 struct musb *musb = hw_ep->musb; 280 void __iomem *fifo = hw_ep->fifo; 281 282 if (unlikely(len == 0)) 283 return; 284 285 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 286 'R', hw_ep->epnum, fifo, len, dst); 287 288 /* we can't assume unaligned writes work */ 289 if (likely((0x01 & (unsigned long) dst) == 0)) { 290 u16 index = 0; 291 292 /* best case is 32bit-aligned destination address */ 293 if ((0x02 & (unsigned long) dst) == 0) { 294 if (len >= 4) { 295 ioread32_rep(fifo, dst, len >> 2); 296 index = len & ~0x03; 297 } 298 if (len & 0x02) { 299 *(u16 *)&dst[index] = musb_readw(fifo, 0); 300 index += 2; 301 } 302 } else { 303 if (len >= 2) { 304 ioread16_rep(fifo, dst, len >> 1); 305 index = len & ~0x01; 306 } 307 } 308 if (len & 0x01) 309 dst[index] = musb_readb(fifo, 0); 310 } else { 311 /* byte aligned */ 312 ioread8_rep(fifo, dst, len); 313 } 314 } 315 #endif 316 317 #endif /* normal PIO */ 318 319 320 /*-------------------------------------------------------------------------*/ 321 322 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 323 static const u8 musb_test_packet[53] = { 324 /* implicit SYNC then DATA0 to start */ 325 326 /* JKJKJKJK x9 */ 327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 328 /* JJKKJJKK x8 */ 329 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 330 /* JJJJKKKK x8 */ 331 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 332 /* JJJJJJJKKKKKKK x8 */ 333 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 334 /* JJJJJJJK x8 */ 335 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 336 /* JKKKKKKK x10, JK */ 337 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 338 339 /* implicit CRC16 then EOP to end */ 340 }; 341 342 void musb_load_testpacket(struct musb *musb) 343 { 344 void __iomem *regs = musb->endpoints[0].regs; 345 346 musb_ep_select(musb->mregs, 0); 347 musb_write_fifo(musb->control_ep, 348 sizeof(musb_test_packet), musb_test_packet); 349 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 350 } 351 352 /*-------------------------------------------------------------------------*/ 353 354 /* 355 * Handles OTG hnp timeouts, such as b_ase0_brst 356 */ 357 static void musb_otg_timer_func(unsigned long data) 358 { 359 struct musb *musb = (struct musb *)data; 360 unsigned long flags; 361 362 spin_lock_irqsave(&musb->lock, flags); 363 switch (musb->xceiv->state) { 364 case OTG_STATE_B_WAIT_ACON: 365 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 366 musb_g_disconnect(musb); 367 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 368 musb->is_active = 0; 369 break; 370 case OTG_STATE_A_SUSPEND: 371 case OTG_STATE_A_WAIT_BCON: 372 dev_dbg(musb->controller, "HNP: %s timeout\n", 373 usb_otg_state_string(musb->xceiv->state)); 374 musb_platform_set_vbus(musb, 0); 375 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 376 break; 377 default: 378 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 379 usb_otg_state_string(musb->xceiv->state)); 380 } 381 spin_unlock_irqrestore(&musb->lock, flags); 382 } 383 384 /* 385 * Stops the HNP transition. Caller must take care of locking. 386 */ 387 void musb_hnp_stop(struct musb *musb) 388 { 389 struct usb_hcd *hcd = musb->hcd; 390 void __iomem *mbase = musb->mregs; 391 u8 reg; 392 393 dev_dbg(musb->controller, "HNP: stop from %s\n", 394 usb_otg_state_string(musb->xceiv->state)); 395 396 switch (musb->xceiv->state) { 397 case OTG_STATE_A_PERIPHERAL: 398 musb_g_disconnect(musb); 399 dev_dbg(musb->controller, "HNP: back to %s\n", 400 usb_otg_state_string(musb->xceiv->state)); 401 break; 402 case OTG_STATE_B_HOST: 403 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 404 if (hcd) 405 hcd->self.is_b_host = 0; 406 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 407 MUSB_DEV_MODE(musb); 408 reg = musb_readb(mbase, MUSB_POWER); 409 reg |= MUSB_POWER_SUSPENDM; 410 musb_writeb(mbase, MUSB_POWER, reg); 411 /* REVISIT: Start SESSION_REQUEST here? */ 412 break; 413 default: 414 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 415 usb_otg_state_string(musb->xceiv->state)); 416 } 417 418 /* 419 * When returning to A state after HNP, avoid hub_port_rebounce(), 420 * which cause occasional OPT A "Did not receive reset after connect" 421 * errors. 422 */ 423 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 424 } 425 426 /* 427 * Interrupt Service Routine to record USB "global" interrupts. 428 * Since these do not happen often and signify things of 429 * paramount importance, it seems OK to check them individually; 430 * the order of the tests is specified in the manual 431 * 432 * @param musb instance pointer 433 * @param int_usb register contents 434 * @param devctl 435 * @param power 436 */ 437 438 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 439 u8 devctl) 440 { 441 struct usb_otg *otg = musb->xceiv->otg; 442 irqreturn_t handled = IRQ_NONE; 443 444 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl, 445 int_usb); 446 447 /* in host mode, the peripheral may issue remote wakeup. 448 * in peripheral mode, the host may resume the link. 449 * spurious RESUME irqs happen too, paired with SUSPEND. 450 */ 451 if (int_usb & MUSB_INTR_RESUME) { 452 handled = IRQ_HANDLED; 453 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state)); 454 455 if (devctl & MUSB_DEVCTL_HM) { 456 void __iomem *mbase = musb->mregs; 457 u8 power; 458 459 switch (musb->xceiv->state) { 460 case OTG_STATE_A_SUSPEND: 461 /* remote wakeup? later, GetPortStatus 462 * will stop RESUME signaling 463 */ 464 465 power = musb_readb(musb->mregs, MUSB_POWER); 466 if (power & MUSB_POWER_SUSPENDM) { 467 /* spurious */ 468 musb->int_usb &= ~MUSB_INTR_SUSPEND; 469 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 470 break; 471 } 472 473 power &= ~MUSB_POWER_SUSPENDM; 474 musb_writeb(mbase, MUSB_POWER, 475 power | MUSB_POWER_RESUME); 476 477 musb->port1_status |= 478 (USB_PORT_STAT_C_SUSPEND << 16) 479 | MUSB_PORT_STAT_RESUME; 480 schedule_delayed_work( 481 &musb->finish_resume_work, 20); 482 483 musb->xceiv->state = OTG_STATE_A_HOST; 484 musb->is_active = 1; 485 musb_host_resume_root_hub(musb); 486 break; 487 case OTG_STATE_B_WAIT_ACON: 488 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 489 musb->is_active = 1; 490 MUSB_DEV_MODE(musb); 491 break; 492 default: 493 WARNING("bogus %s RESUME (%s)\n", 494 "host", 495 usb_otg_state_string(musb->xceiv->state)); 496 } 497 } else { 498 switch (musb->xceiv->state) { 499 case OTG_STATE_A_SUSPEND: 500 /* possibly DISCONNECT is upcoming */ 501 musb->xceiv->state = OTG_STATE_A_HOST; 502 musb_host_resume_root_hub(musb); 503 break; 504 case OTG_STATE_B_WAIT_ACON: 505 case OTG_STATE_B_PERIPHERAL: 506 /* disconnect while suspended? we may 507 * not get a disconnect irq... 508 */ 509 if ((devctl & MUSB_DEVCTL_VBUS) 510 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 511 ) { 512 musb->int_usb |= MUSB_INTR_DISCONNECT; 513 musb->int_usb &= ~MUSB_INTR_SUSPEND; 514 break; 515 } 516 musb_g_resume(musb); 517 break; 518 case OTG_STATE_B_IDLE: 519 musb->int_usb &= ~MUSB_INTR_SUSPEND; 520 break; 521 default: 522 WARNING("bogus %s RESUME (%s)\n", 523 "peripheral", 524 usb_otg_state_string(musb->xceiv->state)); 525 } 526 } 527 } 528 529 /* see manual for the order of the tests */ 530 if (int_usb & MUSB_INTR_SESSREQ) { 531 void __iomem *mbase = musb->mregs; 532 533 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 534 && (devctl & MUSB_DEVCTL_BDEVICE)) { 535 dev_dbg(musb->controller, "SessReq while on B state\n"); 536 return IRQ_HANDLED; 537 } 538 539 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 540 usb_otg_state_string(musb->xceiv->state)); 541 542 /* IRQ arrives from ID pin sense or (later, if VBUS power 543 * is removed) SRP. responses are time critical: 544 * - turn on VBUS (with silicon-specific mechanism) 545 * - go through A_WAIT_VRISE 546 * - ... to A_WAIT_BCON. 547 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 548 */ 549 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 550 musb->ep0_stage = MUSB_EP0_START; 551 musb->xceiv->state = OTG_STATE_A_IDLE; 552 MUSB_HST_MODE(musb); 553 musb_platform_set_vbus(musb, 1); 554 555 handled = IRQ_HANDLED; 556 } 557 558 if (int_usb & MUSB_INTR_VBUSERROR) { 559 int ignore = 0; 560 561 /* During connection as an A-Device, we may see a short 562 * current spikes causing voltage drop, because of cable 563 * and peripheral capacitance combined with vbus draw. 564 * (So: less common with truly self-powered devices, where 565 * vbus doesn't act like a power supply.) 566 * 567 * Such spikes are short; usually less than ~500 usec, max 568 * of ~2 msec. That is, they're not sustained overcurrent 569 * errors, though they're reported using VBUSERROR irqs. 570 * 571 * Workarounds: (a) hardware: use self powered devices. 572 * (b) software: ignore non-repeated VBUS errors. 573 * 574 * REVISIT: do delays from lots of DEBUG_KERNEL checks 575 * make trouble here, keeping VBUS < 4.4V ? 576 */ 577 switch (musb->xceiv->state) { 578 case OTG_STATE_A_HOST: 579 /* recovery is dicey once we've gotten past the 580 * initial stages of enumeration, but if VBUS 581 * stayed ok at the other end of the link, and 582 * another reset is due (at least for high speed, 583 * to redo the chirp etc), it might work OK... 584 */ 585 case OTG_STATE_A_WAIT_BCON: 586 case OTG_STATE_A_WAIT_VRISE: 587 if (musb->vbuserr_retry) { 588 void __iomem *mbase = musb->mregs; 589 590 musb->vbuserr_retry--; 591 ignore = 1; 592 devctl |= MUSB_DEVCTL_SESSION; 593 musb_writeb(mbase, MUSB_DEVCTL, devctl); 594 } else { 595 musb->port1_status |= 596 USB_PORT_STAT_OVERCURRENT 597 | (USB_PORT_STAT_C_OVERCURRENT << 16); 598 } 599 break; 600 default: 601 break; 602 } 603 604 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, 605 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 606 usb_otg_state_string(musb->xceiv->state), 607 devctl, 608 ({ char *s; 609 switch (devctl & MUSB_DEVCTL_VBUS) { 610 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 611 s = "<SessEnd"; break; 612 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 613 s = "<AValid"; break; 614 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 615 s = "<VBusValid"; break; 616 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 617 default: 618 s = "VALID"; break; 619 } s; }), 620 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 621 musb->port1_status); 622 623 /* go through A_WAIT_VFALL then start a new session */ 624 if (!ignore) 625 musb_platform_set_vbus(musb, 0); 626 handled = IRQ_HANDLED; 627 } 628 629 if (int_usb & MUSB_INTR_SUSPEND) { 630 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n", 631 usb_otg_state_string(musb->xceiv->state), devctl); 632 handled = IRQ_HANDLED; 633 634 switch (musb->xceiv->state) { 635 case OTG_STATE_A_PERIPHERAL: 636 /* We also come here if the cable is removed, since 637 * this silicon doesn't report ID-no-longer-grounded. 638 * 639 * We depend on T(a_wait_bcon) to shut us down, and 640 * hope users don't do anything dicey during this 641 * undesired detour through A_WAIT_BCON. 642 */ 643 musb_hnp_stop(musb); 644 musb_host_resume_root_hub(musb); 645 musb_root_disconnect(musb); 646 musb_platform_try_idle(musb, jiffies 647 + msecs_to_jiffies(musb->a_wait_bcon 648 ? : OTG_TIME_A_WAIT_BCON)); 649 650 break; 651 case OTG_STATE_B_IDLE: 652 if (!musb->is_active) 653 break; 654 case OTG_STATE_B_PERIPHERAL: 655 musb_g_suspend(musb); 656 musb->is_active = otg->gadget->b_hnp_enable; 657 if (musb->is_active) { 658 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 659 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 660 mod_timer(&musb->otg_timer, jiffies 661 + msecs_to_jiffies( 662 OTG_TIME_B_ASE0_BRST)); 663 } 664 break; 665 case OTG_STATE_A_WAIT_BCON: 666 if (musb->a_wait_bcon != 0) 667 musb_platform_try_idle(musb, jiffies 668 + msecs_to_jiffies(musb->a_wait_bcon)); 669 break; 670 case OTG_STATE_A_HOST: 671 musb->xceiv->state = OTG_STATE_A_SUSPEND; 672 musb->is_active = otg->host->b_hnp_enable; 673 break; 674 case OTG_STATE_B_HOST: 675 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 676 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 677 break; 678 default: 679 /* "should not happen" */ 680 musb->is_active = 0; 681 break; 682 } 683 } 684 685 if (int_usb & MUSB_INTR_CONNECT) { 686 struct usb_hcd *hcd = musb->hcd; 687 688 handled = IRQ_HANDLED; 689 musb->is_active = 1; 690 691 musb->ep0_stage = MUSB_EP0_START; 692 693 /* flush endpoints when transitioning from Device Mode */ 694 if (is_peripheral_active(musb)) { 695 /* REVISIT HNP; just force disconnect */ 696 } 697 musb->intrtxe = musb->epmask; 698 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); 699 musb->intrrxe = musb->epmask & 0xfffe; 700 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); 701 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 702 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 703 |USB_PORT_STAT_HIGH_SPEED 704 |USB_PORT_STAT_ENABLE 705 ); 706 musb->port1_status |= USB_PORT_STAT_CONNECTION 707 |(USB_PORT_STAT_C_CONNECTION << 16); 708 709 /* high vs full speed is just a guess until after reset */ 710 if (devctl & MUSB_DEVCTL_LSDEV) 711 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 712 713 /* indicate new connection to OTG machine */ 714 switch (musb->xceiv->state) { 715 case OTG_STATE_B_PERIPHERAL: 716 if (int_usb & MUSB_INTR_SUSPEND) { 717 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 718 int_usb &= ~MUSB_INTR_SUSPEND; 719 goto b_host; 720 } else 721 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 722 break; 723 case OTG_STATE_B_WAIT_ACON: 724 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 725 b_host: 726 musb->xceiv->state = OTG_STATE_B_HOST; 727 if (musb->hcd) 728 musb->hcd->self.is_b_host = 1; 729 del_timer(&musb->otg_timer); 730 break; 731 default: 732 if ((devctl & MUSB_DEVCTL_VBUS) 733 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 734 musb->xceiv->state = OTG_STATE_A_HOST; 735 if (hcd) 736 hcd->self.is_b_host = 0; 737 } 738 break; 739 } 740 741 musb_host_poke_root_hub(musb); 742 743 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 744 usb_otg_state_string(musb->xceiv->state), devctl); 745 } 746 747 if (int_usb & MUSB_INTR_DISCONNECT) { 748 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 749 usb_otg_state_string(musb->xceiv->state), 750 MUSB_MODE(musb), devctl); 751 handled = IRQ_HANDLED; 752 753 switch (musb->xceiv->state) { 754 case OTG_STATE_A_HOST: 755 case OTG_STATE_A_SUSPEND: 756 musb_host_resume_root_hub(musb); 757 musb_root_disconnect(musb); 758 if (musb->a_wait_bcon != 0) 759 musb_platform_try_idle(musb, jiffies 760 + msecs_to_jiffies(musb->a_wait_bcon)); 761 break; 762 case OTG_STATE_B_HOST: 763 /* REVISIT this behaves for "real disconnect" 764 * cases; make sure the other transitions from 765 * from B_HOST act right too. The B_HOST code 766 * in hnp_stop() is currently not used... 767 */ 768 musb_root_disconnect(musb); 769 if (musb->hcd) 770 musb->hcd->self.is_b_host = 0; 771 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 772 MUSB_DEV_MODE(musb); 773 musb_g_disconnect(musb); 774 break; 775 case OTG_STATE_A_PERIPHERAL: 776 musb_hnp_stop(musb); 777 musb_root_disconnect(musb); 778 /* FALLTHROUGH */ 779 case OTG_STATE_B_WAIT_ACON: 780 /* FALLTHROUGH */ 781 case OTG_STATE_B_PERIPHERAL: 782 case OTG_STATE_B_IDLE: 783 musb_g_disconnect(musb); 784 break; 785 default: 786 WARNING("unhandled DISCONNECT transition (%s)\n", 787 usb_otg_state_string(musb->xceiv->state)); 788 break; 789 } 790 } 791 792 /* mentor saves a bit: bus reset and babble share the same irq. 793 * only host sees babble; only peripheral sees bus reset. 794 */ 795 if (int_usb & MUSB_INTR_RESET) { 796 handled = IRQ_HANDLED; 797 if ((devctl & MUSB_DEVCTL_HM) != 0) { 798 /* 799 * Looks like non-HS BABBLE can be ignored, but 800 * HS BABBLE is an error condition. For HS the solution 801 * is to avoid babble in the first place and fix what 802 * caused BABBLE. When HS BABBLE happens we can only 803 * stop the session. 804 */ 805 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 806 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 807 else { 808 ERR("Stopping host session -- babble\n"); 809 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 810 } 811 } else { 812 dev_dbg(musb->controller, "BUS RESET as %s\n", 813 usb_otg_state_string(musb->xceiv->state)); 814 switch (musb->xceiv->state) { 815 case OTG_STATE_A_SUSPEND: 816 musb_g_reset(musb); 817 /* FALLTHROUGH */ 818 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 819 /* never use invalid T(a_wait_bcon) */ 820 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 821 usb_otg_state_string(musb->xceiv->state), 822 TA_WAIT_BCON(musb)); 823 mod_timer(&musb->otg_timer, jiffies 824 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 825 break; 826 case OTG_STATE_A_PERIPHERAL: 827 del_timer(&musb->otg_timer); 828 musb_g_reset(musb); 829 break; 830 case OTG_STATE_B_WAIT_ACON: 831 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 832 usb_otg_state_string(musb->xceiv->state)); 833 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 834 musb_g_reset(musb); 835 break; 836 case OTG_STATE_B_IDLE: 837 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 838 /* FALLTHROUGH */ 839 case OTG_STATE_B_PERIPHERAL: 840 musb_g_reset(musb); 841 break; 842 default: 843 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 844 usb_otg_state_string(musb->xceiv->state)); 845 } 846 } 847 } 848 849 #if 0 850 /* REVISIT ... this would be for multiplexing periodic endpoints, or 851 * supporting transfer phasing to prevent exceeding ISO bandwidth 852 * limits of a given frame or microframe. 853 * 854 * It's not needed for peripheral side, which dedicates endpoints; 855 * though it _might_ use SOF irqs for other purposes. 856 * 857 * And it's not currently needed for host side, which also dedicates 858 * endpoints, relies on TX/RX interval registers, and isn't claimed 859 * to support ISO transfers yet. 860 */ 861 if (int_usb & MUSB_INTR_SOF) { 862 void __iomem *mbase = musb->mregs; 863 struct musb_hw_ep *ep; 864 u8 epnum; 865 u16 frame; 866 867 dev_dbg(musb->controller, "START_OF_FRAME\n"); 868 handled = IRQ_HANDLED; 869 870 /* start any periodic Tx transfers waiting for current frame */ 871 frame = musb_readw(mbase, MUSB_FRAME); 872 ep = musb->endpoints; 873 for (epnum = 1; (epnum < musb->nr_endpoints) 874 && (musb->epmask >= (1 << epnum)); 875 epnum++, ep++) { 876 /* 877 * FIXME handle framecounter wraps (12 bits) 878 * eliminate duplicated StartUrb logic 879 */ 880 if (ep->dwWaitFrame >= frame) { 881 ep->dwWaitFrame = 0; 882 pr_debug("SOF --> periodic TX%s on %d\n", 883 ep->tx_channel ? " DMA" : "", 884 epnum); 885 if (!ep->tx_channel) 886 musb_h_tx_start(musb, epnum); 887 else 888 cppi_hostdma_start(musb, epnum); 889 } 890 } /* end of for loop */ 891 } 892 #endif 893 894 schedule_work(&musb->irq_work); 895 896 return handled; 897 } 898 899 /*-------------------------------------------------------------------------*/ 900 901 static void musb_generic_disable(struct musb *musb) 902 { 903 void __iomem *mbase = musb->mregs; 904 u16 temp; 905 906 /* disable interrupts */ 907 musb_writeb(mbase, MUSB_INTRUSBE, 0); 908 musb->intrtxe = 0; 909 musb_writew(mbase, MUSB_INTRTXE, 0); 910 musb->intrrxe = 0; 911 musb_writew(mbase, MUSB_INTRRXE, 0); 912 913 /* off */ 914 musb_writeb(mbase, MUSB_DEVCTL, 0); 915 916 /* flush pending interrupts */ 917 temp = musb_readb(mbase, MUSB_INTRUSB); 918 temp = musb_readw(mbase, MUSB_INTRTX); 919 temp = musb_readw(mbase, MUSB_INTRRX); 920 921 } 922 923 /* 924 * Program the HDRC to start (enable interrupts, dma, etc.). 925 */ 926 void musb_start(struct musb *musb) 927 { 928 void __iomem *regs = musb->mregs; 929 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 930 931 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 932 933 /* Set INT enable registers, enable interrupts */ 934 musb->intrtxe = musb->epmask; 935 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); 936 musb->intrrxe = musb->epmask & 0xfffe; 937 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); 938 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 939 940 musb_writeb(regs, MUSB_TESTMODE, 0); 941 942 /* put into basic highspeed mode and start session */ 943 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 944 | MUSB_POWER_HSENAB 945 /* ENSUSPEND wedges tusb */ 946 /* | MUSB_POWER_ENSUSPEND */ 947 ); 948 949 musb->is_active = 0; 950 devctl = musb_readb(regs, MUSB_DEVCTL); 951 devctl &= ~MUSB_DEVCTL_SESSION; 952 953 /* session started after: 954 * (a) ID-grounded irq, host mode; 955 * (b) vbus present/connect IRQ, peripheral mode; 956 * (c) peripheral initiates, using SRP 957 */ 958 if (musb->port_mode != MUSB_PORT_MODE_HOST && 959 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { 960 musb->is_active = 1; 961 } else { 962 devctl |= MUSB_DEVCTL_SESSION; 963 } 964 965 musb_platform_enable(musb); 966 musb_writeb(regs, MUSB_DEVCTL, devctl); 967 } 968 969 /* 970 * Make the HDRC stop (disable interrupts, etc.); 971 * reversible by musb_start 972 * called on gadget driver unregister 973 * with controller locked, irqs blocked 974 * acts as a NOP unless some role activated the hardware 975 */ 976 void musb_stop(struct musb *musb) 977 { 978 /* stop IRQs, timers, ... */ 979 musb_platform_disable(musb); 980 musb_generic_disable(musb); 981 dev_dbg(musb->controller, "HDRC disabled\n"); 982 983 /* FIXME 984 * - mark host and/or peripheral drivers unusable/inactive 985 * - disable DMA (and enable it in HdrcStart) 986 * - make sure we can musb_start() after musb_stop(); with 987 * OTG mode, gadget driver module rmmod/modprobe cycles that 988 * - ... 989 */ 990 musb_platform_try_idle(musb, 0); 991 } 992 993 static void musb_shutdown(struct platform_device *pdev) 994 { 995 struct musb *musb = dev_to_musb(&pdev->dev); 996 unsigned long flags; 997 998 pm_runtime_get_sync(musb->controller); 999 1000 musb_host_cleanup(musb); 1001 musb_gadget_cleanup(musb); 1002 1003 spin_lock_irqsave(&musb->lock, flags); 1004 musb_platform_disable(musb); 1005 musb_generic_disable(musb); 1006 spin_unlock_irqrestore(&musb->lock, flags); 1007 1008 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1009 musb_platform_exit(musb); 1010 1011 pm_runtime_put(musb->controller); 1012 /* FIXME power down */ 1013 } 1014 1015 1016 /*-------------------------------------------------------------------------*/ 1017 1018 /* 1019 * The silicon either has hard-wired endpoint configurations, or else 1020 * "dynamic fifo" sizing. The driver has support for both, though at this 1021 * writing only the dynamic sizing is very well tested. Since we switched 1022 * away from compile-time hardware parameters, we can no longer rely on 1023 * dead code elimination to leave only the relevant one in the object file. 1024 * 1025 * We don't currently use dynamic fifo setup capability to do anything 1026 * more than selecting one of a bunch of predefined configurations. 1027 */ 1028 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1029 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1030 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1031 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1032 || defined(CONFIG_USB_MUSB_AM35X) \ 1033 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 1034 || defined(CONFIG_USB_MUSB_DSPS) \ 1035 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 1036 static ushort fifo_mode = 4; 1037 #elif defined(CONFIG_USB_MUSB_UX500) \ 1038 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1039 static ushort fifo_mode = 5; 1040 #else 1041 static ushort fifo_mode = 2; 1042 #endif 1043 1044 /* "modprobe ... fifo_mode=1" etc */ 1045 module_param(fifo_mode, ushort, 0); 1046 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1047 1048 /* 1049 * tables defining fifo_mode values. define more if you like. 1050 * for host side, make sure both halves of ep1 are set up. 1051 */ 1052 1053 /* mode 0 - fits in 2KB */ 1054 static struct musb_fifo_cfg mode_0_cfg[] = { 1055 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1056 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1057 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1058 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1059 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1060 }; 1061 1062 /* mode 1 - fits in 4KB */ 1063 static struct musb_fifo_cfg mode_1_cfg[] = { 1064 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1065 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1066 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1067 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1068 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1069 }; 1070 1071 /* mode 2 - fits in 4KB */ 1072 static struct musb_fifo_cfg mode_2_cfg[] = { 1073 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1074 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1075 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1076 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1077 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1078 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1079 }; 1080 1081 /* mode 3 - fits in 4KB */ 1082 static struct musb_fifo_cfg mode_3_cfg[] = { 1083 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1084 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1085 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1086 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1087 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1088 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1089 }; 1090 1091 /* mode 4 - fits in 16KB */ 1092 static struct musb_fifo_cfg mode_4_cfg[] = { 1093 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1094 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1095 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1096 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1097 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1098 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1099 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1100 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1101 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1102 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1103 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1104 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1105 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1106 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1107 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1108 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1109 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1110 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1111 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1112 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1113 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1114 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1115 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1116 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1117 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1118 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1119 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1120 }; 1121 1122 /* mode 5 - fits in 8KB */ 1123 static struct musb_fifo_cfg mode_5_cfg[] = { 1124 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1125 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1126 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1127 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1128 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1129 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1130 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1131 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1132 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1133 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1134 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1135 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1136 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1137 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1138 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1139 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1140 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1141 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1142 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1143 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1144 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1145 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1146 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1147 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1148 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1149 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1150 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1151 }; 1152 1153 /* 1154 * configure a fifo; for non-shared endpoints, this may be called 1155 * once for a tx fifo and once for an rx fifo. 1156 * 1157 * returns negative errno or offset for next fifo. 1158 */ 1159 static int 1160 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1161 const struct musb_fifo_cfg *cfg, u16 offset) 1162 { 1163 void __iomem *mbase = musb->mregs; 1164 int size = 0; 1165 u16 maxpacket = cfg->maxpacket; 1166 u16 c_off = offset >> 3; 1167 u8 c_size; 1168 1169 /* expect hw_ep has already been zero-initialized */ 1170 1171 size = ffs(max(maxpacket, (u16) 8)) - 1; 1172 maxpacket = 1 << size; 1173 1174 c_size = size - 3; 1175 if (cfg->mode == BUF_DOUBLE) { 1176 if ((offset + (maxpacket << 1)) > 1177 (1 << (musb->config->ram_bits + 2))) 1178 return -EMSGSIZE; 1179 c_size |= MUSB_FIFOSZ_DPB; 1180 } else { 1181 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1182 return -EMSGSIZE; 1183 } 1184 1185 /* configure the FIFO */ 1186 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1187 1188 /* EP0 reserved endpoint for control, bidirectional; 1189 * EP1 reserved for bulk, two unidirectional halves. 1190 */ 1191 if (hw_ep->epnum == 1) 1192 musb->bulk_ep = hw_ep; 1193 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1194 switch (cfg->style) { 1195 case FIFO_TX: 1196 musb_write_txfifosz(mbase, c_size); 1197 musb_write_txfifoadd(mbase, c_off); 1198 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1199 hw_ep->max_packet_sz_tx = maxpacket; 1200 break; 1201 case FIFO_RX: 1202 musb_write_rxfifosz(mbase, c_size); 1203 musb_write_rxfifoadd(mbase, c_off); 1204 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1205 hw_ep->max_packet_sz_rx = maxpacket; 1206 break; 1207 case FIFO_RXTX: 1208 musb_write_txfifosz(mbase, c_size); 1209 musb_write_txfifoadd(mbase, c_off); 1210 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1211 hw_ep->max_packet_sz_rx = maxpacket; 1212 1213 musb_write_rxfifosz(mbase, c_size); 1214 musb_write_rxfifoadd(mbase, c_off); 1215 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1216 hw_ep->max_packet_sz_tx = maxpacket; 1217 1218 hw_ep->is_shared_fifo = true; 1219 break; 1220 } 1221 1222 /* NOTE rx and tx endpoint irqs aren't managed separately, 1223 * which happens to be ok 1224 */ 1225 musb->epmask |= (1 << hw_ep->epnum); 1226 1227 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1228 } 1229 1230 static struct musb_fifo_cfg ep0_cfg = { 1231 .style = FIFO_RXTX, .maxpacket = 64, 1232 }; 1233 1234 static int ep_config_from_table(struct musb *musb) 1235 { 1236 const struct musb_fifo_cfg *cfg; 1237 unsigned i, n; 1238 int offset; 1239 struct musb_hw_ep *hw_ep = musb->endpoints; 1240 1241 if (musb->config->fifo_cfg) { 1242 cfg = musb->config->fifo_cfg; 1243 n = musb->config->fifo_cfg_size; 1244 goto done; 1245 } 1246 1247 switch (fifo_mode) { 1248 default: 1249 fifo_mode = 0; 1250 /* FALLTHROUGH */ 1251 case 0: 1252 cfg = mode_0_cfg; 1253 n = ARRAY_SIZE(mode_0_cfg); 1254 break; 1255 case 1: 1256 cfg = mode_1_cfg; 1257 n = ARRAY_SIZE(mode_1_cfg); 1258 break; 1259 case 2: 1260 cfg = mode_2_cfg; 1261 n = ARRAY_SIZE(mode_2_cfg); 1262 break; 1263 case 3: 1264 cfg = mode_3_cfg; 1265 n = ARRAY_SIZE(mode_3_cfg); 1266 break; 1267 case 4: 1268 cfg = mode_4_cfg; 1269 n = ARRAY_SIZE(mode_4_cfg); 1270 break; 1271 case 5: 1272 cfg = mode_5_cfg; 1273 n = ARRAY_SIZE(mode_5_cfg); 1274 break; 1275 } 1276 1277 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1278 musb_driver_name, fifo_mode); 1279 1280 1281 done: 1282 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1283 /* assert(offset > 0) */ 1284 1285 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1286 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1287 */ 1288 1289 for (i = 0; i < n; i++) { 1290 u8 epn = cfg->hw_ep_num; 1291 1292 if (epn >= musb->config->num_eps) { 1293 pr_debug("%s: invalid ep %d\n", 1294 musb_driver_name, epn); 1295 return -EINVAL; 1296 } 1297 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1298 if (offset < 0) { 1299 pr_debug("%s: mem overrun, ep %d\n", 1300 musb_driver_name, epn); 1301 return offset; 1302 } 1303 epn++; 1304 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1305 } 1306 1307 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1308 musb_driver_name, 1309 n + 1, musb->config->num_eps * 2 - 1, 1310 offset, (1 << (musb->config->ram_bits + 2))); 1311 1312 if (!musb->bulk_ep) { 1313 pr_debug("%s: missing bulk\n", musb_driver_name); 1314 return -EINVAL; 1315 } 1316 1317 return 0; 1318 } 1319 1320 1321 /* 1322 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1323 * @param musb the controller 1324 */ 1325 static int ep_config_from_hw(struct musb *musb) 1326 { 1327 u8 epnum = 0; 1328 struct musb_hw_ep *hw_ep; 1329 void __iomem *mbase = musb->mregs; 1330 int ret = 0; 1331 1332 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1333 1334 /* FIXME pick up ep0 maxpacket size */ 1335 1336 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1337 musb_ep_select(mbase, epnum); 1338 hw_ep = musb->endpoints + epnum; 1339 1340 ret = musb_read_fifosize(musb, hw_ep, epnum); 1341 if (ret < 0) 1342 break; 1343 1344 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1345 1346 /* pick an RX/TX endpoint for bulk */ 1347 if (hw_ep->max_packet_sz_tx < 512 1348 || hw_ep->max_packet_sz_rx < 512) 1349 continue; 1350 1351 /* REVISIT: this algorithm is lazy, we should at least 1352 * try to pick a double buffered endpoint. 1353 */ 1354 if (musb->bulk_ep) 1355 continue; 1356 musb->bulk_ep = hw_ep; 1357 } 1358 1359 if (!musb->bulk_ep) { 1360 pr_debug("%s: missing bulk\n", musb_driver_name); 1361 return -EINVAL; 1362 } 1363 1364 return 0; 1365 } 1366 1367 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1368 1369 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1370 * configure endpoints, or take their config from silicon 1371 */ 1372 static int musb_core_init(u16 musb_type, struct musb *musb) 1373 { 1374 u8 reg; 1375 char *type; 1376 char aInfo[90], aRevision[32], aDate[12]; 1377 void __iomem *mbase = musb->mregs; 1378 int status = 0; 1379 int i; 1380 1381 /* log core options (read using indexed model) */ 1382 reg = musb_read_configdata(mbase); 1383 1384 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1385 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1386 strcat(aInfo, ", dyn FIFOs"); 1387 musb->dyn_fifo = true; 1388 } 1389 if (reg & MUSB_CONFIGDATA_MPRXE) { 1390 strcat(aInfo, ", bulk combine"); 1391 musb->bulk_combine = true; 1392 } 1393 if (reg & MUSB_CONFIGDATA_MPTXE) { 1394 strcat(aInfo, ", bulk split"); 1395 musb->bulk_split = true; 1396 } 1397 if (reg & MUSB_CONFIGDATA_HBRXE) { 1398 strcat(aInfo, ", HB-ISO Rx"); 1399 musb->hb_iso_rx = true; 1400 } 1401 if (reg & MUSB_CONFIGDATA_HBTXE) { 1402 strcat(aInfo, ", HB-ISO Tx"); 1403 musb->hb_iso_tx = true; 1404 } 1405 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1406 strcat(aInfo, ", SoftConn"); 1407 1408 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1409 musb_driver_name, reg, aInfo); 1410 1411 aDate[0] = 0; 1412 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1413 musb->is_multipoint = 1; 1414 type = "M"; 1415 } else { 1416 musb->is_multipoint = 0; 1417 type = ""; 1418 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1419 printk(KERN_ERR 1420 "%s: kernel must blacklist external hubs\n", 1421 musb_driver_name); 1422 #endif 1423 } 1424 1425 /* log release info */ 1426 musb->hwvers = musb_read_hwvers(mbase); 1427 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1428 MUSB_HWVERS_MINOR(musb->hwvers), 1429 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1430 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1431 musb_driver_name, type, aRevision, aDate); 1432 1433 /* configure ep0 */ 1434 musb_configure_ep0(musb); 1435 1436 /* discover endpoint configuration */ 1437 musb->nr_endpoints = 1; 1438 musb->epmask = 1; 1439 1440 if (musb->dyn_fifo) 1441 status = ep_config_from_table(musb); 1442 else 1443 status = ep_config_from_hw(musb); 1444 1445 if (status < 0) 1446 return status; 1447 1448 /* finish init, and print endpoint config */ 1449 for (i = 0; i < musb->nr_endpoints; i++) { 1450 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1451 1452 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1453 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1454 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1455 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1456 hw_ep->fifo_sync_va = 1457 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1458 1459 if (i == 0) 1460 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1461 else 1462 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1463 #endif 1464 1465 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1466 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1467 hw_ep->rx_reinit = 1; 1468 hw_ep->tx_reinit = 1; 1469 1470 if (hw_ep->max_packet_sz_tx) { 1471 dev_dbg(musb->controller, 1472 "%s: hw_ep %d%s, %smax %d\n", 1473 musb_driver_name, i, 1474 hw_ep->is_shared_fifo ? "shared" : "tx", 1475 hw_ep->tx_double_buffered 1476 ? "doublebuffer, " : "", 1477 hw_ep->max_packet_sz_tx); 1478 } 1479 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1480 dev_dbg(musb->controller, 1481 "%s: hw_ep %d%s, %smax %d\n", 1482 musb_driver_name, i, 1483 "rx", 1484 hw_ep->rx_double_buffered 1485 ? "doublebuffer, " : "", 1486 hw_ep->max_packet_sz_rx); 1487 } 1488 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1489 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1490 } 1491 1492 return 0; 1493 } 1494 1495 /*-------------------------------------------------------------------------*/ 1496 1497 /* 1498 * handle all the irqs defined by the HDRC core. for now we expect: other 1499 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1500 * will be assigned, and the irq will already have been acked. 1501 * 1502 * called in irq context with spinlock held, irqs blocked 1503 */ 1504 irqreturn_t musb_interrupt(struct musb *musb) 1505 { 1506 irqreturn_t retval = IRQ_NONE; 1507 u8 devctl; 1508 int ep_num; 1509 u32 reg; 1510 1511 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1512 1513 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1514 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1515 musb->int_usb, musb->int_tx, musb->int_rx); 1516 1517 /* the core can interrupt us for multiple reasons; docs have 1518 * a generic interrupt flowchart to follow 1519 */ 1520 if (musb->int_usb) 1521 retval |= musb_stage0_irq(musb, musb->int_usb, 1522 devctl); 1523 1524 /* "stage 1" is handling endpoint irqs */ 1525 1526 /* handle endpoint 0 first */ 1527 if (musb->int_tx & 1) { 1528 if (devctl & MUSB_DEVCTL_HM) 1529 retval |= musb_h_ep0_irq(musb); 1530 else 1531 retval |= musb_g_ep0_irq(musb); 1532 } 1533 1534 /* RX on endpoints 1-15 */ 1535 reg = musb->int_rx >> 1; 1536 ep_num = 1; 1537 while (reg) { 1538 if (reg & 1) { 1539 /* musb_ep_select(musb->mregs, ep_num); */ 1540 /* REVISIT just retval = ep->rx_irq(...) */ 1541 retval = IRQ_HANDLED; 1542 if (devctl & MUSB_DEVCTL_HM) 1543 musb_host_rx(musb, ep_num); 1544 else 1545 musb_g_rx(musb, ep_num); 1546 } 1547 1548 reg >>= 1; 1549 ep_num++; 1550 } 1551 1552 /* TX on endpoints 1-15 */ 1553 reg = musb->int_tx >> 1; 1554 ep_num = 1; 1555 while (reg) { 1556 if (reg & 1) { 1557 /* musb_ep_select(musb->mregs, ep_num); */ 1558 /* REVISIT just retval |= ep->tx_irq(...) */ 1559 retval = IRQ_HANDLED; 1560 if (devctl & MUSB_DEVCTL_HM) 1561 musb_host_tx(musb, ep_num); 1562 else 1563 musb_g_tx(musb, ep_num); 1564 } 1565 reg >>= 1; 1566 ep_num++; 1567 } 1568 1569 return retval; 1570 } 1571 EXPORT_SYMBOL_GPL(musb_interrupt); 1572 1573 #ifndef CONFIG_MUSB_PIO_ONLY 1574 static bool use_dma = 1; 1575 1576 /* "modprobe ... use_dma=0" etc */ 1577 module_param(use_dma, bool, 0); 1578 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1579 1580 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1581 { 1582 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1583 1584 /* called with controller lock already held */ 1585 1586 if (!epnum) { 1587 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1588 if (!is_cppi_enabled()) { 1589 /* endpoint 0 */ 1590 if (devctl & MUSB_DEVCTL_HM) 1591 musb_h_ep0_irq(musb); 1592 else 1593 musb_g_ep0_irq(musb); 1594 } 1595 #endif 1596 } else { 1597 /* endpoints 1..15 */ 1598 if (transmit) { 1599 if (devctl & MUSB_DEVCTL_HM) 1600 musb_host_tx(musb, epnum); 1601 else 1602 musb_g_tx(musb, epnum); 1603 } else { 1604 /* receive */ 1605 if (devctl & MUSB_DEVCTL_HM) 1606 musb_host_rx(musb, epnum); 1607 else 1608 musb_g_rx(musb, epnum); 1609 } 1610 } 1611 } 1612 EXPORT_SYMBOL_GPL(musb_dma_completion); 1613 1614 #else 1615 #define use_dma 0 1616 #endif 1617 1618 /*-------------------------------------------------------------------------*/ 1619 1620 static ssize_t 1621 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1622 { 1623 struct musb *musb = dev_to_musb(dev); 1624 unsigned long flags; 1625 int ret = -EINVAL; 1626 1627 spin_lock_irqsave(&musb->lock, flags); 1628 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state)); 1629 spin_unlock_irqrestore(&musb->lock, flags); 1630 1631 return ret; 1632 } 1633 1634 static ssize_t 1635 musb_mode_store(struct device *dev, struct device_attribute *attr, 1636 const char *buf, size_t n) 1637 { 1638 struct musb *musb = dev_to_musb(dev); 1639 unsigned long flags; 1640 int status; 1641 1642 spin_lock_irqsave(&musb->lock, flags); 1643 if (sysfs_streq(buf, "host")) 1644 status = musb_platform_set_mode(musb, MUSB_HOST); 1645 else if (sysfs_streq(buf, "peripheral")) 1646 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1647 else if (sysfs_streq(buf, "otg")) 1648 status = musb_platform_set_mode(musb, MUSB_OTG); 1649 else 1650 status = -EINVAL; 1651 spin_unlock_irqrestore(&musb->lock, flags); 1652 1653 return (status == 0) ? n : status; 1654 } 1655 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1656 1657 static ssize_t 1658 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1659 const char *buf, size_t n) 1660 { 1661 struct musb *musb = dev_to_musb(dev); 1662 unsigned long flags; 1663 unsigned long val; 1664 1665 if (sscanf(buf, "%lu", &val) < 1) { 1666 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1667 return -EINVAL; 1668 } 1669 1670 spin_lock_irqsave(&musb->lock, flags); 1671 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1672 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1673 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1674 musb->is_active = 0; 1675 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1676 spin_unlock_irqrestore(&musb->lock, flags); 1677 1678 return n; 1679 } 1680 1681 static ssize_t 1682 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1683 { 1684 struct musb *musb = dev_to_musb(dev); 1685 unsigned long flags; 1686 unsigned long val; 1687 int vbus; 1688 1689 spin_lock_irqsave(&musb->lock, flags); 1690 val = musb->a_wait_bcon; 1691 /* FIXME get_vbus_status() is normally #defined as false... 1692 * and is effectively TUSB-specific. 1693 */ 1694 vbus = musb_platform_get_vbus_status(musb); 1695 spin_unlock_irqrestore(&musb->lock, flags); 1696 1697 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1698 vbus ? "on" : "off", val); 1699 } 1700 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1701 1702 /* Gadget drivers can't know that a host is connected so they might want 1703 * to start SRP, but users can. This allows userspace to trigger SRP. 1704 */ 1705 static ssize_t 1706 musb_srp_store(struct device *dev, struct device_attribute *attr, 1707 const char *buf, size_t n) 1708 { 1709 struct musb *musb = dev_to_musb(dev); 1710 unsigned short srp; 1711 1712 if (sscanf(buf, "%hu", &srp) != 1 1713 || (srp != 1)) { 1714 dev_err(dev, "SRP: Value must be 1\n"); 1715 return -EINVAL; 1716 } 1717 1718 if (srp == 1) 1719 musb_g_wakeup(musb); 1720 1721 return n; 1722 } 1723 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1724 1725 static struct attribute *musb_attributes[] = { 1726 &dev_attr_mode.attr, 1727 &dev_attr_vbus.attr, 1728 &dev_attr_srp.attr, 1729 NULL 1730 }; 1731 1732 static const struct attribute_group musb_attr_group = { 1733 .attrs = musb_attributes, 1734 }; 1735 1736 /* Only used to provide driver mode change events */ 1737 static void musb_irq_work(struct work_struct *data) 1738 { 1739 struct musb *musb = container_of(data, struct musb, irq_work); 1740 1741 if (musb->xceiv->state != musb->xceiv_old_state) { 1742 musb->xceiv_old_state = musb->xceiv->state; 1743 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1744 } 1745 } 1746 1747 /* -------------------------------------------------------------------------- 1748 * Init support 1749 */ 1750 1751 static struct musb *allocate_instance(struct device *dev, 1752 struct musb_hdrc_config *config, void __iomem *mbase) 1753 { 1754 struct musb *musb; 1755 struct musb_hw_ep *ep; 1756 int epnum; 1757 int ret; 1758 1759 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); 1760 if (!musb) 1761 return NULL; 1762 1763 INIT_LIST_HEAD(&musb->control); 1764 INIT_LIST_HEAD(&musb->in_bulk); 1765 INIT_LIST_HEAD(&musb->out_bulk); 1766 1767 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1768 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1769 musb->mregs = mbase; 1770 musb->ctrl_base = mbase; 1771 musb->nIrq = -ENODEV; 1772 musb->config = config; 1773 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1774 for (epnum = 0, ep = musb->endpoints; 1775 epnum < musb->config->num_eps; 1776 epnum++, ep++) { 1777 ep->musb = musb; 1778 ep->epnum = epnum; 1779 } 1780 1781 musb->controller = dev; 1782 1783 ret = musb_host_alloc(musb); 1784 if (ret < 0) 1785 goto err_free; 1786 1787 dev_set_drvdata(dev, musb); 1788 1789 return musb; 1790 1791 err_free: 1792 return NULL; 1793 } 1794 1795 static void musb_free(struct musb *musb) 1796 { 1797 /* this has multiple entry modes. it handles fault cleanup after 1798 * probe(), where things may be partially set up, as well as rmmod 1799 * cleanup after everything's been de-activated. 1800 */ 1801 1802 #ifdef CONFIG_SYSFS 1803 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1804 #endif 1805 1806 if (musb->nIrq >= 0) { 1807 if (musb->irq_wake) 1808 disable_irq_wake(musb->nIrq); 1809 free_irq(musb->nIrq, musb); 1810 } 1811 1812 musb_host_free(musb); 1813 } 1814 1815 static void musb_deassert_reset(struct work_struct *work) 1816 { 1817 struct musb *musb; 1818 unsigned long flags; 1819 1820 musb = container_of(work, struct musb, deassert_reset_work.work); 1821 1822 spin_lock_irqsave(&musb->lock, flags); 1823 1824 if (musb->port1_status & USB_PORT_STAT_RESET) 1825 musb_port_reset(musb, false); 1826 1827 spin_unlock_irqrestore(&musb->lock, flags); 1828 } 1829 1830 /* 1831 * Perform generic per-controller initialization. 1832 * 1833 * @dev: the controller (already clocked, etc) 1834 * @nIrq: IRQ number 1835 * @ctrl: virtual address of controller registers, 1836 * not yet corrected for platform-specific offsets 1837 */ 1838 static int 1839 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1840 { 1841 int status; 1842 struct musb *musb; 1843 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 1844 1845 /* The driver might handle more features than the board; OK. 1846 * Fail when the board needs a feature that's not enabled. 1847 */ 1848 if (!plat) { 1849 dev_dbg(dev, "no platform_data?\n"); 1850 status = -ENODEV; 1851 goto fail0; 1852 } 1853 1854 /* allocate */ 1855 musb = allocate_instance(dev, plat->config, ctrl); 1856 if (!musb) { 1857 status = -ENOMEM; 1858 goto fail0; 1859 } 1860 1861 pm_runtime_use_autosuspend(musb->controller); 1862 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1863 pm_runtime_enable(musb->controller); 1864 1865 spin_lock_init(&musb->lock); 1866 musb->board_set_power = plat->set_power; 1867 musb->min_power = plat->min_power; 1868 musb->ops = plat->platform_ops; 1869 musb->port_mode = plat->mode; 1870 1871 /* The musb_platform_init() call: 1872 * - adjusts musb->mregs 1873 * - sets the musb->isr 1874 * - may initialize an integrated transceiver 1875 * - initializes musb->xceiv, usually by otg_get_phy() 1876 * - stops powering VBUS 1877 * 1878 * There are various transceiver configurations. Blackfin, 1879 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1880 * external/discrete ones in various flavors (twl4030 family, 1881 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1882 */ 1883 status = musb_platform_init(musb); 1884 if (status < 0) 1885 goto fail1; 1886 1887 if (!musb->isr) { 1888 status = -ENODEV; 1889 goto fail2; 1890 } 1891 1892 if (!musb->xceiv->io_ops) { 1893 musb->xceiv->io_dev = musb->controller; 1894 musb->xceiv->io_priv = musb->mregs; 1895 musb->xceiv->io_ops = &musb_ulpi_access; 1896 } 1897 1898 pm_runtime_get_sync(musb->controller); 1899 1900 if (use_dma && dev->dma_mask) { 1901 musb->dma_controller = dma_controller_create(musb, musb->mregs); 1902 if (IS_ERR(musb->dma_controller)) { 1903 status = PTR_ERR(musb->dma_controller); 1904 goto fail2_5; 1905 } 1906 } 1907 1908 /* be sure interrupts are disabled before connecting ISR */ 1909 musb_platform_disable(musb); 1910 musb_generic_disable(musb); 1911 1912 /* Init IRQ workqueue before request_irq */ 1913 INIT_WORK(&musb->irq_work, musb_irq_work); 1914 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); 1915 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); 1916 1917 /* setup musb parts of the core (especially endpoints) */ 1918 status = musb_core_init(plat->config->multipoint 1919 ? MUSB_CONTROLLER_MHDRC 1920 : MUSB_CONTROLLER_HDRC, musb); 1921 if (status < 0) 1922 goto fail3; 1923 1924 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1925 1926 /* attach to the IRQ */ 1927 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1928 dev_err(dev, "request_irq %d failed!\n", nIrq); 1929 status = -ENODEV; 1930 goto fail3; 1931 } 1932 musb->nIrq = nIrq; 1933 /* FIXME this handles wakeup irqs wrong */ 1934 if (enable_irq_wake(nIrq) == 0) { 1935 musb->irq_wake = 1; 1936 device_init_wakeup(dev, 1); 1937 } else { 1938 musb->irq_wake = 0; 1939 } 1940 1941 /* program PHY to use external vBus if required */ 1942 if (plat->extvbus) { 1943 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 1944 busctl |= MUSB_ULPI_USE_EXTVBUS; 1945 musb_write_ulpi_buscontrol(musb->mregs, busctl); 1946 } 1947 1948 if (musb->xceiv->otg->default_a) { 1949 MUSB_HST_MODE(musb); 1950 musb->xceiv->state = OTG_STATE_A_IDLE; 1951 } else { 1952 MUSB_DEV_MODE(musb); 1953 musb->xceiv->state = OTG_STATE_B_IDLE; 1954 } 1955 1956 switch (musb->port_mode) { 1957 case MUSB_PORT_MODE_HOST: 1958 status = musb_host_setup(musb, plat->power); 1959 if (status < 0) 1960 goto fail3; 1961 status = musb_platform_set_mode(musb, MUSB_HOST); 1962 break; 1963 case MUSB_PORT_MODE_GADGET: 1964 status = musb_gadget_setup(musb); 1965 if (status < 0) 1966 goto fail3; 1967 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1968 break; 1969 case MUSB_PORT_MODE_DUAL_ROLE: 1970 status = musb_host_setup(musb, plat->power); 1971 if (status < 0) 1972 goto fail3; 1973 status = musb_gadget_setup(musb); 1974 if (status) { 1975 musb_host_cleanup(musb); 1976 goto fail3; 1977 } 1978 status = musb_platform_set_mode(musb, MUSB_OTG); 1979 break; 1980 default: 1981 dev_err(dev, "unsupported port mode %d\n", musb->port_mode); 1982 break; 1983 } 1984 1985 if (status < 0) 1986 goto fail3; 1987 1988 status = musb_init_debugfs(musb); 1989 if (status < 0) 1990 goto fail4; 1991 1992 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 1993 if (status) 1994 goto fail5; 1995 1996 pm_runtime_put(musb->controller); 1997 1998 return 0; 1999 2000 fail5: 2001 musb_exit_debugfs(musb); 2002 2003 fail4: 2004 musb_gadget_cleanup(musb); 2005 musb_host_cleanup(musb); 2006 2007 fail3: 2008 cancel_work_sync(&musb->irq_work); 2009 cancel_delayed_work_sync(&musb->finish_resume_work); 2010 cancel_delayed_work_sync(&musb->deassert_reset_work); 2011 if (musb->dma_controller) 2012 dma_controller_destroy(musb->dma_controller); 2013 fail2_5: 2014 pm_runtime_put_sync(musb->controller); 2015 2016 fail2: 2017 if (musb->irq_wake) 2018 device_init_wakeup(dev, 0); 2019 musb_platform_exit(musb); 2020 2021 fail1: 2022 pm_runtime_disable(musb->controller); 2023 dev_err(musb->controller, 2024 "musb_init_controller failed with status %d\n", status); 2025 2026 musb_free(musb); 2027 2028 fail0: 2029 2030 return status; 2031 2032 } 2033 2034 /*-------------------------------------------------------------------------*/ 2035 2036 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2037 * bridge to a platform device; this driver then suffices. 2038 */ 2039 static int musb_probe(struct platform_device *pdev) 2040 { 2041 struct device *dev = &pdev->dev; 2042 int irq = platform_get_irq_byname(pdev, "mc"); 2043 struct resource *iomem; 2044 void __iomem *base; 2045 2046 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2047 if (!iomem || irq <= 0) 2048 return -ENODEV; 2049 2050 base = devm_ioremap_resource(dev, iomem); 2051 if (IS_ERR(base)) 2052 return PTR_ERR(base); 2053 2054 return musb_init_controller(dev, irq, base); 2055 } 2056 2057 static int musb_remove(struct platform_device *pdev) 2058 { 2059 struct device *dev = &pdev->dev; 2060 struct musb *musb = dev_to_musb(dev); 2061 2062 /* this gets called on rmmod. 2063 * - Host mode: host may still be active 2064 * - Peripheral mode: peripheral is deactivated (or never-activated) 2065 * - OTG mode: both roles are deactivated (or never-activated) 2066 */ 2067 musb_exit_debugfs(musb); 2068 musb_shutdown(pdev); 2069 2070 if (musb->dma_controller) 2071 dma_controller_destroy(musb->dma_controller); 2072 2073 cancel_work_sync(&musb->irq_work); 2074 cancel_delayed_work_sync(&musb->finish_resume_work); 2075 cancel_delayed_work_sync(&musb->deassert_reset_work); 2076 musb_free(musb); 2077 device_init_wakeup(dev, 0); 2078 return 0; 2079 } 2080 2081 #ifdef CONFIG_PM 2082 2083 static void musb_save_context(struct musb *musb) 2084 { 2085 int i; 2086 void __iomem *musb_base = musb->mregs; 2087 void __iomem *epio; 2088 2089 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2090 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2091 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2092 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2093 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2094 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2095 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2096 2097 for (i = 0; i < musb->config->num_eps; ++i) { 2098 struct musb_hw_ep *hw_ep; 2099 2100 hw_ep = &musb->endpoints[i]; 2101 if (!hw_ep) 2102 continue; 2103 2104 epio = hw_ep->regs; 2105 if (!epio) 2106 continue; 2107 2108 musb_writeb(musb_base, MUSB_INDEX, i); 2109 musb->context.index_regs[i].txmaxp = 2110 musb_readw(epio, MUSB_TXMAXP); 2111 musb->context.index_regs[i].txcsr = 2112 musb_readw(epio, MUSB_TXCSR); 2113 musb->context.index_regs[i].rxmaxp = 2114 musb_readw(epio, MUSB_RXMAXP); 2115 musb->context.index_regs[i].rxcsr = 2116 musb_readw(epio, MUSB_RXCSR); 2117 2118 if (musb->dyn_fifo) { 2119 musb->context.index_regs[i].txfifoadd = 2120 musb_read_txfifoadd(musb_base); 2121 musb->context.index_regs[i].rxfifoadd = 2122 musb_read_rxfifoadd(musb_base); 2123 musb->context.index_regs[i].txfifosz = 2124 musb_read_txfifosz(musb_base); 2125 musb->context.index_regs[i].rxfifosz = 2126 musb_read_rxfifosz(musb_base); 2127 } 2128 2129 musb->context.index_regs[i].txtype = 2130 musb_readb(epio, MUSB_TXTYPE); 2131 musb->context.index_regs[i].txinterval = 2132 musb_readb(epio, MUSB_TXINTERVAL); 2133 musb->context.index_regs[i].rxtype = 2134 musb_readb(epio, MUSB_RXTYPE); 2135 musb->context.index_regs[i].rxinterval = 2136 musb_readb(epio, MUSB_RXINTERVAL); 2137 2138 musb->context.index_regs[i].txfunaddr = 2139 musb_read_txfunaddr(musb_base, i); 2140 musb->context.index_regs[i].txhubaddr = 2141 musb_read_txhubaddr(musb_base, i); 2142 musb->context.index_regs[i].txhubport = 2143 musb_read_txhubport(musb_base, i); 2144 2145 musb->context.index_regs[i].rxfunaddr = 2146 musb_read_rxfunaddr(musb_base, i); 2147 musb->context.index_regs[i].rxhubaddr = 2148 musb_read_rxhubaddr(musb_base, i); 2149 musb->context.index_regs[i].rxhubport = 2150 musb_read_rxhubport(musb_base, i); 2151 } 2152 } 2153 2154 static void musb_restore_context(struct musb *musb) 2155 { 2156 int i; 2157 void __iomem *musb_base = musb->mregs; 2158 void __iomem *ep_target_regs; 2159 void __iomem *epio; 2160 2161 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2162 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2163 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2164 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2165 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); 2166 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); 2167 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2168 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2169 2170 for (i = 0; i < musb->config->num_eps; ++i) { 2171 struct musb_hw_ep *hw_ep; 2172 2173 hw_ep = &musb->endpoints[i]; 2174 if (!hw_ep) 2175 continue; 2176 2177 epio = hw_ep->regs; 2178 if (!epio) 2179 continue; 2180 2181 musb_writeb(musb_base, MUSB_INDEX, i); 2182 musb_writew(epio, MUSB_TXMAXP, 2183 musb->context.index_regs[i].txmaxp); 2184 musb_writew(epio, MUSB_TXCSR, 2185 musb->context.index_regs[i].txcsr); 2186 musb_writew(epio, MUSB_RXMAXP, 2187 musb->context.index_regs[i].rxmaxp); 2188 musb_writew(epio, MUSB_RXCSR, 2189 musb->context.index_regs[i].rxcsr); 2190 2191 if (musb->dyn_fifo) { 2192 musb_write_txfifosz(musb_base, 2193 musb->context.index_regs[i].txfifosz); 2194 musb_write_rxfifosz(musb_base, 2195 musb->context.index_regs[i].rxfifosz); 2196 musb_write_txfifoadd(musb_base, 2197 musb->context.index_regs[i].txfifoadd); 2198 musb_write_rxfifoadd(musb_base, 2199 musb->context.index_regs[i].rxfifoadd); 2200 } 2201 2202 musb_writeb(epio, MUSB_TXTYPE, 2203 musb->context.index_regs[i].txtype); 2204 musb_writeb(epio, MUSB_TXINTERVAL, 2205 musb->context.index_regs[i].txinterval); 2206 musb_writeb(epio, MUSB_RXTYPE, 2207 musb->context.index_regs[i].rxtype); 2208 musb_writeb(epio, MUSB_RXINTERVAL, 2209 2210 musb->context.index_regs[i].rxinterval); 2211 musb_write_txfunaddr(musb_base, i, 2212 musb->context.index_regs[i].txfunaddr); 2213 musb_write_txhubaddr(musb_base, i, 2214 musb->context.index_regs[i].txhubaddr); 2215 musb_write_txhubport(musb_base, i, 2216 musb->context.index_regs[i].txhubport); 2217 2218 ep_target_regs = 2219 musb_read_target_reg_base(i, musb_base); 2220 2221 musb_write_rxfunaddr(ep_target_regs, 2222 musb->context.index_regs[i].rxfunaddr); 2223 musb_write_rxhubaddr(ep_target_regs, 2224 musb->context.index_regs[i].rxhubaddr); 2225 musb_write_rxhubport(ep_target_regs, 2226 musb->context.index_regs[i].rxhubport); 2227 } 2228 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2229 } 2230 2231 static int musb_suspend(struct device *dev) 2232 { 2233 struct musb *musb = dev_to_musb(dev); 2234 unsigned long flags; 2235 2236 spin_lock_irqsave(&musb->lock, flags); 2237 2238 if (is_peripheral_active(musb)) { 2239 /* FIXME force disconnect unless we know USB will wake 2240 * the system up quickly enough to respond ... 2241 */ 2242 } else if (is_host_active(musb)) { 2243 /* we know all the children are suspended; sometimes 2244 * they will even be wakeup-enabled. 2245 */ 2246 } 2247 2248 musb_save_context(musb); 2249 2250 spin_unlock_irqrestore(&musb->lock, flags); 2251 return 0; 2252 } 2253 2254 static int musb_resume_noirq(struct device *dev) 2255 { 2256 struct musb *musb = dev_to_musb(dev); 2257 2258 /* 2259 * For static cmos like DaVinci, register values were preserved 2260 * unless for some reason the whole soc powered down or the USB 2261 * module got reset through the PSC (vs just being disabled). 2262 * 2263 * For the DSPS glue layer though, a full register restore has to 2264 * be done. As it shouldn't harm other platforms, we do it 2265 * unconditionally. 2266 */ 2267 2268 musb_restore_context(musb); 2269 2270 return 0; 2271 } 2272 2273 static int musb_runtime_suspend(struct device *dev) 2274 { 2275 struct musb *musb = dev_to_musb(dev); 2276 2277 musb_save_context(musb); 2278 2279 return 0; 2280 } 2281 2282 static int musb_runtime_resume(struct device *dev) 2283 { 2284 struct musb *musb = dev_to_musb(dev); 2285 static int first = 1; 2286 2287 /* 2288 * When pm_runtime_get_sync called for the first time in driver 2289 * init, some of the structure is still not initialized which is 2290 * used in restore function. But clock needs to be 2291 * enabled before any register access, so 2292 * pm_runtime_get_sync has to be called. 2293 * Also context restore without save does not make 2294 * any sense 2295 */ 2296 if (!first) 2297 musb_restore_context(musb); 2298 first = 0; 2299 2300 return 0; 2301 } 2302 2303 static const struct dev_pm_ops musb_dev_pm_ops = { 2304 .suspend = musb_suspend, 2305 .resume_noirq = musb_resume_noirq, 2306 .runtime_suspend = musb_runtime_suspend, 2307 .runtime_resume = musb_runtime_resume, 2308 }; 2309 2310 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2311 #else 2312 #define MUSB_DEV_PM_OPS NULL 2313 #endif 2314 2315 static struct platform_driver musb_driver = { 2316 .driver = { 2317 .name = (char *)musb_driver_name, 2318 .bus = &platform_bus_type, 2319 .owner = THIS_MODULE, 2320 .pm = MUSB_DEV_PM_OPS, 2321 }, 2322 .probe = musb_probe, 2323 .remove = musb_remove, 2324 .shutdown = musb_shutdown, 2325 }; 2326 2327 module_platform_driver(musb_driver); 2328