1 /* 2 * Texas Instruments DA8xx/OMAP-L1x "glue layer" 3 * 4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 5 * 6 * Based on the DaVinci "glue layer" code. 7 * Copyright (C) 2005-2006 by Texas Instruments 8 * 9 * DT support 10 * Copyright (c) 2016 Petr Kulhavy <petr@barix.com> 11 * 12 * This file is part of the Inventra Controller Driver for Linux. 13 * 14 * The Inventra Controller Driver for Linux is free software; you 15 * can redistribute it and/or modify it under the terms of the GNU 16 * General Public License version 2 as published by the Free Software 17 * Foundation. 18 * 19 * The Inventra Controller Driver for Linux is distributed in 20 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 21 * without even the implied warranty of MERCHANTABILITY or 22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 23 * License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with The Inventra Controller Driver for Linux ; if not, 27 * write to the Free Software Foundation, Inc., 59 Temple Place, 28 * Suite 330, Boston, MA 02111-1307 USA 29 * 30 */ 31 32 #include <linux/module.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/io.h> 36 #include <linux/of_platform.h> 37 #include <linux/phy/phy.h> 38 #include <linux/platform_device.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/usb/usb_phy_generic.h> 41 42 #include "musb_core.h" 43 44 /* 45 * DA8XX specific definitions 46 */ 47 48 /* USB 2.0 OTG module registers */ 49 #define DA8XX_USB_REVISION_REG 0x00 50 #define DA8XX_USB_CTRL_REG 0x04 51 #define DA8XX_USB_STAT_REG 0x08 52 #define DA8XX_USB_EMULATION_REG 0x0c 53 #define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */ 54 #define DA8XX_USB_AUTOREQ_REG 0x14 55 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18 56 #define DA8XX_USB_TEARDOWN_REG 0x1c 57 #define DA8XX_USB_INTR_SRC_REG 0x20 58 #define DA8XX_USB_INTR_SRC_SET_REG 0x24 59 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28 60 #define DA8XX_USB_INTR_MASK_REG 0x2c 61 #define DA8XX_USB_INTR_MASK_SET_REG 0x30 62 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34 63 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38 64 #define DA8XX_USB_END_OF_INTR_REG 0x3c 65 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2)) 66 67 /* Control register bits */ 68 #define DA8XX_SOFT_RESET_MASK 1 69 70 #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */ 71 #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */ 72 73 /* USB interrupt register bits */ 74 #define DA8XX_INTR_USB_SHIFT 16 75 #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */ 76 /* interrupts and DRVVBUS interrupt */ 77 #define DA8XX_INTR_DRVVBUS 0x100 78 #define DA8XX_INTR_RX_SHIFT 8 79 #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT) 80 #define DA8XX_INTR_TX_SHIFT 0 81 #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT) 82 83 #define DA8XX_MENTOR_CORE_OFFSET 0x400 84 85 struct da8xx_glue { 86 struct device *dev; 87 struct platform_device *musb; 88 struct platform_device *usb_phy; 89 struct clk *clk; 90 struct phy *phy; 91 }; 92 93 /* 94 * Because we don't set CTRL.UINT, it's "important" to: 95 * - not read/write INTRUSB/INTRUSBE (except during 96 * initial setup, as a workaround); 97 * - use INTSET/INTCLR instead. 98 */ 99 100 /** 101 * da8xx_musb_enable - enable interrupts 102 */ 103 static void da8xx_musb_enable(struct musb *musb) 104 { 105 void __iomem *reg_base = musb->ctrl_base; 106 u32 mask; 107 108 /* Workaround: setup IRQs through both register sets. */ 109 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) | 110 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) | 111 DA8XX_INTR_USB_MASK; 112 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); 113 114 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 115 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, 116 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT); 117 } 118 119 /** 120 * da8xx_musb_disable - disable HDRC and flush interrupts 121 */ 122 static void da8xx_musb_disable(struct musb *musb) 123 { 124 void __iomem *reg_base = musb->ctrl_base; 125 126 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, 127 DA8XX_INTR_USB_MASK | 128 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK); 129 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 130 } 131 132 #define portstate(stmt) stmt 133 134 static void da8xx_musb_set_vbus(struct musb *musb, int is_on) 135 { 136 WARN_ON(is_on && is_peripheral_active(musb)); 137 } 138 139 #define POLL_SECONDS 2 140 141 static struct timer_list otg_workaround; 142 143 static void otg_timer(unsigned long _musb) 144 { 145 struct musb *musb = (void *)_musb; 146 void __iomem *mregs = musb->mregs; 147 u8 devctl; 148 unsigned long flags; 149 150 /* 151 * We poll because DaVinci's won't expose several OTG-critical 152 * status change events (from the transceiver) otherwise. 153 */ 154 devctl = musb_readb(mregs, MUSB_DEVCTL); 155 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 156 usb_otg_state_string(musb->xceiv->otg->state)); 157 158 spin_lock_irqsave(&musb->lock, flags); 159 switch (musb->xceiv->otg->state) { 160 case OTG_STATE_A_WAIT_BCON: 161 devctl &= ~MUSB_DEVCTL_SESSION; 162 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 163 164 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 165 if (devctl & MUSB_DEVCTL_BDEVICE) { 166 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 167 MUSB_DEV_MODE(musb); 168 } else { 169 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 170 MUSB_HST_MODE(musb); 171 } 172 break; 173 case OTG_STATE_A_WAIT_VFALL: 174 /* 175 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3 176 * RTL seems to mis-handle session "start" otherwise (or in 177 * our case "recover"), in routine "VBUS was valid by the time 178 * VBUSERR got reported during enumeration" cases. 179 */ 180 if (devctl & MUSB_DEVCTL_VBUS) { 181 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 182 break; 183 } 184 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 185 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG, 186 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT); 187 break; 188 case OTG_STATE_B_IDLE: 189 /* 190 * There's no ID-changed IRQ, so we have no good way to tell 191 * when to switch to the A-Default state machine (by setting 192 * the DEVCTL.Session bit). 193 * 194 * Workaround: whenever we're in B_IDLE, try setting the 195 * session flag every few seconds. If it works, ID was 196 * grounded and we're now in the A-Default state machine. 197 * 198 * NOTE: setting the session flag is _supposed_ to trigger 199 * SRP but clearly it doesn't. 200 */ 201 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION); 202 devctl = musb_readb(mregs, MUSB_DEVCTL); 203 if (devctl & MUSB_DEVCTL_BDEVICE) 204 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 205 else 206 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 207 break; 208 default: 209 break; 210 } 211 spin_unlock_irqrestore(&musb->lock, flags); 212 } 213 214 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout) 215 { 216 static unsigned long last_timer; 217 218 if (timeout == 0) 219 timeout = jiffies + msecs_to_jiffies(3); 220 221 /* Never idle if active, or when VBUS timeout is not set as host */ 222 if (musb->is_active || (musb->a_wait_bcon == 0 && 223 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { 224 dev_dbg(musb->controller, "%s active, deleting timer\n", 225 usb_otg_state_string(musb->xceiv->otg->state)); 226 del_timer(&otg_workaround); 227 last_timer = jiffies; 228 return; 229 } 230 231 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 232 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); 233 return; 234 } 235 last_timer = timeout; 236 237 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 238 usb_otg_state_string(musb->xceiv->otg->state), 239 jiffies_to_msecs(timeout - jiffies)); 240 mod_timer(&otg_workaround, timeout); 241 } 242 243 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci) 244 { 245 struct musb *musb = hci; 246 void __iomem *reg_base = musb->ctrl_base; 247 struct usb_otg *otg = musb->xceiv->otg; 248 unsigned long flags; 249 irqreturn_t ret = IRQ_NONE; 250 u32 status; 251 252 spin_lock_irqsave(&musb->lock, flags); 253 254 /* 255 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through 256 * the Mentor registers (except for setup), use the TI ones and EOI. 257 */ 258 259 /* Acknowledge and handle non-CPPI interrupts */ 260 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); 261 if (!status) 262 goto eoi; 263 264 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); 265 dev_dbg(musb->controller, "USB IRQ %08x\n", status); 266 267 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT; 268 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT; 269 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT; 270 271 /* 272 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 273 * DA8xx's missing ID change IRQ. We need an ID change IRQ to 274 * switch appropriately between halves of the OTG state machine. 275 * Managing DEVCTL.Session per Mentor docs requires that we know its 276 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set. 277 * Also, DRVVBUS pulses for SRP (but not at 5 V)... 278 */ 279 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) { 280 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); 281 void __iomem *mregs = musb->mregs; 282 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 283 int err; 284 285 err = musb->int_usb & MUSB_INTR_VBUSERROR; 286 if (err) { 287 /* 288 * The Mentor core doesn't debounce VBUS as needed 289 * to cope with device connect current spikes. This 290 * means it's not uncommon for bus-powered devices 291 * to get VBUS errors during enumeration. 292 * 293 * This is a workaround, but newer RTL from Mentor 294 * seems to allow a better one: "re"-starting sessions 295 * without waiting for VBUS to stop registering in 296 * devctl. 297 */ 298 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 299 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 300 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 301 WARNING("VBUS error workaround (delay coming)\n"); 302 } else if (drvvbus) { 303 MUSB_HST_MODE(musb); 304 otg->default_a = 1; 305 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 306 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 307 del_timer(&otg_workaround); 308 } else { 309 musb->is_active = 0; 310 MUSB_DEV_MODE(musb); 311 otg->default_a = 0; 312 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 313 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 314 } 315 316 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 317 drvvbus ? "on" : "off", 318 usb_otg_state_string(musb->xceiv->otg->state), 319 err ? " ERROR" : "", 320 devctl); 321 ret = IRQ_HANDLED; 322 } 323 324 if (musb->int_tx || musb->int_rx || musb->int_usb) 325 ret |= musb_interrupt(musb); 326 327 eoi: 328 /* EOI needs to be written for the IRQ to be re-asserted. */ 329 if (ret == IRQ_HANDLED || status) 330 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 331 332 /* Poll for ID change */ 333 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) 334 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 335 336 spin_unlock_irqrestore(&musb->lock, flags); 337 338 return ret; 339 } 340 341 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode) 342 { 343 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 344 enum phy_mode phy_mode; 345 346 /* 347 * The PHY has some issues when it is forced in device or host mode. 348 * Unless the user request another mode, configure the PHY in OTG mode. 349 */ 350 if (!musb->is_initialized) 351 return phy_set_mode(glue->phy, PHY_MODE_USB_OTG); 352 353 switch (musb_mode) { 354 case MUSB_HOST: /* Force VBUS valid, ID = 0 */ 355 phy_mode = PHY_MODE_USB_HOST; 356 break; 357 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ 358 phy_mode = PHY_MODE_USB_DEVICE; 359 break; 360 case MUSB_OTG: /* Don't override the VBUS/ID comparators */ 361 phy_mode = PHY_MODE_USB_OTG; 362 break; 363 default: 364 return -EINVAL; 365 } 366 367 return phy_set_mode(glue->phy, phy_mode); 368 } 369 370 static int da8xx_musb_init(struct musb *musb) 371 { 372 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 373 void __iomem *reg_base = musb->ctrl_base; 374 u32 rev; 375 int ret = -ENODEV; 376 377 musb->mregs += DA8XX_MENTOR_CORE_OFFSET; 378 379 ret = clk_prepare_enable(glue->clk); 380 if (ret) { 381 dev_err(glue->dev, "failed to enable clock\n"); 382 return ret; 383 } 384 385 /* Returns zero if e.g. not clocked */ 386 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG); 387 if (!rev) 388 goto fail; 389 390 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 391 if (IS_ERR_OR_NULL(musb->xceiv)) { 392 ret = -EPROBE_DEFER; 393 goto fail; 394 } 395 396 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb); 397 398 /* Reset the controller */ 399 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); 400 401 /* Start the on-chip PHY and its PLL. */ 402 ret = phy_init(glue->phy); 403 if (ret) { 404 dev_err(glue->dev, "Failed to init phy.\n"); 405 goto fail; 406 } 407 408 ret = phy_power_on(glue->phy); 409 if (ret) { 410 dev_err(glue->dev, "Failed to power on phy.\n"); 411 goto err_phy_power_on; 412 } 413 414 msleep(5); 415 416 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ 417 pr_debug("DA8xx OTG revision %08x, control %02x\n", rev, 418 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); 419 420 musb->isr = da8xx_musb_interrupt; 421 return 0; 422 423 err_phy_power_on: 424 phy_exit(glue->phy); 425 fail: 426 clk_disable_unprepare(glue->clk); 427 return ret; 428 } 429 430 static int da8xx_musb_exit(struct musb *musb) 431 { 432 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 433 434 del_timer_sync(&otg_workaround); 435 436 phy_power_off(glue->phy); 437 phy_exit(glue->phy); 438 clk_disable_unprepare(glue->clk); 439 440 usb_put_phy(musb->xceiv); 441 442 return 0; 443 } 444 445 static inline u8 get_vbus_power(struct device *dev) 446 { 447 struct regulator *vbus_supply; 448 int current_uA; 449 450 vbus_supply = regulator_get_optional(dev, "vbus"); 451 if (IS_ERR(vbus_supply)) 452 return 255; 453 current_uA = regulator_get_current_limit(vbus_supply); 454 regulator_put(vbus_supply); 455 if (current_uA <= 0 || current_uA > 510000) 456 return 255; 457 return current_uA / 1000 / 2; 458 } 459 460 #ifdef CONFIG_USB_TI_CPPI41_DMA 461 static void da8xx_dma_controller_callback(struct dma_controller *c) 462 { 463 struct musb *musb = c->musb; 464 void __iomem *reg_base = musb->ctrl_base; 465 466 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 467 } 468 469 static struct dma_controller * 470 da8xx_dma_controller_create(struct musb *musb, void __iomem *base) 471 { 472 struct dma_controller *controller; 473 474 controller = cppi41_dma_controller_create(musb, base); 475 if (IS_ERR_OR_NULL(controller)) 476 return controller; 477 478 controller->dma_callback = da8xx_dma_controller_callback; 479 480 return controller; 481 } 482 #endif 483 484 static const struct musb_platform_ops da8xx_ops = { 485 .quirks = MUSB_INDEXED_EP | MUSB_PRESERVE_SESSION | 486 MUSB_DMA_CPPI41 | MUSB_DA8XX, 487 .init = da8xx_musb_init, 488 .exit = da8xx_musb_exit, 489 490 .fifo_mode = 2, 491 #ifdef CONFIG_USB_TI_CPPI41_DMA 492 .dma_init = da8xx_dma_controller_create, 493 .dma_exit = cppi41_dma_controller_destroy, 494 #endif 495 .enable = da8xx_musb_enable, 496 .disable = da8xx_musb_disable, 497 498 .set_mode = da8xx_musb_set_mode, 499 .try_idle = da8xx_musb_try_idle, 500 501 .set_vbus = da8xx_musb_set_vbus, 502 }; 503 504 static const struct platform_device_info da8xx_dev_info = { 505 .name = "musb-hdrc", 506 .id = PLATFORM_DEVID_AUTO, 507 .dma_mask = DMA_BIT_MASK(32), 508 }; 509 510 static const struct musb_hdrc_config da8xx_config = { 511 .ram_bits = 10, 512 .num_eps = 5, 513 .multipoint = 1, 514 }; 515 516 static struct of_dev_auxdata da8xx_auxdata_lookup[] = { 517 OF_DEV_AUXDATA("ti,da830-cppi41", 0x01e01000, "cppi41-dmaengine", 518 NULL), 519 {} 520 }; 521 522 static int da8xx_probe(struct platform_device *pdev) 523 { 524 struct resource musb_resources[2]; 525 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 526 struct da8xx_glue *glue; 527 struct platform_device_info pinfo; 528 struct clk *clk; 529 struct device_node *np = pdev->dev.of_node; 530 int ret; 531 532 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 533 if (!glue) 534 return -ENOMEM; 535 536 clk = devm_clk_get(&pdev->dev, "usb20"); 537 if (IS_ERR(clk)) { 538 dev_err(&pdev->dev, "failed to get clock\n"); 539 return PTR_ERR(clk); 540 } 541 542 glue->phy = devm_phy_get(&pdev->dev, "usb-phy"); 543 if (IS_ERR(glue->phy)) { 544 if (PTR_ERR(glue->phy) != -EPROBE_DEFER) 545 dev_err(&pdev->dev, "failed to get phy\n"); 546 return PTR_ERR(glue->phy); 547 } 548 549 glue->dev = &pdev->dev; 550 glue->clk = clk; 551 552 if (IS_ENABLED(CONFIG_OF) && np) { 553 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 554 if (!pdata) 555 return -ENOMEM; 556 557 pdata->config = &da8xx_config; 558 pdata->mode = musb_get_mode(&pdev->dev); 559 pdata->power = get_vbus_power(&pdev->dev); 560 } 561 562 pdata->platform_ops = &da8xx_ops; 563 564 glue->usb_phy = usb_phy_generic_register(); 565 ret = PTR_ERR_OR_ZERO(glue->usb_phy); 566 if (ret) { 567 dev_err(&pdev->dev, "failed to register usb_phy\n"); 568 return ret; 569 } 570 platform_set_drvdata(pdev, glue); 571 572 ret = of_platform_populate(pdev->dev.of_node, NULL, 573 da8xx_auxdata_lookup, &pdev->dev); 574 if (ret) 575 return ret; 576 577 memset(musb_resources, 0x00, sizeof(*musb_resources) * 578 ARRAY_SIZE(musb_resources)); 579 580 musb_resources[0].name = pdev->resource[0].name; 581 musb_resources[0].start = pdev->resource[0].start; 582 musb_resources[0].end = pdev->resource[0].end; 583 musb_resources[0].flags = pdev->resource[0].flags; 584 585 musb_resources[1].name = pdev->resource[1].name; 586 musb_resources[1].start = pdev->resource[1].start; 587 musb_resources[1].end = pdev->resource[1].end; 588 musb_resources[1].flags = pdev->resource[1].flags; 589 590 pinfo = da8xx_dev_info; 591 pinfo.parent = &pdev->dev; 592 pinfo.res = musb_resources; 593 pinfo.num_res = ARRAY_SIZE(musb_resources); 594 pinfo.data = pdata; 595 pinfo.size_data = sizeof(*pdata); 596 597 glue->musb = platform_device_register_full(&pinfo); 598 ret = PTR_ERR_OR_ZERO(glue->musb); 599 if (ret) { 600 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 601 usb_phy_generic_unregister(glue->usb_phy); 602 } 603 604 return ret; 605 } 606 607 static int da8xx_remove(struct platform_device *pdev) 608 { 609 struct da8xx_glue *glue = platform_get_drvdata(pdev); 610 611 platform_device_unregister(glue->musb); 612 usb_phy_generic_unregister(glue->usb_phy); 613 614 return 0; 615 } 616 617 #ifdef CONFIG_PM_SLEEP 618 static int da8xx_suspend(struct device *dev) 619 { 620 int ret; 621 struct da8xx_glue *glue = dev_get_drvdata(dev); 622 623 ret = phy_power_off(glue->phy); 624 if (ret) 625 return ret; 626 clk_disable_unprepare(glue->clk); 627 628 return 0; 629 } 630 631 static int da8xx_resume(struct device *dev) 632 { 633 int ret; 634 struct da8xx_glue *glue = dev_get_drvdata(dev); 635 636 ret = clk_prepare_enable(glue->clk); 637 if (ret) 638 return ret; 639 return phy_power_on(glue->phy); 640 } 641 #endif 642 643 static SIMPLE_DEV_PM_OPS(da8xx_pm_ops, da8xx_suspend, da8xx_resume); 644 645 #ifdef CONFIG_OF 646 static const struct of_device_id da8xx_id_table[] = { 647 { 648 .compatible = "ti,da830-musb", 649 }, 650 {}, 651 }; 652 MODULE_DEVICE_TABLE(of, da8xx_id_table); 653 #endif 654 655 static struct platform_driver da8xx_driver = { 656 .probe = da8xx_probe, 657 .remove = da8xx_remove, 658 .driver = { 659 .name = "musb-da8xx", 660 .pm = &da8xx_pm_ops, 661 .of_match_table = of_match_ptr(da8xx_id_table), 662 }, 663 }; 664 665 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer"); 666 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>"); 667 MODULE_LICENSE("GPL v2"); 668 module_platform_driver(da8xx_driver); 669