1 /* 2 * Texas Instruments DA8xx/OMAP-L1x "glue layer" 3 * 4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 5 * 6 * Based on the DaVinci "glue layer" code. 7 * Copyright (C) 2005-2006 by Texas Instruments 8 * 9 * DT support 10 * Copyright (c) 2016 Petr Kulhavy <petr@barix.com> 11 * 12 * This file is part of the Inventra Controller Driver for Linux. 13 * 14 * The Inventra Controller Driver for Linux is free software; you 15 * can redistribute it and/or modify it under the terms of the GNU 16 * General Public License version 2 as published by the Free Software 17 * Foundation. 18 * 19 * The Inventra Controller Driver for Linux is distributed in 20 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 21 * without even the implied warranty of MERCHANTABILITY or 22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 23 * License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with The Inventra Controller Driver for Linux ; if not, 27 * write to the Free Software Foundation, Inc., 59 Temple Place, 28 * Suite 330, Boston, MA 02111-1307 USA 29 * 30 */ 31 32 #include <linux/module.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/io.h> 36 #include <linux/phy/phy.h> 37 #include <linux/platform_device.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/usb/usb_phy_generic.h> 40 41 #include "musb_core.h" 42 43 /* 44 * DA8XX specific definitions 45 */ 46 47 /* USB 2.0 OTG module registers */ 48 #define DA8XX_USB_REVISION_REG 0x00 49 #define DA8XX_USB_CTRL_REG 0x04 50 #define DA8XX_USB_STAT_REG 0x08 51 #define DA8XX_USB_EMULATION_REG 0x0c 52 #define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */ 53 #define DA8XX_USB_AUTOREQ_REG 0x14 54 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18 55 #define DA8XX_USB_TEARDOWN_REG 0x1c 56 #define DA8XX_USB_INTR_SRC_REG 0x20 57 #define DA8XX_USB_INTR_SRC_SET_REG 0x24 58 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28 59 #define DA8XX_USB_INTR_MASK_REG 0x2c 60 #define DA8XX_USB_INTR_MASK_SET_REG 0x30 61 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34 62 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38 63 #define DA8XX_USB_END_OF_INTR_REG 0x3c 64 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2)) 65 66 /* Control register bits */ 67 #define DA8XX_SOFT_RESET_MASK 1 68 69 #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */ 70 #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */ 71 72 /* USB interrupt register bits */ 73 #define DA8XX_INTR_USB_SHIFT 16 74 #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */ 75 /* interrupts and DRVVBUS interrupt */ 76 #define DA8XX_INTR_DRVVBUS 0x100 77 #define DA8XX_INTR_RX_SHIFT 8 78 #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT) 79 #define DA8XX_INTR_TX_SHIFT 0 80 #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT) 81 82 #define DA8XX_MENTOR_CORE_OFFSET 0x400 83 84 struct da8xx_glue { 85 struct device *dev; 86 struct platform_device *musb; 87 struct platform_device *usb_phy; 88 struct clk *clk; 89 struct phy *phy; 90 }; 91 92 /* 93 * Because we don't set CTRL.UINT, it's "important" to: 94 * - not read/write INTRUSB/INTRUSBE (except during 95 * initial setup, as a workaround); 96 * - use INTSET/INTCLR instead. 97 */ 98 99 /** 100 * da8xx_musb_enable - enable interrupts 101 */ 102 static void da8xx_musb_enable(struct musb *musb) 103 { 104 void __iomem *reg_base = musb->ctrl_base; 105 u32 mask; 106 107 /* Workaround: setup IRQs through both register sets. */ 108 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) | 109 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) | 110 DA8XX_INTR_USB_MASK; 111 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); 112 113 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 114 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, 115 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT); 116 } 117 118 /** 119 * da8xx_musb_disable - disable HDRC and flush interrupts 120 */ 121 static void da8xx_musb_disable(struct musb *musb) 122 { 123 void __iomem *reg_base = musb->ctrl_base; 124 125 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, 126 DA8XX_INTR_USB_MASK | 127 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK); 128 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 129 } 130 131 #define portstate(stmt) stmt 132 133 static void da8xx_musb_set_vbus(struct musb *musb, int is_on) 134 { 135 WARN_ON(is_on && is_peripheral_active(musb)); 136 } 137 138 #define POLL_SECONDS 2 139 140 static struct timer_list otg_workaround; 141 142 static void otg_timer(unsigned long _musb) 143 { 144 struct musb *musb = (void *)_musb; 145 void __iomem *mregs = musb->mregs; 146 u8 devctl; 147 unsigned long flags; 148 149 /* 150 * We poll because DaVinci's won't expose several OTG-critical 151 * status change events (from the transceiver) otherwise. 152 */ 153 devctl = musb_readb(mregs, MUSB_DEVCTL); 154 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 155 usb_otg_state_string(musb->xceiv->otg->state)); 156 157 spin_lock_irqsave(&musb->lock, flags); 158 switch (musb->xceiv->otg->state) { 159 case OTG_STATE_A_WAIT_BCON: 160 devctl &= ~MUSB_DEVCTL_SESSION; 161 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 162 163 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 164 if (devctl & MUSB_DEVCTL_BDEVICE) { 165 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 166 MUSB_DEV_MODE(musb); 167 } else { 168 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 169 MUSB_HST_MODE(musb); 170 } 171 break; 172 case OTG_STATE_A_WAIT_VFALL: 173 /* 174 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3 175 * RTL seems to mis-handle session "start" otherwise (or in 176 * our case "recover"), in routine "VBUS was valid by the time 177 * VBUSERR got reported during enumeration" cases. 178 */ 179 if (devctl & MUSB_DEVCTL_VBUS) { 180 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 181 break; 182 } 183 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 184 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG, 185 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT); 186 break; 187 case OTG_STATE_B_IDLE: 188 /* 189 * There's no ID-changed IRQ, so we have no good way to tell 190 * when to switch to the A-Default state machine (by setting 191 * the DEVCTL.Session bit). 192 * 193 * Workaround: whenever we're in B_IDLE, try setting the 194 * session flag every few seconds. If it works, ID was 195 * grounded and we're now in the A-Default state machine. 196 * 197 * NOTE: setting the session flag is _supposed_ to trigger 198 * SRP but clearly it doesn't. 199 */ 200 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION); 201 devctl = musb_readb(mregs, MUSB_DEVCTL); 202 if (devctl & MUSB_DEVCTL_BDEVICE) 203 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 204 else 205 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 206 break; 207 default: 208 break; 209 } 210 spin_unlock_irqrestore(&musb->lock, flags); 211 } 212 213 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout) 214 { 215 static unsigned long last_timer; 216 217 if (timeout == 0) 218 timeout = jiffies + msecs_to_jiffies(3); 219 220 /* Never idle if active, or when VBUS timeout is not set as host */ 221 if (musb->is_active || (musb->a_wait_bcon == 0 && 222 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { 223 dev_dbg(musb->controller, "%s active, deleting timer\n", 224 usb_otg_state_string(musb->xceiv->otg->state)); 225 del_timer(&otg_workaround); 226 last_timer = jiffies; 227 return; 228 } 229 230 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 231 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); 232 return; 233 } 234 last_timer = timeout; 235 236 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 237 usb_otg_state_string(musb->xceiv->otg->state), 238 jiffies_to_msecs(timeout - jiffies)); 239 mod_timer(&otg_workaround, timeout); 240 } 241 242 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci) 243 { 244 struct musb *musb = hci; 245 void __iomem *reg_base = musb->ctrl_base; 246 struct usb_otg *otg = musb->xceiv->otg; 247 unsigned long flags; 248 irqreturn_t ret = IRQ_NONE; 249 u32 status; 250 251 spin_lock_irqsave(&musb->lock, flags); 252 253 /* 254 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through 255 * the Mentor registers (except for setup), use the TI ones and EOI. 256 */ 257 258 /* Acknowledge and handle non-CPPI interrupts */ 259 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); 260 if (!status) 261 goto eoi; 262 263 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); 264 dev_dbg(musb->controller, "USB IRQ %08x\n", status); 265 266 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT; 267 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT; 268 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT; 269 270 /* 271 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 272 * DA8xx's missing ID change IRQ. We need an ID change IRQ to 273 * switch appropriately between halves of the OTG state machine. 274 * Managing DEVCTL.Session per Mentor docs requires that we know its 275 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set. 276 * Also, DRVVBUS pulses for SRP (but not at 5 V)... 277 */ 278 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) { 279 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); 280 void __iomem *mregs = musb->mregs; 281 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 282 int err; 283 284 err = musb->int_usb & MUSB_INTR_VBUSERROR; 285 if (err) { 286 /* 287 * The Mentor core doesn't debounce VBUS as needed 288 * to cope with device connect current spikes. This 289 * means it's not uncommon for bus-powered devices 290 * to get VBUS errors during enumeration. 291 * 292 * This is a workaround, but newer RTL from Mentor 293 * seems to allow a better one: "re"-starting sessions 294 * without waiting for VBUS to stop registering in 295 * devctl. 296 */ 297 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 298 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 299 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 300 WARNING("VBUS error workaround (delay coming)\n"); 301 } else if (drvvbus) { 302 MUSB_HST_MODE(musb); 303 otg->default_a = 1; 304 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 305 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 306 del_timer(&otg_workaround); 307 } else { 308 musb->is_active = 0; 309 MUSB_DEV_MODE(musb); 310 otg->default_a = 0; 311 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 312 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 313 } 314 315 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 316 drvvbus ? "on" : "off", 317 usb_otg_state_string(musb->xceiv->otg->state), 318 err ? " ERROR" : "", 319 devctl); 320 ret = IRQ_HANDLED; 321 } 322 323 if (musb->int_tx || musb->int_rx || musb->int_usb) 324 ret |= musb_interrupt(musb); 325 326 eoi: 327 /* EOI needs to be written for the IRQ to be re-asserted. */ 328 if (ret == IRQ_HANDLED || status) 329 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 330 331 /* Poll for ID change */ 332 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) 333 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 334 335 spin_unlock_irqrestore(&musb->lock, flags); 336 337 return ret; 338 } 339 340 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode) 341 { 342 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 343 enum phy_mode phy_mode; 344 345 /* 346 * The PHY has some issues when it is forced in device or host mode. 347 * Unless the user request another mode, configure the PHY in OTG mode. 348 */ 349 if (!musb->is_initialized) 350 return phy_set_mode(glue->phy, PHY_MODE_USB_OTG); 351 352 switch (musb_mode) { 353 case MUSB_HOST: /* Force VBUS valid, ID = 0 */ 354 phy_mode = PHY_MODE_USB_HOST; 355 break; 356 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ 357 phy_mode = PHY_MODE_USB_DEVICE; 358 break; 359 case MUSB_OTG: /* Don't override the VBUS/ID comparators */ 360 phy_mode = PHY_MODE_USB_OTG; 361 break; 362 default: 363 return -EINVAL; 364 } 365 366 return phy_set_mode(glue->phy, phy_mode); 367 } 368 369 static int da8xx_musb_init(struct musb *musb) 370 { 371 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 372 void __iomem *reg_base = musb->ctrl_base; 373 u32 rev; 374 int ret = -ENODEV; 375 376 musb->mregs += DA8XX_MENTOR_CORE_OFFSET; 377 378 ret = clk_prepare_enable(glue->clk); 379 if (ret) { 380 dev_err(glue->dev, "failed to enable clock\n"); 381 return ret; 382 } 383 384 /* Returns zero if e.g. not clocked */ 385 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG); 386 if (!rev) 387 goto fail; 388 389 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 390 if (IS_ERR_OR_NULL(musb->xceiv)) { 391 ret = -EPROBE_DEFER; 392 goto fail; 393 } 394 395 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb); 396 397 /* Reset the controller */ 398 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); 399 400 /* Start the on-chip PHY and its PLL. */ 401 ret = phy_init(glue->phy); 402 if (ret) { 403 dev_err(glue->dev, "Failed to init phy.\n"); 404 goto fail; 405 } 406 407 ret = phy_power_on(glue->phy); 408 if (ret) { 409 dev_err(glue->dev, "Failed to power on phy.\n"); 410 goto err_phy_power_on; 411 } 412 413 msleep(5); 414 415 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ 416 pr_debug("DA8xx OTG revision %08x, control %02x\n", rev, 417 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); 418 419 musb->isr = da8xx_musb_interrupt; 420 return 0; 421 422 err_phy_power_on: 423 phy_exit(glue->phy); 424 fail: 425 clk_disable_unprepare(glue->clk); 426 return ret; 427 } 428 429 static int da8xx_musb_exit(struct musb *musb) 430 { 431 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 432 433 del_timer_sync(&otg_workaround); 434 435 phy_power_off(glue->phy); 436 phy_exit(glue->phy); 437 clk_disable_unprepare(glue->clk); 438 439 usb_put_phy(musb->xceiv); 440 441 return 0; 442 } 443 444 static inline u8 get_vbus_power(struct device *dev) 445 { 446 struct regulator *vbus_supply; 447 int current_uA; 448 449 vbus_supply = regulator_get_optional(dev, "vbus"); 450 if (IS_ERR(vbus_supply)) 451 return 255; 452 current_uA = regulator_get_current_limit(vbus_supply); 453 regulator_put(vbus_supply); 454 if (current_uA <= 0 || current_uA > 510000) 455 return 255; 456 return current_uA / 1000 / 2; 457 } 458 459 static const struct musb_platform_ops da8xx_ops = { 460 .quirks = MUSB_INDEXED_EP | MUSB_PRESERVE_SESSION, 461 .init = da8xx_musb_init, 462 .exit = da8xx_musb_exit, 463 464 .fifo_mode = 2, 465 .enable = da8xx_musb_enable, 466 .disable = da8xx_musb_disable, 467 468 .set_mode = da8xx_musb_set_mode, 469 .try_idle = da8xx_musb_try_idle, 470 471 .set_vbus = da8xx_musb_set_vbus, 472 }; 473 474 static const struct platform_device_info da8xx_dev_info = { 475 .name = "musb-hdrc", 476 .id = PLATFORM_DEVID_AUTO, 477 .dma_mask = DMA_BIT_MASK(32), 478 }; 479 480 static const struct musb_hdrc_config da8xx_config = { 481 .ram_bits = 10, 482 .num_eps = 5, 483 .multipoint = 1, 484 }; 485 486 static int da8xx_probe(struct platform_device *pdev) 487 { 488 struct resource musb_resources[2]; 489 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 490 struct da8xx_glue *glue; 491 struct platform_device_info pinfo; 492 struct clk *clk; 493 struct device_node *np = pdev->dev.of_node; 494 int ret; 495 496 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 497 if (!glue) 498 return -ENOMEM; 499 500 clk = devm_clk_get(&pdev->dev, "usb20"); 501 if (IS_ERR(clk)) { 502 dev_err(&pdev->dev, "failed to get clock\n"); 503 return PTR_ERR(clk); 504 } 505 506 glue->phy = devm_phy_get(&pdev->dev, "usb-phy"); 507 if (IS_ERR(glue->phy)) { 508 if (PTR_ERR(glue->phy) != -EPROBE_DEFER) 509 dev_err(&pdev->dev, "failed to get phy\n"); 510 return PTR_ERR(glue->phy); 511 } 512 513 glue->dev = &pdev->dev; 514 glue->clk = clk; 515 516 if (IS_ENABLED(CONFIG_OF) && np) { 517 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 518 if (!pdata) 519 return -ENOMEM; 520 521 pdata->config = &da8xx_config; 522 pdata->mode = musb_get_mode(&pdev->dev); 523 pdata->power = get_vbus_power(&pdev->dev); 524 } 525 526 pdata->platform_ops = &da8xx_ops; 527 528 glue->usb_phy = usb_phy_generic_register(); 529 ret = PTR_ERR_OR_ZERO(glue->usb_phy); 530 if (ret) { 531 dev_err(&pdev->dev, "failed to register usb_phy\n"); 532 return ret; 533 } 534 platform_set_drvdata(pdev, glue); 535 536 memset(musb_resources, 0x00, sizeof(*musb_resources) * 537 ARRAY_SIZE(musb_resources)); 538 539 musb_resources[0].name = pdev->resource[0].name; 540 musb_resources[0].start = pdev->resource[0].start; 541 musb_resources[0].end = pdev->resource[0].end; 542 musb_resources[0].flags = pdev->resource[0].flags; 543 544 musb_resources[1].name = pdev->resource[1].name; 545 musb_resources[1].start = pdev->resource[1].start; 546 musb_resources[1].end = pdev->resource[1].end; 547 musb_resources[1].flags = pdev->resource[1].flags; 548 549 pinfo = da8xx_dev_info; 550 pinfo.parent = &pdev->dev; 551 pinfo.res = musb_resources; 552 pinfo.num_res = ARRAY_SIZE(musb_resources); 553 pinfo.data = pdata; 554 pinfo.size_data = sizeof(*pdata); 555 556 glue->musb = platform_device_register_full(&pinfo); 557 ret = PTR_ERR_OR_ZERO(glue->musb); 558 if (ret) { 559 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 560 usb_phy_generic_unregister(glue->usb_phy); 561 } 562 563 return ret; 564 } 565 566 static int da8xx_remove(struct platform_device *pdev) 567 { 568 struct da8xx_glue *glue = platform_get_drvdata(pdev); 569 570 platform_device_unregister(glue->musb); 571 usb_phy_generic_unregister(glue->usb_phy); 572 573 return 0; 574 } 575 576 #ifdef CONFIG_PM_SLEEP 577 static int da8xx_suspend(struct device *dev) 578 { 579 int ret; 580 struct da8xx_glue *glue = dev_get_drvdata(dev); 581 582 ret = phy_power_off(glue->phy); 583 if (ret) 584 return ret; 585 clk_disable_unprepare(glue->clk); 586 587 return 0; 588 } 589 590 static int da8xx_resume(struct device *dev) 591 { 592 int ret; 593 struct da8xx_glue *glue = dev_get_drvdata(dev); 594 595 ret = clk_prepare_enable(glue->clk); 596 if (ret) 597 return ret; 598 return phy_power_on(glue->phy); 599 } 600 #endif 601 602 static SIMPLE_DEV_PM_OPS(da8xx_pm_ops, da8xx_suspend, da8xx_resume); 603 604 #ifdef CONFIG_OF 605 static const struct of_device_id da8xx_id_table[] = { 606 { 607 .compatible = "ti,da830-musb", 608 }, 609 {}, 610 }; 611 MODULE_DEVICE_TABLE(of, da8xx_id_table); 612 #endif 613 614 static struct platform_driver da8xx_driver = { 615 .probe = da8xx_probe, 616 .remove = da8xx_remove, 617 .driver = { 618 .name = "musb-da8xx", 619 .pm = &da8xx_pm_ops, 620 .of_match_table = of_match_ptr(da8xx_id_table), 621 }, 622 }; 623 624 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer"); 625 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>"); 626 MODULE_LICENSE("GPL v2"); 627 module_platform_driver(da8xx_driver); 628