1 /* 2 * Texas Instruments DA8xx/OMAP-L1x "glue layer" 3 * 4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 5 * 6 * Based on the DaVinci "glue layer" code. 7 * Copyright (C) 2005-2006 by Texas Instruments 8 * 9 * This file is part of the Inventra Controller Driver for Linux. 10 * 11 * The Inventra Controller Driver for Linux is free software; you 12 * can redistribute it and/or modify it under the terms of the GNU 13 * General Public License version 2 as published by the Free Software 14 * Foundation. 15 * 16 * The Inventra Controller Driver for Linux is distributed in 17 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 18 * without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 * License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with The Inventra Controller Driver for Linux ; if not, 24 * write to the Free Software Foundation, Inc., 59 Temple Place, 25 * Suite 330, Boston, MA 02111-1307 USA 26 * 27 */ 28 29 #include <linux/module.h> 30 #include <linux/clk.h> 31 #include <linux/err.h> 32 #include <linux/io.h> 33 #include <linux/phy/phy.h> 34 #include <linux/platform_device.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/usb/usb_phy_generic.h> 37 38 #include "musb_core.h" 39 40 /* 41 * DA8XX specific definitions 42 */ 43 44 /* USB 2.0 OTG module registers */ 45 #define DA8XX_USB_REVISION_REG 0x00 46 #define DA8XX_USB_CTRL_REG 0x04 47 #define DA8XX_USB_STAT_REG 0x08 48 #define DA8XX_USB_EMULATION_REG 0x0c 49 #define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */ 50 #define DA8XX_USB_AUTOREQ_REG 0x14 51 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18 52 #define DA8XX_USB_TEARDOWN_REG 0x1c 53 #define DA8XX_USB_INTR_SRC_REG 0x20 54 #define DA8XX_USB_INTR_SRC_SET_REG 0x24 55 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28 56 #define DA8XX_USB_INTR_MASK_REG 0x2c 57 #define DA8XX_USB_INTR_MASK_SET_REG 0x30 58 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34 59 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38 60 #define DA8XX_USB_END_OF_INTR_REG 0x3c 61 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2)) 62 63 /* Control register bits */ 64 #define DA8XX_SOFT_RESET_MASK 1 65 66 #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */ 67 #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */ 68 69 /* USB interrupt register bits */ 70 #define DA8XX_INTR_USB_SHIFT 16 71 #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */ 72 /* interrupts and DRVVBUS interrupt */ 73 #define DA8XX_INTR_DRVVBUS 0x100 74 #define DA8XX_INTR_RX_SHIFT 8 75 #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT) 76 #define DA8XX_INTR_TX_SHIFT 0 77 #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT) 78 79 #define DA8XX_MENTOR_CORE_OFFSET 0x400 80 81 struct da8xx_glue { 82 struct device *dev; 83 struct platform_device *musb; 84 struct platform_device *usb_phy; 85 struct clk *clk; 86 struct phy *phy; 87 }; 88 89 /* 90 * Because we don't set CTRL.UINT, it's "important" to: 91 * - not read/write INTRUSB/INTRUSBE (except during 92 * initial setup, as a workaround); 93 * - use INTSET/INTCLR instead. 94 */ 95 96 /** 97 * da8xx_musb_enable - enable interrupts 98 */ 99 static void da8xx_musb_enable(struct musb *musb) 100 { 101 void __iomem *reg_base = musb->ctrl_base; 102 u32 mask; 103 104 /* Workaround: setup IRQs through both register sets. */ 105 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) | 106 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) | 107 DA8XX_INTR_USB_MASK; 108 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); 109 110 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 111 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, 112 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT); 113 } 114 115 /** 116 * da8xx_musb_disable - disable HDRC and flush interrupts 117 */ 118 static void da8xx_musb_disable(struct musb *musb) 119 { 120 void __iomem *reg_base = musb->ctrl_base; 121 122 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, 123 DA8XX_INTR_USB_MASK | 124 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK); 125 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 126 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 127 } 128 129 #define portstate(stmt) stmt 130 131 static void da8xx_musb_set_vbus(struct musb *musb, int is_on) 132 { 133 WARN_ON(is_on && is_peripheral_active(musb)); 134 } 135 136 #define POLL_SECONDS 2 137 138 static struct timer_list otg_workaround; 139 140 static void otg_timer(unsigned long _musb) 141 { 142 struct musb *musb = (void *)_musb; 143 void __iomem *mregs = musb->mregs; 144 u8 devctl; 145 unsigned long flags; 146 147 /* 148 * We poll because DaVinci's won't expose several OTG-critical 149 * status change events (from the transceiver) otherwise. 150 */ 151 devctl = musb_readb(mregs, MUSB_DEVCTL); 152 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 153 usb_otg_state_string(musb->xceiv->otg->state)); 154 155 spin_lock_irqsave(&musb->lock, flags); 156 switch (musb->xceiv->otg->state) { 157 case OTG_STATE_A_WAIT_BCON: 158 devctl &= ~MUSB_DEVCTL_SESSION; 159 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 160 161 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 162 if (devctl & MUSB_DEVCTL_BDEVICE) { 163 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 164 MUSB_DEV_MODE(musb); 165 } else { 166 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 167 MUSB_HST_MODE(musb); 168 } 169 break; 170 case OTG_STATE_A_WAIT_VFALL: 171 /* 172 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3 173 * RTL seems to mis-handle session "start" otherwise (or in 174 * our case "recover"), in routine "VBUS was valid by the time 175 * VBUSERR got reported during enumeration" cases. 176 */ 177 if (devctl & MUSB_DEVCTL_VBUS) { 178 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 179 break; 180 } 181 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 182 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG, 183 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT); 184 break; 185 case OTG_STATE_B_IDLE: 186 /* 187 * There's no ID-changed IRQ, so we have no good way to tell 188 * when to switch to the A-Default state machine (by setting 189 * the DEVCTL.Session bit). 190 * 191 * Workaround: whenever we're in B_IDLE, try setting the 192 * session flag every few seconds. If it works, ID was 193 * grounded and we're now in the A-Default state machine. 194 * 195 * NOTE: setting the session flag is _supposed_ to trigger 196 * SRP but clearly it doesn't. 197 */ 198 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION); 199 devctl = musb_readb(mregs, MUSB_DEVCTL); 200 if (devctl & MUSB_DEVCTL_BDEVICE) 201 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 202 else 203 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 204 break; 205 default: 206 break; 207 } 208 spin_unlock_irqrestore(&musb->lock, flags); 209 } 210 211 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout) 212 { 213 static unsigned long last_timer; 214 215 if (timeout == 0) 216 timeout = jiffies + msecs_to_jiffies(3); 217 218 /* Never idle if active, or when VBUS timeout is not set as host */ 219 if (musb->is_active || (musb->a_wait_bcon == 0 && 220 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { 221 dev_dbg(musb->controller, "%s active, deleting timer\n", 222 usb_otg_state_string(musb->xceiv->otg->state)); 223 del_timer(&otg_workaround); 224 last_timer = jiffies; 225 return; 226 } 227 228 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 229 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); 230 return; 231 } 232 last_timer = timeout; 233 234 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 235 usb_otg_state_string(musb->xceiv->otg->state), 236 jiffies_to_msecs(timeout - jiffies)); 237 mod_timer(&otg_workaround, timeout); 238 } 239 240 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci) 241 { 242 struct musb *musb = hci; 243 void __iomem *reg_base = musb->ctrl_base; 244 struct usb_otg *otg = musb->xceiv->otg; 245 unsigned long flags; 246 irqreturn_t ret = IRQ_NONE; 247 u32 status; 248 249 spin_lock_irqsave(&musb->lock, flags); 250 251 /* 252 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through 253 * the Mentor registers (except for setup), use the TI ones and EOI. 254 */ 255 256 /* Acknowledge and handle non-CPPI interrupts */ 257 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); 258 if (!status) 259 goto eoi; 260 261 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); 262 dev_dbg(musb->controller, "USB IRQ %08x\n", status); 263 264 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT; 265 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT; 266 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT; 267 268 /* 269 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 270 * DA8xx's missing ID change IRQ. We need an ID change IRQ to 271 * switch appropriately between halves of the OTG state machine. 272 * Managing DEVCTL.Session per Mentor docs requires that we know its 273 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set. 274 * Also, DRVVBUS pulses for SRP (but not at 5 V)... 275 */ 276 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) { 277 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); 278 void __iomem *mregs = musb->mregs; 279 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 280 int err; 281 282 err = musb->int_usb & MUSB_INTR_VBUSERROR; 283 if (err) { 284 /* 285 * The Mentor core doesn't debounce VBUS as needed 286 * to cope with device connect current spikes. This 287 * means it's not uncommon for bus-powered devices 288 * to get VBUS errors during enumeration. 289 * 290 * This is a workaround, but newer RTL from Mentor 291 * seems to allow a better one: "re"-starting sessions 292 * without waiting for VBUS to stop registering in 293 * devctl. 294 */ 295 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 296 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 297 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 298 WARNING("VBUS error workaround (delay coming)\n"); 299 } else if (drvvbus) { 300 MUSB_HST_MODE(musb); 301 otg->default_a = 1; 302 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 303 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 304 del_timer(&otg_workaround); 305 } else { 306 musb->is_active = 0; 307 MUSB_DEV_MODE(musb); 308 otg->default_a = 0; 309 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 310 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 311 } 312 313 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 314 drvvbus ? "on" : "off", 315 usb_otg_state_string(musb->xceiv->otg->state), 316 err ? " ERROR" : "", 317 devctl); 318 ret = IRQ_HANDLED; 319 } 320 321 if (musb->int_tx || musb->int_rx || musb->int_usb) 322 ret |= musb_interrupt(musb); 323 324 eoi: 325 /* EOI needs to be written for the IRQ to be re-asserted. */ 326 if (ret == IRQ_HANDLED || status) 327 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 328 329 /* Poll for ID change */ 330 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) 331 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 332 333 spin_unlock_irqrestore(&musb->lock, flags); 334 335 return ret; 336 } 337 338 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode) 339 { 340 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 341 enum phy_mode phy_mode; 342 343 switch (musb_mode) { 344 case MUSB_HOST: /* Force VBUS valid, ID = 0 */ 345 phy_mode = PHY_MODE_USB_HOST; 346 break; 347 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ 348 phy_mode = PHY_MODE_USB_DEVICE; 349 break; 350 case MUSB_OTG: /* Don't override the VBUS/ID comparators */ 351 phy_mode = PHY_MODE_USB_OTG; 352 break; 353 default: 354 return -EINVAL; 355 } 356 357 return phy_set_mode(glue->phy, phy_mode); 358 } 359 360 static int da8xx_musb_init(struct musb *musb) 361 { 362 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 363 void __iomem *reg_base = musb->ctrl_base; 364 u32 rev; 365 int ret = -ENODEV; 366 367 musb->mregs += DA8XX_MENTOR_CORE_OFFSET; 368 369 /* Returns zero if e.g. not clocked */ 370 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG); 371 if (!rev) 372 goto fail; 373 374 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 375 if (IS_ERR_OR_NULL(musb->xceiv)) { 376 ret = -EPROBE_DEFER; 377 goto fail; 378 } 379 380 ret = clk_prepare_enable(glue->clk); 381 if (ret) { 382 dev_err(glue->dev, "failed to enable clock\n"); 383 goto fail; 384 } 385 386 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb); 387 388 /* Reset the controller */ 389 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); 390 391 /* Start the on-chip PHY and its PLL. */ 392 ret = phy_init(glue->phy); 393 if (ret) { 394 dev_err(glue->dev, "Failed to init phy.\n"); 395 goto err_phy_init; 396 } 397 398 ret = phy_power_on(glue->phy); 399 if (ret) { 400 dev_err(glue->dev, "Failed to power on phy.\n"); 401 goto err_phy_power_on; 402 } 403 404 msleep(5); 405 406 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ 407 pr_debug("DA8xx OTG revision %08x, control %02x\n", rev, 408 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); 409 410 musb->isr = da8xx_musb_interrupt; 411 return 0; 412 413 err_phy_power_on: 414 phy_exit(glue->phy); 415 err_phy_init: 416 clk_disable_unprepare(glue->clk); 417 fail: 418 return ret; 419 } 420 421 static int da8xx_musb_exit(struct musb *musb) 422 { 423 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 424 425 del_timer_sync(&otg_workaround); 426 427 phy_power_off(glue->phy); 428 phy_exit(glue->phy); 429 clk_disable_unprepare(glue->clk); 430 431 usb_put_phy(musb->xceiv); 432 433 return 0; 434 } 435 436 static const struct musb_platform_ops da8xx_ops = { 437 .quirks = MUSB_DMA_CPPI | MUSB_INDEXED_EP, 438 .init = da8xx_musb_init, 439 .exit = da8xx_musb_exit, 440 441 .fifo_mode = 2, 442 #ifdef CONFIG_USB_TI_CPPI_DMA 443 .dma_init = cppi_dma_controller_create, 444 .dma_exit = cppi_dma_controller_destroy, 445 #endif 446 .enable = da8xx_musb_enable, 447 .disable = da8xx_musb_disable, 448 449 .set_mode = da8xx_musb_set_mode, 450 .try_idle = da8xx_musb_try_idle, 451 452 .set_vbus = da8xx_musb_set_vbus, 453 }; 454 455 static const struct platform_device_info da8xx_dev_info = { 456 .name = "musb-hdrc", 457 .id = PLATFORM_DEVID_AUTO, 458 .dma_mask = DMA_BIT_MASK(32), 459 }; 460 461 static int da8xx_probe(struct platform_device *pdev) 462 { 463 struct resource musb_resources[2]; 464 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 465 struct da8xx_glue *glue; 466 struct platform_device_info pinfo; 467 struct clk *clk; 468 int ret; 469 470 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 471 if (!glue) 472 return -ENOMEM; 473 474 clk = devm_clk_get(&pdev->dev, "usb20"); 475 if (IS_ERR(clk)) { 476 dev_err(&pdev->dev, "failed to get clock\n"); 477 return PTR_ERR(clk); 478 } 479 480 glue->phy = devm_phy_get(&pdev->dev, "usb-phy"); 481 if (IS_ERR(glue->phy)) { 482 dev_err(&pdev->dev, "failed to get phy\n"); 483 return PTR_ERR(glue->phy); 484 } 485 486 glue->dev = &pdev->dev; 487 glue->clk = clk; 488 489 pdata->platform_ops = &da8xx_ops; 490 491 glue->usb_phy = usb_phy_generic_register(); 492 ret = PTR_ERR_OR_ZERO(glue->usb_phy); 493 if (ret) { 494 dev_err(&pdev->dev, "failed to register usb_phy\n"); 495 return ret; 496 } 497 platform_set_drvdata(pdev, glue); 498 499 memset(musb_resources, 0x00, sizeof(*musb_resources) * 500 ARRAY_SIZE(musb_resources)); 501 502 musb_resources[0].name = pdev->resource[0].name; 503 musb_resources[0].start = pdev->resource[0].start; 504 musb_resources[0].end = pdev->resource[0].end; 505 musb_resources[0].flags = pdev->resource[0].flags; 506 507 musb_resources[1].name = pdev->resource[1].name; 508 musb_resources[1].start = pdev->resource[1].start; 509 musb_resources[1].end = pdev->resource[1].end; 510 musb_resources[1].flags = pdev->resource[1].flags; 511 512 pinfo = da8xx_dev_info; 513 pinfo.parent = &pdev->dev; 514 pinfo.res = musb_resources; 515 pinfo.num_res = ARRAY_SIZE(musb_resources); 516 pinfo.data = pdata; 517 pinfo.size_data = sizeof(*pdata); 518 519 glue->musb = platform_device_register_full(&pinfo); 520 ret = PTR_ERR_OR_ZERO(glue->musb); 521 if (ret) { 522 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 523 usb_phy_generic_unregister(glue->usb_phy); 524 } 525 526 return ret; 527 } 528 529 static int da8xx_remove(struct platform_device *pdev) 530 { 531 struct da8xx_glue *glue = platform_get_drvdata(pdev); 532 533 platform_device_unregister(glue->musb); 534 usb_phy_generic_unregister(glue->usb_phy); 535 536 return 0; 537 } 538 539 static struct platform_driver da8xx_driver = { 540 .probe = da8xx_probe, 541 .remove = da8xx_remove, 542 .driver = { 543 .name = "musb-da8xx", 544 }, 545 }; 546 547 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer"); 548 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>"); 549 MODULE_LICENSE("GPL v2"); 550 module_platform_driver(da8xx_driver); 551