1 /* 2 * Texas Instruments DA8xx/OMAP-L1x "glue layer" 3 * 4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 5 * 6 * Based on the DaVinci "glue layer" code. 7 * Copyright (C) 2005-2006 by Texas Instruments 8 * 9 * This file is part of the Inventra Controller Driver for Linux. 10 * 11 * The Inventra Controller Driver for Linux is free software; you 12 * can redistribute it and/or modify it under the terms of the GNU 13 * General Public License version 2 as published by the Free Software 14 * Foundation. 15 * 16 * The Inventra Controller Driver for Linux is distributed in 17 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 18 * without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 * License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with The Inventra Controller Driver for Linux ; if not, 24 * write to the Free Software Foundation, Inc., 59 Temple Place, 25 * Suite 330, Boston, MA 02111-1307 USA 26 * 27 */ 28 29 #include <linux/init.h> 30 #include <linux/clk.h> 31 #include <linux/io.h> 32 #include <linux/platform_device.h> 33 #include <linux/dma-mapping.h> 34 35 #include <mach/da8xx.h> 36 #include <mach/usb.h> 37 38 #include "musb_core.h" 39 40 /* 41 * DA8XX specific definitions 42 */ 43 44 /* USB 2.0 OTG module registers */ 45 #define DA8XX_USB_REVISION_REG 0x00 46 #define DA8XX_USB_CTRL_REG 0x04 47 #define DA8XX_USB_STAT_REG 0x08 48 #define DA8XX_USB_EMULATION_REG 0x0c 49 #define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */ 50 #define DA8XX_USB_AUTOREQ_REG 0x14 51 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18 52 #define DA8XX_USB_TEARDOWN_REG 0x1c 53 #define DA8XX_USB_INTR_SRC_REG 0x20 54 #define DA8XX_USB_INTR_SRC_SET_REG 0x24 55 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28 56 #define DA8XX_USB_INTR_MASK_REG 0x2c 57 #define DA8XX_USB_INTR_MASK_SET_REG 0x30 58 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34 59 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38 60 #define DA8XX_USB_END_OF_INTR_REG 0x3c 61 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2)) 62 63 /* Control register bits */ 64 #define DA8XX_SOFT_RESET_MASK 1 65 66 #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */ 67 #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */ 68 69 /* USB interrupt register bits */ 70 #define DA8XX_INTR_USB_SHIFT 16 71 #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */ 72 /* interrupts and DRVVBUS interrupt */ 73 #define DA8XX_INTR_DRVVBUS 0x100 74 #define DA8XX_INTR_RX_SHIFT 8 75 #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT) 76 #define DA8XX_INTR_TX_SHIFT 0 77 #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT) 78 79 #define DA8XX_MENTOR_CORE_OFFSET 0x400 80 81 #define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG) 82 83 struct da8xx_glue { 84 struct device *dev; 85 struct platform_device *musb; 86 struct clk *clk; 87 }; 88 89 /* 90 * REVISIT (PM): we should be able to keep the PHY in low power mode most 91 * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0 92 * and, when in host mode, autosuspending idle root ports... PHY_PLLON 93 * (overriding SUSPENDM?) then likely needs to stay off. 94 */ 95 96 static inline void phy_on(void) 97 { 98 u32 cfgchip2 = __raw_readl(CFGCHIP2); 99 100 /* 101 * Start the on-chip PHY and its PLL. 102 */ 103 cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN); 104 cfgchip2 |= CFGCHIP2_PHY_PLLON; 105 __raw_writel(cfgchip2, CFGCHIP2); 106 107 pr_info("Waiting for USB PHY clock good...\n"); 108 while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD)) 109 cpu_relax(); 110 } 111 112 static inline void phy_off(void) 113 { 114 u32 cfgchip2 = __raw_readl(CFGCHIP2); 115 116 /* 117 * Ensure that USB 1.1 reference clock is not being sourced from 118 * USB 2.0 PHY. Otherwise do not power down the PHY. 119 */ 120 if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) && 121 (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) { 122 pr_warning("USB 1.1 clocked from USB 2.0 PHY -- " 123 "can't power it down\n"); 124 return; 125 } 126 127 /* 128 * Power down the on-chip PHY. 129 */ 130 cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN; 131 __raw_writel(cfgchip2, CFGCHIP2); 132 } 133 134 /* 135 * Because we don't set CTRL.UINT, it's "important" to: 136 * - not read/write INTRUSB/INTRUSBE (except during 137 * initial setup, as a workaround); 138 * - use INTSET/INTCLR instead. 139 */ 140 141 /** 142 * da8xx_musb_enable - enable interrupts 143 */ 144 static void da8xx_musb_enable(struct musb *musb) 145 { 146 void __iomem *reg_base = musb->ctrl_base; 147 u32 mask; 148 149 /* Workaround: setup IRQs through both register sets. */ 150 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) | 151 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) | 152 DA8XX_INTR_USB_MASK; 153 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); 154 155 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 156 if (is_otg_enabled(musb)) 157 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, 158 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT); 159 } 160 161 /** 162 * da8xx_musb_disable - disable HDRC and flush interrupts 163 */ 164 static void da8xx_musb_disable(struct musb *musb) 165 { 166 void __iomem *reg_base = musb->ctrl_base; 167 168 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, 169 DA8XX_INTR_USB_MASK | 170 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK); 171 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 172 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 173 } 174 175 #ifdef CONFIG_USB_MUSB_HDRC_HCD 176 #define portstate(stmt) stmt 177 #else 178 #define portstate(stmt) 179 #endif 180 181 static void da8xx_musb_set_vbus(struct musb *musb, int is_on) 182 { 183 WARN_ON(is_on && is_peripheral_active(musb)); 184 } 185 186 #define POLL_SECONDS 2 187 188 static struct timer_list otg_workaround; 189 190 static void otg_timer(unsigned long _musb) 191 { 192 struct musb *musb = (void *)_musb; 193 void __iomem *mregs = musb->mregs; 194 u8 devctl; 195 unsigned long flags; 196 197 /* 198 * We poll because DaVinci's won't expose several OTG-critical 199 * status change events (from the transceiver) otherwise. 200 */ 201 devctl = musb_readb(mregs, MUSB_DEVCTL); 202 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); 203 204 spin_lock_irqsave(&musb->lock, flags); 205 switch (musb->xceiv->state) { 206 case OTG_STATE_A_WAIT_BCON: 207 devctl &= ~MUSB_DEVCTL_SESSION; 208 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 209 210 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 211 if (devctl & MUSB_DEVCTL_BDEVICE) { 212 musb->xceiv->state = OTG_STATE_B_IDLE; 213 MUSB_DEV_MODE(musb); 214 } else { 215 musb->xceiv->state = OTG_STATE_A_IDLE; 216 MUSB_HST_MODE(musb); 217 } 218 break; 219 case OTG_STATE_A_WAIT_VFALL: 220 /* 221 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3 222 * RTL seems to mis-handle session "start" otherwise (or in 223 * our case "recover"), in routine "VBUS was valid by the time 224 * VBUSERR got reported during enumeration" cases. 225 */ 226 if (devctl & MUSB_DEVCTL_VBUS) { 227 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 228 break; 229 } 230 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 231 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG, 232 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT); 233 break; 234 case OTG_STATE_B_IDLE: 235 if (!is_peripheral_enabled(musb)) 236 break; 237 238 /* 239 * There's no ID-changed IRQ, so we have no good way to tell 240 * when to switch to the A-Default state machine (by setting 241 * the DEVCTL.Session bit). 242 * 243 * Workaround: whenever we're in B_IDLE, try setting the 244 * session flag every few seconds. If it works, ID was 245 * grounded and we're now in the A-Default state machine. 246 * 247 * NOTE: setting the session flag is _supposed_ to trigger 248 * SRP but clearly it doesn't. 249 */ 250 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION); 251 devctl = musb_readb(mregs, MUSB_DEVCTL); 252 if (devctl & MUSB_DEVCTL_BDEVICE) 253 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 254 else 255 musb->xceiv->state = OTG_STATE_A_IDLE; 256 break; 257 default: 258 break; 259 } 260 spin_unlock_irqrestore(&musb->lock, flags); 261 } 262 263 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout) 264 { 265 static unsigned long last_timer; 266 267 if (!is_otg_enabled(musb)) 268 return; 269 270 if (timeout == 0) 271 timeout = jiffies + msecs_to_jiffies(3); 272 273 /* Never idle if active, or when VBUS timeout is not set as host */ 274 if (musb->is_active || (musb->a_wait_bcon == 0 && 275 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 276 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 277 del_timer(&otg_workaround); 278 last_timer = jiffies; 279 return; 280 } 281 282 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 283 DBG(4, "Longer idle timer already pending, ignoring...\n"); 284 return; 285 } 286 last_timer = timeout; 287 288 DBG(4, "%s inactive, starting idle timer for %u ms\n", 289 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies)); 290 mod_timer(&otg_workaround, timeout); 291 } 292 293 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci) 294 { 295 struct musb *musb = hci; 296 void __iomem *reg_base = musb->ctrl_base; 297 unsigned long flags; 298 irqreturn_t ret = IRQ_NONE; 299 u32 status; 300 301 spin_lock_irqsave(&musb->lock, flags); 302 303 /* 304 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through 305 * the Mentor registers (except for setup), use the TI ones and EOI. 306 */ 307 308 /* Acknowledge and handle non-CPPI interrupts */ 309 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); 310 if (!status) 311 goto eoi; 312 313 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); 314 DBG(4, "USB IRQ %08x\n", status); 315 316 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT; 317 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT; 318 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT; 319 320 /* 321 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 322 * DA8xx's missing ID change IRQ. We need an ID change IRQ to 323 * switch appropriately between halves of the OTG state machine. 324 * Managing DEVCTL.Session per Mentor docs requires that we know its 325 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set. 326 * Also, DRVVBUS pulses for SRP (but not at 5 V)... 327 */ 328 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) { 329 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); 330 void __iomem *mregs = musb->mregs; 331 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 332 int err; 333 334 err = is_host_enabled(musb) && (musb->int_usb & 335 MUSB_INTR_VBUSERROR); 336 if (err) { 337 /* 338 * The Mentor core doesn't debounce VBUS as needed 339 * to cope with device connect current spikes. This 340 * means it's not uncommon for bus-powered devices 341 * to get VBUS errors during enumeration. 342 * 343 * This is a workaround, but newer RTL from Mentor 344 * seems to allow a better one: "re"-starting sessions 345 * without waiting for VBUS to stop registering in 346 * devctl. 347 */ 348 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 349 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 350 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 351 WARNING("VBUS error workaround (delay coming)\n"); 352 } else if (is_host_enabled(musb) && drvvbus) { 353 MUSB_HST_MODE(musb); 354 musb->xceiv->default_a = 1; 355 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 356 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 357 del_timer(&otg_workaround); 358 } else { 359 musb->is_active = 0; 360 MUSB_DEV_MODE(musb); 361 musb->xceiv->default_a = 0; 362 musb->xceiv->state = OTG_STATE_B_IDLE; 363 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 364 } 365 366 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 367 drvvbus ? "on" : "off", 368 otg_state_string(musb), 369 err ? " ERROR" : "", 370 devctl); 371 ret = IRQ_HANDLED; 372 } 373 374 if (musb->int_tx || musb->int_rx || musb->int_usb) 375 ret |= musb_interrupt(musb); 376 377 eoi: 378 /* EOI needs to be written for the IRQ to be re-asserted. */ 379 if (ret == IRQ_HANDLED || status) 380 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 381 382 /* Poll for ID change */ 383 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) 384 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 385 386 spin_unlock_irqrestore(&musb->lock, flags); 387 388 return ret; 389 } 390 391 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode) 392 { 393 u32 cfgchip2 = __raw_readl(CFGCHIP2); 394 395 cfgchip2 &= ~CFGCHIP2_OTGMODE; 396 switch (musb_mode) { 397 #ifdef CONFIG_USB_MUSB_HDRC_HCD 398 case MUSB_HOST: /* Force VBUS valid, ID = 0 */ 399 cfgchip2 |= CFGCHIP2_FORCE_HOST; 400 break; 401 #endif 402 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 403 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ 404 cfgchip2 |= CFGCHIP2_FORCE_DEVICE; 405 break; 406 #endif 407 #ifdef CONFIG_USB_MUSB_OTG 408 case MUSB_OTG: /* Don't override the VBUS/ID comparators */ 409 cfgchip2 |= CFGCHIP2_NO_OVERRIDE; 410 break; 411 #endif 412 default: 413 DBG(2, "Trying to set unsupported mode %u\n", musb_mode); 414 } 415 416 __raw_writel(cfgchip2, CFGCHIP2); 417 return 0; 418 } 419 420 static int da8xx_musb_init(struct musb *musb) 421 { 422 void __iomem *reg_base = musb->ctrl_base; 423 u32 rev; 424 425 musb->mregs += DA8XX_MENTOR_CORE_OFFSET; 426 427 /* Returns zero if e.g. not clocked */ 428 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG); 429 if (!rev) 430 goto fail; 431 432 usb_nop_xceiv_register(); 433 musb->xceiv = otg_get_transceiver(); 434 if (!musb->xceiv) 435 goto fail; 436 437 if (is_host_enabled(musb)) 438 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb); 439 440 /* Reset the controller */ 441 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); 442 443 /* Start the on-chip PHY and its PLL. */ 444 phy_on(); 445 446 msleep(5); 447 448 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ 449 pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n", 450 rev, __raw_readl(CFGCHIP2), 451 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); 452 453 musb->isr = da8xx_musb_interrupt; 454 return 0; 455 fail: 456 return -ENODEV; 457 } 458 459 static int da8xx_musb_exit(struct musb *musb) 460 { 461 if (is_host_enabled(musb)) 462 del_timer_sync(&otg_workaround); 463 464 phy_off(); 465 466 otg_put_transceiver(musb->xceiv); 467 usb_nop_xceiv_unregister(); 468 469 return 0; 470 } 471 472 static const struct musb_platform_ops da8xx_ops = { 473 .init = da8xx_musb_init, 474 .exit = da8xx_musb_exit, 475 476 .enable = da8xx_musb_enable, 477 .disable = da8xx_musb_disable, 478 479 .set_mode = da8xx_musb_set_mode, 480 .try_idle = da8xx_musb_try_idle, 481 482 .set_vbus = da8xx_musb_set_vbus, 483 }; 484 485 static u64 da8xx_dmamask = DMA_BIT_MASK(32); 486 487 static int __init da8xx_probe(struct platform_device *pdev) 488 { 489 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; 490 struct platform_device *musb; 491 struct da8xx_glue *glue; 492 493 struct clk *clk; 494 495 int ret = -ENOMEM; 496 497 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 498 if (!glue) { 499 dev_err(&pdev->dev, "failed to allocate glue context\n"); 500 goto err0; 501 } 502 503 musb = platform_device_alloc("musb-hdrc", -1); 504 if (!musb) { 505 dev_err(&pdev->dev, "failed to allocate musb device\n"); 506 goto err1; 507 } 508 509 clk = clk_get(&pdev->dev, "usb20"); 510 if (IS_ERR(clk)) { 511 dev_err(&pdev->dev, "failed to get clock\n"); 512 ret = PTR_ERR(clk); 513 goto err2; 514 } 515 516 ret = clk_enable(clk); 517 if (ret) { 518 dev_err(&pdev->dev, "failed to enable clock\n"); 519 goto err3; 520 } 521 522 musb->dev.parent = &pdev->dev; 523 musb->dev.dma_mask = &da8xx_dmamask; 524 musb->dev.coherent_dma_mask = da8xx_dmamask; 525 526 glue->dev = &pdev->dev; 527 glue->musb = musb; 528 glue->clk = clk; 529 530 pdata->platform_ops = &da8xx_ops; 531 532 platform_set_drvdata(pdev, glue); 533 534 ret = platform_device_add_resources(musb, pdev->resource, 535 pdev->num_resources); 536 if (ret) { 537 dev_err(&pdev->dev, "failed to add resources\n"); 538 goto err4; 539 } 540 541 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 542 if (ret) { 543 dev_err(&pdev->dev, "failed to add platform_data\n"); 544 goto err4; 545 } 546 547 ret = platform_device_add(musb); 548 if (ret) { 549 dev_err(&pdev->dev, "failed to register musb device\n"); 550 goto err4; 551 } 552 553 return 0; 554 555 err4: 556 clk_disable(clk); 557 558 err3: 559 clk_put(clk); 560 561 err2: 562 platform_device_put(musb); 563 564 err1: 565 kfree(glue); 566 567 err0: 568 return ret; 569 } 570 571 static int __exit da8xx_remove(struct platform_device *pdev) 572 { 573 struct da8xx_glue *glue = platform_get_drvdata(pdev); 574 575 platform_device_del(glue->musb); 576 platform_device_put(glue->musb); 577 clk_disable(glue->clk); 578 clk_put(glue->clk); 579 kfree(glue); 580 581 return 0; 582 } 583 584 static struct platform_driver da8xx_driver = { 585 .remove = __exit_p(da8xx_remove), 586 .driver = { 587 .name = "musb-da8xx", 588 }, 589 }; 590 591 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer"); 592 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>"); 593 MODULE_LICENSE("GPL v2"); 594 595 static int __init da8xx_init(void) 596 { 597 return platform_driver_probe(&da8xx_driver, da8xx_probe); 598 } 599 subsys_initcall(da8xx_init); 600 601 static void __exit da8xx_exit(void) 602 { 603 platform_driver_unregister(&da8xx_driver); 604 } 605 module_exit(da8xx_exit); 606