1550a7375SFelipe Balbi /* Copyright (C) 2005-2006 by Texas Instruments */ 2550a7375SFelipe Balbi 3550a7375SFelipe Balbi #ifndef _CPPI_DMA_H_ 4550a7375SFelipe Balbi #define _CPPI_DMA_H_ 5550a7375SFelipe Balbi 6550a7375SFelipe Balbi #include <linux/slab.h> 7550a7375SFelipe Balbi #include <linux/list.h> 8550a7375SFelipe Balbi #include <linux/errno.h> 9550a7375SFelipe Balbi #include <linux/dmapool.h> 10239d2218SBin Liu #include <linux/dmaengine.h> 11550a7375SFelipe Balbi 12550a7375SFelipe Balbi #include "musb_core.h" 13239d2218SBin Liu #include "musb_dma.h" 14550a7375SFelipe Balbi 15550a7375SFelipe Balbi /* CPPI RX/TX state RAM */ 16550a7375SFelipe Balbi 17550a7375SFelipe Balbi struct cppi_tx_stateram { 18550a7375SFelipe Balbi u32 tx_head; /* "DMA packet" head descriptor */ 19550a7375SFelipe Balbi u32 tx_buf; 20550a7375SFelipe Balbi u32 tx_current; /* current descriptor */ 21550a7375SFelipe Balbi u32 tx_buf_current; 22550a7375SFelipe Balbi u32 tx_info; /* flags, remaining buflen */ 23550a7375SFelipe Balbi u32 tx_rem_len; 24550a7375SFelipe Balbi u32 tx_dummy; /* unused */ 25550a7375SFelipe Balbi u32 tx_complete; 26550a7375SFelipe Balbi }; 27550a7375SFelipe Balbi 28550a7375SFelipe Balbi struct cppi_rx_stateram { 29550a7375SFelipe Balbi u32 rx_skipbytes; 30550a7375SFelipe Balbi u32 rx_head; 31550a7375SFelipe Balbi u32 rx_sop; /* "DMA packet" head descriptor */ 32550a7375SFelipe Balbi u32 rx_current; /* current descriptor */ 33550a7375SFelipe Balbi u32 rx_buf_current; 34550a7375SFelipe Balbi u32 rx_len_len; 35550a7375SFelipe Balbi u32 rx_cnt_cnt; 36550a7375SFelipe Balbi u32 rx_complete; 37550a7375SFelipe Balbi }; 38550a7375SFelipe Balbi 39550a7375SFelipe Balbi /* hw_options bits in CPPI buffer descriptors */ 40550a7375SFelipe Balbi #define CPPI_SOP_SET ((u32)(1 << 31)) 41550a7375SFelipe Balbi #define CPPI_EOP_SET ((u32)(1 << 30)) 42550a7375SFelipe Balbi #define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */ 43550a7375SFelipe Balbi #define CPPI_EOQ_MASK ((u32)(1 << 28)) 44550a7375SFelipe Balbi #define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */ 45550a7375SFelipe Balbi #define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */ 46550a7375SFelipe Balbi 47550a7375SFelipe Balbi #define CPPI_RECV_PKTLEN_MASK 0xFFFF 48550a7375SFelipe Balbi #define CPPI_BUFFER_LEN_MASK 0xFFFF 49550a7375SFelipe Balbi 50550a7375SFelipe Balbi #define CPPI_TEAR_READY ((u32)(1 << 31)) 51550a7375SFelipe Balbi 52550a7375SFelipe Balbi /* CPPI data structure definitions */ 53550a7375SFelipe Balbi 54550a7375SFelipe Balbi #define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */ 55550a7375SFelipe Balbi 56550a7375SFelipe Balbi struct cppi_descriptor { 57550a7375SFelipe Balbi /* hardware overlay */ 58550a7375SFelipe Balbi u32 hw_next; /* next buffer descriptor Pointer */ 59550a7375SFelipe Balbi u32 hw_bufp; /* i/o buffer pointer */ 60550a7375SFelipe Balbi u32 hw_off_len; /* buffer_offset16, buffer_length16 */ 61550a7375SFelipe Balbi u32 hw_options; /* flags: SOP, EOP etc*/ 62550a7375SFelipe Balbi 63550a7375SFelipe Balbi struct cppi_descriptor *next; 64550a7375SFelipe Balbi dma_addr_t dma; /* address of this descriptor */ 65550a7375SFelipe Balbi u32 buflen; /* for RX: original buffer length */ 66550a7375SFelipe Balbi } __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN))); 67550a7375SFelipe Balbi 68550a7375SFelipe Balbi 69550a7375SFelipe Balbi struct cppi; 70550a7375SFelipe Balbi 71550a7375SFelipe Balbi /* CPPI Channel Control structure */ 72550a7375SFelipe Balbi struct cppi_channel { 73550a7375SFelipe Balbi struct dma_channel channel; 74550a7375SFelipe Balbi 75550a7375SFelipe Balbi /* back pointer to the DMA controller structure */ 76550a7375SFelipe Balbi struct cppi *controller; 77550a7375SFelipe Balbi 78550a7375SFelipe Balbi /* which direction of which endpoint? */ 79550a7375SFelipe Balbi struct musb_hw_ep *hw_ep; 80550a7375SFelipe Balbi bool transmit; 81550a7375SFelipe Balbi u8 index; 82550a7375SFelipe Balbi 83550a7375SFelipe Balbi /* DMA modes: RNDIS or "transparent" */ 84550a7375SFelipe Balbi u8 is_rndis; 85550a7375SFelipe Balbi 86550a7375SFelipe Balbi /* book keeping for current transfer request */ 87550a7375SFelipe Balbi dma_addr_t buf_dma; 88550a7375SFelipe Balbi u32 buf_len; 89550a7375SFelipe Balbi u32 maxpacket; 90550a7375SFelipe Balbi u32 offset; /* dma requested */ 91550a7375SFelipe Balbi 92550a7375SFelipe Balbi void __iomem *state_ram; /* CPPI state */ 93550a7375SFelipe Balbi 94550a7375SFelipe Balbi struct cppi_descriptor *freelist; 95550a7375SFelipe Balbi 96550a7375SFelipe Balbi /* BD management fields */ 97550a7375SFelipe Balbi struct cppi_descriptor *head; 98550a7375SFelipe Balbi struct cppi_descriptor *tail; 99550a7375SFelipe Balbi struct cppi_descriptor *last_processed; 100550a7375SFelipe Balbi 101550a7375SFelipe Balbi /* use tx_complete in host role to track endpoints waiting for 102550a7375SFelipe Balbi * FIFONOTEMPTY to clear. 103550a7375SFelipe Balbi */ 104550a7375SFelipe Balbi struct list_head tx_complete; 105550a7375SFelipe Balbi }; 106550a7375SFelipe Balbi 107550a7375SFelipe Balbi /* CPPI DMA controller object */ 108550a7375SFelipe Balbi struct cppi { 109550a7375SFelipe Balbi struct dma_controller controller; 110550a7375SFelipe Balbi struct musb *musb; 111550a7375SFelipe Balbi void __iomem *mregs; /* Mentor regs */ 112550a7375SFelipe Balbi void __iomem *tibase; /* TI/CPPI regs */ 113550a7375SFelipe Balbi 11491e9c4feSSergei Shtylyov int irq; 11591e9c4feSSergei Shtylyov 116c767c1c6SDavid Brownell struct cppi_channel tx[4]; 117c767c1c6SDavid Brownell struct cppi_channel rx[4]; 118550a7375SFelipe Balbi 119550a7375SFelipe Balbi struct dma_pool *pool; 120550a7375SFelipe Balbi 121550a7375SFelipe Balbi struct list_head tx_complete; 122550a7375SFelipe Balbi }; 123550a7375SFelipe Balbi 12491e9c4feSSergei Shtylyov /* CPPI IRQ handler */ 12591e9c4feSSergei Shtylyov extern irqreturn_t cppi_interrupt(int, void *); 126550a7375SFelipe Balbi 127239d2218SBin Liu struct cppi41_dma_channel { 128239d2218SBin Liu struct dma_channel channel; 129239d2218SBin Liu struct cppi41_dma_controller *controller; 130239d2218SBin Liu struct musb_hw_ep *hw_ep; 131239d2218SBin Liu struct dma_chan *dc; 132239d2218SBin Liu dma_cookie_t cookie; 133239d2218SBin Liu u8 port_num; 134239d2218SBin Liu u8 is_tx; 135239d2218SBin Liu u8 is_allocated; 136239d2218SBin Liu u8 usb_toggle; 137239d2218SBin Liu 138239d2218SBin Liu dma_addr_t buf_addr; 139239d2218SBin Liu u32 total_len; 140239d2218SBin Liu u32 prog_len; 141239d2218SBin Liu u32 transferred; 142239d2218SBin Liu u32 packet_sz; 143239d2218SBin Liu struct list_head tx_check; 144239d2218SBin Liu int tx_zlp; 145239d2218SBin Liu }; 146239d2218SBin Liu 147550a7375SFelipe Balbi #endif /* end of ifndef _CPPI_DMA_H_ */ 148