1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016 MediaTek Inc. 4 * 5 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/iopoll.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_wakeirq.h> 16 #include <linux/reset.h> 17 18 #include "mtu3.h" 19 #include "mtu3_dr.h" 20 #include "mtu3_debug.h" 21 22 /* u2-port0 should be powered on and enabled; */ 23 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks) 24 { 25 void __iomem *ibase = ssusb->ippc_base; 26 u32 value, check_val; 27 int ret; 28 29 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE | 30 SSUSB_REF_RST_B_STS; 31 32 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, 33 (check_val == (value & check_val)), 100, 20000); 34 if (ret) { 35 dev_err(ssusb->dev, "clks of sts1 are not stable!\n"); 36 return ret; 37 } 38 39 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, 40 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000); 41 if (ret) { 42 dev_err(ssusb->dev, "mac2 clock is not stable\n"); 43 return ret; 44 } 45 46 return 0; 47 } 48 49 static int wait_for_ip_sleep(struct ssusb_mtk *ssusb) 50 { 51 bool sleep_check = true; 52 u32 value; 53 int ret; 54 55 if (!ssusb->is_host) 56 sleep_check = ssusb_gadget_ip_sleep_check(ssusb); 57 58 if (!sleep_check) 59 return 0; 60 61 /* wait for ip enter sleep mode */ 62 ret = readl_poll_timeout(ssusb->ippc_base + U3D_SSUSB_IP_PW_STS1, value, 63 (value & SSUSB_IP_SLEEP_STS), 100, 100000); 64 if (ret) { 65 dev_err(ssusb->dev, "ip sleep failed!!!\n"); 66 ret = -EBUSY; 67 } else { 68 /* workaround: avoid wrong wakeup signal latch for some soc */ 69 usleep_range(100, 200); 70 } 71 72 return ret; 73 } 74 75 static int ssusb_phy_init(struct ssusb_mtk *ssusb) 76 { 77 int i; 78 int ret; 79 80 for (i = 0; i < ssusb->num_phys; i++) { 81 ret = phy_init(ssusb->phys[i]); 82 if (ret) 83 goto exit_phy; 84 } 85 return 0; 86 87 exit_phy: 88 for (; i > 0; i--) 89 phy_exit(ssusb->phys[i - 1]); 90 91 return ret; 92 } 93 94 static int ssusb_phy_exit(struct ssusb_mtk *ssusb) 95 { 96 int i; 97 98 for (i = 0; i < ssusb->num_phys; i++) 99 phy_exit(ssusb->phys[i]); 100 101 return 0; 102 } 103 104 static int ssusb_phy_power_on(struct ssusb_mtk *ssusb) 105 { 106 int i; 107 int ret; 108 109 for (i = 0; i < ssusb->num_phys; i++) { 110 ret = phy_power_on(ssusb->phys[i]); 111 if (ret) 112 goto power_off_phy; 113 } 114 return 0; 115 116 power_off_phy: 117 for (; i > 0; i--) 118 phy_power_off(ssusb->phys[i - 1]); 119 120 return ret; 121 } 122 123 static void ssusb_phy_power_off(struct ssusb_mtk *ssusb) 124 { 125 unsigned int i; 126 127 for (i = 0; i < ssusb->num_phys; i++) 128 phy_power_off(ssusb->phys[i]); 129 } 130 131 static int ssusb_rscs_init(struct ssusb_mtk *ssusb) 132 { 133 int ret = 0; 134 135 ret = regulator_enable(ssusb->vusb33); 136 if (ret) { 137 dev_err(ssusb->dev, "failed to enable vusb33\n"); 138 goto vusb33_err; 139 } 140 141 ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks); 142 if (ret) 143 goto clks_err; 144 145 ret = ssusb_phy_init(ssusb); 146 if (ret) { 147 dev_err(ssusb->dev, "failed to init phy\n"); 148 goto phy_init_err; 149 } 150 151 ret = ssusb_phy_power_on(ssusb); 152 if (ret) { 153 dev_err(ssusb->dev, "failed to power on phy\n"); 154 goto phy_err; 155 } 156 157 return 0; 158 159 phy_err: 160 ssusb_phy_exit(ssusb); 161 phy_init_err: 162 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks); 163 clks_err: 164 regulator_disable(ssusb->vusb33); 165 vusb33_err: 166 return ret; 167 } 168 169 static void ssusb_rscs_exit(struct ssusb_mtk *ssusb) 170 { 171 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks); 172 regulator_disable(ssusb->vusb33); 173 ssusb_phy_power_off(ssusb); 174 ssusb_phy_exit(ssusb); 175 } 176 177 static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb) 178 { 179 /* reset whole ip (xhci & u3d) */ 180 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); 181 udelay(1); 182 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); 183 184 /* 185 * device ip may be powered on in firmware/BROM stage before entering 186 * kernel stage; 187 * power down device ip, otherwise ip-sleep will fail when working as 188 * host only mode 189 */ 190 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 191 } 192 193 static void ssusb_u3_drd_check(struct ssusb_mtk *ssusb) 194 { 195 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; 196 u32 dev_u3p_num; 197 u32 host_u3p_num; 198 u32 value; 199 200 /* u3 port0 is disabled */ 201 if (ssusb->u3p_dis_msk & BIT(0)) { 202 otg_sx->is_u3_drd = false; 203 goto out; 204 } 205 206 value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_DEV_CAP); 207 dev_u3p_num = SSUSB_IP_DEV_U3_PORT_NUM(value); 208 209 value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP); 210 host_u3p_num = SSUSB_IP_XHCI_U3_PORT_NUM(value); 211 212 otg_sx->is_u3_drd = !!(dev_u3p_num && host_u3p_num); 213 214 out: 215 dev_info(ssusb->dev, "usb3-drd: %d\n", otg_sx->is_u3_drd); 216 } 217 218 static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb) 219 { 220 struct device_node *node = pdev->dev.of_node; 221 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; 222 struct clk_bulk_data *clks = ssusb->clks; 223 struct device *dev = &pdev->dev; 224 int i; 225 int ret; 226 227 ssusb->vusb33 = devm_regulator_get(dev, "vusb33"); 228 if (IS_ERR(ssusb->vusb33)) { 229 dev_err(dev, "failed to get vusb33\n"); 230 return PTR_ERR(ssusb->vusb33); 231 } 232 233 clks[0].id = "sys_ck"; 234 clks[1].id = "ref_ck"; 235 clks[2].id = "mcu_ck"; 236 clks[3].id = "dma_ck"; 237 ret = devm_clk_bulk_get_optional(dev, BULK_CLKS_CNT, clks); 238 if (ret) 239 return ret; 240 241 ssusb->num_phys = of_count_phandle_with_args(node, 242 "phys", "#phy-cells"); 243 if (ssusb->num_phys > 0) { 244 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys, 245 sizeof(*ssusb->phys), GFP_KERNEL); 246 if (!ssusb->phys) 247 return -ENOMEM; 248 } else { 249 ssusb->num_phys = 0; 250 } 251 252 for (i = 0; i < ssusb->num_phys; i++) { 253 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i); 254 if (IS_ERR(ssusb->phys[i])) { 255 dev_err(dev, "failed to get phy-%d\n", i); 256 return PTR_ERR(ssusb->phys[i]); 257 } 258 } 259 260 ssusb->ippc_base = devm_platform_ioremap_resource_byname(pdev, "ippc"); 261 if (IS_ERR(ssusb->ippc_base)) 262 return PTR_ERR(ssusb->ippc_base); 263 264 ssusb->wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup"); 265 if (ssusb->wakeup_irq == -EPROBE_DEFER) 266 return ssusb->wakeup_irq; 267 268 ssusb->dr_mode = usb_get_dr_mode(dev); 269 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) 270 ssusb->dr_mode = USB_DR_MODE_OTG; 271 272 of_property_read_u32(node, "mediatek,u3p-dis-msk", &ssusb->u3p_dis_msk); 273 274 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL) 275 goto out; 276 277 /* if host role is supported */ 278 ret = ssusb_wakeup_of_property_parse(ssusb, node); 279 if (ret) { 280 dev_err(dev, "failed to parse uwk property\n"); 281 return ret; 282 } 283 284 /* optional property, ignore the error if it does not exist */ 285 of_property_read_u32(node, "mediatek,u2p-dis-msk", 286 &ssusb->u2p_dis_msk); 287 288 otg_sx->vbus = devm_regulator_get(dev, "vbus"); 289 if (IS_ERR(otg_sx->vbus)) { 290 dev_err(dev, "failed to get vbus\n"); 291 return PTR_ERR(otg_sx->vbus); 292 } 293 294 if (ssusb->dr_mode == USB_DR_MODE_HOST) 295 goto out; 296 297 /* if dual-role mode is supported */ 298 otg_sx->manual_drd_enabled = 299 of_property_read_bool(node, "enable-manual-drd"); 300 otg_sx->role_sw_used = of_property_read_bool(node, "usb-role-switch"); 301 302 /* can't disable port0 when use dual-role mode */ 303 ssusb->u2p_dis_msk &= ~0x1; 304 305 if (otg_sx->role_sw_used || otg_sx->manual_drd_enabled) 306 goto out; 307 308 if (of_property_read_bool(node, "extcon")) { 309 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0); 310 if (IS_ERR(otg_sx->edev)) { 311 return dev_err_probe(dev, PTR_ERR(otg_sx->edev), 312 "couldn't get extcon device\n"); 313 } 314 } 315 316 out: 317 dev_info(dev, "dr_mode: %d, drd: %s\n", ssusb->dr_mode, 318 otg_sx->manual_drd_enabled ? "manual" : "auto"); 319 dev_info(dev, "u2p_dis_msk: %x, u3p_dis_msk: %x\n", 320 ssusb->u2p_dis_msk, ssusb->u3p_dis_msk); 321 322 return 0; 323 } 324 325 static int mtu3_probe(struct platform_device *pdev) 326 { 327 struct device_node *node = pdev->dev.of_node; 328 struct device *dev = &pdev->dev; 329 struct ssusb_mtk *ssusb; 330 int ret = -ENOMEM; 331 332 /* all elements are set to ZERO as default value */ 333 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL); 334 if (!ssusb) 335 return -ENOMEM; 336 337 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 338 if (ret) { 339 dev_err(dev, "No suitable DMA config available\n"); 340 return -ENOTSUPP; 341 } 342 343 platform_set_drvdata(pdev, ssusb); 344 ssusb->dev = dev; 345 346 ret = get_ssusb_rscs(pdev, ssusb); 347 if (ret) 348 return ret; 349 350 ssusb_debugfs_create_root(ssusb); 351 352 /* enable power domain */ 353 pm_runtime_set_active(dev); 354 pm_runtime_use_autosuspend(dev); 355 pm_runtime_set_autosuspend_delay(dev, 4000); 356 pm_runtime_enable(dev); 357 pm_runtime_get_sync(dev); 358 359 ret = ssusb_rscs_init(ssusb); 360 if (ret) 361 goto comm_init_err; 362 363 if (ssusb->wakeup_irq > 0) { 364 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, ssusb->wakeup_irq); 365 if (ret) { 366 dev_err(dev, "failed to set wakeup irq %d\n", ssusb->wakeup_irq); 367 goto comm_exit; 368 } 369 dev_info(dev, "wakeup irq %d\n", ssusb->wakeup_irq); 370 } 371 372 ret = device_reset_optional(dev); 373 if (ret) { 374 dev_err_probe(dev, ret, "failed to reset controller\n"); 375 goto comm_exit; 376 } 377 378 ssusb_ip_sw_reset(ssusb); 379 ssusb_u3_drd_check(ssusb); 380 381 if (IS_ENABLED(CONFIG_USB_MTU3_HOST)) 382 ssusb->dr_mode = USB_DR_MODE_HOST; 383 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET)) 384 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL; 385 386 /* default as host */ 387 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL); 388 389 switch (ssusb->dr_mode) { 390 case USB_DR_MODE_PERIPHERAL: 391 ret = ssusb_gadget_init(ssusb); 392 if (ret) { 393 dev_err(dev, "failed to initialize gadget\n"); 394 goto comm_exit; 395 } 396 break; 397 case USB_DR_MODE_HOST: 398 ret = ssusb_host_init(ssusb, node); 399 if (ret) { 400 dev_err(dev, "failed to initialize host\n"); 401 goto comm_exit; 402 } 403 break; 404 case USB_DR_MODE_OTG: 405 ret = ssusb_gadget_init(ssusb); 406 if (ret) { 407 dev_err(dev, "failed to initialize gadget\n"); 408 goto comm_exit; 409 } 410 411 ret = ssusb_host_init(ssusb, node); 412 if (ret) { 413 dev_err(dev, "failed to initialize host\n"); 414 goto gadget_exit; 415 } 416 417 ret = ssusb_otg_switch_init(ssusb); 418 if (ret) { 419 dev_err(dev, "failed to initialize switch\n"); 420 goto host_exit; 421 } 422 break; 423 default: 424 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode); 425 ret = -EINVAL; 426 goto comm_exit; 427 } 428 429 device_enable_async_suspend(dev); 430 pm_runtime_mark_last_busy(dev); 431 pm_runtime_put_autosuspend(dev); 432 pm_runtime_forbid(dev); 433 434 return 0; 435 436 host_exit: 437 ssusb_host_exit(ssusb); 438 gadget_exit: 439 ssusb_gadget_exit(ssusb); 440 comm_exit: 441 ssusb_rscs_exit(ssusb); 442 comm_init_err: 443 pm_runtime_put_noidle(dev); 444 pm_runtime_disable(dev); 445 ssusb_debugfs_remove_root(ssusb); 446 447 return ret; 448 } 449 450 static int mtu3_remove(struct platform_device *pdev) 451 { 452 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); 453 454 pm_runtime_get_sync(&pdev->dev); 455 456 switch (ssusb->dr_mode) { 457 case USB_DR_MODE_PERIPHERAL: 458 ssusb_gadget_exit(ssusb); 459 break; 460 case USB_DR_MODE_HOST: 461 ssusb_host_exit(ssusb); 462 break; 463 case USB_DR_MODE_OTG: 464 ssusb_otg_switch_exit(ssusb); 465 ssusb_gadget_exit(ssusb); 466 ssusb_host_exit(ssusb); 467 break; 468 default: 469 return -EINVAL; 470 } 471 472 ssusb_rscs_exit(ssusb); 473 ssusb_debugfs_remove_root(ssusb); 474 pm_runtime_disable(&pdev->dev); 475 pm_runtime_put_noidle(&pdev->dev); 476 pm_runtime_set_suspended(&pdev->dev); 477 478 return 0; 479 } 480 481 static int resume_ip_and_ports(struct ssusb_mtk *ssusb, pm_message_t msg) 482 { 483 switch (ssusb->dr_mode) { 484 case USB_DR_MODE_PERIPHERAL: 485 ssusb_gadget_resume(ssusb, msg); 486 break; 487 case USB_DR_MODE_HOST: 488 ssusb_host_resume(ssusb, false); 489 break; 490 case USB_DR_MODE_OTG: 491 ssusb_host_resume(ssusb, !ssusb->is_host); 492 if (!ssusb->is_host) 493 ssusb_gadget_resume(ssusb, msg); 494 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 return 0; 501 } 502 503 static int mtu3_suspend_common(struct device *dev, pm_message_t msg) 504 { 505 struct ssusb_mtk *ssusb = dev_get_drvdata(dev); 506 int ret = 0; 507 508 dev_dbg(dev, "%s\n", __func__); 509 510 switch (ssusb->dr_mode) { 511 case USB_DR_MODE_PERIPHERAL: 512 ret = ssusb_gadget_suspend(ssusb, msg); 513 if (ret) 514 goto err; 515 516 break; 517 case USB_DR_MODE_HOST: 518 ssusb_host_suspend(ssusb); 519 break; 520 case USB_DR_MODE_OTG: 521 if (!ssusb->is_host) { 522 ret = ssusb_gadget_suspend(ssusb, msg); 523 if (ret) 524 goto err; 525 } 526 ssusb_host_suspend(ssusb); 527 break; 528 default: 529 return -EINVAL; 530 } 531 532 ret = wait_for_ip_sleep(ssusb); 533 if (ret) 534 goto sleep_err; 535 536 ssusb_phy_power_off(ssusb); 537 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks); 538 ssusb_wakeup_set(ssusb, true); 539 return 0; 540 541 sleep_err: 542 resume_ip_and_ports(ssusb, msg); 543 err: 544 return ret; 545 } 546 547 static int mtu3_resume_common(struct device *dev, pm_message_t msg) 548 { 549 struct ssusb_mtk *ssusb = dev_get_drvdata(dev); 550 int ret; 551 552 dev_dbg(dev, "%s\n", __func__); 553 554 ssusb_wakeup_set(ssusb, false); 555 ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks); 556 if (ret) 557 goto clks_err; 558 559 ret = ssusb_phy_power_on(ssusb); 560 if (ret) 561 goto phy_err; 562 563 return resume_ip_and_ports(ssusb, msg); 564 565 phy_err: 566 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks); 567 clks_err: 568 return ret; 569 } 570 571 static int __maybe_unused mtu3_suspend(struct device *dev) 572 { 573 return mtu3_suspend_common(dev, PMSG_SUSPEND); 574 } 575 576 static int __maybe_unused mtu3_resume(struct device *dev) 577 { 578 return mtu3_resume_common(dev, PMSG_SUSPEND); 579 } 580 581 static int __maybe_unused mtu3_runtime_suspend(struct device *dev) 582 { 583 if (!device_may_wakeup(dev)) 584 return 0; 585 586 return mtu3_suspend_common(dev, PMSG_AUTO_SUSPEND); 587 } 588 589 static int __maybe_unused mtu3_runtime_resume(struct device *dev) 590 { 591 if (!device_may_wakeup(dev)) 592 return 0; 593 594 return mtu3_resume_common(dev, PMSG_AUTO_SUSPEND); 595 } 596 597 static const struct dev_pm_ops mtu3_pm_ops = { 598 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume) 599 SET_RUNTIME_PM_OPS(mtu3_runtime_suspend, 600 mtu3_runtime_resume, NULL) 601 }; 602 603 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL) 604 605 static const struct of_device_id mtu3_of_match[] = { 606 {.compatible = "mediatek,mt8173-mtu3",}, 607 {.compatible = "mediatek,mtu3",}, 608 {}, 609 }; 610 MODULE_DEVICE_TABLE(of, mtu3_of_match); 611 612 static struct platform_driver mtu3_driver = { 613 .probe = mtu3_probe, 614 .remove = mtu3_remove, 615 .driver = { 616 .name = MTU3_DRIVER_NAME, 617 .pm = DEV_PM_OPS, 618 .of_match_table = mtu3_of_match, 619 }, 620 }; 621 module_platform_driver(mtu3_driver); 622 623 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 624 MODULE_LICENSE("GPL v2"); 625 MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver"); 626