1 /* 2 * Copyright (C) 2016 MediaTek Inc. 3 * 4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/iopoll.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 27 #include "mtu3.h" 28 #include "mtu3_dr.h" 29 30 /* u2-port0 should be powered on and enabled; */ 31 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks) 32 { 33 void __iomem *ibase = ssusb->ippc_base; 34 u32 value, check_val; 35 int ret; 36 37 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE | 38 SSUSB_REF_RST_B_STS; 39 40 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, 41 (check_val == (value & check_val)), 100, 20000); 42 if (ret) { 43 dev_err(ssusb->dev, "clks of sts1 are not stable!\n"); 44 return ret; 45 } 46 47 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, 48 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000); 49 if (ret) { 50 dev_err(ssusb->dev, "mac2 clock is not stable\n"); 51 return ret; 52 } 53 54 return 0; 55 } 56 57 static int ssusb_phy_init(struct ssusb_mtk *ssusb) 58 { 59 int i; 60 int ret; 61 62 for (i = 0; i < ssusb->num_phys; i++) { 63 ret = phy_init(ssusb->phys[i]); 64 if (ret) 65 goto exit_phy; 66 } 67 return 0; 68 69 exit_phy: 70 for (; i > 0; i--) 71 phy_exit(ssusb->phys[i - 1]); 72 73 return ret; 74 } 75 76 static int ssusb_phy_exit(struct ssusb_mtk *ssusb) 77 { 78 int i; 79 80 for (i = 0; i < ssusb->num_phys; i++) 81 phy_exit(ssusb->phys[i]); 82 83 return 0; 84 } 85 86 static int ssusb_phy_power_on(struct ssusb_mtk *ssusb) 87 { 88 int i; 89 int ret; 90 91 for (i = 0; i < ssusb->num_phys; i++) { 92 ret = phy_power_on(ssusb->phys[i]); 93 if (ret) 94 goto power_off_phy; 95 } 96 return 0; 97 98 power_off_phy: 99 for (; i > 0; i--) 100 phy_power_off(ssusb->phys[i - 1]); 101 102 return ret; 103 } 104 105 static void ssusb_phy_power_off(struct ssusb_mtk *ssusb) 106 { 107 unsigned int i; 108 109 for (i = 0; i < ssusb->num_phys; i++) 110 phy_power_off(ssusb->phys[i]); 111 } 112 113 static int ssusb_rscs_init(struct ssusb_mtk *ssusb) 114 { 115 int ret = 0; 116 117 ret = regulator_enable(ssusb->vusb33); 118 if (ret) { 119 dev_err(ssusb->dev, "failed to enable vusb33\n"); 120 goto vusb33_err; 121 } 122 123 ret = clk_prepare_enable(ssusb->sys_clk); 124 if (ret) { 125 dev_err(ssusb->dev, "failed to enable sys_clk\n"); 126 goto sys_clk_err; 127 } 128 129 ret = clk_prepare_enable(ssusb->ref_clk); 130 if (ret) { 131 dev_err(ssusb->dev, "failed to enable ref_clk\n"); 132 goto ref_clk_err; 133 } 134 135 ret = ssusb_phy_init(ssusb); 136 if (ret) { 137 dev_err(ssusb->dev, "failed to init phy\n"); 138 goto phy_init_err; 139 } 140 141 ret = ssusb_phy_power_on(ssusb); 142 if (ret) { 143 dev_err(ssusb->dev, "failed to power on phy\n"); 144 goto phy_err; 145 } 146 147 return 0; 148 149 phy_err: 150 ssusb_phy_exit(ssusb); 151 phy_init_err: 152 clk_disable_unprepare(ssusb->ref_clk); 153 ref_clk_err: 154 clk_disable_unprepare(ssusb->sys_clk); 155 sys_clk_err: 156 regulator_disable(ssusb->vusb33); 157 vusb33_err: 158 159 return ret; 160 } 161 162 static void ssusb_rscs_exit(struct ssusb_mtk *ssusb) 163 { 164 clk_disable_unprepare(ssusb->sys_clk); 165 clk_disable_unprepare(ssusb->ref_clk); 166 regulator_disable(ssusb->vusb33); 167 ssusb_phy_power_off(ssusb); 168 ssusb_phy_exit(ssusb); 169 } 170 171 static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb) 172 { 173 /* reset whole ip (xhci & u3d) */ 174 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); 175 udelay(1); 176 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); 177 } 178 179 static int get_iddig_pinctrl(struct ssusb_mtk *ssusb) 180 { 181 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; 182 183 otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev); 184 if (IS_ERR(otg_sx->id_pinctrl)) { 185 dev_err(ssusb->dev, "Cannot find id pinctrl!\n"); 186 return PTR_ERR(otg_sx->id_pinctrl); 187 } 188 189 otg_sx->id_float = 190 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float"); 191 if (IS_ERR(otg_sx->id_float)) { 192 dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n"); 193 return PTR_ERR(otg_sx->id_float); 194 } 195 196 otg_sx->id_ground = 197 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground"); 198 if (IS_ERR(otg_sx->id_ground)) { 199 dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n"); 200 return PTR_ERR(otg_sx->id_ground); 201 } 202 203 return 0; 204 } 205 206 static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb) 207 { 208 struct device_node *node = pdev->dev.of_node; 209 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; 210 struct device *dev = &pdev->dev; 211 struct regulator *vbus; 212 struct resource *res; 213 int i; 214 int ret; 215 216 ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33"); 217 if (IS_ERR(ssusb->vusb33)) { 218 dev_err(dev, "failed to get vusb33\n"); 219 return PTR_ERR(ssusb->vusb33); 220 } 221 222 ssusb->sys_clk = devm_clk_get(dev, "sys_ck"); 223 if (IS_ERR(ssusb->sys_clk)) { 224 dev_err(dev, "failed to get sys clock\n"); 225 return PTR_ERR(ssusb->sys_clk); 226 } 227 228 /* 229 * reference clock is usually a "fixed-clock", make it optional 230 * for backward compatibility and ignore the error if it does 231 * not exist. 232 */ 233 ssusb->ref_clk = devm_clk_get(dev, "ref_ck"); 234 if (IS_ERR(ssusb->ref_clk)) { 235 if (PTR_ERR(ssusb->ref_clk) == -EPROBE_DEFER) 236 return -EPROBE_DEFER; 237 238 ssusb->ref_clk = NULL; 239 } 240 241 ssusb->num_phys = of_count_phandle_with_args(node, 242 "phys", "#phy-cells"); 243 if (ssusb->num_phys > 0) { 244 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys, 245 sizeof(*ssusb->phys), GFP_KERNEL); 246 if (!ssusb->phys) 247 return -ENOMEM; 248 } else { 249 ssusb->num_phys = 0; 250 } 251 252 for (i = 0; i < ssusb->num_phys; i++) { 253 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i); 254 if (IS_ERR(ssusb->phys[i])) { 255 dev_err(dev, "failed to get phy-%d\n", i); 256 return PTR_ERR(ssusb->phys[i]); 257 } 258 } 259 260 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 261 ssusb->ippc_base = devm_ioremap_resource(dev, res); 262 if (IS_ERR(ssusb->ippc_base)) 263 return PTR_ERR(ssusb->ippc_base); 264 265 ssusb->dr_mode = usb_get_dr_mode(dev); 266 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) { 267 dev_err(dev, "dr_mode is error\n"); 268 return -EINVAL; 269 } 270 271 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL) 272 return 0; 273 274 /* if host role is supported */ 275 ret = ssusb_wakeup_of_property_parse(ssusb, node); 276 if (ret) 277 return ret; 278 279 if (ssusb->dr_mode != USB_DR_MODE_OTG) 280 return 0; 281 282 /* if dual-role mode is supported */ 283 vbus = devm_regulator_get(&pdev->dev, "vbus"); 284 if (IS_ERR(vbus)) { 285 dev_err(dev, "failed to get vbus\n"); 286 return PTR_ERR(vbus); 287 } 288 otg_sx->vbus = vbus; 289 290 otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd"); 291 otg_sx->manual_drd_enabled = 292 of_property_read_bool(node, "enable-manual-drd"); 293 294 if (of_property_read_bool(node, "extcon")) { 295 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0); 296 if (IS_ERR(otg_sx->edev)) { 297 dev_err(ssusb->dev, "couldn't get extcon device\n"); 298 return -EPROBE_DEFER; 299 } 300 if (otg_sx->manual_drd_enabled) { 301 ret = get_iddig_pinctrl(ssusb); 302 if (ret) 303 return ret; 304 } 305 } 306 307 dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n", 308 ssusb->dr_mode, otg_sx->is_u3_drd); 309 310 return 0; 311 } 312 313 static int mtu3_probe(struct platform_device *pdev) 314 { 315 struct device_node *node = pdev->dev.of_node; 316 struct device *dev = &pdev->dev; 317 struct ssusb_mtk *ssusb; 318 int ret = -ENOMEM; 319 320 /* all elements are set to ZERO as default value */ 321 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL); 322 if (!ssusb) 323 return -ENOMEM; 324 325 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 326 if (ret) { 327 dev_err(dev, "No suitable DMA config available\n"); 328 return -ENOTSUPP; 329 } 330 331 platform_set_drvdata(pdev, ssusb); 332 ssusb->dev = dev; 333 334 ret = get_ssusb_rscs(pdev, ssusb); 335 if (ret) 336 return ret; 337 338 /* enable power domain */ 339 pm_runtime_enable(dev); 340 pm_runtime_get_sync(dev); 341 device_enable_async_suspend(dev); 342 343 ret = ssusb_rscs_init(ssusb); 344 if (ret) 345 goto comm_init_err; 346 347 ssusb_ip_sw_reset(ssusb); 348 349 if (IS_ENABLED(CONFIG_USB_MTU3_HOST)) 350 ssusb->dr_mode = USB_DR_MODE_HOST; 351 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET)) 352 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL; 353 354 /* default as host */ 355 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL); 356 357 switch (ssusb->dr_mode) { 358 case USB_DR_MODE_PERIPHERAL: 359 ret = ssusb_gadget_init(ssusb); 360 if (ret) { 361 dev_err(dev, "failed to initialize gadget\n"); 362 goto comm_exit; 363 } 364 break; 365 case USB_DR_MODE_HOST: 366 ret = ssusb_host_init(ssusb, node); 367 if (ret) { 368 dev_err(dev, "failed to initialize host\n"); 369 goto comm_exit; 370 } 371 break; 372 case USB_DR_MODE_OTG: 373 ret = ssusb_gadget_init(ssusb); 374 if (ret) { 375 dev_err(dev, "failed to initialize gadget\n"); 376 goto comm_exit; 377 } 378 379 ret = ssusb_host_init(ssusb, node); 380 if (ret) { 381 dev_err(dev, "failed to initialize host\n"); 382 goto gadget_exit; 383 } 384 385 ssusb_otg_switch_init(ssusb); 386 break; 387 default: 388 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode); 389 ret = -EINVAL; 390 goto comm_exit; 391 } 392 393 return 0; 394 395 gadget_exit: 396 ssusb_gadget_exit(ssusb); 397 comm_exit: 398 ssusb_rscs_exit(ssusb); 399 comm_init_err: 400 pm_runtime_put_sync(dev); 401 pm_runtime_disable(dev); 402 403 return ret; 404 } 405 406 static int mtu3_remove(struct platform_device *pdev) 407 { 408 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); 409 410 switch (ssusb->dr_mode) { 411 case USB_DR_MODE_PERIPHERAL: 412 ssusb_gadget_exit(ssusb); 413 break; 414 case USB_DR_MODE_HOST: 415 ssusb_host_exit(ssusb); 416 break; 417 case USB_DR_MODE_OTG: 418 ssusb_otg_switch_exit(ssusb); 419 ssusb_gadget_exit(ssusb); 420 ssusb_host_exit(ssusb); 421 break; 422 default: 423 return -EINVAL; 424 } 425 426 ssusb_rscs_exit(ssusb); 427 pm_runtime_put_sync(&pdev->dev); 428 pm_runtime_disable(&pdev->dev); 429 430 return 0; 431 } 432 433 /* 434 * when support dual-role mode, we reject suspend when 435 * it works as device mode; 436 */ 437 static int __maybe_unused mtu3_suspend(struct device *dev) 438 { 439 struct platform_device *pdev = to_platform_device(dev); 440 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); 441 442 dev_dbg(dev, "%s\n", __func__); 443 444 /* REVISIT: disconnect it for only device mode? */ 445 if (!ssusb->is_host) 446 return 0; 447 448 ssusb_host_disable(ssusb, true); 449 ssusb_phy_power_off(ssusb); 450 clk_disable_unprepare(ssusb->sys_clk); 451 clk_disable_unprepare(ssusb->ref_clk); 452 ssusb_wakeup_enable(ssusb); 453 454 return 0; 455 } 456 457 static int __maybe_unused mtu3_resume(struct device *dev) 458 { 459 struct platform_device *pdev = to_platform_device(dev); 460 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); 461 int ret; 462 463 dev_dbg(dev, "%s\n", __func__); 464 465 if (!ssusb->is_host) 466 return 0; 467 468 ssusb_wakeup_disable(ssusb); 469 ret = clk_prepare_enable(ssusb->sys_clk); 470 if (ret) 471 goto err_sys_clk; 472 473 ret = clk_prepare_enable(ssusb->ref_clk); 474 if (ret) 475 goto err_ref_clk; 476 477 ret = ssusb_phy_power_on(ssusb); 478 if (ret) 479 goto err_power_on; 480 481 ssusb_host_enable(ssusb); 482 483 return 0; 484 485 err_power_on: 486 clk_disable_unprepare(ssusb->ref_clk); 487 err_ref_clk: 488 clk_disable_unprepare(ssusb->sys_clk); 489 err_sys_clk: 490 return ret; 491 } 492 493 static const struct dev_pm_ops mtu3_pm_ops = { 494 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume) 495 }; 496 497 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL) 498 499 #ifdef CONFIG_OF 500 501 static const struct of_device_id mtu3_of_match[] = { 502 {.compatible = "mediatek,mt8173-mtu3",}, 503 {.compatible = "mediatek,mtu3",}, 504 {}, 505 }; 506 507 MODULE_DEVICE_TABLE(of, mtu3_of_match); 508 509 #endif 510 511 static struct platform_driver mtu3_driver = { 512 .probe = mtu3_probe, 513 .remove = mtu3_remove, 514 .driver = { 515 .name = MTU3_DRIVER_NAME, 516 .pm = DEV_PM_OPS, 517 .of_match_table = of_match_ptr(mtu3_of_match), 518 }, 519 }; 520 module_platform_driver(mtu3_driver); 521 522 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 523 MODULE_LICENSE("GPL v2"); 524 MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver"); 525