1 /* 2 * Copyright (C) 2016 MediaTek Inc. 3 * 4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/iopoll.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_irq.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 27 #include "mtu3.h" 28 #include "mtu3_dr.h" 29 30 /* u2-port0 should be powered on and enabled; */ 31 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks) 32 { 33 void __iomem *ibase = ssusb->ippc_base; 34 u32 value, check_val; 35 int ret; 36 37 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE | 38 SSUSB_REF_RST_B_STS; 39 40 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, 41 (check_val == (value & check_val)), 100, 20000); 42 if (ret) { 43 dev_err(ssusb->dev, "clks of sts1 are not stable!\n"); 44 return ret; 45 } 46 47 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, 48 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000); 49 if (ret) { 50 dev_err(ssusb->dev, "mac2 clock is not stable\n"); 51 return ret; 52 } 53 54 return 0; 55 } 56 57 static int ssusb_phy_init(struct ssusb_mtk *ssusb) 58 { 59 int i; 60 int ret; 61 62 for (i = 0; i < ssusb->num_phys; i++) { 63 ret = phy_init(ssusb->phys[i]); 64 if (ret) 65 goto exit_phy; 66 } 67 return 0; 68 69 exit_phy: 70 for (; i > 0; i--) 71 phy_exit(ssusb->phys[i - 1]); 72 73 return ret; 74 } 75 76 static int ssusb_phy_exit(struct ssusb_mtk *ssusb) 77 { 78 int i; 79 80 for (i = 0; i < ssusb->num_phys; i++) 81 phy_exit(ssusb->phys[i]); 82 83 return 0; 84 } 85 86 static int ssusb_phy_power_on(struct ssusb_mtk *ssusb) 87 { 88 int i; 89 int ret; 90 91 for (i = 0; i < ssusb->num_phys; i++) { 92 ret = phy_power_on(ssusb->phys[i]); 93 if (ret) 94 goto power_off_phy; 95 } 96 return 0; 97 98 power_off_phy: 99 for (; i > 0; i--) 100 phy_power_off(ssusb->phys[i - 1]); 101 102 return ret; 103 } 104 105 static void ssusb_phy_power_off(struct ssusb_mtk *ssusb) 106 { 107 unsigned int i; 108 109 for (i = 0; i < ssusb->num_phys; i++) 110 phy_power_off(ssusb->phys[i]); 111 } 112 113 static int ssusb_rscs_init(struct ssusb_mtk *ssusb) 114 { 115 int ret = 0; 116 117 ret = regulator_enable(ssusb->vusb33); 118 if (ret) { 119 dev_err(ssusb->dev, "failed to enable vusb33\n"); 120 goto vusb33_err; 121 } 122 123 ret = clk_prepare_enable(ssusb->sys_clk); 124 if (ret) { 125 dev_err(ssusb->dev, "failed to enable sys_clk\n"); 126 goto clk_err; 127 } 128 129 ret = ssusb_phy_init(ssusb); 130 if (ret) { 131 dev_err(ssusb->dev, "failed to init phy\n"); 132 goto phy_init_err; 133 } 134 135 ret = ssusb_phy_power_on(ssusb); 136 if (ret) { 137 dev_err(ssusb->dev, "failed to power on phy\n"); 138 goto phy_err; 139 } 140 141 return 0; 142 143 phy_err: 144 ssusb_phy_exit(ssusb); 145 phy_init_err: 146 clk_disable_unprepare(ssusb->sys_clk); 147 clk_err: 148 regulator_disable(ssusb->vusb33); 149 vusb33_err: 150 151 return ret; 152 } 153 154 static void ssusb_rscs_exit(struct ssusb_mtk *ssusb) 155 { 156 clk_disable_unprepare(ssusb->sys_clk); 157 regulator_disable(ssusb->vusb33); 158 ssusb_phy_power_off(ssusb); 159 ssusb_phy_exit(ssusb); 160 } 161 162 static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb) 163 { 164 /* reset whole ip (xhci & u3d) */ 165 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); 166 udelay(1); 167 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); 168 } 169 170 static int get_iddig_pinctrl(struct ssusb_mtk *ssusb) 171 { 172 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; 173 174 otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev); 175 if (IS_ERR(otg_sx->id_pinctrl)) { 176 dev_err(ssusb->dev, "Cannot find id pinctrl!\n"); 177 return PTR_ERR(otg_sx->id_pinctrl); 178 } 179 180 otg_sx->id_float = 181 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float"); 182 if (IS_ERR(otg_sx->id_float)) { 183 dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n"); 184 return PTR_ERR(otg_sx->id_float); 185 } 186 187 otg_sx->id_ground = 188 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground"); 189 if (IS_ERR(otg_sx->id_ground)) { 190 dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n"); 191 return PTR_ERR(otg_sx->id_ground); 192 } 193 194 return 0; 195 } 196 197 static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb) 198 { 199 struct device_node *node = pdev->dev.of_node; 200 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; 201 struct device *dev = &pdev->dev; 202 struct regulator *vbus; 203 struct resource *res; 204 int i; 205 int ret; 206 207 ssusb->num_phys = of_count_phandle_with_args(node, 208 "phys", "#phy-cells"); 209 if (ssusb->num_phys > 0) { 210 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys, 211 sizeof(*ssusb->phys), GFP_KERNEL); 212 if (!ssusb->phys) 213 return -ENOMEM; 214 } else { 215 ssusb->num_phys = 0; 216 } 217 218 for (i = 0; i < ssusb->num_phys; i++) { 219 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i); 220 if (IS_ERR(ssusb->phys[i])) { 221 dev_err(dev, "failed to get phy-%d\n", i); 222 return PTR_ERR(ssusb->phys[i]); 223 } 224 } 225 226 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 227 ssusb->ippc_base = devm_ioremap_resource(dev, res); 228 if (IS_ERR(ssusb->ippc_base)) { 229 dev_err(dev, "failed to map memory for ippc\n"); 230 return PTR_ERR(ssusb->ippc_base); 231 } 232 233 ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33"); 234 if (IS_ERR(ssusb->vusb33)) { 235 dev_err(dev, "failed to get vusb33\n"); 236 return PTR_ERR(ssusb->vusb33); 237 } 238 239 ssusb->sys_clk = devm_clk_get(dev, "sys_ck"); 240 if (IS_ERR(ssusb->sys_clk)) { 241 dev_err(dev, "failed to get sys clock\n"); 242 return PTR_ERR(ssusb->sys_clk); 243 } 244 245 ssusb->dr_mode = usb_get_dr_mode(dev); 246 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) { 247 dev_err(dev, "dr_mode is error\n"); 248 return -EINVAL; 249 } 250 251 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL) 252 return 0; 253 254 /* if host role is supported */ 255 ret = ssusb_wakeup_of_property_parse(ssusb, node); 256 if (ret) 257 return ret; 258 259 if (ssusb->dr_mode != USB_DR_MODE_OTG) 260 return 0; 261 262 /* if dual-role mode is supported */ 263 vbus = devm_regulator_get(&pdev->dev, "vbus"); 264 if (IS_ERR(vbus)) { 265 dev_err(dev, "failed to get vbus\n"); 266 return PTR_ERR(vbus); 267 } 268 otg_sx->vbus = vbus; 269 270 otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd"); 271 otg_sx->manual_drd_enabled = 272 of_property_read_bool(node, "enable-manual-drd"); 273 274 if (of_property_read_bool(node, "extcon")) { 275 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0); 276 if (IS_ERR(otg_sx->edev)) { 277 dev_err(ssusb->dev, "couldn't get extcon device\n"); 278 return -EPROBE_DEFER; 279 } 280 if (otg_sx->manual_drd_enabled) { 281 ret = get_iddig_pinctrl(ssusb); 282 if (ret) 283 return ret; 284 } 285 } 286 287 dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n", 288 ssusb->dr_mode, otg_sx->is_u3_drd); 289 290 return 0; 291 } 292 293 static int mtu3_probe(struct platform_device *pdev) 294 { 295 struct device_node *node = pdev->dev.of_node; 296 struct device *dev = &pdev->dev; 297 struct ssusb_mtk *ssusb; 298 int ret = -ENOMEM; 299 300 /* all elements are set to ZERO as default value */ 301 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL); 302 if (!ssusb) 303 return -ENOMEM; 304 305 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 306 if (ret) { 307 dev_err(dev, "No suitable DMA config available\n"); 308 return -ENOTSUPP; 309 } 310 311 platform_set_drvdata(pdev, ssusb); 312 ssusb->dev = dev; 313 314 ret = get_ssusb_rscs(pdev, ssusb); 315 if (ret) 316 return ret; 317 318 /* enable power domain */ 319 pm_runtime_enable(dev); 320 pm_runtime_get_sync(dev); 321 device_enable_async_suspend(dev); 322 323 ret = ssusb_rscs_init(ssusb); 324 if (ret) 325 goto comm_init_err; 326 327 ssusb_ip_sw_reset(ssusb); 328 329 if (IS_ENABLED(CONFIG_USB_MTU3_HOST)) 330 ssusb->dr_mode = USB_DR_MODE_HOST; 331 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET)) 332 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL; 333 334 /* default as host */ 335 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL); 336 337 switch (ssusb->dr_mode) { 338 case USB_DR_MODE_PERIPHERAL: 339 ret = ssusb_gadget_init(ssusb); 340 if (ret) { 341 dev_err(dev, "failed to initialize gadget\n"); 342 goto comm_exit; 343 } 344 break; 345 case USB_DR_MODE_HOST: 346 ret = ssusb_host_init(ssusb, node); 347 if (ret) { 348 dev_err(dev, "failed to initialize host\n"); 349 goto comm_exit; 350 } 351 break; 352 case USB_DR_MODE_OTG: 353 ret = ssusb_gadget_init(ssusb); 354 if (ret) { 355 dev_err(dev, "failed to initialize gadget\n"); 356 goto comm_exit; 357 } 358 359 ret = ssusb_host_init(ssusb, node); 360 if (ret) { 361 dev_err(dev, "failed to initialize host\n"); 362 goto gadget_exit; 363 } 364 365 ssusb_otg_switch_init(ssusb); 366 break; 367 default: 368 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode); 369 ret = -EINVAL; 370 goto comm_exit; 371 } 372 373 return 0; 374 375 gadget_exit: 376 ssusb_gadget_exit(ssusb); 377 comm_exit: 378 ssusb_rscs_exit(ssusb); 379 comm_init_err: 380 pm_runtime_put_sync(dev); 381 pm_runtime_disable(dev); 382 383 return ret; 384 } 385 386 static int mtu3_remove(struct platform_device *pdev) 387 { 388 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); 389 390 switch (ssusb->dr_mode) { 391 case USB_DR_MODE_PERIPHERAL: 392 ssusb_gadget_exit(ssusb); 393 break; 394 case USB_DR_MODE_HOST: 395 ssusb_host_exit(ssusb); 396 break; 397 case USB_DR_MODE_OTG: 398 ssusb_otg_switch_exit(ssusb); 399 ssusb_gadget_exit(ssusb); 400 ssusb_host_exit(ssusb); 401 break; 402 default: 403 return -EINVAL; 404 } 405 406 ssusb_rscs_exit(ssusb); 407 pm_runtime_put_sync(&pdev->dev); 408 pm_runtime_disable(&pdev->dev); 409 410 return 0; 411 } 412 413 /* 414 * when support dual-role mode, we reject suspend when 415 * it works as device mode; 416 */ 417 static int __maybe_unused mtu3_suspend(struct device *dev) 418 { 419 struct platform_device *pdev = to_platform_device(dev); 420 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); 421 422 dev_dbg(dev, "%s\n", __func__); 423 424 /* REVISIT: disconnect it for only device mode? */ 425 if (!ssusb->is_host) 426 return 0; 427 428 ssusb_host_disable(ssusb, true); 429 ssusb_phy_power_off(ssusb); 430 clk_disable_unprepare(ssusb->sys_clk); 431 ssusb_wakeup_enable(ssusb); 432 433 return 0; 434 } 435 436 static int __maybe_unused mtu3_resume(struct device *dev) 437 { 438 struct platform_device *pdev = to_platform_device(dev); 439 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); 440 441 dev_dbg(dev, "%s\n", __func__); 442 443 if (!ssusb->is_host) 444 return 0; 445 446 ssusb_wakeup_disable(ssusb); 447 clk_prepare_enable(ssusb->sys_clk); 448 ssusb_phy_power_on(ssusb); 449 ssusb_host_enable(ssusb); 450 451 return 0; 452 } 453 454 static const struct dev_pm_ops mtu3_pm_ops = { 455 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume) 456 }; 457 458 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL) 459 460 #ifdef CONFIG_OF 461 462 static const struct of_device_id mtu3_of_match[] = { 463 {.compatible = "mediatek,mt8173-mtu3",}, 464 {}, 465 }; 466 467 MODULE_DEVICE_TABLE(of, mtu3_of_match); 468 469 #endif 470 471 static struct platform_driver mtu3_driver = { 472 .probe = mtu3_probe, 473 .remove = mtu3_remove, 474 .driver = { 475 .name = MTU3_DRIVER_NAME, 476 .pm = DEV_PM_OPS, 477 .of_match_table = of_match_ptr(mtu3_of_match), 478 }, 479 }; 480 module_platform_driver(mtu3_driver); 481 482 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 483 MODULE_LICENSE("GPL v2"); 484 MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver"); 485