1 /* 2 * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions 3 * 4 * Copyright (C) 2016 MediaTek Inc. 5 * 6 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef _SSUSB_HW_REGS_H_ 20 #define _SSUSB_HW_REGS_H_ 21 22 /* segment offset of MAC register */ 23 #define SSUSB_DEV_BASE 0x0000 24 #define SSUSB_EPCTL_CSR_BASE 0x0800 25 #define SSUSB_USB3_MAC_CSR_BASE 0x1400 26 #define SSUSB_USB3_SYS_CSR_BASE 0x1400 27 #define SSUSB_USB2_CSR_BASE 0x2400 28 29 /* IPPC register in Infra */ 30 #define SSUSB_SIFSLV_IPPC_BASE 0x0000 31 32 /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */ 33 34 #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000) 35 #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004) 36 #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008) 37 #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C) 38 39 #define U3D_EPISR (SSUSB_DEV_BASE + 0x0080) 40 #define U3D_EPIER (SSUSB_DEV_BASE + 0x0084) 41 #define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088) 42 #define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C) 43 44 #define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100) 45 #define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108) 46 #define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C) 47 #define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110) 48 #define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114) 49 #define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118) 50 51 #define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210) 52 #define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214) 53 #define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218) 54 55 #define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300) 56 57 #define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400) 58 #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404) 59 #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408) 60 #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C) 61 62 #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510) 63 #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514) 64 #define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518) 65 66 #define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610) 67 #define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614) 68 #define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618) 69 #define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C) 70 71 #define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700) 72 #define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704) 73 #define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708) 74 #define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C) 75 #define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710) 76 #define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714) 77 #define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718) 78 #define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C) 79 80 #define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780) 81 #define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784) 82 #define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788) 83 #define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C) 84 #define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0) 85 #define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4) 86 #define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8) 87 #define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC) 88 #define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0) 89 #define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4) 90 #define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8) 91 #define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC) 92 93 #define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04) 94 #define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08) 95 #define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C) 96 #define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10) 97 #define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84) 98 99 /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/ 100 101 /* U3D_LV1ISR */ 102 #define EP_CTRL_INTR BIT(5) 103 #define MAC2_INTR BIT(4) 104 #define DMA_INTR BIT(3) 105 #define MAC3_INTR BIT(2) 106 #define QMU_INTR BIT(1) 107 #define BMU_INTR BIT(0) 108 109 /* U3D_LV1IECR */ 110 #define LV1IECR_MSK GENMASK(31, 0) 111 112 /* U3D_EPISR */ 113 #define EPRISR(x) (BIT(16) << (x)) 114 #define EPTISR(x) (BIT(0) << (x)) 115 #define EP0ISR BIT(0) 116 117 /* U3D_EP0CSR */ 118 #define EP0_SENDSTALL BIT(25) 119 #define EP0_FIFOFULL BIT(23) 120 #define EP0_SENTSTALL BIT(22) 121 #define EP0_DPHTX BIT(20) 122 #define EP0_DATAEND BIT(19) 123 #define EP0_TXPKTRDY BIT(18) 124 #define EP0_SETUPPKTRDY BIT(17) 125 #define EP0_RXPKTRDY BIT(16) 126 #define EP0_MAXPKTSZ_MSK GENMASK(9, 0) 127 #define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK) 128 #define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL)) 129 130 /* U3D_TX1CSR0 */ 131 #define TX_DMAREQEN BIT(29) 132 #define TX_FIFOFULL BIT(25) 133 #define TX_FIFOEMPTY BIT(24) 134 #define TX_SENTSTALL BIT(22) 135 #define TX_SENDSTALL BIT(21) 136 #define TX_TXPKTRDY BIT(16) 137 #define TX_TXMAXPKTSZ_MSK GENMASK(10, 0) 138 #define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK) 139 #define TX_W1C_BITS (~(TX_SENTSTALL)) 140 141 /* U3D_TX1CSR1 */ 142 #define TX_MULT(x) (((x) & 0x3) << 22) 143 #define TX_MAX_PKT(x) (((x) & 0x3f) << 16) 144 #define TX_SLOT(x) (((x) & 0x3f) << 8) 145 #define TX_TYPE(x) (((x) & 0x3) << 4) 146 #define TX_SS_BURST(x) (((x) & 0xf) << 0) 147 148 /* for TX_TYPE & RX_TYPE */ 149 #define TYPE_BULK (0x0) 150 #define TYPE_INT (0x1) 151 #define TYPE_ISO (0x2) 152 #define TYPE_MASK (0x3) 153 154 /* U3D_TX1CSR2 */ 155 #define TX_BINTERVAL(x) (((x) & 0xff) << 24) 156 #define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16) 157 #define TX_FIFOADDR(x) (((x) & 0x1fff) << 0) 158 159 /* U3D_RX1CSR0 */ 160 #define RX_DMAREQEN BIT(29) 161 #define RX_SENTSTALL BIT(22) 162 #define RX_SENDSTALL BIT(21) 163 #define RX_RXPKTRDY BIT(16) 164 #define RX_RXMAXPKTSZ_MSK GENMASK(10, 0) 165 #define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK) 166 #define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY)) 167 168 /* U3D_RX1CSR1 */ 169 #define RX_MULT(x) (((x) & 0x3) << 22) 170 #define RX_MAX_PKT(x) (((x) & 0x3f) << 16) 171 #define RX_SLOT(x) (((x) & 0x3f) << 8) 172 #define RX_TYPE(x) (((x) & 0x3) << 4) 173 #define RX_SS_BURST(x) (((x) & 0xf) << 0) 174 175 /* U3D_RX1CSR2 */ 176 #define RX_BINTERVAL(x) (((x) & 0xff) << 24) 177 #define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16) 178 #define RX_FIFOADDR(x) (((x) & 0x1fff) << 0) 179 180 /* U3D_QCR0 */ 181 #define QMU_RX_CS_EN(x) (BIT(16) << (x)) 182 #define QMU_TX_CS_EN(x) (BIT(0) << (x)) 183 #define QMU_CS16B_EN BIT(0) 184 185 /* U3D_QCR1 */ 186 #define QMU_TX_ZLP(x) (BIT(0) << (x)) 187 188 /* U3D_QCR3 */ 189 #define QMU_RX_COZ(x) (BIT(16) << (x)) 190 #define QMU_RX_ZLP(x) (BIT(0) << (x)) 191 192 /* U3D_TXQCSR1 */ 193 /* U3D_RXQCSR1 */ 194 #define QMU_Q_ACTIVE BIT(15) 195 #define QMU_Q_STOP BIT(2) 196 #define QMU_Q_RESUME BIT(1) 197 #define QMU_Q_START BIT(0) 198 199 /* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */ 200 #define QMU_RX_DONE_INT(x) (BIT(16) << (x)) 201 #define QMU_TX_DONE_INT(x) (BIT(0) << (x)) 202 203 /* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */ 204 #define RXQ_ZLPERR_INT BIT(20) 205 #define RXQ_LENERR_INT BIT(18) 206 #define RXQ_CSERR_INT BIT(17) 207 #define RXQ_EMPTY_INT BIT(16) 208 #define TXQ_LENERR_INT BIT(2) 209 #define TXQ_CSERR_INT BIT(1) 210 #define TXQ_EMPTY_INT BIT(0) 211 212 /* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */ 213 #define QMU_TX_LEN_ERR(x) (BIT(16) << (x)) 214 #define QMU_TX_CS_ERR(x) (BIT(0) << (x)) 215 216 /* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */ 217 #define QMU_RX_LEN_ERR(x) (BIT(16) << (x)) 218 #define QMU_RX_CS_ERR(x) (BIT(0) << (x)) 219 220 /* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */ 221 #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n)) 222 223 /* U3D_CAP_EPINFO */ 224 #define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f) 225 #define CAP_TX_EP_NUM(x) ((x) & 0x1f) 226 227 /* U3D_MISC_CTRL */ 228 #define VBUS_ON BIT(1) 229 #define VBUS_FRC_EN BIT(0) 230 231 232 /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/ 233 234 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000) 235 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004) 236 237 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050) 238 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054) 239 240 /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/ 241 242 /* U3D_DEVICE_CONF */ 243 #define DEV_ADDR_MSK GENMASK(30, 24) 244 #define DEV_ADDR(x) ((0x7f & (x)) << 24) 245 #define HW_USB2_3_SEL BIT(18) 246 #define SW_USB2_3_SEL_EN BIT(17) 247 #define SW_USB2_3_SEL BIT(16) 248 #define SSUSB_DEV_SPEED(x) ((x) & 0x7) 249 250 /* U3D_EP_RST */ 251 #define EP1_IN_RST BIT(17) 252 #define EP1_OUT_RST BIT(1) 253 #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum)) 254 #define EP0_RST BIT(0) 255 256 /* U3D_DEV_LINK_INTR_ENABLE */ 257 /* U3D_DEV_LINK_INTR */ 258 #define SSUSB_DEV_SPEED_CHG_INTR BIT(0) 259 260 261 /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/ 262 263 #define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010) 264 #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C) 265 266 #define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C) 267 #define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140) 268 269 /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/ 270 271 /* U3D_LTSSM_CTRL */ 272 #define FORCE_POLLING_FAIL BIT(4) 273 #define FORCE_RXDETECT_FAIL BIT(3) 274 #define SOFT_U3_EXIT_EN BIT(2) 275 #define COMPLIANCE_EN BIT(1) 276 #define U1_GO_U2_EN BIT(0) 277 278 /* U3D_USB3_CONFIG */ 279 #define USB3_EN BIT(0) 280 281 /* U3D_LTSSM_INTR_ENABLE */ 282 /* U3D_LTSSM_INTR */ 283 #define U3_RESUME_INTR BIT(18) 284 #define U3_LFPS_TMOUT_INTR BIT(17) 285 #define VBUS_FALL_INTR BIT(16) 286 #define VBUS_RISE_INTR BIT(15) 287 #define RXDET_SUCCESS_INTR BIT(14) 288 #define EXIT_U3_INTR BIT(13) 289 #define EXIT_U2_INTR BIT(12) 290 #define EXIT_U1_INTR BIT(11) 291 #define ENTER_U3_INTR BIT(10) 292 #define ENTER_U2_INTR BIT(9) 293 #define ENTER_U1_INTR BIT(8) 294 #define ENTER_U0_INTR BIT(7) 295 #define RECOVERY_INTR BIT(6) 296 #define WARM_RST_INTR BIT(5) 297 #define HOT_RST_INTR BIT(4) 298 #define LOOPBACK_INTR BIT(3) 299 #define COMPLIANCE_INTR BIT(2) 300 #define SS_DISABLE_INTR BIT(1) 301 #define SS_INACTIVE_INTR BIT(0) 302 303 /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/ 304 305 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C) 306 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210) 307 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214) 308 309 /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/ 310 311 /* U3D_LINK_UX_INACT_TIMER */ 312 #define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16) 313 #define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16) 314 #define U2_INACT_TIMEOUT_MSK GENMASK(15, 8) 315 #define U1_INACT_TIMEOUT_MSK GENMASK(7, 0) 316 #define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff) 317 318 /* U3D_LINK_POWER_CONTROL */ 319 #define SW_U2_ACCEPT_ENABLE BIT(9) 320 #define SW_U1_ACCEPT_ENABLE BIT(8) 321 #define UX_EXIT BIT(5) 322 #define LGO_U3 BIT(4) 323 #define LGO_U2 BIT(3) 324 #define LGO_U1 BIT(2) 325 #define SW_U2_REQUEST_ENABLE BIT(1) 326 #define SW_U1_REQUEST_ENABLE BIT(0) 327 328 /* U3D_LINK_ERR_COUNT */ 329 #define CLR_LINK_ERR_CNT BIT(16) 330 #define LINK_ERROR_COUNT GENMASK(15, 0) 331 332 /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/ 333 334 #define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004) 335 #define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C) 336 #define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014) 337 #define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018) 338 #define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C) 339 #define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024) 340 #define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C) 341 #define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044) 342 #define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C) 343 344 /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/ 345 346 /* U3D_POWER_MANAGEMENT */ 347 #define LPM_BESL_STALL BIT(14) 348 #define LPM_BESLD_STALL BIT(13) 349 #define LPM_RWP BIT(11) 350 #define LPM_HRWE BIT(10) 351 #define LPM_MODE(x) (((x) & 0x3) << 8) 352 #define ISO_UPDATE BIT(7) 353 #define SOFT_CONN BIT(6) 354 #define HS_ENABLE BIT(5) 355 #define RESUME BIT(2) 356 #define SUSPENDM_ENABLE BIT(0) 357 358 /* U3D_DEVICE_CONTROL */ 359 #define DC_HOSTREQ BIT(1) 360 #define DC_SESSION BIT(0) 361 362 /* U3D_USB2_TEST_MODE */ 363 #define U2U3_AUTO_SWITCH BIT(10) 364 #define LPM_FORCE_STALL BIT(8) 365 #define FIFO_ACCESS BIT(6) 366 #define FORCE_FS BIT(5) 367 #define FORCE_HS BIT(4) 368 #define TEST_PACKET_MODE BIT(3) 369 #define TEST_K_MODE BIT(2) 370 #define TEST_J_MODE BIT(1) 371 #define TEST_SE0_NAK_MODE BIT(0) 372 373 /* U3D_COMMON_USB_INTR_ENABLE */ 374 /* U3D_COMMON_USB_INTR */ 375 #define LPM_RESUME_INTR BIT(9) 376 #define LPM_INTR BIT(8) 377 #define DISCONN_INTR BIT(5) 378 #define CONN_INTR BIT(4) 379 #define SOF_INTR BIT(3) 380 #define RESET_INTR BIT(2) 381 #define RESUME_INTR BIT(1) 382 #define SUSPEND_INTR BIT(0) 383 384 /* U3D_LINK_RESET_INFO */ 385 #define WTCHRP_MSK GENMASK(19, 16) 386 387 /* U3D_USB20_LPM_PARAMETER */ 388 #define LPM_BESLCK_U3(x) (((x) & 0xf) << 12) 389 #define LPM_BESLCK(x) (((x) & 0xf) << 8) 390 #define LPM_BESLDCK(x) (((x) & 0xf) << 4) 391 #define LPM_BESL GENMASK(3, 0) 392 393 /* U3D_USB20_MISC_CONTROL */ 394 #define LPM_U3_ACK_EN BIT(0) 395 396 /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/ 397 398 #define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000) 399 #define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004) 400 #define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008) 401 #define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C) 402 #define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010) 403 #define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014) 404 #define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018) 405 #define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C) 406 #define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024) 407 #define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028) 408 #define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C) 409 #define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030) 410 #define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050) 411 #define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C) 412 #define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098) 413 #define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0) 414 #define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4) 415 #define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8) 416 417 /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/ 418 419 /* U3D_SSUSB_IP_PW_CTRL0 */ 420 #define SSUSB_IP_SW_RST BIT(0) 421 422 /* U3D_SSUSB_IP_PW_CTRL1 */ 423 #define SSUSB_IP_HOST_PDN BIT(0) 424 425 /* U3D_SSUSB_IP_PW_CTRL2 */ 426 #define SSUSB_IP_DEV_PDN BIT(0) 427 428 /* U3D_SSUSB_IP_PW_CTRL3 */ 429 #define SSUSB_IP_PCIE_PDN BIT(0) 430 431 /* U3D_SSUSB_IP_PW_STS1 */ 432 #define SSUSB_IP_SLEEP_STS BIT(30) 433 #define SSUSB_U3_MAC_RST_B_STS BIT(16) 434 #define SSUSB_XHCI_RST_B_STS BIT(11) 435 #define SSUSB_SYS125_RST_B_STS BIT(10) 436 #define SSUSB_REF_RST_B_STS BIT(8) 437 #define SSUSB_SYSPLL_STABLE BIT(0) 438 439 /* U3D_SSUSB_IP_PW_STS2 */ 440 #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0) 441 442 /* U3D_SSUSB_OTG_STS */ 443 #define SSUSB_VBUS_VALID BIT(9) 444 445 /* U3D_SSUSB_OTG_STS_CLR */ 446 #define SSUSB_VBUS_INTR_CLR BIT(6) 447 448 /* U3D_SSUSB_IP_XHCI_CAP */ 449 #define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff) 450 #define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff) 451 452 /* U3D_SSUSB_IP_DEV_CAP */ 453 #define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff) 454 455 /* U3D_SSUSB_OTG_INT_EN */ 456 #define SSUSB_VBUS_CHG_INT_A_EN BIT(7) 457 #define SSUSB_VBUS_CHG_INT_B_EN BIT(6) 458 459 /* U3D_SSUSB_U3_CTRL_0P */ 460 #define SSUSB_U3_PORT_HOST_SEL BIT(2) 461 #define SSUSB_U3_PORT_PDN BIT(1) 462 #define SSUSB_U3_PORT_DIS BIT(0) 463 464 /* U3D_SSUSB_U2_CTRL_0P */ 465 #define SSUSB_U2_PORT_OTG_SEL BIT(7) 466 #define SSUSB_U2_PORT_HOST_SEL BIT(2) 467 #define SSUSB_U2_PORT_PDN BIT(1) 468 #define SSUSB_U2_PORT_DIS BIT(0) 469 470 /* U3D_SSUSB_DEV_RST_CTRL */ 471 #define SSUSB_DEV_SW_RST BIT(0) 472 473 #endif /* _SSUSB_HW_REGS_H_ */ 474