1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mtu3_core.c - hardware access layer and gadget init/exit of 4 * MediaTek usb3 Dual-Role Controller Driver 5 * 6 * Copyright (C) 2016 MediaTek Inc. 7 * 8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 9 */ 10 11 #include <linux/dma-mapping.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 #include <linux/platform_device.h> 17 18 #include "mtu3.h" 19 #include "mtu3_dr.h" 20 #include "mtu3_debug.h" 21 #include "mtu3_trace.h" 22 23 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size) 24 { 25 struct mtu3_fifo_info *fifo = mep->fifo; 26 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT); 27 u32 start_bit; 28 29 /* ensure that @mep->fifo_seg_size is power of two */ 30 num_bits = roundup_pow_of_two(num_bits); 31 if (num_bits > fifo->limit) 32 return -EINVAL; 33 34 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT; 35 num_bits = num_bits * (mep->slot + 1); 36 start_bit = bitmap_find_next_zero_area(fifo->bitmap, 37 fifo->limit, 0, num_bits, 0); 38 if (start_bit >= fifo->limit) 39 return -EOVERFLOW; 40 41 bitmap_set(fifo->bitmap, start_bit, num_bits); 42 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT; 43 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit; 44 45 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n", 46 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit); 47 48 return mep->fifo_addr; 49 } 50 51 static void ep_fifo_free(struct mtu3_ep *mep) 52 { 53 struct mtu3_fifo_info *fifo = mep->fifo; 54 u32 addr = mep->fifo_addr; 55 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT; 56 u32 start_bit; 57 58 if (unlikely(addr < fifo->base || bits > fifo->limit)) 59 return; 60 61 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT; 62 bitmap_clear(fifo->bitmap, start_bit, bits); 63 mep->fifo_size = 0; 64 mep->fifo_seg_size = 0; 65 66 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n", 67 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit); 68 } 69 70 /* enable/disable U3D SS function */ 71 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable) 72 { 73 /* If usb3_en==0, LTSSM will go to SS.Disable state */ 74 if (enable) 75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); 76 else 77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); 78 79 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable); 80 } 81 82 /* set/clear U3D HS device soft connect */ 83 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable) 84 { 85 if (enable) { 86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, 87 SOFT_CONN | SUSPENDM_ENABLE); 88 } else { 89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, 90 SOFT_CONN | SUSPENDM_ENABLE); 91 } 92 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable); 93 } 94 95 /* only port0 of U2/U3 supports device mode */ 96 static int mtu3_device_enable(struct mtu3 *mtu) 97 { 98 void __iomem *ibase = mtu->ippc_base; 99 u32 check_clk = 0; 100 101 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 102 103 if (mtu->is_u3_ip) { 104 check_clk = SSUSB_U3_MAC_RST_B_STS; 105 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), 106 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN | 107 SSUSB_U3_PORT_HOST_SEL)); 108 } 109 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), 110 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN | 111 SSUSB_U2_PORT_HOST_SEL)); 112 113 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) { 114 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); 115 if (mtu->is_u3_ip) 116 mtu3_setbits(ibase, SSUSB_U3_CTRL(0), 117 SSUSB_U3_PORT_DUAL_MODE); 118 } 119 120 return ssusb_check_clocks(mtu->ssusb, check_clk); 121 } 122 123 static void mtu3_device_disable(struct mtu3 *mtu) 124 { 125 void __iomem *ibase = mtu->ippc_base; 126 127 if (mtu->is_u3_ip) 128 mtu3_setbits(ibase, SSUSB_U3_CTRL(0), 129 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN)); 130 131 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), 132 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN); 133 134 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) { 135 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); 136 if (mtu->is_u3_ip) 137 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), 138 SSUSB_U3_PORT_DUAL_MODE); 139 } 140 141 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 142 } 143 144 /* reset U3D's device module. */ 145 static void mtu3_device_reset(struct mtu3 *mtu) 146 { 147 void __iomem *ibase = mtu->ippc_base; 148 149 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); 150 udelay(1); 151 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); 152 } 153 154 static void mtu3_intr_status_clear(struct mtu3 *mtu) 155 { 156 void __iomem *mbase = mtu->mac_base; 157 158 /* Clear EP0 and Tx/Rx EPn interrupts status */ 159 mtu3_writel(mbase, U3D_EPISR, ~0x0); 160 /* Clear U2 USB common interrupts status */ 161 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0); 162 /* Clear U3 LTSSM interrupts status */ 163 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0); 164 /* Clear speed change interrupt status */ 165 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0); 166 /* Clear QMU interrupt status */ 167 mtu3_writel(mbase, U3D_QISAR0, ~0x0); 168 } 169 170 /* disable all interrupts */ 171 static void mtu3_intr_disable(struct mtu3 *mtu) 172 { 173 /* Disable level 1 interrupts */ 174 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0); 175 /* Disable endpoint interrupts */ 176 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0); 177 mtu3_intr_status_clear(mtu); 178 } 179 180 /* enable system global interrupt */ 181 static void mtu3_intr_enable(struct mtu3 *mtu) 182 { 183 void __iomem *mbase = mtu->mac_base; 184 u32 value; 185 186 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */ 187 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR; 188 mtu3_writel(mbase, U3D_LV1IESR, value); 189 190 /* Enable U2 common USB interrupts */ 191 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR; 192 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value); 193 194 if (mtu->is_u3_ip) { 195 /* Enable U3 LTSSM interrupts */ 196 value = HOT_RST_INTR | WARM_RST_INTR | 197 ENTER_U3_INTR | EXIT_U3_INTR; 198 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value); 199 } 200 201 /* Enable QMU interrupts. */ 202 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT | 203 RXQ_LENERR_INT | RXQ_ZLPERR_INT; 204 mtu3_writel(mbase, U3D_QIESR1, value); 205 206 /* Enable speed change interrupt */ 207 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR); 208 } 209 210 static void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed) 211 { 212 void __iomem *mbase = mtu->mac_base; 213 214 if (speed > mtu->max_speed) 215 speed = mtu->max_speed; 216 217 switch (speed) { 218 case USB_SPEED_FULL: 219 /* disable U3 SS function */ 220 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN); 221 /* disable HS function */ 222 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); 223 break; 224 case USB_SPEED_HIGH: 225 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN); 226 /* HS/FS detected by HW */ 227 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); 228 break; 229 case USB_SPEED_SUPER: 230 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0), 231 SSUSB_U3_PORT_SSP_SPEED); 232 break; 233 case USB_SPEED_SUPER_PLUS: 234 mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0), 235 SSUSB_U3_PORT_SSP_SPEED); 236 break; 237 default: 238 dev_err(mtu->dev, "invalid speed: %s\n", 239 usb_speed_string(speed)); 240 return; 241 } 242 243 mtu->speed = speed; 244 dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed)); 245 } 246 247 /* CSR registers will be reset to default value if port is disabled */ 248 static void mtu3_csr_init(struct mtu3 *mtu) 249 { 250 void __iomem *mbase = mtu->mac_base; 251 252 if (mtu->is_u3_ip) { 253 /* disable LGO_U1/U2 by default */ 254 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL, 255 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE); 256 /* enable accept LGO_U1/U2 link command from host */ 257 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL, 258 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE); 259 /* device responses to u3_exit from host automatically */ 260 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN); 261 /* automatically build U2 link when U3 detect fail */ 262 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH); 263 /* auto clear SOFT_CONN when clear USB3_EN if work as HS */ 264 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN); 265 } 266 267 /* delay about 0.1us from detecting reset to send chirp-K */ 268 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK); 269 /* enable automatical HWRW from L1 */ 270 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE); 271 } 272 273 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */ 274 static void mtu3_ep_reset(struct mtu3_ep *mep) 275 { 276 struct mtu3 *mtu = mep->mtu; 277 u32 rst_bit = EP_RST(mep->is_in, mep->epnum); 278 279 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit); 280 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit); 281 } 282 283 /* set/clear the stall and toggle bits for non-ep0 */ 284 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set) 285 { 286 struct mtu3 *mtu = mep->mtu; 287 void __iomem *mbase = mtu->mac_base; 288 u8 epnum = mep->epnum; 289 u32 csr; 290 291 if (mep->is_in) { /* TX */ 292 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS; 293 if (set) 294 csr |= TX_SENDSTALL; 295 else 296 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL; 297 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr); 298 } else { /* RX */ 299 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS; 300 if (set) 301 csr |= RX_SENDSTALL; 302 else 303 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL; 304 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr); 305 } 306 307 if (!set) { 308 mtu3_ep_reset(mep); 309 mep->flags &= ~MTU3_EP_STALL; 310 } else { 311 mep->flags |= MTU3_EP_STALL; 312 } 313 314 dev_dbg(mtu->dev, "%s: %s\n", mep->name, 315 set ? "SEND STALL" : "CLEAR STALL, with EP RESET"); 316 } 317 318 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on) 319 { 320 if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER) 321 mtu3_ss_func_set(mtu, is_on); 322 else 323 mtu3_hs_softconn_set(mtu, is_on); 324 325 dev_info(mtu->dev, "gadget (%s) pullup D%s\n", 326 usb_speed_string(mtu->speed), is_on ? "+" : "-"); 327 } 328 329 void mtu3_start(struct mtu3 *mtu) 330 { 331 void __iomem *mbase = mtu->mac_base; 332 333 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__, 334 mtu3_readl(mbase, U3D_DEVICE_CONTROL)); 335 336 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 337 if (mtu->is_u3_ip) 338 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN); 339 340 mtu3_clrbits(mtu->ippc_base, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN); 341 342 mtu3_csr_init(mtu); 343 mtu3_set_speed(mtu, mtu->speed); 344 345 /* Initialize the default interrupts */ 346 mtu3_intr_enable(mtu); 347 mtu->is_active = 1; 348 349 if (mtu->softconnect) 350 mtu3_dev_on_off(mtu, 1); 351 } 352 353 void mtu3_stop(struct mtu3 *mtu) 354 { 355 dev_dbg(mtu->dev, "%s\n", __func__); 356 357 mtu3_intr_disable(mtu); 358 359 if (mtu->softconnect) 360 mtu3_dev_on_off(mtu, 0); 361 362 mtu->is_active = 0; 363 364 if (mtu->is_u3_ip) 365 mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN); 366 367 mtu3_setbits(mtu->ippc_base, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN); 368 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 369 } 370 371 /* for non-ep0 */ 372 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep, 373 int interval, int burst, int mult) 374 { 375 void __iomem *mbase = mtu->mac_base; 376 bool gen2cp = mtu->gen2cp; 377 int epnum = mep->epnum; 378 u32 csr0, csr1, csr2; 379 int fifo_sgsz, fifo_addr; 380 int num_pkts; 381 382 fifo_addr = ep_fifo_alloc(mep, mep->maxp); 383 if (fifo_addr < 0) { 384 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp); 385 return -ENOMEM; 386 } 387 fifo_sgsz = ilog2(mep->fifo_seg_size); 388 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz, 389 mep->fifo_seg_size, mep->fifo_size); 390 391 if (mep->is_in) { 392 csr0 = TX_TXMAXPKTSZ(mep->maxp); 393 csr0 |= TX_DMAREQEN; 394 395 num_pkts = (burst + 1) * (mult + 1) - 1; 396 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot); 397 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult); 398 399 csr2 = TX_FIFOADDR(fifo_addr >> 4); 400 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz); 401 402 switch (mep->type) { 403 case USB_ENDPOINT_XFER_BULK: 404 csr1 |= TX_TYPE(TYPE_BULK); 405 break; 406 case USB_ENDPOINT_XFER_ISOC: 407 csr1 |= TX_TYPE(TYPE_ISO); 408 csr2 |= TX_BINTERVAL(interval); 409 break; 410 case USB_ENDPOINT_XFER_INT: 411 csr1 |= TX_TYPE(TYPE_INT); 412 csr2 |= TX_BINTERVAL(interval); 413 break; 414 } 415 416 /* Enable QMU Done interrupt */ 417 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum)); 418 419 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0); 420 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1); 421 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2); 422 423 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n", 424 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)), 425 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)), 426 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum))); 427 } else { 428 csr0 = RX_RXMAXPKTSZ(mep->maxp); 429 csr0 |= RX_DMAREQEN; 430 431 num_pkts = (burst + 1) * (mult + 1) - 1; 432 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot); 433 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult); 434 435 csr2 = RX_FIFOADDR(fifo_addr >> 4); 436 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz); 437 438 switch (mep->type) { 439 case USB_ENDPOINT_XFER_BULK: 440 csr1 |= RX_TYPE(TYPE_BULK); 441 break; 442 case USB_ENDPOINT_XFER_ISOC: 443 csr1 |= RX_TYPE(TYPE_ISO); 444 csr2 |= RX_BINTERVAL(interval); 445 break; 446 case USB_ENDPOINT_XFER_INT: 447 csr1 |= RX_TYPE(TYPE_INT); 448 csr2 |= RX_BINTERVAL(interval); 449 break; 450 } 451 452 /*Enable QMU Done interrupt */ 453 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum)); 454 455 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0); 456 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1); 457 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2); 458 459 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n", 460 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)), 461 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)), 462 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum))); 463 } 464 465 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2); 466 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n", 467 __func__, mep->name, mep->fifo_addr, mep->fifo_size, 468 fifo_sgsz, mep->fifo_seg_size); 469 470 return 0; 471 } 472 473 /* for non-ep0 */ 474 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep) 475 { 476 void __iomem *mbase = mtu->mac_base; 477 int epnum = mep->epnum; 478 479 if (mep->is_in) { 480 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0); 481 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0); 482 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0); 483 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum)); 484 } else { 485 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0); 486 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0); 487 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0); 488 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum)); 489 } 490 491 mtu3_ep_reset(mep); 492 ep_fifo_free(mep); 493 494 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name); 495 } 496 497 /* 498 * Two scenarios: 499 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs 500 * are separated; 501 * 2. when supports only HS, the fifo is shared for all EPs, and 502 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate 503 * the total fifo size of non-ep0, and ep0's is fixed to 64B, 504 * so the total fifo size is 64B + @EPNTXFFSZ; 505 * Due to the first 64B should be reserved for EP0, non-ep0's fifo 506 * starts from offset 64 and are divided into two equal parts for 507 * TX or RX EPs for simplification. 508 */ 509 static void get_ep_fifo_config(struct mtu3 *mtu) 510 { 511 struct mtu3_fifo_info *tx_fifo; 512 struct mtu3_fifo_info *rx_fifo; 513 u32 fifosize; 514 515 if (mtu->is_u3_ip) { 516 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ); 517 tx_fifo = &mtu->tx_fifo; 518 tx_fifo->base = 0; 519 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT; 520 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 521 522 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ); 523 rx_fifo = &mtu->rx_fifo; 524 rx_fifo->base = 0; 525 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT; 526 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 527 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT; 528 } else { 529 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ); 530 tx_fifo = &mtu->tx_fifo; 531 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE; 532 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1; 533 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 534 535 rx_fifo = &mtu->rx_fifo; 536 rx_fifo->base = 537 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT; 538 rx_fifo->limit = tx_fifo->limit; 539 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 540 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT; 541 } 542 543 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n", 544 __func__, tx_fifo->base, tx_fifo->limit, 545 rx_fifo->base, rx_fifo->limit); 546 } 547 548 static void mtu3_ep0_setup(struct mtu3 *mtu) 549 { 550 u32 maxpacket = mtu->g.ep0->maxpacket; 551 u32 csr; 552 553 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket); 554 555 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR); 556 csr &= ~EP0_MAXPKTSZ_MSK; 557 csr |= EP0_MAXPKTSZ(maxpacket); 558 csr &= EP0_W1C_BITS; 559 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); 560 561 /* Enable EP0 interrupt */ 562 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR); 563 } 564 565 static int mtu3_mem_alloc(struct mtu3 *mtu) 566 { 567 void __iomem *mbase = mtu->mac_base; 568 struct mtu3_ep *ep_array; 569 int in_ep_num, out_ep_num; 570 u32 cap_epinfo; 571 int ret; 572 int i; 573 574 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO); 575 in_ep_num = CAP_TX_EP_NUM(cap_epinfo); 576 out_ep_num = CAP_RX_EP_NUM(cap_epinfo); 577 578 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n", 579 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num, 580 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num); 581 582 /* one for ep0, another is reserved */ 583 mtu->num_eps = min(in_ep_num, out_ep_num) + 1; 584 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL); 585 if (ep_array == NULL) 586 return -ENOMEM; 587 588 mtu->ep_array = ep_array; 589 mtu->in_eps = ep_array; 590 mtu->out_eps = &ep_array[mtu->num_eps]; 591 /* ep0 uses in_eps[0], out_eps[0] is reserved */ 592 mtu->ep0 = mtu->in_eps; 593 mtu->ep0->mtu = mtu; 594 mtu->ep0->epnum = 0; 595 596 for (i = 1; i < mtu->num_eps; i++) { 597 struct mtu3_ep *mep = mtu->in_eps + i; 598 599 mep->fifo = &mtu->tx_fifo; 600 mep = mtu->out_eps + i; 601 mep->fifo = &mtu->rx_fifo; 602 } 603 604 get_ep_fifo_config(mtu); 605 606 ret = mtu3_qmu_init(mtu); 607 if (ret) 608 kfree(mtu->ep_array); 609 610 return ret; 611 } 612 613 static void mtu3_mem_free(struct mtu3 *mtu) 614 { 615 mtu3_qmu_exit(mtu); 616 kfree(mtu->ep_array); 617 } 618 619 static void mtu3_regs_init(struct mtu3 *mtu) 620 { 621 void __iomem *mbase = mtu->mac_base; 622 623 /* be sure interrupts are disabled before registration of ISR */ 624 mtu3_intr_disable(mtu); 625 626 mtu3_csr_init(mtu); 627 628 /* U2/U3 detected by HW */ 629 mtu3_writel(mbase, U3D_DEVICE_CONF, 0); 630 /* vbus detected by HW */ 631 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON); 632 /* use new QMU format when HW version >= 0x1003 */ 633 if (mtu->gen2cp) 634 mtu3_writel(mbase, U3D_QFCR, ~0x0); 635 } 636 637 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu) 638 { 639 void __iomem *mbase = mtu->mac_base; 640 enum usb_device_speed udev_speed; 641 u32 maxpkt = 64; 642 u32 link; 643 u32 speed; 644 645 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR); 646 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE); 647 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */ 648 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link); 649 650 if (!(link & SSUSB_DEV_SPEED_CHG_INTR)) 651 return IRQ_NONE; 652 653 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF)); 654 655 switch (speed) { 656 case MTU3_SPEED_FULL: 657 udev_speed = USB_SPEED_FULL; 658 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */ 659 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf) 660 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa)); 661 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, 662 LPM_BESL_STALL | LPM_BESLD_STALL); 663 break; 664 case MTU3_SPEED_HIGH: 665 udev_speed = USB_SPEED_HIGH; 666 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */ 667 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf) 668 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa)); 669 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, 670 LPM_BESL_STALL | LPM_BESLD_STALL); 671 break; 672 case MTU3_SPEED_SUPER: 673 udev_speed = USB_SPEED_SUPER; 674 maxpkt = 512; 675 break; 676 case MTU3_SPEED_SUPER_PLUS: 677 udev_speed = USB_SPEED_SUPER_PLUS; 678 maxpkt = 512; 679 break; 680 default: 681 udev_speed = USB_SPEED_UNKNOWN; 682 break; 683 } 684 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed)); 685 mtu3_dbg_trace(mtu->dev, "link speed %s", 686 usb_speed_string(udev_speed)); 687 688 mtu->g.speed = udev_speed; 689 mtu->g.ep0->maxpacket = maxpkt; 690 mtu->ep0_state = MU3D_EP0_STATE_SETUP; 691 692 if (udev_speed == USB_SPEED_UNKNOWN) 693 mtu3_gadget_disconnect(mtu); 694 else 695 mtu3_ep0_setup(mtu); 696 697 return IRQ_HANDLED; 698 } 699 700 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu) 701 { 702 void __iomem *mbase = mtu->mac_base; 703 u32 ltssm; 704 705 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR); 706 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE); 707 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */ 708 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm); 709 trace_mtu3_u3_ltssm_isr(ltssm); 710 711 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR)) 712 mtu3_gadget_reset(mtu); 713 714 if (ltssm & VBUS_FALL_INTR) { 715 mtu3_ss_func_set(mtu, false); 716 mtu3_gadget_reset(mtu); 717 } 718 719 if (ltssm & VBUS_RISE_INTR) 720 mtu3_ss_func_set(mtu, true); 721 722 if (ltssm & EXIT_U3_INTR) 723 mtu3_gadget_resume(mtu); 724 725 if (ltssm & ENTER_U3_INTR) 726 mtu3_gadget_suspend(mtu); 727 728 return IRQ_HANDLED; 729 } 730 731 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu) 732 { 733 void __iomem *mbase = mtu->mac_base; 734 u32 u2comm; 735 736 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR); 737 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE); 738 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */ 739 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm); 740 trace_mtu3_u2_common_isr(u2comm); 741 742 if (u2comm & SUSPEND_INTR) 743 mtu3_gadget_suspend(mtu); 744 745 if (u2comm & RESUME_INTR) 746 mtu3_gadget_resume(mtu); 747 748 if (u2comm & RESET_INTR) 749 mtu3_gadget_reset(mtu); 750 751 return IRQ_HANDLED; 752 } 753 754 static irqreturn_t mtu3_irq(int irq, void *data) 755 { 756 struct mtu3 *mtu = (struct mtu3 *)data; 757 unsigned long flags; 758 u32 level1; 759 760 spin_lock_irqsave(&mtu->lock, flags); 761 762 /* U3D_LV1ISR is RU */ 763 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR); 764 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER); 765 766 if (level1 & EP_CTRL_INTR) 767 mtu3_link_isr(mtu); 768 769 if (level1 & MAC2_INTR) 770 mtu3_u2_common_isr(mtu); 771 772 if (level1 & MAC3_INTR) 773 mtu3_u3_ltssm_isr(mtu); 774 775 if (level1 & BMU_INTR) 776 mtu3_ep0_isr(mtu); 777 778 if (level1 & QMU_INTR) 779 mtu3_qmu_isr(mtu); 780 781 spin_unlock_irqrestore(&mtu->lock, flags); 782 783 return IRQ_HANDLED; 784 } 785 786 static void mtu3_check_params(struct mtu3 *mtu) 787 { 788 /* check the max_speed parameter */ 789 switch (mtu->max_speed) { 790 case USB_SPEED_FULL: 791 case USB_SPEED_HIGH: 792 case USB_SPEED_SUPER: 793 case USB_SPEED_SUPER_PLUS: 794 break; 795 default: 796 dev_err(mtu->dev, "invalid max_speed: %s\n", 797 usb_speed_string(mtu->max_speed)); 798 fallthrough; 799 case USB_SPEED_UNKNOWN: 800 /* default as SSP */ 801 mtu->max_speed = USB_SPEED_SUPER_PLUS; 802 break; 803 } 804 805 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH)) 806 mtu->max_speed = USB_SPEED_HIGH; 807 808 mtu->speed = mtu->max_speed; 809 810 dev_info(mtu->dev, "max_speed: %s\n", 811 usb_speed_string(mtu->max_speed)); 812 } 813 814 static int mtu3_hw_init(struct mtu3 *mtu) 815 { 816 u32 value; 817 int ret; 818 819 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS); 820 mtu->hw_version = IP_TRUNK_VERS(value); 821 mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003); 822 823 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP); 824 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value); 825 826 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version, 827 mtu->is_u3_ip ? "U3" : "U2"); 828 829 mtu3_check_params(mtu); 830 831 mtu3_device_reset(mtu); 832 833 ret = mtu3_device_enable(mtu); 834 if (ret) { 835 dev_err(mtu->dev, "device enable failed %d\n", ret); 836 return ret; 837 } 838 839 ret = mtu3_mem_alloc(mtu); 840 if (ret) 841 return -ENOMEM; 842 843 mtu3_regs_init(mtu); 844 845 return 0; 846 } 847 848 static void mtu3_hw_exit(struct mtu3 *mtu) 849 { 850 mtu3_device_disable(mtu); 851 mtu3_mem_free(mtu); 852 } 853 854 /* 855 * we set 32-bit DMA mask by default, here check whether the controller 856 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask. 857 */ 858 static int mtu3_set_dma_mask(struct mtu3 *mtu) 859 { 860 struct device *dev = mtu->dev; 861 bool is_36bit = false; 862 int ret = 0; 863 u32 value; 864 865 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL); 866 if (value & DMA_ADDR_36BIT) { 867 is_36bit = true; 868 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); 869 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */ 870 if (ret) { 871 is_36bit = false; 872 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 873 } 874 } 875 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32"); 876 877 return ret; 878 } 879 880 int ssusb_gadget_init(struct ssusb_mtk *ssusb) 881 { 882 struct device *dev = ssusb->dev; 883 struct platform_device *pdev = to_platform_device(dev); 884 struct mtu3 *mtu = NULL; 885 int ret = -ENOMEM; 886 887 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL); 888 if (mtu == NULL) 889 return -ENOMEM; 890 891 mtu->irq = platform_get_irq(pdev, 0); 892 if (mtu->irq < 0) 893 return mtu->irq; 894 dev_info(dev, "irq %d\n", mtu->irq); 895 896 mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac"); 897 if (IS_ERR(mtu->mac_base)) { 898 dev_err(dev, "error mapping memory for dev mac\n"); 899 return PTR_ERR(mtu->mac_base); 900 } 901 902 spin_lock_init(&mtu->lock); 903 mtu->dev = dev; 904 mtu->ippc_base = ssusb->ippc_base; 905 ssusb->mac_base = mtu->mac_base; 906 ssusb->u3d = mtu; 907 mtu->ssusb = ssusb; 908 mtu->max_speed = usb_get_maximum_speed(dev); 909 910 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n", 911 mtu->mac_base, mtu->ippc_base); 912 913 ret = mtu3_hw_init(mtu); 914 if (ret) { 915 dev_err(dev, "mtu3 hw init failed:%d\n", ret); 916 return ret; 917 } 918 919 ret = mtu3_set_dma_mask(mtu); 920 if (ret) { 921 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret); 922 goto dma_mask_err; 923 } 924 925 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu); 926 if (ret) { 927 dev_err(dev, "request irq %d failed!\n", mtu->irq); 928 goto irq_err; 929 } 930 931 device_init_wakeup(dev, true); 932 933 /* power down device IP for power saving by default */ 934 mtu3_stop(mtu); 935 936 ret = mtu3_gadget_setup(mtu); 937 if (ret) { 938 dev_err(dev, "mtu3 gadget init failed:%d\n", ret); 939 goto gadget_err; 940 } 941 942 ssusb_dev_debugfs_init(ssusb); 943 944 dev_dbg(dev, " %s() done...\n", __func__); 945 946 return 0; 947 948 gadget_err: 949 device_init_wakeup(dev, false); 950 951 dma_mask_err: 952 irq_err: 953 mtu3_hw_exit(mtu); 954 ssusb->u3d = NULL; 955 dev_err(dev, " %s() fail...\n", __func__); 956 957 return ret; 958 } 959 960 void ssusb_gadget_exit(struct ssusb_mtk *ssusb) 961 { 962 struct mtu3 *mtu = ssusb->u3d; 963 964 mtu3_gadget_cleanup(mtu); 965 device_init_wakeup(ssusb->dev, false); 966 mtu3_hw_exit(mtu); 967 } 968