1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mtu3_core.c - hardware access layer and gadget init/exit of 4 * MediaTek usb3 Dual-Role Controller Driver 5 * 6 * Copyright (C) 2016 MediaTek Inc. 7 * 8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 9 */ 10 11 #include <linux/dma-mapping.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 #include <linux/platform_device.h> 17 18 #include "mtu3.h" 19 20 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size) 21 { 22 struct mtu3_fifo_info *fifo = mep->fifo; 23 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT); 24 u32 start_bit; 25 26 /* ensure that @mep->fifo_seg_size is power of two */ 27 num_bits = roundup_pow_of_two(num_bits); 28 if (num_bits > fifo->limit) 29 return -EINVAL; 30 31 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT; 32 num_bits = num_bits * (mep->slot + 1); 33 start_bit = bitmap_find_next_zero_area(fifo->bitmap, 34 fifo->limit, 0, num_bits, 0); 35 if (start_bit >= fifo->limit) 36 return -EOVERFLOW; 37 38 bitmap_set(fifo->bitmap, start_bit, num_bits); 39 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT; 40 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit; 41 42 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n", 43 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit); 44 45 return mep->fifo_addr; 46 } 47 48 static void ep_fifo_free(struct mtu3_ep *mep) 49 { 50 struct mtu3_fifo_info *fifo = mep->fifo; 51 u32 addr = mep->fifo_addr; 52 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT; 53 u32 start_bit; 54 55 if (unlikely(addr < fifo->base || bits > fifo->limit)) 56 return; 57 58 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT; 59 bitmap_clear(fifo->bitmap, start_bit, bits); 60 mep->fifo_size = 0; 61 mep->fifo_seg_size = 0; 62 63 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n", 64 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit); 65 } 66 67 /* enable/disable U3D SS function */ 68 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable) 69 { 70 /* If usb3_en==0, LTSSM will go to SS.Disable state */ 71 if (enable) 72 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); 73 else 74 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); 75 76 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable); 77 } 78 79 /* set/clear U3D HS device soft connect */ 80 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable) 81 { 82 if (enable) { 83 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, 84 SOFT_CONN | SUSPENDM_ENABLE); 85 } else { 86 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, 87 SOFT_CONN | SUSPENDM_ENABLE); 88 } 89 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable); 90 } 91 92 /* only port0 of U2/U3 supports device mode */ 93 static int mtu3_device_enable(struct mtu3 *mtu) 94 { 95 void __iomem *ibase = mtu->ippc_base; 96 u32 check_clk = 0; 97 98 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 99 100 if (mtu->is_u3_ip) { 101 check_clk = SSUSB_U3_MAC_RST_B_STS; 102 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), 103 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN | 104 SSUSB_U3_PORT_HOST_SEL)); 105 } 106 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), 107 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN | 108 SSUSB_U2_PORT_HOST_SEL)); 109 110 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) { 111 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); 112 if (mtu->is_u3_ip) 113 mtu3_setbits(ibase, SSUSB_U3_CTRL(0), 114 SSUSB_U3_PORT_DUAL_MODE); 115 } 116 117 return ssusb_check_clocks(mtu->ssusb, check_clk); 118 } 119 120 static void mtu3_device_disable(struct mtu3 *mtu) 121 { 122 void __iomem *ibase = mtu->ippc_base; 123 124 if (mtu->is_u3_ip) 125 mtu3_setbits(ibase, SSUSB_U3_CTRL(0), 126 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN)); 127 128 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), 129 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN); 130 131 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) 132 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); 133 134 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 135 } 136 137 /* reset U3D's device module. */ 138 static void mtu3_device_reset(struct mtu3 *mtu) 139 { 140 void __iomem *ibase = mtu->ippc_base; 141 142 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); 143 udelay(1); 144 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); 145 } 146 147 /* disable all interrupts */ 148 static void mtu3_intr_disable(struct mtu3 *mtu) 149 { 150 void __iomem *mbase = mtu->mac_base; 151 152 /* Disable level 1 interrupts */ 153 mtu3_writel(mbase, U3D_LV1IECR, ~0x0); 154 /* Disable endpoint interrupts */ 155 mtu3_writel(mbase, U3D_EPIECR, ~0x0); 156 } 157 158 static void mtu3_intr_status_clear(struct mtu3 *mtu) 159 { 160 void __iomem *mbase = mtu->mac_base; 161 162 /* Clear EP0 and Tx/Rx EPn interrupts status */ 163 mtu3_writel(mbase, U3D_EPISR, ~0x0); 164 /* Clear U2 USB common interrupts status */ 165 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0); 166 /* Clear U3 LTSSM interrupts status */ 167 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0); 168 /* Clear speed change interrupt status */ 169 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0); 170 } 171 172 /* enable system global interrupt */ 173 static void mtu3_intr_enable(struct mtu3 *mtu) 174 { 175 void __iomem *mbase = mtu->mac_base; 176 u32 value; 177 178 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */ 179 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR; 180 mtu3_writel(mbase, U3D_LV1IESR, value); 181 182 /* Enable U2 common USB interrupts */ 183 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR | LPM_RESUME_INTR; 184 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value); 185 186 if (mtu->is_u3_ip) { 187 /* Enable U3 LTSSM interrupts */ 188 value = HOT_RST_INTR | WARM_RST_INTR | 189 ENTER_U3_INTR | EXIT_U3_INTR; 190 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value); 191 } 192 193 /* Enable QMU interrupts. */ 194 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT | 195 RXQ_LENERR_INT | RXQ_ZLPERR_INT; 196 mtu3_writel(mbase, U3D_QIESR1, value); 197 198 /* Enable speed change interrupt */ 199 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR); 200 } 201 202 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */ 203 static void mtu3_ep_reset(struct mtu3_ep *mep) 204 { 205 struct mtu3 *mtu = mep->mtu; 206 u32 rst_bit = EP_RST(mep->is_in, mep->epnum); 207 208 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit); 209 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit); 210 } 211 212 /* set/clear the stall and toggle bits for non-ep0 */ 213 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set) 214 { 215 struct mtu3 *mtu = mep->mtu; 216 void __iomem *mbase = mtu->mac_base; 217 u8 epnum = mep->epnum; 218 u32 csr; 219 220 if (mep->is_in) { /* TX */ 221 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS; 222 if (set) 223 csr |= TX_SENDSTALL; 224 else 225 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL; 226 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr); 227 } else { /* RX */ 228 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS; 229 if (set) 230 csr |= RX_SENDSTALL; 231 else 232 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL; 233 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr); 234 } 235 236 if (!set) { 237 mtu3_ep_reset(mep); 238 mep->flags &= ~MTU3_EP_STALL; 239 } else { 240 mep->flags |= MTU3_EP_STALL; 241 } 242 243 dev_dbg(mtu->dev, "%s: %s\n", mep->name, 244 set ? "SEND STALL" : "CLEAR STALL, with EP RESET"); 245 } 246 247 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on) 248 { 249 if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER) 250 mtu3_ss_func_set(mtu, is_on); 251 else 252 mtu3_hs_softconn_set(mtu, is_on); 253 254 dev_info(mtu->dev, "gadget (%s) pullup D%s\n", 255 usb_speed_string(mtu->max_speed), is_on ? "+" : "-"); 256 } 257 258 void mtu3_start(struct mtu3 *mtu) 259 { 260 void __iomem *mbase = mtu->mac_base; 261 262 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__, 263 mtu3_readl(mbase, U3D_DEVICE_CONTROL)); 264 265 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 266 267 /* 268 * When disable U2 port, USB2_CSR's register will be reset to 269 * default value after re-enable it again(HS is enabled by default). 270 * So if force mac to work as FS, disable HS function. 271 */ 272 if (mtu->max_speed == USB_SPEED_FULL) 273 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); 274 275 /* Initialize the default interrupts */ 276 mtu3_intr_enable(mtu); 277 mtu->is_active = 1; 278 279 if (mtu->softconnect) 280 mtu3_dev_on_off(mtu, 1); 281 } 282 283 void mtu3_stop(struct mtu3 *mtu) 284 { 285 dev_dbg(mtu->dev, "%s\n", __func__); 286 287 mtu3_intr_disable(mtu); 288 mtu3_intr_status_clear(mtu); 289 290 if (mtu->softconnect) 291 mtu3_dev_on_off(mtu, 0); 292 293 mtu->is_active = 0; 294 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); 295 } 296 297 /* for non-ep0 */ 298 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep, 299 int interval, int burst, int mult) 300 { 301 void __iomem *mbase = mtu->mac_base; 302 int epnum = mep->epnum; 303 u32 csr0, csr1, csr2; 304 int fifo_sgsz, fifo_addr; 305 int num_pkts; 306 307 fifo_addr = ep_fifo_alloc(mep, mep->maxp); 308 if (fifo_addr < 0) { 309 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp); 310 return -ENOMEM; 311 } 312 fifo_sgsz = ilog2(mep->fifo_seg_size); 313 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz, 314 mep->fifo_seg_size, mep->fifo_size); 315 316 if (mep->is_in) { 317 csr0 = TX_TXMAXPKTSZ(mep->maxp); 318 csr0 |= TX_DMAREQEN; 319 320 num_pkts = (burst + 1) * (mult + 1) - 1; 321 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot); 322 csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult); 323 324 csr2 = TX_FIFOADDR(fifo_addr >> 4); 325 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz); 326 327 switch (mep->type) { 328 case USB_ENDPOINT_XFER_BULK: 329 csr1 |= TX_TYPE(TYPE_BULK); 330 break; 331 case USB_ENDPOINT_XFER_ISOC: 332 csr1 |= TX_TYPE(TYPE_ISO); 333 csr2 |= TX_BINTERVAL(interval); 334 break; 335 case USB_ENDPOINT_XFER_INT: 336 csr1 |= TX_TYPE(TYPE_INT); 337 csr2 |= TX_BINTERVAL(interval); 338 break; 339 } 340 341 /* Enable QMU Done interrupt */ 342 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum)); 343 344 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0); 345 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1); 346 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2); 347 348 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n", 349 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)), 350 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)), 351 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum))); 352 } else { 353 csr0 = RX_RXMAXPKTSZ(mep->maxp); 354 csr0 |= RX_DMAREQEN; 355 356 num_pkts = (burst + 1) * (mult + 1) - 1; 357 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot); 358 csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult); 359 360 csr2 = RX_FIFOADDR(fifo_addr >> 4); 361 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz); 362 363 switch (mep->type) { 364 case USB_ENDPOINT_XFER_BULK: 365 csr1 |= RX_TYPE(TYPE_BULK); 366 break; 367 case USB_ENDPOINT_XFER_ISOC: 368 csr1 |= RX_TYPE(TYPE_ISO); 369 csr2 |= RX_BINTERVAL(interval); 370 break; 371 case USB_ENDPOINT_XFER_INT: 372 csr1 |= RX_TYPE(TYPE_INT); 373 csr2 |= RX_BINTERVAL(interval); 374 break; 375 } 376 377 /*Enable QMU Done interrupt */ 378 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum)); 379 380 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0); 381 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1); 382 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2); 383 384 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n", 385 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)), 386 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)), 387 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum))); 388 } 389 390 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2); 391 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n", 392 __func__, mep->name, mep->fifo_addr, mep->fifo_size, 393 fifo_sgsz, mep->fifo_seg_size); 394 395 return 0; 396 } 397 398 /* for non-ep0 */ 399 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep) 400 { 401 void __iomem *mbase = mtu->mac_base; 402 int epnum = mep->epnum; 403 404 if (mep->is_in) { 405 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0); 406 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0); 407 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0); 408 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum)); 409 } else { 410 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0); 411 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0); 412 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0); 413 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum)); 414 } 415 416 mtu3_ep_reset(mep); 417 ep_fifo_free(mep); 418 419 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name); 420 } 421 422 /* 423 * Two scenarios: 424 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs 425 * are separated; 426 * 2. when supports only HS, the fifo is shared for all EPs, and 427 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate 428 * the total fifo size of non-ep0, and ep0's is fixed to 64B, 429 * so the total fifo size is 64B + @EPNTXFFSZ; 430 * Due to the first 64B should be reserved for EP0, non-ep0's fifo 431 * starts from offset 64 and are divided into two equal parts for 432 * TX or RX EPs for simplification. 433 */ 434 static void get_ep_fifo_config(struct mtu3 *mtu) 435 { 436 struct mtu3_fifo_info *tx_fifo; 437 struct mtu3_fifo_info *rx_fifo; 438 u32 fifosize; 439 440 if (mtu->is_u3_ip) { 441 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ); 442 tx_fifo = &mtu->tx_fifo; 443 tx_fifo->base = 0; 444 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT; 445 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 446 447 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ); 448 rx_fifo = &mtu->rx_fifo; 449 rx_fifo->base = 0; 450 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT; 451 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 452 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT; 453 } else { 454 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ); 455 tx_fifo = &mtu->tx_fifo; 456 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE; 457 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1; 458 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 459 460 rx_fifo = &mtu->rx_fifo; 461 rx_fifo->base = 462 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT; 463 rx_fifo->limit = tx_fifo->limit; 464 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); 465 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT; 466 } 467 468 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n", 469 __func__, tx_fifo->base, tx_fifo->limit, 470 rx_fifo->base, rx_fifo->limit); 471 } 472 473 void mtu3_ep0_setup(struct mtu3 *mtu) 474 { 475 u32 maxpacket = mtu->g.ep0->maxpacket; 476 u32 csr; 477 478 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket); 479 480 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR); 481 csr &= ~EP0_MAXPKTSZ_MSK; 482 csr |= EP0_MAXPKTSZ(maxpacket); 483 csr &= EP0_W1C_BITS; 484 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); 485 486 /* Enable EP0 interrupt */ 487 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR); 488 } 489 490 static int mtu3_mem_alloc(struct mtu3 *mtu) 491 { 492 void __iomem *mbase = mtu->mac_base; 493 struct mtu3_ep *ep_array; 494 int in_ep_num, out_ep_num; 495 u32 cap_epinfo; 496 int ret; 497 int i; 498 499 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO); 500 in_ep_num = CAP_TX_EP_NUM(cap_epinfo); 501 out_ep_num = CAP_RX_EP_NUM(cap_epinfo); 502 503 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n", 504 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num, 505 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num); 506 507 /* one for ep0, another is reserved */ 508 mtu->num_eps = min(in_ep_num, out_ep_num) + 1; 509 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL); 510 if (ep_array == NULL) 511 return -ENOMEM; 512 513 mtu->ep_array = ep_array; 514 mtu->in_eps = ep_array; 515 mtu->out_eps = &ep_array[mtu->num_eps]; 516 /* ep0 uses in_eps[0], out_eps[0] is reserved */ 517 mtu->ep0 = mtu->in_eps; 518 mtu->ep0->mtu = mtu; 519 mtu->ep0->epnum = 0; 520 521 for (i = 1; i < mtu->num_eps; i++) { 522 struct mtu3_ep *mep = mtu->in_eps + i; 523 524 mep->fifo = &mtu->tx_fifo; 525 mep = mtu->out_eps + i; 526 mep->fifo = &mtu->rx_fifo; 527 } 528 529 get_ep_fifo_config(mtu); 530 531 ret = mtu3_qmu_init(mtu); 532 if (ret) 533 kfree(mtu->ep_array); 534 535 return ret; 536 } 537 538 static void mtu3_mem_free(struct mtu3 *mtu) 539 { 540 mtu3_qmu_exit(mtu); 541 kfree(mtu->ep_array); 542 } 543 544 static void mtu3_set_speed(struct mtu3 *mtu) 545 { 546 void __iomem *mbase = mtu->mac_base; 547 548 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH)) 549 mtu->max_speed = USB_SPEED_HIGH; 550 551 if (mtu->max_speed == USB_SPEED_FULL) { 552 /* disable U3 SS function */ 553 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN); 554 /* disable HS function */ 555 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); 556 } else if (mtu->max_speed == USB_SPEED_HIGH) { 557 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN); 558 /* HS/FS detected by HW */ 559 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); 560 } else if (mtu->max_speed == USB_SPEED_SUPER) { 561 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0), 562 SSUSB_U3_PORT_SSP_SPEED); 563 } 564 565 dev_info(mtu->dev, "max_speed: %s\n", 566 usb_speed_string(mtu->max_speed)); 567 } 568 569 static void mtu3_regs_init(struct mtu3 *mtu) 570 { 571 572 void __iomem *mbase = mtu->mac_base; 573 574 /* be sure interrupts are disabled before registration of ISR */ 575 mtu3_intr_disable(mtu); 576 mtu3_intr_status_clear(mtu); 577 578 if (mtu->is_u3_ip) { 579 /* disable LGO_U1/U2 by default */ 580 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL, 581 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE | 582 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE); 583 /* device responses to u3_exit from host automatically */ 584 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN); 585 /* automatically build U2 link when U3 detect fail */ 586 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH); 587 } 588 589 mtu3_set_speed(mtu); 590 591 /* delay about 0.1us from detecting reset to send chirp-K */ 592 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK); 593 /* U2/U3 detected by HW */ 594 mtu3_writel(mbase, U3D_DEVICE_CONF, 0); 595 /* enable QMU 16B checksum */ 596 mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN); 597 /* vbus detected by HW */ 598 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON); 599 } 600 601 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu) 602 { 603 void __iomem *mbase = mtu->mac_base; 604 enum usb_device_speed udev_speed; 605 u32 maxpkt = 64; 606 u32 link; 607 u32 speed; 608 609 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR); 610 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE); 611 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */ 612 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link); 613 614 if (!(link & SSUSB_DEV_SPEED_CHG_INTR)) 615 return IRQ_NONE; 616 617 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF)); 618 619 switch (speed) { 620 case MTU3_SPEED_FULL: 621 udev_speed = USB_SPEED_FULL; 622 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */ 623 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf) 624 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa)); 625 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, 626 LPM_BESL_STALL | LPM_BESLD_STALL); 627 break; 628 case MTU3_SPEED_HIGH: 629 udev_speed = USB_SPEED_HIGH; 630 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */ 631 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf) 632 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa)); 633 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, 634 LPM_BESL_STALL | LPM_BESLD_STALL); 635 break; 636 case MTU3_SPEED_SUPER: 637 udev_speed = USB_SPEED_SUPER; 638 maxpkt = 512; 639 break; 640 case MTU3_SPEED_SUPER_PLUS: 641 udev_speed = USB_SPEED_SUPER_PLUS; 642 maxpkt = 512; 643 break; 644 default: 645 udev_speed = USB_SPEED_UNKNOWN; 646 break; 647 } 648 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed)); 649 650 mtu->g.speed = udev_speed; 651 mtu->g.ep0->maxpacket = maxpkt; 652 mtu->ep0_state = MU3D_EP0_STATE_SETUP; 653 654 if (udev_speed == USB_SPEED_UNKNOWN) 655 mtu3_gadget_disconnect(mtu); 656 else 657 mtu3_ep0_setup(mtu); 658 659 return IRQ_HANDLED; 660 } 661 662 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu) 663 { 664 void __iomem *mbase = mtu->mac_base; 665 u32 ltssm; 666 667 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR); 668 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE); 669 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */ 670 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm); 671 672 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR)) 673 mtu3_gadget_reset(mtu); 674 675 if (ltssm & VBUS_FALL_INTR) { 676 mtu3_ss_func_set(mtu, false); 677 mtu3_gadget_reset(mtu); 678 } 679 680 if (ltssm & VBUS_RISE_INTR) 681 mtu3_ss_func_set(mtu, true); 682 683 if (ltssm & EXIT_U3_INTR) 684 mtu3_gadget_resume(mtu); 685 686 if (ltssm & ENTER_U3_INTR) 687 mtu3_gadget_suspend(mtu); 688 689 return IRQ_HANDLED; 690 } 691 692 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu) 693 { 694 void __iomem *mbase = mtu->mac_base; 695 u32 u2comm; 696 697 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR); 698 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE); 699 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */ 700 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm); 701 702 if (u2comm & SUSPEND_INTR) 703 mtu3_gadget_suspend(mtu); 704 705 if (u2comm & RESUME_INTR) 706 mtu3_gadget_resume(mtu); 707 708 if (u2comm & RESET_INTR) 709 mtu3_gadget_reset(mtu); 710 711 if (u2comm & LPM_RESUME_INTR) { 712 if (!(mtu3_readl(mbase, U3D_POWER_MANAGEMENT) & LPM_HRWE)) 713 mtu3_setbits(mbase, U3D_USB20_MISC_CONTROL, 714 LPM_U3_ACK_EN); 715 } 716 717 return IRQ_HANDLED; 718 } 719 720 static irqreturn_t mtu3_irq(int irq, void *data) 721 { 722 struct mtu3 *mtu = (struct mtu3 *)data; 723 unsigned long flags; 724 u32 level1; 725 726 spin_lock_irqsave(&mtu->lock, flags); 727 728 /* U3D_LV1ISR is RU */ 729 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR); 730 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER); 731 732 if (level1 & EP_CTRL_INTR) 733 mtu3_link_isr(mtu); 734 735 if (level1 & MAC2_INTR) 736 mtu3_u2_common_isr(mtu); 737 738 if (level1 & MAC3_INTR) 739 mtu3_u3_ltssm_isr(mtu); 740 741 if (level1 & BMU_INTR) 742 mtu3_ep0_isr(mtu); 743 744 if (level1 & QMU_INTR) 745 mtu3_qmu_isr(mtu); 746 747 spin_unlock_irqrestore(&mtu->lock, flags); 748 749 return IRQ_HANDLED; 750 } 751 752 static int mtu3_hw_init(struct mtu3 *mtu) 753 { 754 u32 cap_dev; 755 int ret; 756 757 mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID); 758 759 cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP); 760 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev); 761 762 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version, 763 mtu->is_u3_ip ? "U3" : "U2"); 764 765 mtu3_device_reset(mtu); 766 767 ret = mtu3_device_enable(mtu); 768 if (ret) { 769 dev_err(mtu->dev, "device enable failed %d\n", ret); 770 return ret; 771 } 772 773 ret = mtu3_mem_alloc(mtu); 774 if (ret) 775 return -ENOMEM; 776 777 mtu3_regs_init(mtu); 778 779 return 0; 780 } 781 782 static void mtu3_hw_exit(struct mtu3 *mtu) 783 { 784 mtu3_device_disable(mtu); 785 mtu3_mem_free(mtu); 786 } 787 788 /** 789 * we set 32-bit DMA mask by default, here check whether the controller 790 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask. 791 */ 792 static int mtu3_set_dma_mask(struct mtu3 *mtu) 793 { 794 struct device *dev = mtu->dev; 795 bool is_36bit = false; 796 int ret = 0; 797 u32 value; 798 799 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL); 800 if (value & DMA_ADDR_36BIT) { 801 is_36bit = true; 802 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); 803 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */ 804 if (ret) { 805 is_36bit = false; 806 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 807 } 808 } 809 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32"); 810 811 return ret; 812 } 813 814 int ssusb_gadget_init(struct ssusb_mtk *ssusb) 815 { 816 struct device *dev = ssusb->dev; 817 struct platform_device *pdev = to_platform_device(dev); 818 struct mtu3 *mtu = NULL; 819 struct resource *res; 820 int ret = -ENOMEM; 821 822 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL); 823 if (mtu == NULL) 824 return -ENOMEM; 825 826 mtu->irq = platform_get_irq(pdev, 0); 827 if (mtu->irq < 0) { 828 dev_err(dev, "fail to get irq number\n"); 829 return mtu->irq; 830 } 831 dev_info(dev, "irq %d\n", mtu->irq); 832 833 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 834 mtu->mac_base = devm_ioremap_resource(dev, res); 835 if (IS_ERR(mtu->mac_base)) { 836 dev_err(dev, "error mapping memory for dev mac\n"); 837 return PTR_ERR(mtu->mac_base); 838 } 839 840 spin_lock_init(&mtu->lock); 841 mtu->dev = dev; 842 mtu->ippc_base = ssusb->ippc_base; 843 ssusb->mac_base = mtu->mac_base; 844 ssusb->u3d = mtu; 845 mtu->ssusb = ssusb; 846 mtu->max_speed = usb_get_maximum_speed(dev); 847 848 /* check the max_speed parameter */ 849 switch (mtu->max_speed) { 850 case USB_SPEED_FULL: 851 case USB_SPEED_HIGH: 852 case USB_SPEED_SUPER: 853 case USB_SPEED_SUPER_PLUS: 854 break; 855 default: 856 dev_err(dev, "invalid max_speed: %s\n", 857 usb_speed_string(mtu->max_speed)); 858 /* fall through */ 859 case USB_SPEED_UNKNOWN: 860 /* default as SSP */ 861 mtu->max_speed = USB_SPEED_SUPER_PLUS; 862 break; 863 } 864 865 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n", 866 mtu->mac_base, mtu->ippc_base); 867 868 ret = mtu3_hw_init(mtu); 869 if (ret) { 870 dev_err(dev, "mtu3 hw init failed:%d\n", ret); 871 return ret; 872 } 873 874 ret = mtu3_set_dma_mask(mtu); 875 if (ret) { 876 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret); 877 goto dma_mask_err; 878 } 879 880 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu); 881 if (ret) { 882 dev_err(dev, "request irq %d failed!\n", mtu->irq); 883 goto irq_err; 884 } 885 886 device_init_wakeup(dev, true); 887 888 ret = mtu3_gadget_setup(mtu); 889 if (ret) { 890 dev_err(dev, "mtu3 gadget init failed:%d\n", ret); 891 goto gadget_err; 892 } 893 894 /* init as host mode, power down device IP for power saving */ 895 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) 896 mtu3_stop(mtu); 897 898 dev_dbg(dev, " %s() done...\n", __func__); 899 900 return 0; 901 902 gadget_err: 903 device_init_wakeup(dev, false); 904 905 dma_mask_err: 906 irq_err: 907 mtu3_hw_exit(mtu); 908 ssusb->u3d = NULL; 909 dev_err(dev, " %s() fail...\n", __func__); 910 911 return ret; 912 } 913 914 void ssusb_gadget_exit(struct ssusb_mtk *ssusb) 915 { 916 struct mtu3 *mtu = ssusb->u3d; 917 918 mtu3_gadget_cleanup(mtu); 919 device_init_wakeup(ssusb->dev, false); 920 mtu3_hw_exit(mtu); 921 } 922