1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mtu3.h - MediaTek USB3 DRD header 4 * 5 * Copyright (C) 2016 MediaTek Inc. 6 * 7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #ifndef __MTU3_H__ 11 #define __MTU3_H__ 12 13 #include <linux/device.h> 14 #include <linux/dmapool.h> 15 #include <linux/extcon.h> 16 #include <linux/interrupt.h> 17 #include <linux/list.h> 18 #include <linux/phy/phy.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/usb.h> 21 #include <linux/usb/ch9.h> 22 #include <linux/usb/gadget.h> 23 #include <linux/usb/otg.h> 24 25 struct mtu3; 26 struct mtu3_ep; 27 struct mtu3_request; 28 29 #include "mtu3_hw_regs.h" 30 #include "mtu3_qmu.h" 31 32 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10)) 33 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10)) 34 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10)) 35 36 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10)) 37 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10)) 38 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10)) 39 40 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4)) 41 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4)) 42 43 #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10)) 44 #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10)) 45 #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10)) 46 47 #define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10)) 48 #define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10)) 49 #define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10)) 50 51 #define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08)) 52 #define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08)) 53 54 #define MTU3_DRIVER_NAME "mtu3" 55 #define DMA_ADDR_INVALID (~(dma_addr_t)0) 56 57 #define MTU3_EP_ENABLED BIT(0) 58 #define MTU3_EP_STALL BIT(1) 59 #define MTU3_EP_WEDGE BIT(2) 60 #define MTU3_EP_BUSY BIT(3) 61 62 #define MTU3_U3_IP_SLOT_DEFAULT 2 63 #define MTU3_U2_IP_SLOT_DEFAULT 1 64 65 /** 66 * Normally the device works on HS or SS, to simplify fifo management, 67 * devide fifo into some 512B parts, use bitmap to manage it; And 68 * 128 bits size of bitmap is large enough, that means it can manage 69 * up to 64KB fifo size. 70 * NOTE: MTU3_EP_FIFO_UNIT should be power of two 71 */ 72 #define MTU3_EP_FIFO_UNIT (1 << 9) 73 #define MTU3_FIFO_BIT_SIZE 128 74 #define MTU3_U2_IP_EP0_FIFO_SIZE 64 75 76 /** 77 * Maximum size of ep0 response buffer for ch9 requests, 78 * the SET_SEL request uses 6 so far, and GET_STATUS is 2 79 */ 80 #define EP0_RESPONSE_BUF 6 81 82 /* device operated link and speed got from DEVICE_CONF register */ 83 enum mtu3_speed { 84 MTU3_SPEED_INACTIVE = 0, 85 MTU3_SPEED_FULL = 1, 86 MTU3_SPEED_HIGH = 3, 87 MTU3_SPEED_SUPER = 4, 88 MTU3_SPEED_SUPER_PLUS = 5, 89 }; 90 91 /** 92 * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP 93 * without data stage. 94 * @MU3D_EP0_STATE_TX: IN data stage 95 * @MU3D_EP0_STATE_RX: OUT data stage 96 * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and 97 * waits for its completion interrupt 98 * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared 99 * after receives a SETUP. 100 */ 101 enum mtu3_g_ep0_state { 102 MU3D_EP0_STATE_SETUP = 1, 103 MU3D_EP0_STATE_TX, 104 MU3D_EP0_STATE_RX, 105 MU3D_EP0_STATE_TX_END, 106 MU3D_EP0_STATE_STALL, 107 }; 108 109 /** 110 * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode 111 * by IDPIN signal. 112 * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG 113 * IDPIN signal. 114 * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode. 115 */ 116 enum mtu3_dr_force_mode { 117 MTU3_DR_FORCE_NONE = 0, 118 MTU3_DR_FORCE_HOST, 119 MTU3_DR_FORCE_DEVICE, 120 }; 121 122 /** 123 * @base: the base address of fifo 124 * @limit: the bitmap size in bits 125 * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT 126 */ 127 struct mtu3_fifo_info { 128 u32 base; 129 u32 limit; 130 DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE); 131 }; 132 133 /** 134 * General Purpose Descriptor (GPD): 135 * The format of TX GPD is a little different from RX one. 136 * And the size of GPD is 16 bytes. 137 * 138 * @flag: 139 * bit0: Hardware Own (HWO) 140 * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported 141 * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1 142 * bit7: Interrupt On Completion (IOC) 143 * @chksum: This is used to validate the contents of this GPD; 144 * If TXQ_CS_EN / RXQ_CS_EN bit is set, an interrupt is issued 145 * when checksum validation fails; 146 * Checksum value is calculated over the 16 bytes of the GPD by default; 147 * @data_buf_len (RX ONLY): This value indicates the length of 148 * the assigned data buffer 149 * @tx_ext_addr (TX ONLY): [3:0] are 4 extension bits of @buffer, 150 * [7:4] are 4 extension bits of @next_gpd 151 * @next_gpd: Physical address of the next GPD 152 * @buffer: Physical address of the data buffer 153 * @buf_len: 154 * (TX): This value indicates the length of the assigned data buffer 155 * (RX): The total length of data received 156 * @ext_len: reserved 157 * @rx_ext_addr(RX ONLY): [3:0] are 4 extension bits of @buffer, 158 * [7:4] are 4 extension bits of @next_gpd 159 * @ext_flag: 160 * bit5 (TX ONLY): Zero Length Packet (ZLP), 161 */ 162 struct qmu_gpd { 163 __u8 flag; 164 __u8 chksum; 165 union { 166 __le16 data_buf_len; 167 __le16 tx_ext_addr; 168 }; 169 __le32 next_gpd; 170 __le32 buffer; 171 __le16 buf_len; 172 union { 173 __u8 ext_len; 174 __u8 rx_ext_addr; 175 }; 176 __u8 ext_flag; 177 } __packed; 178 179 /** 180 * dma: physical base address of GPD segment 181 * start: virtual base address of GPD segment 182 * end: the last GPD element 183 * enqueue: the first empty GPD to use 184 * dequeue: the first completed GPD serviced by ISR 185 * NOTE: the size of GPD ring should be >= 2 186 */ 187 struct mtu3_gpd_ring { 188 dma_addr_t dma; 189 struct qmu_gpd *start; 190 struct qmu_gpd *end; 191 struct qmu_gpd *enqueue; 192 struct qmu_gpd *dequeue; 193 }; 194 195 /** 196 * @vbus: vbus 5V used by host mode 197 * @edev: external connector used to detect vbus and iddig changes 198 * @vbus_nb: notifier for vbus detection 199 * @vbus_work : work of vbus detection notifier, used to avoid sleep in 200 * notifier callback which is atomic context 201 * @vbus_event : event of vbus detecion notifier 202 * @id_nb : notifier for iddig(idpin) detection 203 * @id_work : work of iddig detection notifier 204 * @id_event : event of iddig detecion notifier 205 * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not 206 * @manual_drd_enabled: it's true when supports dual-role device by debugfs 207 * to switch host/device modes depending on user input. 208 */ 209 struct otg_switch_mtk { 210 struct regulator *vbus; 211 struct extcon_dev *edev; 212 struct notifier_block vbus_nb; 213 struct work_struct vbus_work; 214 unsigned long vbus_event; 215 struct notifier_block id_nb; 216 struct work_struct id_work; 217 unsigned long id_event; 218 bool is_u3_drd; 219 bool manual_drd_enabled; 220 }; 221 222 /** 223 * @mac_base: register base address of device MAC, exclude xHCI's 224 * @ippc_base: register base address of IP Power and Clock interface (IPPC) 225 * @vusb33: usb3.3V shared by device/host IP 226 * @sys_clk: system clock of mtu3, shared by device/host IP 227 * @ref_clk: reference clock 228 * @mcu_clk: mcu_bus_ck clock for AHB bus etc 229 * @dma_clk: dma_bus_ck clock for AXI bus etc 230 * @dr_mode: works in which mode: 231 * host only, device only or dual-role mode 232 * @u2_ports: number of usb2.0 host ports 233 * @u3_ports: number of usb3.0 host ports 234 * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to 235 * disable u3port0, bit1==1 to disable u3port1,... etc 236 * @dbgfs_root: only used when supports manual dual-role switch via debugfs 237 * @uwk_en: it's true when supports remote wakeup in host mode 238 * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM 239 * @uwk_reg_base: the base address of the wakeup glue layer in @uwk 240 * @uwk_vers: the version of the wakeup glue layer 241 */ 242 struct ssusb_mtk { 243 struct device *dev; 244 struct mtu3 *u3d; 245 void __iomem *mac_base; 246 void __iomem *ippc_base; 247 struct phy **phys; 248 int num_phys; 249 /* common power & clock */ 250 struct regulator *vusb33; 251 struct clk *sys_clk; 252 struct clk *ref_clk; 253 struct clk *mcu_clk; 254 struct clk *dma_clk; 255 /* otg */ 256 struct otg_switch_mtk otg_switch; 257 enum usb_dr_mode dr_mode; 258 bool is_host; 259 int u2_ports; 260 int u3_ports; 261 int u3p_dis_msk; 262 struct dentry *dbgfs_root; 263 /* usb wakeup for host mode */ 264 bool uwk_en; 265 struct regmap *uwk; 266 u32 uwk_reg_base; 267 u32 uwk_vers; 268 }; 269 270 /** 271 * @fifo_size: it is (@slot + 1) * @fifo_seg_size 272 * @fifo_seg_size: it is roundup_pow_of_two(@maxp) 273 */ 274 struct mtu3_ep { 275 struct usb_ep ep; 276 char name[12]; 277 struct mtu3 *mtu; 278 u8 epnum; 279 u8 type; 280 u8 is_in; 281 u16 maxp; 282 int slot; 283 u32 fifo_size; 284 u32 fifo_addr; 285 u32 fifo_seg_size; 286 struct mtu3_fifo_info *fifo; 287 288 struct list_head req_list; 289 struct mtu3_gpd_ring gpd_ring; 290 const struct usb_ss_ep_comp_descriptor *comp_desc; 291 const struct usb_endpoint_descriptor *desc; 292 293 int flags; 294 u8 wedged; 295 u8 busy; 296 }; 297 298 struct mtu3_request { 299 struct usb_request request; 300 struct list_head list; 301 struct mtu3_ep *mep; 302 struct mtu3 *mtu; 303 struct qmu_gpd *gpd; 304 int epnum; 305 }; 306 307 static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev) 308 { 309 return dev_get_drvdata(dev); 310 } 311 312 /** 313 * struct mtu3 - device driver instance data. 314 * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only, 315 * MTU3_U3_IP_SLOT_DEFAULT for U3 IP 316 * @may_wakeup: means device's remote wakeup is enabled 317 * @is_self_powered: is reported in device status and the config descriptor 318 * @delayed_status: true when function drivers ask for delayed status 319 * @ep0_req: dummy request used while handling standard USB requests 320 * for GET_STATUS and SET_SEL 321 * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests 322 */ 323 struct mtu3 { 324 spinlock_t lock; 325 struct ssusb_mtk *ssusb; 326 struct device *dev; 327 void __iomem *mac_base; 328 void __iomem *ippc_base; 329 int irq; 330 331 struct mtu3_fifo_info tx_fifo; 332 struct mtu3_fifo_info rx_fifo; 333 334 struct mtu3_ep *ep_array; 335 struct mtu3_ep *in_eps; 336 struct mtu3_ep *out_eps; 337 struct mtu3_ep *ep0; 338 int num_eps; 339 int slot; 340 int active_ep; 341 342 struct dma_pool *qmu_gpd_pool; 343 enum mtu3_g_ep0_state ep0_state; 344 struct usb_gadget g; /* the gadget */ 345 struct usb_gadget_driver *gadget_driver; 346 struct mtu3_request ep0_req; 347 u8 setup_buf[EP0_RESPONSE_BUF]; 348 u32 max_speed; 349 350 unsigned is_active:1; 351 unsigned may_wakeup:1; 352 unsigned is_self_powered:1; 353 unsigned test_mode:1; 354 unsigned softconnect:1; 355 unsigned u1_enable:1; 356 unsigned u2_enable:1; 357 unsigned is_u3_ip:1; 358 unsigned delayed_status:1; 359 360 u8 address; 361 u8 test_mode_nr; 362 u32 hw_version; 363 }; 364 365 static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g) 366 { 367 return container_of(g, struct mtu3, g); 368 } 369 370 static inline int is_first_entry(const struct list_head *list, 371 const struct list_head *head) 372 { 373 return list_is_last(head, list); 374 } 375 376 static inline struct mtu3_request *to_mtu3_request(struct usb_request *req) 377 { 378 return req ? container_of(req, struct mtu3_request, request) : NULL; 379 } 380 381 static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep) 382 { 383 return ep ? container_of(ep, struct mtu3_ep, ep) : NULL; 384 } 385 386 static inline struct mtu3_request *next_request(struct mtu3_ep *mep) 387 { 388 return list_first_entry_or_null(&mep->req_list, struct mtu3_request, 389 list); 390 } 391 392 static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data) 393 { 394 writel(data, base + offset); 395 } 396 397 static inline u32 mtu3_readl(void __iomem *base, u32 offset) 398 { 399 return readl(base + offset); 400 } 401 402 static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits) 403 { 404 void __iomem *addr = base + offset; 405 u32 tmp = readl(addr); 406 407 writel((tmp | (bits)), addr); 408 } 409 410 static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits) 411 { 412 void __iomem *addr = base + offset; 413 u32 tmp = readl(addr); 414 415 writel((tmp & ~(bits)), addr); 416 } 417 418 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks); 419 struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); 420 void mtu3_free_request(struct usb_ep *ep, struct usb_request *req); 421 void mtu3_req_complete(struct mtu3_ep *mep, 422 struct usb_request *req, int status); 423 424 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep, 425 int interval, int burst, int mult); 426 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep); 427 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set); 428 void mtu3_ep0_setup(struct mtu3 *mtu); 429 void mtu3_start(struct mtu3 *mtu); 430 void mtu3_stop(struct mtu3 *mtu); 431 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on); 432 433 int mtu3_gadget_setup(struct mtu3 *mtu); 434 void mtu3_gadget_cleanup(struct mtu3 *mtu); 435 void mtu3_gadget_reset(struct mtu3 *mtu); 436 void mtu3_gadget_suspend(struct mtu3 *mtu); 437 void mtu3_gadget_resume(struct mtu3 *mtu); 438 void mtu3_gadget_disconnect(struct mtu3 *mtu); 439 440 irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu); 441 extern const struct usb_ep_ops mtu3_ep0_ops; 442 443 #endif 444