1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mtu3.h - MediaTek USB3 DRD header 4 * 5 * Copyright (C) 2016 MediaTek Inc. 6 * 7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #ifndef __MTU3_H__ 11 #define __MTU3_H__ 12 13 #include <linux/clk.h> 14 #include <linux/device.h> 15 #include <linux/dmapool.h> 16 #include <linux/extcon.h> 17 #include <linux/interrupt.h> 18 #include <linux/list.h> 19 #include <linux/phy/phy.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/usb.h> 22 #include <linux/usb/ch9.h> 23 #include <linux/usb/gadget.h> 24 #include <linux/usb/otg.h> 25 #include <linux/usb/role.h> 26 27 struct mtu3; 28 struct mtu3_ep; 29 struct mtu3_request; 30 31 #include "mtu3_hw_regs.h" 32 #include "mtu3_qmu.h" 33 34 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10)) 35 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10)) 36 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10)) 37 38 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10)) 39 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10)) 40 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10)) 41 42 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4)) 43 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4)) 44 45 #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10)) 46 #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10)) 47 #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10)) 48 49 #define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10)) 50 #define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10)) 51 #define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10)) 52 53 #define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08)) 54 #define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08)) 55 56 #define MTU3_DRIVER_NAME "mtu3" 57 #define DMA_ADDR_INVALID (~(dma_addr_t)0) 58 59 #define MTU3_EP_ENABLED BIT(0) 60 #define MTU3_EP_STALL BIT(1) 61 #define MTU3_EP_WEDGE BIT(2) 62 #define MTU3_EP_BUSY BIT(3) 63 64 #define MTU3_U3_IP_SLOT_DEFAULT 2 65 #define MTU3_U2_IP_SLOT_DEFAULT 1 66 67 /** 68 * IP TRUNK version 69 * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver: 70 * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted, 71 * but not backward compatible 72 * 2. QMU extend buffer length supported 73 */ 74 #define MTU3_TRUNK_VERS_1003 0x1003 75 76 /** 77 * Normally the device works on HS or SS, to simplify fifo management, 78 * devide fifo into some 512B parts, use bitmap to manage it; And 79 * 128 bits size of bitmap is large enough, that means it can manage 80 * up to 64KB fifo size. 81 * NOTE: MTU3_EP_FIFO_UNIT should be power of two 82 */ 83 #define MTU3_EP_FIFO_UNIT (1 << 9) 84 #define MTU3_FIFO_BIT_SIZE 128 85 #define MTU3_U2_IP_EP0_FIFO_SIZE 64 86 87 /** 88 * Maximum size of ep0 response buffer for ch9 requests, 89 * the SET_SEL request uses 6 so far, and GET_STATUS is 2 90 */ 91 #define EP0_RESPONSE_BUF 6 92 93 #define BULK_CLKS_CNT 4 94 95 /* device operated link and speed got from DEVICE_CONF register */ 96 enum mtu3_speed { 97 MTU3_SPEED_INACTIVE = 0, 98 MTU3_SPEED_FULL = 1, 99 MTU3_SPEED_HIGH = 3, 100 MTU3_SPEED_SUPER = 4, 101 MTU3_SPEED_SUPER_PLUS = 5, 102 }; 103 104 /** 105 * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP 106 * without data stage. 107 * @MU3D_EP0_STATE_TX: IN data stage 108 * @MU3D_EP0_STATE_RX: OUT data stage 109 * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and 110 * waits for its completion interrupt 111 * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared 112 * after receives a SETUP. 113 */ 114 enum mtu3_g_ep0_state { 115 MU3D_EP0_STATE_SETUP = 1, 116 MU3D_EP0_STATE_TX, 117 MU3D_EP0_STATE_RX, 118 MU3D_EP0_STATE_TX_END, 119 MU3D_EP0_STATE_STALL, 120 }; 121 122 /** 123 * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode 124 * by IDPIN signal. 125 * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG 126 * IDPIN signal. 127 * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode. 128 */ 129 enum mtu3_dr_force_mode { 130 MTU3_DR_FORCE_NONE = 0, 131 MTU3_DR_FORCE_HOST, 132 MTU3_DR_FORCE_DEVICE, 133 }; 134 135 /** 136 * @base: the base address of fifo 137 * @limit: the bitmap size in bits 138 * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT 139 */ 140 struct mtu3_fifo_info { 141 u32 base; 142 u32 limit; 143 DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE); 144 }; 145 146 /** 147 * General Purpose Descriptor (GPD): 148 * The format of TX GPD is a little different from RX one. 149 * And the size of GPD is 16 bytes. 150 * 151 * @dw0_info: 152 * bit0: Hardware Own (HWO) 153 * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported 154 * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1 155 * bit6: [EL] Zero Length Packet (ZLP), moved from @dw3_info[29] 156 * bit7: Interrupt On Completion (IOC) 157 * bit[31:16]: ([EL] bit[31:12]) allow data buffer length (RX ONLY), 158 * the buffer length of the data to receive 159 * bit[23:16]: ([EL] bit[31:24]) extension address (TX ONLY), 160 * lower 4 bits are extension bits of @buffer, 161 * upper 4 bits are extension bits of @next_gpd 162 * @next_gpd: Physical address of the next GPD 163 * @buffer: Physical address of the data buffer 164 * @dw3_info: 165 * bit[15:0]: ([EL] bit[19:0]) data buffer length, 166 * (TX): the buffer length of the data to transmit 167 * (RX): The total length of data received 168 * bit[23:16]: ([EL] bit[31:24]) extension address (RX ONLY), 169 * lower 4 bits are extension bits of @buffer, 170 * upper 4 bits are extension bits of @next_gpd 171 * bit29: ([EL] abandoned) Zero Length Packet (ZLP) (TX ONLY) 172 */ 173 struct qmu_gpd { 174 __le32 dw0_info; 175 __le32 next_gpd; 176 __le32 buffer; 177 __le32 dw3_info; 178 } __packed; 179 180 /** 181 * dma: physical base address of GPD segment 182 * start: virtual base address of GPD segment 183 * end: the last GPD element 184 * enqueue: the first empty GPD to use 185 * dequeue: the first completed GPD serviced by ISR 186 * NOTE: the size of GPD ring should be >= 2 187 */ 188 struct mtu3_gpd_ring { 189 dma_addr_t dma; 190 struct qmu_gpd *start; 191 struct qmu_gpd *end; 192 struct qmu_gpd *enqueue; 193 struct qmu_gpd *dequeue; 194 }; 195 196 /** 197 * @vbus: vbus 5V used by host mode 198 * @edev: external connector used to detect vbus and iddig changes 199 * @id_nb : notifier for iddig(idpin) detection 200 * @dr_work : work for drd mode switch, used to avoid sleep in atomic context 201 * @desired_role : role desired to switch 202 * @default_role : default mode while usb role is USB_ROLE_NONE 203 * @role_sw : use USB Role Switch to support dual-role switch, can't use 204 * extcon at the same time, and extcon is deprecated. 205 * @role_sw_used : true when the USB Role Switch is used. 206 * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not 207 * @manual_drd_enabled: it's true when supports dual-role device by debugfs 208 * to switch host/device modes depending on user input. 209 */ 210 struct otg_switch_mtk { 211 struct regulator *vbus; 212 struct extcon_dev *edev; 213 struct notifier_block id_nb; 214 struct work_struct dr_work; 215 enum usb_role desired_role; 216 enum usb_role default_role; 217 struct usb_role_switch *role_sw; 218 bool role_sw_used; 219 bool is_u3_drd; 220 bool manual_drd_enabled; 221 }; 222 223 /** 224 * @mac_base: register base address of device MAC, exclude xHCI's 225 * @ippc_base: register base address of IP Power and Clock interface (IPPC) 226 * @vusb33: usb3.3V shared by device/host IP 227 * @dr_mode: works in which mode: 228 * host only, device only or dual-role mode 229 * @u2_ports: number of usb2.0 host ports 230 * @u3_ports: number of usb3.0 host ports 231 * @u2p_dis_msk: mask of disabling usb2 ports, e.g. bit0==1 to 232 * disable u2port0, bit1==1 to disable u2port1,... etc, 233 * but when use dual-role mode, can't disable u2port0 234 * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to 235 * disable u3port0, bit1==1 to disable u3port1,... etc 236 * @dbgfs_root: only used when supports manual dual-role switch via debugfs 237 * @uwk_en: it's true when supports remote wakeup in host mode 238 * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM 239 * @uwk_reg_base: the base address of the wakeup glue layer in @uwk 240 * @uwk_vers: the version of the wakeup glue layer 241 */ 242 struct ssusb_mtk { 243 struct device *dev; 244 struct mtu3 *u3d; 245 void __iomem *mac_base; 246 void __iomem *ippc_base; 247 struct phy **phys; 248 int num_phys; 249 int wakeup_irq; 250 /* common power & clock */ 251 struct regulator *vusb33; 252 struct clk_bulk_data clks[BULK_CLKS_CNT]; 253 /* otg */ 254 struct otg_switch_mtk otg_switch; 255 enum usb_dr_mode dr_mode; 256 bool is_host; 257 int u2_ports; 258 int u3_ports; 259 int u2p_dis_msk; 260 int u3p_dis_msk; 261 struct dentry *dbgfs_root; 262 /* usb wakeup for host mode */ 263 bool uwk_en; 264 struct regmap *uwk; 265 u32 uwk_reg_base; 266 u32 uwk_vers; 267 }; 268 269 /** 270 * @fifo_size: it is (@slot + 1) * @fifo_seg_size 271 * @fifo_seg_size: it is roundup_pow_of_two(@maxp) 272 */ 273 struct mtu3_ep { 274 struct usb_ep ep; 275 char name[12]; 276 struct mtu3 *mtu; 277 u8 epnum; 278 u8 type; 279 u8 is_in; 280 u16 maxp; 281 int slot; 282 u32 fifo_size; 283 u32 fifo_addr; 284 u32 fifo_seg_size; 285 struct mtu3_fifo_info *fifo; 286 287 struct list_head req_list; 288 struct mtu3_gpd_ring gpd_ring; 289 const struct usb_ss_ep_comp_descriptor *comp_desc; 290 const struct usb_endpoint_descriptor *desc; 291 292 int flags; 293 }; 294 295 struct mtu3_request { 296 struct usb_request request; 297 struct list_head list; 298 struct mtu3_ep *mep; 299 struct mtu3 *mtu; 300 struct qmu_gpd *gpd; 301 int epnum; 302 }; 303 304 static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev) 305 { 306 return dev_get_drvdata(dev); 307 } 308 309 /** 310 * struct mtu3 - device driver instance data. 311 * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only, 312 * MTU3_U3_IP_SLOT_DEFAULT for U3 IP 313 * @may_wakeup: means device's remote wakeup is enabled 314 * @is_self_powered: is reported in device status and the config descriptor 315 * @delayed_status: true when function drivers ask for delayed status 316 * @gen2cp: compatible with USB3 Gen2 IP 317 * @ep0_req: dummy request used while handling standard USB requests 318 * for GET_STATUS and SET_SEL 319 * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests 320 */ 321 struct mtu3 { 322 spinlock_t lock; 323 struct ssusb_mtk *ssusb; 324 struct device *dev; 325 void __iomem *mac_base; 326 void __iomem *ippc_base; 327 int irq; 328 329 struct mtu3_fifo_info tx_fifo; 330 struct mtu3_fifo_info rx_fifo; 331 332 struct mtu3_ep *ep_array; 333 struct mtu3_ep *in_eps; 334 struct mtu3_ep *out_eps; 335 struct mtu3_ep *ep0; 336 int num_eps; 337 int slot; 338 int active_ep; 339 340 struct dma_pool *qmu_gpd_pool; 341 enum mtu3_g_ep0_state ep0_state; 342 struct usb_gadget g; /* the gadget */ 343 struct usb_gadget_driver *gadget_driver; 344 struct mtu3_request ep0_req; 345 u8 setup_buf[EP0_RESPONSE_BUF]; 346 enum usb_device_speed max_speed; 347 enum usb_device_speed speed; 348 349 unsigned is_active:1; 350 unsigned may_wakeup:1; 351 unsigned is_self_powered:1; 352 unsigned test_mode:1; 353 unsigned softconnect:1; 354 unsigned u1_enable:1; 355 unsigned u2_enable:1; 356 unsigned is_u3_ip:1; 357 unsigned delayed_status:1; 358 unsigned gen2cp:1; 359 unsigned connected:1; 360 361 u8 address; 362 u8 test_mode_nr; 363 u32 hw_version; 364 }; 365 366 static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g) 367 { 368 return container_of(g, struct mtu3, g); 369 } 370 371 static inline struct mtu3_request *to_mtu3_request(struct usb_request *req) 372 { 373 return req ? container_of(req, struct mtu3_request, request) : NULL; 374 } 375 376 static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep) 377 { 378 return ep ? container_of(ep, struct mtu3_ep, ep) : NULL; 379 } 380 381 static inline struct mtu3_request *next_request(struct mtu3_ep *mep) 382 { 383 return list_first_entry_or_null(&mep->req_list, struct mtu3_request, 384 list); 385 } 386 387 static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data) 388 { 389 writel(data, base + offset); 390 } 391 392 static inline u32 mtu3_readl(void __iomem *base, u32 offset) 393 { 394 return readl(base + offset); 395 } 396 397 static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits) 398 { 399 void __iomem *addr = base + offset; 400 u32 tmp = readl(addr); 401 402 writel((tmp | (bits)), addr); 403 } 404 405 static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits) 406 { 407 void __iomem *addr = base + offset; 408 u32 tmp = readl(addr); 409 410 writel((tmp & ~(bits)), addr); 411 } 412 413 int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks); 414 struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); 415 void mtu3_free_request(struct usb_ep *ep, struct usb_request *req); 416 void mtu3_req_complete(struct mtu3_ep *mep, 417 struct usb_request *req, int status); 418 419 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep, 420 int interval, int burst, int mult); 421 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep); 422 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set); 423 void mtu3_start(struct mtu3 *mtu); 424 void mtu3_stop(struct mtu3 *mtu); 425 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on); 426 427 int mtu3_gadget_setup(struct mtu3 *mtu); 428 void mtu3_gadget_cleanup(struct mtu3 *mtu); 429 void mtu3_gadget_reset(struct mtu3 *mtu); 430 void mtu3_gadget_suspend(struct mtu3 *mtu); 431 void mtu3_gadget_resume(struct mtu3 *mtu); 432 void mtu3_gadget_disconnect(struct mtu3 *mtu); 433 434 irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu); 435 extern const struct usb_ep_ops mtu3_ep0_ops; 436 437 #endif 438