1df2069acSChunfeng Yun /* 2df2069acSChunfeng Yun * mtu3.h - MediaTek USB3 DRD header 3df2069acSChunfeng Yun * 4df2069acSChunfeng Yun * Copyright (C) 2016 MediaTek Inc. 5df2069acSChunfeng Yun * 6df2069acSChunfeng Yun * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 7df2069acSChunfeng Yun * 8df2069acSChunfeng Yun * This software is licensed under the terms of the GNU General Public 9df2069acSChunfeng Yun * License version 2, as published by the Free Software Foundation, and 10df2069acSChunfeng Yun * may be copied, distributed, and modified under those terms. 11df2069acSChunfeng Yun * 12df2069acSChunfeng Yun * This program is distributed in the hope that it will be useful, 13df2069acSChunfeng Yun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14df2069acSChunfeng Yun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15df2069acSChunfeng Yun * GNU General Public License for more details. 16df2069acSChunfeng Yun * 17df2069acSChunfeng Yun */ 18df2069acSChunfeng Yun 19df2069acSChunfeng Yun #ifndef __MTU3_H__ 20df2069acSChunfeng Yun #define __MTU3_H__ 21df2069acSChunfeng Yun 22df2069acSChunfeng Yun #include <linux/device.h> 23df2069acSChunfeng Yun #include <linux/dmapool.h> 24df2069acSChunfeng Yun #include <linux/interrupt.h> 25df2069acSChunfeng Yun #include <linux/list.h> 26df2069acSChunfeng Yun #include <linux/phy/phy.h> 27df2069acSChunfeng Yun #include <linux/regulator/consumer.h> 28df2069acSChunfeng Yun #include <linux/usb.h> 29df2069acSChunfeng Yun #include <linux/usb/ch9.h> 30df2069acSChunfeng Yun #include <linux/usb/gadget.h> 31df2069acSChunfeng Yun #include <linux/usb/otg.h> 32df2069acSChunfeng Yun 33df2069acSChunfeng Yun struct mtu3; 34df2069acSChunfeng Yun struct mtu3_ep; 35df2069acSChunfeng Yun struct mtu3_request; 36df2069acSChunfeng Yun 37df2069acSChunfeng Yun #include "mtu3_hw_regs.h" 38df2069acSChunfeng Yun #include "mtu3_qmu.h" 39df2069acSChunfeng Yun 40df2069acSChunfeng Yun #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10)) 41df2069acSChunfeng Yun #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10)) 42df2069acSChunfeng Yun #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10)) 43df2069acSChunfeng Yun 44df2069acSChunfeng Yun #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10)) 45df2069acSChunfeng Yun #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10)) 46df2069acSChunfeng Yun #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10)) 47df2069acSChunfeng Yun 48df2069acSChunfeng Yun #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10)) 49df2069acSChunfeng Yun #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10)) 50df2069acSChunfeng Yun #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10)) 51df2069acSChunfeng Yun 52df2069acSChunfeng Yun #define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10)) 53df2069acSChunfeng Yun #define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10)) 54df2069acSChunfeng Yun #define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10)) 55df2069acSChunfeng Yun 56a29de31bSChunfeng Yun #define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08)) 57df2069acSChunfeng Yun #define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08)) 58df2069acSChunfeng Yun 59df2069acSChunfeng Yun #define MTU3_DRIVER_NAME "mtu3" 60df2069acSChunfeng Yun #define DMA_ADDR_INVALID (~(dma_addr_t)0) 61df2069acSChunfeng Yun 62df2069acSChunfeng Yun #define MTU3_EP_ENABLED BIT(0) 63df2069acSChunfeng Yun #define MTU3_EP_STALL BIT(1) 64df2069acSChunfeng Yun #define MTU3_EP_WEDGE BIT(2) 65df2069acSChunfeng Yun #define MTU3_EP_BUSY BIT(3) 66df2069acSChunfeng Yun 67a29de31bSChunfeng Yun #define MTU3_U3_IP_SLOT_DEFAULT 2 68df2069acSChunfeng Yun #define MTU3_U2_IP_SLOT_DEFAULT 1 69df2069acSChunfeng Yun 70df2069acSChunfeng Yun /** 71df2069acSChunfeng Yun * Normally the device works on HS or SS, to simplify fifo management, 72df2069acSChunfeng Yun * devide fifo into some 512B parts, use bitmap to manage it; And 73df2069acSChunfeng Yun * 128 bits size of bitmap is large enough, that means it can manage 74df2069acSChunfeng Yun * up to 64KB fifo size. 75df2069acSChunfeng Yun * NOTE: MTU3_EP_FIFO_UNIT should be power of two 76df2069acSChunfeng Yun */ 77df2069acSChunfeng Yun #define MTU3_EP_FIFO_UNIT (1 << 9) 78df2069acSChunfeng Yun #define MTU3_FIFO_BIT_SIZE 128 79df2069acSChunfeng Yun #define MTU3_U2_IP_EP0_FIFO_SIZE 64 80df2069acSChunfeng Yun 81df2069acSChunfeng Yun /** 82df2069acSChunfeng Yun * Maximum size of ep0 response buffer for ch9 requests, 83df2069acSChunfeng Yun * the SET_SEL request uses 6 so far, and GET_STATUS is 2 84df2069acSChunfeng Yun */ 85df2069acSChunfeng Yun #define EP0_RESPONSE_BUF 6 86df2069acSChunfeng Yun 87df2069acSChunfeng Yun /* device operated link and speed got from DEVICE_CONF register */ 88df2069acSChunfeng Yun enum mtu3_speed { 89df2069acSChunfeng Yun MTU3_SPEED_INACTIVE = 0, 90df2069acSChunfeng Yun MTU3_SPEED_FULL = 1, 91df2069acSChunfeng Yun MTU3_SPEED_HIGH = 3, 92a29de31bSChunfeng Yun MTU3_SPEED_SUPER = 4, 93df2069acSChunfeng Yun }; 94df2069acSChunfeng Yun 95df2069acSChunfeng Yun /** 96df2069acSChunfeng Yun * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP 97df2069acSChunfeng Yun * without data stage. 98df2069acSChunfeng Yun * @MU3D_EP0_STATE_TX: IN data stage 99df2069acSChunfeng Yun * @MU3D_EP0_STATE_RX: OUT data stage 100df2069acSChunfeng Yun * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and 101df2069acSChunfeng Yun * waits for its completion interrupt 102df2069acSChunfeng Yun * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared 103df2069acSChunfeng Yun * after receives a SETUP. 104df2069acSChunfeng Yun */ 105df2069acSChunfeng Yun enum mtu3_g_ep0_state { 106df2069acSChunfeng Yun MU3D_EP0_STATE_SETUP = 1, 107df2069acSChunfeng Yun MU3D_EP0_STATE_TX, 108df2069acSChunfeng Yun MU3D_EP0_STATE_RX, 109df2069acSChunfeng Yun MU3D_EP0_STATE_TX_END, 110df2069acSChunfeng Yun MU3D_EP0_STATE_STALL, 111df2069acSChunfeng Yun }; 112df2069acSChunfeng Yun 113df2069acSChunfeng Yun /** 114df2069acSChunfeng Yun * @base: the base address of fifo 115df2069acSChunfeng Yun * @limit: the bitmap size in bits 116df2069acSChunfeng Yun * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT 117df2069acSChunfeng Yun */ 118df2069acSChunfeng Yun struct mtu3_fifo_info { 119df2069acSChunfeng Yun u32 base; 120df2069acSChunfeng Yun u32 limit; 121df2069acSChunfeng Yun DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE); 122df2069acSChunfeng Yun }; 123df2069acSChunfeng Yun 124df2069acSChunfeng Yun /** 125df2069acSChunfeng Yun * General Purpose Descriptor (GPD): 126df2069acSChunfeng Yun * The format of TX GPD is a little different from RX one. 127df2069acSChunfeng Yun * And the size of GPD is 16 bytes. 128df2069acSChunfeng Yun * 129df2069acSChunfeng Yun * @flag: 130df2069acSChunfeng Yun * bit0: Hardware Own (HWO) 131df2069acSChunfeng Yun * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported 132df2069acSChunfeng Yun * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1 133df2069acSChunfeng Yun * bit7: Interrupt On Completion (IOC) 134df2069acSChunfeng Yun * @chksum: This is used to validate the contents of this GPD; 135df2069acSChunfeng Yun * If TXQ_CS_EN / RXQ_CS_EN bit is set, an interrupt is issued 136df2069acSChunfeng Yun * when checksum validation fails; 137df2069acSChunfeng Yun * Checksum value is calculated over the 16 bytes of the GPD by default; 138df2069acSChunfeng Yun * @data_buf_len (RX ONLY): This value indicates the length of 139df2069acSChunfeng Yun * the assigned data buffer 140df2069acSChunfeng Yun * @next_gpd: Physical address of the next GPD 141df2069acSChunfeng Yun * @buffer: Physical address of the data buffer 142df2069acSChunfeng Yun * @buf_len: 143df2069acSChunfeng Yun * (TX): This value indicates the length of the assigned data buffer 144df2069acSChunfeng Yun * (RX): The total length of data received 145df2069acSChunfeng Yun * @ext_len: reserved 146df2069acSChunfeng Yun * @ext_flag: 147df2069acSChunfeng Yun * bit5 (TX ONLY): Zero Length Packet (ZLP), 148df2069acSChunfeng Yun */ 149df2069acSChunfeng Yun struct qmu_gpd { 150df2069acSChunfeng Yun __u8 flag; 151df2069acSChunfeng Yun __u8 chksum; 152df2069acSChunfeng Yun __le16 data_buf_len; 153df2069acSChunfeng Yun __le32 next_gpd; 154df2069acSChunfeng Yun __le32 buffer; 155df2069acSChunfeng Yun __le16 buf_len; 156df2069acSChunfeng Yun __u8 ext_len; 157df2069acSChunfeng Yun __u8 ext_flag; 158df2069acSChunfeng Yun } __packed; 159df2069acSChunfeng Yun 160df2069acSChunfeng Yun /** 161df2069acSChunfeng Yun * dma: physical base address of GPD segment 162df2069acSChunfeng Yun * start: virtual base address of GPD segment 163df2069acSChunfeng Yun * end: the last GPD element 164df2069acSChunfeng Yun * enqueue: the first empty GPD to use 165df2069acSChunfeng Yun * dequeue: the first completed GPD serviced by ISR 166df2069acSChunfeng Yun * NOTE: the size of GPD ring should be >= 2 167df2069acSChunfeng Yun */ 168df2069acSChunfeng Yun struct mtu3_gpd_ring { 169df2069acSChunfeng Yun dma_addr_t dma; 170df2069acSChunfeng Yun struct qmu_gpd *start; 171df2069acSChunfeng Yun struct qmu_gpd *end; 172df2069acSChunfeng Yun struct qmu_gpd *enqueue; 173df2069acSChunfeng Yun struct qmu_gpd *dequeue; 174df2069acSChunfeng Yun }; 175b3f4e727SChunfeng Yun /** 176b3f4e727SChunfeng Yun * @mac_base: register base address of device MAC, exclude xHCI's 177b3f4e727SChunfeng Yun * @ippc_base: register base address of ip port controller interface (IPPC) 178b3f4e727SChunfeng Yun * @vusb33: usb3.3V shared by device/host IP 179b3f4e727SChunfeng Yun * @sys_clk: system clock of mtu3, shared by device/host IP 180b3f4e727SChunfeng Yun * @dr_mode: works in which mode: 181b3f4e727SChunfeng Yun * host only, device only or dual-role mode 182b3f4e727SChunfeng Yun * @u2_ports: number of usb2.0 host ports 183b3f4e727SChunfeng Yun * @u3_ports: number of usb3.0 host ports 184b3f4e727SChunfeng Yun * @wakeup_en: it's true when supports remote wakeup in host mode 185b3f4e727SChunfeng Yun * @wk_deb_p0: port0's wakeup debounce clock 186b3f4e727SChunfeng Yun * @wk_deb_p1: it's optional, and depends on port1 is supported or not 187b3f4e727SChunfeng Yun */ 188b3f4e727SChunfeng Yun struct ssusb_mtk { 189b3f4e727SChunfeng Yun struct device *dev; 190b3f4e727SChunfeng Yun struct mtu3 *u3d; 191b3f4e727SChunfeng Yun void __iomem *mac_base; 192b3f4e727SChunfeng Yun void __iomem *ippc_base; 193b3f4e727SChunfeng Yun struct phy **phys; 194b3f4e727SChunfeng Yun int num_phys; 195b3f4e727SChunfeng Yun /* common power & clock */ 196b3f4e727SChunfeng Yun struct regulator *vusb33; 197b3f4e727SChunfeng Yun struct clk *sys_clk; 198b3f4e727SChunfeng Yun /* otg */ 199b3f4e727SChunfeng Yun enum usb_dr_mode dr_mode; 200b3f4e727SChunfeng Yun bool is_host; 201b3f4e727SChunfeng Yun int u2_ports; 202b3f4e727SChunfeng Yun int u3_ports; 203b3f4e727SChunfeng Yun /* usb wakeup for host mode */ 204b3f4e727SChunfeng Yun bool wakeup_en; 205b3f4e727SChunfeng Yun struct clk *wk_deb_p0; 206b3f4e727SChunfeng Yun struct clk *wk_deb_p1; 207b3f4e727SChunfeng Yun struct regmap *pericfg; 208b3f4e727SChunfeng Yun }; 209df2069acSChunfeng Yun 210df2069acSChunfeng Yun /** 211df2069acSChunfeng Yun * @fifo_size: it is (@slot + 1) * @fifo_seg_size 212df2069acSChunfeng Yun * @fifo_seg_size: it is roundup_pow_of_two(@maxp) 213df2069acSChunfeng Yun */ 214df2069acSChunfeng Yun struct mtu3_ep { 215df2069acSChunfeng Yun struct usb_ep ep; 216df2069acSChunfeng Yun char name[12]; 217df2069acSChunfeng Yun struct mtu3 *mtu; 218df2069acSChunfeng Yun u8 epnum; 219df2069acSChunfeng Yun u8 type; 220df2069acSChunfeng Yun u8 is_in; 221df2069acSChunfeng Yun u16 maxp; 222df2069acSChunfeng Yun int slot; 223df2069acSChunfeng Yun u32 fifo_size; 224df2069acSChunfeng Yun u32 fifo_addr; 225df2069acSChunfeng Yun u32 fifo_seg_size; 226df2069acSChunfeng Yun struct mtu3_fifo_info *fifo; 227df2069acSChunfeng Yun 228df2069acSChunfeng Yun struct list_head req_list; 229df2069acSChunfeng Yun struct mtu3_gpd_ring gpd_ring; 230a29de31bSChunfeng Yun const struct usb_ss_ep_comp_descriptor *comp_desc; 231df2069acSChunfeng Yun const struct usb_endpoint_descriptor *desc; 232df2069acSChunfeng Yun 233df2069acSChunfeng Yun int flags; 234df2069acSChunfeng Yun u8 wedged; 235df2069acSChunfeng Yun u8 busy; 236df2069acSChunfeng Yun }; 237df2069acSChunfeng Yun 238df2069acSChunfeng Yun struct mtu3_request { 239df2069acSChunfeng Yun struct usb_request request; 240df2069acSChunfeng Yun struct list_head list; 241df2069acSChunfeng Yun struct mtu3_ep *mep; 242df2069acSChunfeng Yun struct mtu3 *mtu; 243df2069acSChunfeng Yun struct qmu_gpd *gpd; 244df2069acSChunfeng Yun int epnum; 245df2069acSChunfeng Yun }; 246df2069acSChunfeng Yun 247b3f4e727SChunfeng Yun static inline struct ssusb_mtk *dev_to_ssusb(struct device *dev) 248b3f4e727SChunfeng Yun { 249b3f4e727SChunfeng Yun return dev_get_drvdata(dev); 250b3f4e727SChunfeng Yun } 251b3f4e727SChunfeng Yun 252df2069acSChunfeng Yun /** 253df2069acSChunfeng Yun * struct mtu3 - device driver instance data. 254a29de31bSChunfeng Yun * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only, 255a29de31bSChunfeng Yun * MTU3_U3_IP_SLOT_DEFAULT for U3 IP 256df2069acSChunfeng Yun * @may_wakeup: means device's remote wakeup is enabled 257df2069acSChunfeng Yun * @is_self_powered: is reported in device status and the config descriptor 258df2069acSChunfeng Yun * @ep0_req: dummy request used while handling standard USB requests 259df2069acSChunfeng Yun * for GET_STATUS and SET_SEL 260df2069acSChunfeng Yun * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests 261df2069acSChunfeng Yun */ 262df2069acSChunfeng Yun struct mtu3 { 263df2069acSChunfeng Yun spinlock_t lock; 264b3f4e727SChunfeng Yun struct ssusb_mtk *ssusb; 265df2069acSChunfeng Yun struct device *dev; 266df2069acSChunfeng Yun void __iomem *mac_base; 267df2069acSChunfeng Yun void __iomem *ippc_base; 268df2069acSChunfeng Yun int irq; 269df2069acSChunfeng Yun 270df2069acSChunfeng Yun struct mtu3_fifo_info tx_fifo; 271df2069acSChunfeng Yun struct mtu3_fifo_info rx_fifo; 272df2069acSChunfeng Yun 273df2069acSChunfeng Yun struct mtu3_ep *ep_array; 274df2069acSChunfeng Yun struct mtu3_ep *in_eps; 275df2069acSChunfeng Yun struct mtu3_ep *out_eps; 276df2069acSChunfeng Yun struct mtu3_ep *ep0; 277df2069acSChunfeng Yun int num_eps; 278df2069acSChunfeng Yun int slot; 279df2069acSChunfeng Yun int active_ep; 280df2069acSChunfeng Yun 281df2069acSChunfeng Yun struct dma_pool *qmu_gpd_pool; 282df2069acSChunfeng Yun enum mtu3_g_ep0_state ep0_state; 283df2069acSChunfeng Yun struct usb_gadget g; /* the gadget */ 284df2069acSChunfeng Yun struct usb_gadget_driver *gadget_driver; 285df2069acSChunfeng Yun struct mtu3_request ep0_req; 286df2069acSChunfeng Yun u8 setup_buf[EP0_RESPONSE_BUF]; 287a29de31bSChunfeng Yun u32 max_speed; 288df2069acSChunfeng Yun 289df2069acSChunfeng Yun unsigned is_active:1; 290df2069acSChunfeng Yun unsigned may_wakeup:1; 291df2069acSChunfeng Yun unsigned is_self_powered:1; 292df2069acSChunfeng Yun unsigned test_mode:1; 293df2069acSChunfeng Yun unsigned softconnect:1; 294a29de31bSChunfeng Yun unsigned u1_enable:1; 295a29de31bSChunfeng Yun unsigned u2_enable:1; 296a29de31bSChunfeng Yun unsigned is_u3_ip:1; 297df2069acSChunfeng Yun 298df2069acSChunfeng Yun u8 address; 299df2069acSChunfeng Yun u8 test_mode_nr; 300df2069acSChunfeng Yun u32 hw_version; 301df2069acSChunfeng Yun }; 302df2069acSChunfeng Yun 303df2069acSChunfeng Yun static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g) 304df2069acSChunfeng Yun { 305df2069acSChunfeng Yun return container_of(g, struct mtu3, g); 306df2069acSChunfeng Yun } 307df2069acSChunfeng Yun 308df2069acSChunfeng Yun static inline int is_first_entry(const struct list_head *list, 309df2069acSChunfeng Yun const struct list_head *head) 310df2069acSChunfeng Yun { 311df2069acSChunfeng Yun return list_is_last(head, list); 312df2069acSChunfeng Yun } 313df2069acSChunfeng Yun 314df2069acSChunfeng Yun static inline struct mtu3_request *to_mtu3_request(struct usb_request *req) 315df2069acSChunfeng Yun { 316df2069acSChunfeng Yun return req ? container_of(req, struct mtu3_request, request) : NULL; 317df2069acSChunfeng Yun } 318df2069acSChunfeng Yun 319df2069acSChunfeng Yun static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep) 320df2069acSChunfeng Yun { 321df2069acSChunfeng Yun return ep ? container_of(ep, struct mtu3_ep, ep) : NULL; 322df2069acSChunfeng Yun } 323df2069acSChunfeng Yun 324df2069acSChunfeng Yun static inline struct mtu3_request *next_request(struct mtu3_ep *mep) 325df2069acSChunfeng Yun { 326df2069acSChunfeng Yun struct list_head *queue = &mep->req_list; 327df2069acSChunfeng Yun 328df2069acSChunfeng Yun if (list_empty(queue)) 329df2069acSChunfeng Yun return NULL; 330df2069acSChunfeng Yun 331df2069acSChunfeng Yun return list_first_entry(queue, struct mtu3_request, list); 332df2069acSChunfeng Yun } 333df2069acSChunfeng Yun 334df2069acSChunfeng Yun static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data) 335df2069acSChunfeng Yun { 336df2069acSChunfeng Yun writel(data, base + offset); 337df2069acSChunfeng Yun } 338df2069acSChunfeng Yun 339df2069acSChunfeng Yun static inline u32 mtu3_readl(void __iomem *base, u32 offset) 340df2069acSChunfeng Yun { 341df2069acSChunfeng Yun return readl(base + offset); 342df2069acSChunfeng Yun } 343df2069acSChunfeng Yun 344df2069acSChunfeng Yun static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits) 345df2069acSChunfeng Yun { 346df2069acSChunfeng Yun void __iomem *addr = base + offset; 347df2069acSChunfeng Yun u32 tmp = readl(addr); 348df2069acSChunfeng Yun 349df2069acSChunfeng Yun writel((tmp | (bits)), addr); 350df2069acSChunfeng Yun } 351df2069acSChunfeng Yun 352df2069acSChunfeng Yun static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits) 353df2069acSChunfeng Yun { 354df2069acSChunfeng Yun void __iomem *addr = base + offset; 355df2069acSChunfeng Yun u32 tmp = readl(addr); 356df2069acSChunfeng Yun 357df2069acSChunfeng Yun writel((tmp & ~(bits)), addr); 358df2069acSChunfeng Yun } 359df2069acSChunfeng Yun 360b3f4e727SChunfeng Yun int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks); 361df2069acSChunfeng Yun struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); 362df2069acSChunfeng Yun void mtu3_free_request(struct usb_ep *ep, struct usb_request *req); 363df2069acSChunfeng Yun void mtu3_req_complete(struct mtu3_ep *mep, 364df2069acSChunfeng Yun struct usb_request *req, int status); 365df2069acSChunfeng Yun 366df2069acSChunfeng Yun int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep, 367df2069acSChunfeng Yun int interval, int burst, int mult); 368df2069acSChunfeng Yun void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep); 369df2069acSChunfeng Yun void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set); 370df2069acSChunfeng Yun void mtu3_ep0_setup(struct mtu3 *mtu); 371df2069acSChunfeng Yun void mtu3_start(struct mtu3 *mtu); 372df2069acSChunfeng Yun void mtu3_stop(struct mtu3 *mtu); 373a29de31bSChunfeng Yun void mtu3_dev_on_off(struct mtu3 *mtu, int is_on); 374df2069acSChunfeng Yun 375df2069acSChunfeng Yun int mtu3_gadget_setup(struct mtu3 *mtu); 376df2069acSChunfeng Yun void mtu3_gadget_cleanup(struct mtu3 *mtu); 377df2069acSChunfeng Yun void mtu3_gadget_reset(struct mtu3 *mtu); 378df2069acSChunfeng Yun void mtu3_gadget_suspend(struct mtu3 *mtu); 379df2069acSChunfeng Yun void mtu3_gadget_resume(struct mtu3 *mtu); 380df2069acSChunfeng Yun void mtu3_gadget_disconnect(struct mtu3 *mtu); 381df2069acSChunfeng Yun 382df2069acSChunfeng Yun irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu); 383df2069acSChunfeng Yun extern const struct usb_ep_ops mtu3_ep0_ops; 384df2069acSChunfeng Yun 385df2069acSChunfeng Yun #endif 386