1 /* 2 * Driver for the NXP ISP1760 chip 3 * 4 * Copyright 2014 Laurent Pinchart 5 * Copyright 2007 Sebastian Siewior 6 * 7 * Contacts: 8 * Sebastian Siewior <bigeasy@linutronix.de> 9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * version 2 as published by the Free Software Foundation. 14 */ 15 16 #ifndef _ISP1760_REGS_H_ 17 #define _ISP1760_REGS_H_ 18 19 /* ----------------------------------------------------------------------------- 20 * Host Controller 21 */ 22 23 /* EHCI capability registers */ 24 #define HC_CAPLENGTH 0x000 25 #define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */ 26 #define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */ 27 28 #define HC_HCSPARAMS 0x004 29 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */ 30 #define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */ 31 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */ 32 33 #define HC_HCCPARAMS 0x008 34 #define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */ 35 #define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */ 36 37 /* EHCI operational registers */ 38 #define HC_USBCMD 0x020 39 #define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */ 40 #define CMD_RESET (1 << 1) /* reset HC not bus */ 41 #define CMD_RUN (1 << 0) /* start/stop HC */ 42 43 #define HC_USBSTS 0x024 44 #define STS_PCD (1 << 2) /* port change detect */ 45 46 #define HC_FRINDEX 0x02c 47 48 #define HC_CONFIGFLAG 0x060 49 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ 50 51 #define HC_PORTSC1 0x064 52 #define PORT_OWNER (1 << 13) /* true: companion hc owns this port */ 53 #define PORT_POWER (1 << 12) /* true: has power (see PPC) */ 54 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ 55 #define PORT_RESET (1 << 8) /* reset port */ 56 #define PORT_SUSPEND (1 << 7) /* suspend port */ 57 #define PORT_RESUME (1 << 6) /* resume it */ 58 #define PORT_PE (1 << 2) /* port enable */ 59 #define PORT_CSC (1 << 1) /* connect status change */ 60 #define PORT_CONNECT (1 << 0) /* device connected */ 61 #define PORT_RWC_BITS (PORT_CSC) 62 63 #define HC_ISO_PTD_DONEMAP_REG 0x130 64 #define HC_ISO_PTD_SKIPMAP_REG 0x134 65 #define HC_ISO_PTD_LASTPTD_REG 0x138 66 #define HC_INT_PTD_DONEMAP_REG 0x140 67 #define HC_INT_PTD_SKIPMAP_REG 0x144 68 #define HC_INT_PTD_LASTPTD_REG 0x148 69 #define HC_ATL_PTD_DONEMAP_REG 0x150 70 #define HC_ATL_PTD_SKIPMAP_REG 0x154 71 #define HC_ATL_PTD_LASTPTD_REG 0x158 72 73 /* Configuration Register */ 74 #define HC_HW_MODE_CTRL 0x300 75 #define ALL_ATX_RESET (1 << 31) 76 #define HW_ANA_DIGI_OC (1 << 15) 77 #define HW_DEV_DMA (1 << 11) 78 #define HW_COMN_IRQ (1 << 10) 79 #define HW_COMN_DMA (1 << 9) 80 #define HW_DATA_BUS_32BIT (1 << 8) 81 #define HW_DACK_POL_HIGH (1 << 6) 82 #define HW_DREQ_POL_HIGH (1 << 5) 83 #define HW_INTR_HIGH_ACT (1 << 2) 84 #define HW_INTR_EDGE_TRIG (1 << 1) 85 #define HW_GLOBAL_INTR_EN (1 << 0) 86 87 #define HC_CHIP_ID_REG 0x304 88 #define HC_SCRATCH_REG 0x308 89 90 #define HC_RESET_REG 0x30c 91 #define SW_RESET_RESET_HC (1 << 1) 92 #define SW_RESET_RESET_ALL (1 << 0) 93 94 #define HC_BUFFER_STATUS_REG 0x334 95 #define ISO_BUF_FILL (1 << 2) 96 #define INT_BUF_FILL (1 << 1) 97 #define ATL_BUF_FILL (1 << 0) 98 99 #define HC_MEMORY_REG 0x33c 100 #define ISP_BANK(x) ((x) << 16) 101 102 #define HC_PORT1_CTRL 0x374 103 #define PORT1_POWER (3 << 3) 104 #define PORT1_INIT1 (1 << 7) 105 #define PORT1_INIT2 (1 << 23) 106 #define HW_OTG_CTRL_SET 0x374 107 #define HW_OTG_CTRL_CLR 0x376 108 #define HW_OTG_DISABLE (1 << 10) 109 #define HW_OTG_SE0_EN (1 << 9) 110 #define HW_BDIS_ACON_EN (1 << 8) 111 #define HW_SW_SEL_HC_DC (1 << 7) 112 #define HW_VBUS_CHRG (1 << 6) 113 #define HW_VBUS_DISCHRG (1 << 5) 114 #define HW_VBUS_DRV (1 << 4) 115 #define HW_SEL_CP_EXT (1 << 3) 116 #define HW_DM_PULLDOWN (1 << 2) 117 #define HW_DP_PULLDOWN (1 << 1) 118 #define HW_DP_PULLUP (1 << 0) 119 120 /* Interrupt Register */ 121 #define HC_INTERRUPT_REG 0x310 122 123 #define HC_INTERRUPT_ENABLE 0x314 124 #define HC_ISO_INT (1 << 9) 125 #define HC_ATL_INT (1 << 8) 126 #define HC_INTL_INT (1 << 7) 127 #define HC_EOT_INT (1 << 3) 128 #define HC_SOT_INT (1 << 1) 129 #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT) 130 131 #define HC_ISO_IRQ_MASK_OR_REG 0x318 132 #define HC_INT_IRQ_MASK_OR_REG 0x31c 133 #define HC_ATL_IRQ_MASK_OR_REG 0x320 134 #define HC_ISO_IRQ_MASK_AND_REG 0x324 135 #define HC_INT_IRQ_MASK_AND_REG 0x328 136 #define HC_ATL_IRQ_MASK_AND_REG 0x32c 137 138 /* ----------------------------------------------------------------------------- 139 * Peripheral Controller 140 */ 141 142 /* Initialization Registers */ 143 #define DC_ADDRESS 0x0200 144 #define DC_DEVEN (1 << 7) 145 146 #define DC_MODE 0x020c 147 #define DC_DMACLKON (1 << 9) 148 #define DC_VBUSSTAT (1 << 8) 149 #define DC_CLKAON (1 << 7) 150 #define DC_SNDRSU (1 << 6) 151 #define DC_GOSUSP (1 << 5) 152 #define DC_SFRESET (1 << 4) 153 #define DC_GLINTENA (1 << 3) 154 #define DC_WKUPCS (1 << 2) 155 156 #define DC_INTCONF 0x0210 157 #define DC_CDBGMOD_ACK_NAK (0 << 6) 158 #define DC_CDBGMOD_ACK (1 << 6) 159 #define DC_CDBGMOD_ACK_1NAK (2 << 6) 160 #define DC_DDBGMODIN_ACK_NAK (0 << 4) 161 #define DC_DDBGMODIN_ACK (1 << 4) 162 #define DC_DDBGMODIN_ACK_1NAK (2 << 4) 163 #define DC_DDBGMODOUT_ACK_NYET_NAK (0 << 2) 164 #define DC_DDBGMODOUT_ACK_NYET (1 << 2) 165 #define DC_DDBGMODOUT_ACK_NYET_1NAK (2 << 2) 166 #define DC_INTLVL (1 << 1) 167 #define DC_INTPOL (1 << 0) 168 169 #define DC_DEBUG 0x0212 170 #define DC_INTENABLE 0x0214 171 #define DC_IEPTX(n) (1 << (11 + 2 * (n))) 172 #define DC_IEPRX(n) (1 << (10 + 2 * (n))) 173 #define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) 174 #define DC_IEP0SETUP (1 << 8) 175 #define DC_IEVBUS (1 << 7) 176 #define DC_IEDMA (1 << 6) 177 #define DC_IEHS_STA (1 << 5) 178 #define DC_IERESM (1 << 4) 179 #define DC_IESUSP (1 << 3) 180 #define DC_IEPSOF (1 << 2) 181 #define DC_IESOF (1 << 1) 182 #define DC_IEBRST (1 << 0) 183 184 /* Data Flow Registers */ 185 #define DC_EPINDEX 0x022c 186 #define DC_EP0SETUP (1 << 5) 187 #define DC_ENDPIDX(n) ((n) << 1) 188 #define DC_EPDIR (1 << 0) 189 190 #define DC_CTRLFUNC 0x0228 191 #define DC_CLBUF (1 << 4) 192 #define DC_VENDP (1 << 3) 193 #define DC_DSEN (1 << 2) 194 #define DC_STATUS (1 << 1) 195 #define DC_STALL (1 << 0) 196 197 #define DC_DATAPORT 0x0220 198 #define DC_BUFLEN 0x021c 199 #define DC_DATACOUNT_MASK 0xffff 200 #define DC_BUFSTAT 0x021e 201 #define DC_EPMAXPKTSZ 0x0204 202 203 #define DC_EPTYPE 0x0208 204 #define DC_NOEMPKT (1 << 4) 205 #define DC_EPENABLE (1 << 3) 206 #define DC_DBLBUF (1 << 2) 207 #define DC_ENDPTYP_ISOC (1 << 0) 208 #define DC_ENDPTYP_BULK (2 << 0) 209 #define DC_ENDPTYP_INTERRUPT (3 << 0) 210 211 /* DMA Registers */ 212 #define DC_DMACMD 0x0230 213 #define DC_DMATXCOUNT 0x0234 214 #define DC_DMACONF 0x0238 215 #define DC_DMAHW 0x023c 216 #define DC_DMAINTREASON 0x0250 217 #define DC_DMAINTEN 0x0254 218 #define DC_DMAEP 0x0258 219 #define DC_DMABURSTCOUNT 0x0264 220 221 /* General Registers */ 222 #define DC_INTERRUPT 0x0218 223 #define DC_CHIPID 0x0270 224 #define DC_FRAMENUM 0x0274 225 #define DC_SCRATCH 0x0278 226 #define DC_UNLOCKDEV 0x027c 227 #define DC_INTPULSEWIDTH 0x0280 228 #define DC_TESTMODE 0x0284 229 230 #endif 231