1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Driver for the NXP ISP1760 chip 4 * 5 * Copyright 2021 Linaro, Rui Miguel Silva 6 * Copyright 2014 Laurent Pinchart 7 * Copyright 2007 Sebastian Siewior 8 * 9 * Contacts: 10 * Sebastian Siewior <bigeasy@linutronix.de> 11 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 12 * Rui Miguel Silva <rui.silva@linaro.org> 13 */ 14 15 #ifndef _ISP176x_REGS_H_ 16 #define _ISP176x_REGS_H_ 17 18 /* ----------------------------------------------------------------------------- 19 * Host Controller 20 */ 21 22 /* ISP1760/31 */ 23 /* EHCI capability registers */ 24 #define ISP176x_HC_VERSION 0x002 25 #define ISP176x_HC_HCSPARAMS 0x004 26 #define ISP176x_HC_HCCPARAMS 0x008 27 28 /* EHCI operational registers */ 29 #define ISP176x_HC_USBCMD 0x020 30 #define ISP176x_HC_USBSTS 0x024 31 #define ISP176x_HC_FRINDEX 0x02c 32 33 #define ISP176x_HC_CONFIGFLAG 0x060 34 #define ISP176x_HC_PORTSC1 0x064 35 36 #define ISP176x_HC_ISO_PTD_DONEMAP 0x130 37 #define ISP176x_HC_ISO_PTD_SKIPMAP 0x134 38 #define ISP176x_HC_ISO_PTD_LASTPTD 0x138 39 #define ISP176x_HC_INT_PTD_DONEMAP 0x140 40 #define ISP176x_HC_INT_PTD_SKIPMAP 0x144 41 #define ISP176x_HC_INT_PTD_LASTPTD 0x148 42 #define ISP176x_HC_ATL_PTD_DONEMAP 0x150 43 #define ISP176x_HC_ATL_PTD_SKIPMAP 0x154 44 #define ISP176x_HC_ATL_PTD_LASTPTD 0x158 45 46 /* Configuration Register */ 47 #define ISP176x_HC_HW_MODE_CTRL 0x300 48 #define ISP176x_HC_CHIP_ID 0x304 49 #define ISP176x_HC_SCRATCH 0x308 50 #define ISP176x_HC_RESET 0x30c 51 #define ISP176x_HC_BUFFER_STATUS 0x334 52 #define ISP176x_HC_MEMORY 0x33c 53 54 /* Interrupt Register */ 55 #define ISP176x_HC_INTERRUPT 0x310 56 #define ISP176x_HC_INTERRUPT_ENABLE 0x314 57 #define ISP176x_HC_ISO_IRQ_MASK_OR 0x318 58 #define ISP176x_HC_INT_IRQ_MASK_OR 0x31c 59 #define ISP176x_HC_ATL_IRQ_MASK_OR 0x320 60 #define ISP176x_HC_ISO_IRQ_MASK_AND 0x324 61 #define ISP176x_HC_INT_IRQ_MASK_AND 0x328 62 #define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c 63 64 #define ISP176x_HC_OTG_CTRL_SET 0x374 65 #define ISP176x_HC_OTG_CTRL_CLEAR 0x376 66 67 enum isp176x_host_controller_fields { 68 /* HC_PORTSC1 */ 69 PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, 70 PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, 71 /* HC_HCSPARAMS */ 72 HCS_PPC, HCS_N_PORTS, 73 /* HC_HCCPARAMS */ 74 HCC_ISOC_CACHE, HCC_ISOC_THRES, 75 /* HC_USBCMD */ 76 CMD_LRESET, CMD_RESET, CMD_RUN, 77 /* HC_USBSTS */ 78 STS_PCD, 79 /* HC_FRINDEX */ 80 HC_FRINDEX, 81 /* HC_CONFIGFLAG */ 82 FLAG_CF, 83 /* ISO/INT/ATL PTD */ 84 HC_ISO_PTD_DONEMAP, HC_ISO_PTD_SKIPMAP, HC_ISO_PTD_LASTPTD, 85 HC_INT_PTD_DONEMAP, HC_INT_PTD_SKIPMAP, HC_INT_PTD_LASTPTD, 86 HC_ATL_PTD_DONEMAP, HC_ATL_PTD_SKIPMAP, HC_ATL_PTD_LASTPTD, 87 /* HC_HW_MODE_CTRL */ 88 ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA, 89 HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT, 90 HW_INTF_LOCK, HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, 91 /* HC_CHIP_ID */ 92 HC_CHIP_ID_HIGH, HC_CHIP_ID_LOW, HC_CHIP_REV, 93 /* HC_SCRATCH */ 94 HC_SCRATCH, 95 /* HC_RESET */ 96 SW_RESET_RESET_ATX, SW_RESET_RESET_HC, SW_RESET_RESET_ALL, 97 /* HC_BUFFER_STATUS */ 98 ISO_BUF_FILL, INT_BUF_FILL, ATL_BUF_FILL, 99 /* HC_MEMORY */ 100 MEM_BANK_SEL, MEM_START_ADDR, 101 /* HC_DATA */ 102 HC_DATA, 103 /* HC_INTERRUPT */ 104 HC_INTERRUPT, 105 /* HC_INTERRUPT_ENABLE */ 106 HC_INT_IRQ_ENABLE, HC_ATL_IRQ_ENABLE, 107 /* INTERRUPT MASKS */ 108 HC_ISO_IRQ_MASK_OR, HC_INT_IRQ_MASK_OR, HC_ATL_IRQ_MASK_OR, 109 HC_ISO_IRQ_MASK_AND, HC_INT_IRQ_MASK_AND, HC_ATL_IRQ_MASK_AND, 110 /* HW_OTG_CTRL_SET */ 111 HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, 112 HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, HW_HC_2_DIS, 113 /* HW_OTG_CTRL_CLR */ 114 HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, 115 HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, 116 HW_DP_PULLUP_CLEAR, HW_HC_2_DIS_CLEAR, 117 /* Last element */ 118 HC_FIELD_MAX, 119 }; 120 121 /* ISP1763 */ 122 /* EHCI operational registers */ 123 #define ISP1763_HC_USBCMD 0x8c 124 #define ISP1763_HC_USBSTS 0x90 125 #define ISP1763_HC_FRINDEX 0x98 126 127 #define ISP1763_HC_CONFIGFLAG 0x9c 128 #define ISP1763_HC_PORTSC1 0xa0 129 130 #define ISP1763_HC_ISO_PTD_DONEMAP 0xa4 131 #define ISP1763_HC_ISO_PTD_SKIPMAP 0xa6 132 #define ISP1763_HC_ISO_PTD_LASTPTD 0xa8 133 #define ISP1763_HC_INT_PTD_DONEMAP 0xaa 134 #define ISP1763_HC_INT_PTD_SKIPMAP 0xac 135 #define ISP1763_HC_INT_PTD_LASTPTD 0xae 136 #define ISP1763_HC_ATL_PTD_DONEMAP 0xb0 137 #define ISP1763_HC_ATL_PTD_SKIPMAP 0xb2 138 #define ISP1763_HC_ATL_PTD_LASTPTD 0xb4 139 140 /* Configuration Register */ 141 #define ISP1763_HC_HW_MODE_CTRL 0xb6 142 #define ISP1763_HC_CHIP_REV 0x70 143 #define ISP1763_HC_CHIP_ID 0x72 144 #define ISP1763_HC_SCRATCH 0x78 145 #define ISP1763_HC_RESET 0xb8 146 #define ISP1763_HC_BUFFER_STATUS 0xba 147 #define ISP1763_HC_MEMORY 0xc4 148 #define ISP1763_HC_DATA 0xc6 149 150 /* Interrupt Register */ 151 #define ISP1763_HC_INTERRUPT 0xd4 152 #define ISP1763_HC_INTERRUPT_ENABLE 0xd6 153 #define ISP1763_HC_ISO_IRQ_MASK_OR 0xd8 154 #define ISP1763_HC_INT_IRQ_MASK_OR 0xda 155 #define ISP1763_HC_ATL_IRQ_MASK_OR 0xdc 156 #define ISP1763_HC_ISO_IRQ_MASK_AND 0xde 157 #define ISP1763_HC_INT_IRQ_MASK_AND 0xe0 158 #define ISP1763_HC_ATL_IRQ_MASK_AND 0xe2 159 160 #define ISP1763_HC_OTG_CTRL_SET 0xe4 161 #define ISP1763_HC_OTG_CTRL_CLEAR 0xe6 162 163 /* ----------------------------------------------------------------------------- 164 * Peripheral Controller 165 */ 166 167 #define DC_IEPTX(n) (1 << (11 + 2 * (n))) 168 #define DC_IEPRX(n) (1 << (10 + 2 * (n))) 169 #define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) 170 171 #define ISP176x_DC_CDBGMOD_ACK BIT(6) 172 #define ISP176x_DC_DDBGMODIN_ACK BIT(4) 173 #define ISP176x_DC_DDBGMODOUT_ACK BIT(2) 174 175 #define ISP176x_DC_IEP0SETUP BIT(8) 176 #define ISP176x_DC_IEVBUS BIT(7) 177 #define ISP176x_DC_IEHS_STA BIT(5) 178 #define ISP176x_DC_IERESM BIT(4) 179 #define ISP176x_DC_IESUSP BIT(3) 180 #define ISP176x_DC_IEBRST BIT(0) 181 182 #define ISP176x_DC_ENDPTYP_ISOC 0x01 183 #define ISP176x_DC_ENDPTYP_BULK 0x02 184 #define ISP176x_DC_ENDPTYP_INTERRUPT 0x03 185 186 /* Initialization Registers */ 187 #define ISP176x_DC_ADDRESS 0x0200 188 #define ISP176x_DC_MODE 0x020c 189 #define ISP176x_DC_INTCONF 0x0210 190 #define ISP176x_DC_DEBUG 0x0212 191 #define ISP176x_DC_INTENABLE 0x0214 192 193 /* Data Flow Registers */ 194 #define ISP176x_DC_EPMAXPKTSZ 0x0204 195 #define ISP176x_DC_EPTYPE 0x0208 196 197 #define ISP176x_DC_BUFLEN 0x021c 198 #define ISP176x_DC_BUFSTAT 0x021e 199 #define ISP176x_DC_DATAPORT 0x0220 200 201 #define ISP176x_DC_CTRLFUNC 0x0228 202 #define ISP176x_DC_EPINDEX 0x022c 203 204 /* DMA Registers */ 205 #define ISP176x_DC_DMACMD 0x0230 206 #define ISP176x_DC_DMATXCOUNT 0x0234 207 #define ISP176x_DC_DMACONF 0x0238 208 #define ISP176x_DC_DMAHW 0x023c 209 #define ISP176x_DC_DMAINTREASON 0x0250 210 #define ISP176x_DC_DMAINTEN 0x0254 211 #define ISP176x_DC_DMAEP 0x0258 212 #define ISP176x_DC_DMABURSTCOUNT 0x0264 213 214 /* General Registers */ 215 #define ISP176x_DC_INTERRUPT 0x0218 216 #define ISP176x_DC_CHIPID 0x0270 217 #define ISP176x_DC_FRAMENUM 0x0274 218 #define ISP176x_DC_SCRATCH 0x0278 219 #define ISP176x_DC_UNLOCKDEV 0x027c 220 #define ISP176x_DC_INTPULSEWIDTH 0x0280 221 #define ISP176x_DC_TESTMODE 0x0284 222 223 enum isp176x_device_controller_fields { 224 /* DC_ADDRESS */ 225 DC_DEVEN, DC_DEVADDR, 226 /* DC_MODE */ 227 DC_VBUSSTAT, DC_SFRESET, DC_GLINTENA, 228 /* DC_INTCONF */ 229 DC_CDBGMOD_ACK, DC_DDBGMODIN_ACK, DC_DDBGMODOUT_ACK, DC_INTPOL, 230 /* DC_INTENABLE */ 231 DC_IEPRXTX_7, DC_IEPRXTX_6, DC_IEPRXTX_5, DC_IEPRXTX_4, DC_IEPRXTX_3, 232 DC_IEPRXTX_2, DC_IEPRXTX_1, DC_IEPRXTX_0, 233 DC_IEP0SETUP, DC_IEVBUS, DC_IEHS_STA, DC_IERESM, DC_IESUSP, DC_IEBRST, 234 /* DC_EPINDEX */ 235 DC_EP0SETUP, DC_ENDPIDX, DC_EPDIR, 236 /* DC_CTRLFUNC */ 237 DC_CLBUF, DC_VENDP, DC_DSEN, DC_STATUS, DC_STALL, 238 /* DC_BUFLEN */ 239 DC_BUFLEN, 240 /* DC_EPMAXPKTSZ */ 241 DC_FFOSZ, 242 /* DC_EPTYPE */ 243 DC_EPENABLE, DC_ENDPTYP, 244 /* DC_FRAMENUM */ 245 DC_FRAMENUM, DC_UFRAMENUM, 246 /* DC_CHIP_ID */ 247 DC_CHIP_ID_HIGH, DC_CHIP_ID_LOW, 248 /* DC_SCRATCH */ 249 DC_SCRATCH, 250 /* Last element */ 251 DC_FIELD_MAX, 252 }; 253 254 /* ISP1763 */ 255 /* Initialization Registers */ 256 #define ISP1763_DC_ADDRESS 0x00 257 #define ISP1763_DC_MODE 0x0c 258 #define ISP1763_DC_INTCONF 0x10 259 #define ISP1763_DC_INTENABLE 0x14 260 261 /* Data Flow Registers */ 262 #define ISP1763_DC_EPMAXPKTSZ 0x04 263 #define ISP1763_DC_EPTYPE 0x08 264 265 #define ISP1763_DC_BUFLEN 0x1c 266 #define ISP1763_DC_BUFSTAT 0x1e 267 #define ISP1763_DC_DATAPORT 0x20 268 269 #define ISP1763_DC_CTRLFUNC 0x28 270 #define ISP1763_DC_EPINDEX 0x2c 271 272 /* DMA Registers */ 273 #define ISP1763_DC_DMACMD 0x30 274 #define ISP1763_DC_DMATXCOUNT 0x34 275 #define ISP1763_DC_DMACONF 0x38 276 #define ISP1763_DC_DMAHW 0x3c 277 #define ISP1763_DC_DMAINTREASON 0x50 278 #define ISP1763_DC_DMAINTEN 0x54 279 #define ISP1763_DC_DMAEP 0x58 280 #define ISP1763_DC_DMABURSTCOUNT 0x64 281 282 /* General Registers */ 283 #define ISP1763_DC_INTERRUPT 0x18 284 #define ISP1763_DC_CHIPID_LOW 0x70 285 #define ISP1763_DC_CHIPID_HIGH 0x72 286 #define ISP1763_DC_FRAMENUM 0x74 287 #define ISP1763_DC_SCRATCH 0x78 288 #define ISP1763_DC_UNLOCKDEV 0x7c 289 #define ISP1763_DC_INTPULSEWIDTH 0x80 290 #define ISP1763_DC_TESTMODE 0x84 291 292 #endif 293