1 /* 2 * Driver for the NXP ISP1760 chip 3 * 4 * However, the code might contain some bugs. What doesn't work for sure is: 5 * - ISO 6 * - OTG 7 e The interrupt line is configured as active low, level. 8 * 9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> 10 * 11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> 12 * 13 */ 14 #include <linux/gpio/consumer.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/usb.h> 20 #include <linux/usb/hcd.h> 21 #include <linux/debugfs.h> 22 #include <linux/uaccess.h> 23 #include <linux/io.h> 24 #include <linux/mm.h> 25 #include <linux/timer.h> 26 #include <asm/unaligned.h> 27 #include <asm/cacheflush.h> 28 29 #include "isp1760-core.h" 30 #include "isp1760-hcd.h" 31 #include "isp1760-regs.h" 32 33 static struct kmem_cache *qtd_cachep; 34 static struct kmem_cache *qh_cachep; 35 static struct kmem_cache *urb_listitem_cachep; 36 37 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 38 struct isp1760_qtd *qtd); 39 40 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) 41 { 42 return *(struct isp1760_hcd **)hcd->hcd_priv; 43 } 44 45 /* urb state*/ 46 #define DELETE_URB (0x0008) 47 #define NO_TRANSFER_ACTIVE (0xffffffff) 48 49 /* Philips Proprietary Transfer Descriptor (PTD) */ 50 typedef __u32 __bitwise __dw; 51 struct ptd { 52 __dw dw0; 53 __dw dw1; 54 __dw dw2; 55 __dw dw3; 56 __dw dw4; 57 __dw dw5; 58 __dw dw6; 59 __dw dw7; 60 }; 61 #define PTD_OFFSET 0x0400 62 #define ISO_PTD_OFFSET 0x0400 63 #define INT_PTD_OFFSET 0x0800 64 #define ATL_PTD_OFFSET 0x0c00 65 #define PAYLOAD_OFFSET 0x1000 66 67 68 /* ATL */ 69 /* DW0 */ 70 #define DW0_VALID_BIT 1 71 #define FROM_DW0_VALID(x) ((x) & 0x01) 72 #define TO_DW0_LENGTH(x) (((u32) x) << 3) 73 #define TO_DW0_MAXPACKET(x) (((u32) x) << 18) 74 #define TO_DW0_MULTI(x) (((u32) x) << 29) 75 #define TO_DW0_ENDPOINT(x) (((u32) x) << 31) 76 /* DW1 */ 77 #define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3) 78 #define TO_DW1_PID_TOKEN(x) (((u32) x) << 10) 79 #define DW1_TRANS_BULK ((u32) 2 << 12) 80 #define DW1_TRANS_INT ((u32) 3 << 12) 81 #define DW1_TRANS_SPLIT ((u32) 1 << 14) 82 #define DW1_SE_USB_LOSPEED ((u32) 2 << 16) 83 #define TO_DW1_PORT_NUM(x) (((u32) x) << 18) 84 #define TO_DW1_HUB_NUM(x) (((u32) x) << 25) 85 /* DW2 */ 86 #define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8) 87 #define TO_DW2_RL(x) ((x) << 25) 88 #define FROM_DW2_RL(x) (((x) >> 25) & 0xf) 89 /* DW3 */ 90 #define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff) 91 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff) 92 #define TO_DW3_NAKCOUNT(x) ((x) << 19) 93 #define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf) 94 #define TO_DW3_CERR(x) ((x) << 23) 95 #define FROM_DW3_CERR(x) (((x) >> 23) & 0x3) 96 #define TO_DW3_DATA_TOGGLE(x) ((x) << 25) 97 #define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1) 98 #define TO_DW3_PING(x) ((x) << 26) 99 #define FROM_DW3_PING(x) (((x) >> 26) & 0x1) 100 #define DW3_ERROR_BIT (1 << 28) 101 #define DW3_BABBLE_BIT (1 << 29) 102 #define DW3_HALT_BIT (1 << 30) 103 #define DW3_ACTIVE_BIT (1 << 31) 104 #define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01) 105 106 #define INT_UNDERRUN (1 << 2) 107 #define INT_BABBLE (1 << 1) 108 #define INT_EXACT (1 << 0) 109 110 #define SETUP_PID (2) 111 #define IN_PID (1) 112 #define OUT_PID (0) 113 114 /* Errata 1 */ 115 #define RL_COUNTER (0) 116 #define NAK_COUNTER (0) 117 #define ERR_COUNTER (2) 118 119 struct isp1760_qtd { 120 u8 packet_type; 121 void *data_buffer; 122 u32 payload_addr; 123 124 /* the rest is HCD-private */ 125 struct list_head qtd_list; 126 struct urb *urb; 127 size_t length; 128 size_t actual_length; 129 130 /* QTD_ENQUEUED: waiting for transfer (inactive) */ 131 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ 132 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only 133 interrupt handler may touch this qtd! */ 134 /* QTD_XFER_COMPLETE: payload has been transferred successfully */ 135 /* QTD_RETIRE: transfer error/abort qtd */ 136 #define QTD_ENQUEUED 0 137 #define QTD_PAYLOAD_ALLOC 1 138 #define QTD_XFER_STARTED 2 139 #define QTD_XFER_COMPLETE 3 140 #define QTD_RETIRE 4 141 u32 status; 142 }; 143 144 /* Queue head, one for each active endpoint */ 145 struct isp1760_qh { 146 struct list_head qh_list; 147 struct list_head qtd_list; 148 u32 toggle; 149 u32 ping; 150 int slot; 151 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ 152 }; 153 154 struct urb_listitem { 155 struct list_head urb_list; 156 struct urb *urb; 157 }; 158 159 /* 160 * Access functions for isp176x registers (addresses 0..0x03FF). 161 */ 162 static u32 reg_read32(void __iomem *base, u32 reg) 163 { 164 return isp1760_read32(base, reg); 165 } 166 167 static void reg_write32(void __iomem *base, u32 reg, u32 val) 168 { 169 isp1760_write32(base, reg, val); 170 } 171 172 /* 173 * Access functions for isp176x memory (offset >= 0x0400). 174 * 175 * bank_reads8() reads memory locations prefetched by an earlier write to 176 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- 177 * bank optimizations, you should use the more generic mem_reads8() below. 178 * 179 * For access to ptd memory, use the specialized ptd_read() and ptd_write() 180 * below. 181 * 182 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() 183 * doesn't quite work because some people have to enforce 32-bit access 184 */ 185 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, 186 __u32 *dst, u32 bytes) 187 { 188 __u32 __iomem *src; 189 u32 val; 190 __u8 *src_byteptr; 191 __u8 *dst_byteptr; 192 193 src = src_base + (bank_addr | src_offset); 194 195 if (src_offset < PAYLOAD_OFFSET) { 196 while (bytes >= 4) { 197 *dst = le32_to_cpu(__raw_readl(src)); 198 bytes -= 4; 199 src++; 200 dst++; 201 } 202 } else { 203 while (bytes >= 4) { 204 *dst = __raw_readl(src); 205 bytes -= 4; 206 src++; 207 dst++; 208 } 209 } 210 211 if (!bytes) 212 return; 213 214 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully 215 * allocated. 216 */ 217 if (src_offset < PAYLOAD_OFFSET) 218 val = le32_to_cpu(__raw_readl(src)); 219 else 220 val = __raw_readl(src); 221 222 dst_byteptr = (void *) dst; 223 src_byteptr = (void *) &val; 224 while (bytes > 0) { 225 *dst_byteptr = *src_byteptr; 226 dst_byteptr++; 227 src_byteptr++; 228 bytes--; 229 } 230 } 231 232 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, 233 u32 bytes) 234 { 235 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); 236 ndelay(90); 237 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); 238 } 239 240 static void mem_writes8(void __iomem *dst_base, u32 dst_offset, 241 __u32 const *src, u32 bytes) 242 { 243 __u32 __iomem *dst; 244 245 dst = dst_base + dst_offset; 246 247 if (dst_offset < PAYLOAD_OFFSET) { 248 while (bytes >= 4) { 249 __raw_writel(cpu_to_le32(*src), dst); 250 bytes -= 4; 251 src++; 252 dst++; 253 } 254 } else { 255 while (bytes >= 4) { 256 __raw_writel(*src, dst); 257 bytes -= 4; 258 src++; 259 dst++; 260 } 261 } 262 263 if (!bytes) 264 return; 265 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the 266 * extra bytes should not be read by the HW. 267 */ 268 269 if (dst_offset < PAYLOAD_OFFSET) 270 __raw_writel(cpu_to_le32(*src), dst); 271 else 272 __raw_writel(*src, dst); 273 } 274 275 /* 276 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, 277 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. 278 */ 279 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, 280 struct ptd *ptd) 281 { 282 reg_write32(base, HC_MEMORY_REG, 283 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); 284 ndelay(90); 285 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), 286 (void *) ptd, sizeof(*ptd)); 287 } 288 289 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, 290 struct ptd *ptd) 291 { 292 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), 293 &ptd->dw1, 7*sizeof(ptd->dw1)); 294 /* Make sure dw0 gets written last (after other dw's and after payload) 295 since it contains the enable bit */ 296 wmb(); 297 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, 298 sizeof(ptd->dw0)); 299 } 300 301 302 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ 303 static void init_memory(struct isp1760_hcd *priv) 304 { 305 int i, curr; 306 u32 payload_addr; 307 308 payload_addr = PAYLOAD_OFFSET; 309 for (i = 0; i < BLOCK_1_NUM; i++) { 310 priv->memory_pool[i].start = payload_addr; 311 priv->memory_pool[i].size = BLOCK_1_SIZE; 312 priv->memory_pool[i].free = 1; 313 payload_addr += priv->memory_pool[i].size; 314 } 315 316 curr = i; 317 for (i = 0; i < BLOCK_2_NUM; i++) { 318 priv->memory_pool[curr + i].start = payload_addr; 319 priv->memory_pool[curr + i].size = BLOCK_2_SIZE; 320 priv->memory_pool[curr + i].free = 1; 321 payload_addr += priv->memory_pool[curr + i].size; 322 } 323 324 curr = i; 325 for (i = 0; i < BLOCK_3_NUM; i++) { 326 priv->memory_pool[curr + i].start = payload_addr; 327 priv->memory_pool[curr + i].size = BLOCK_3_SIZE; 328 priv->memory_pool[curr + i].free = 1; 329 payload_addr += priv->memory_pool[curr + i].size; 330 } 331 332 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); 333 } 334 335 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 336 { 337 struct isp1760_hcd *priv = hcd_to_priv(hcd); 338 int i; 339 340 WARN_ON(qtd->payload_addr); 341 342 if (!qtd->length) 343 return; 344 345 for (i = 0; i < BLOCKS; i++) { 346 if (priv->memory_pool[i].size >= qtd->length && 347 priv->memory_pool[i].free) { 348 priv->memory_pool[i].free = 0; 349 qtd->payload_addr = priv->memory_pool[i].start; 350 return; 351 } 352 } 353 } 354 355 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 356 { 357 struct isp1760_hcd *priv = hcd_to_priv(hcd); 358 int i; 359 360 if (!qtd->payload_addr) 361 return; 362 363 for (i = 0; i < BLOCKS; i++) { 364 if (priv->memory_pool[i].start == qtd->payload_addr) { 365 WARN_ON(priv->memory_pool[i].free); 366 priv->memory_pool[i].free = 1; 367 qtd->payload_addr = 0; 368 return; 369 } 370 } 371 372 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", 373 __func__, qtd->payload_addr); 374 WARN_ON(1); 375 qtd->payload_addr = 0; 376 } 377 378 static int handshake(struct usb_hcd *hcd, u32 reg, 379 u32 mask, u32 done, int usec) 380 { 381 u32 result; 382 383 do { 384 result = reg_read32(hcd->regs, reg); 385 if (result == ~0) 386 return -ENODEV; 387 result &= mask; 388 if (result == done) 389 return 0; 390 udelay(1); 391 usec--; 392 } while (usec > 0); 393 return -ETIMEDOUT; 394 } 395 396 /* reset a non-running (STS_HALT == 1) controller */ 397 static int ehci_reset(struct usb_hcd *hcd) 398 { 399 struct isp1760_hcd *priv = hcd_to_priv(hcd); 400 401 u32 command = reg_read32(hcd->regs, HC_USBCMD); 402 403 command |= CMD_RESET; 404 reg_write32(hcd->regs, HC_USBCMD, command); 405 hcd->state = HC_STATE_HALT; 406 priv->next_statechange = jiffies; 407 408 return handshake(hcd, HC_USBCMD, CMD_RESET, 0, 250 * 1000); 409 } 410 411 static struct isp1760_qh *qh_alloc(gfp_t flags) 412 { 413 struct isp1760_qh *qh; 414 415 qh = kmem_cache_zalloc(qh_cachep, flags); 416 if (!qh) 417 return NULL; 418 419 INIT_LIST_HEAD(&qh->qh_list); 420 INIT_LIST_HEAD(&qh->qtd_list); 421 qh->slot = -1; 422 423 return qh; 424 } 425 426 static void qh_free(struct isp1760_qh *qh) 427 { 428 WARN_ON(!list_empty(&qh->qtd_list)); 429 WARN_ON(qh->slot > -1); 430 kmem_cache_free(qh_cachep, qh); 431 } 432 433 /* one-time init, only for memory state */ 434 static int priv_init(struct usb_hcd *hcd) 435 { 436 struct isp1760_hcd *priv = hcd_to_priv(hcd); 437 u32 hcc_params; 438 int i; 439 440 spin_lock_init(&priv->lock); 441 442 for (i = 0; i < QH_END; i++) 443 INIT_LIST_HEAD(&priv->qh_list[i]); 444 445 /* 446 * hw default: 1K periodic list heads, one per frame. 447 * periodic_size can shrink by USBCMD update if hcc_params allows. 448 */ 449 priv->periodic_size = DEFAULT_I_TDPS; 450 451 /* controllers may cache some of the periodic schedule ... */ 452 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); 453 /* full frame cache */ 454 if (HCC_ISOC_CACHE(hcc_params)) 455 priv->i_thresh = 8; 456 else /* N microframes cached */ 457 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 458 459 return 0; 460 } 461 462 static int isp1760_hc_setup(struct usb_hcd *hcd) 463 { 464 struct isp1760_hcd *priv = hcd_to_priv(hcd); 465 int result; 466 u32 scratch, hwmode; 467 468 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); 469 /* Change bus pattern */ 470 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); 471 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); 472 if (scratch != 0xdeadbabe) { 473 dev_err(hcd->self.controller, "Scratch test failed.\n"); 474 return -ENODEV; 475 } 476 477 /* 478 * The RESET_HC bit in the SW_RESET register is supposed to reset the 479 * host controller without touching the CPU interface registers, but at 480 * least on the ISP1761 it seems to behave as the RESET_ALL bit and 481 * reset the whole device. We thus can't use it here, so let's reset 482 * the host controller through the EHCI USB Command register. The device 483 * has been reset in core code anyway, so this shouldn't matter. 484 */ 485 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); 486 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 487 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 488 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 489 490 result = ehci_reset(hcd); 491 if (result) 492 return result; 493 494 /* Step 11 passed */ 495 496 /* ATL reset */ 497 hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET; 498 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); 499 mdelay(10); 500 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); 501 502 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); 503 504 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); 505 506 return priv_init(hcd); 507 } 508 509 static u32 base_to_chip(u32 base) 510 { 511 return ((base - 0x400) >> 3); 512 } 513 514 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) 515 { 516 struct urb *urb; 517 518 if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) 519 return 1; 520 521 urb = qtd->urb; 522 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); 523 return (qtd->urb != urb); 524 } 525 526 /* magic numbers that can affect system performance */ 527 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 528 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 529 #define EHCI_TUNE_RL_TT 0 530 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 531 #define EHCI_TUNE_MULT_TT 1 532 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 533 534 static void create_ptd_atl(struct isp1760_qh *qh, 535 struct isp1760_qtd *qtd, struct ptd *ptd) 536 { 537 u32 maxpacket; 538 u32 multi; 539 u32 rl = RL_COUNTER; 540 u32 nak = NAK_COUNTER; 541 542 memset(ptd, 0, sizeof(*ptd)); 543 544 /* according to 3.6.2, max packet len can not be > 0x400 */ 545 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, 546 usb_pipeout(qtd->urb->pipe)); 547 multi = 1 + ((maxpacket >> 11) & 0x3); 548 maxpacket &= 0x7ff; 549 550 /* DW0 */ 551 ptd->dw0 = DW0_VALID_BIT; 552 ptd->dw0 |= TO_DW0_LENGTH(qtd->length); 553 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); 554 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); 555 556 /* DW1 */ 557 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; 558 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); 559 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); 560 561 if (usb_pipebulk(qtd->urb->pipe)) 562 ptd->dw1 |= DW1_TRANS_BULK; 563 else if (usb_pipeint(qtd->urb->pipe)) 564 ptd->dw1 |= DW1_TRANS_INT; 565 566 if (qtd->urb->dev->speed != USB_SPEED_HIGH) { 567 /* split transaction */ 568 569 ptd->dw1 |= DW1_TRANS_SPLIT; 570 if (qtd->urb->dev->speed == USB_SPEED_LOW) 571 ptd->dw1 |= DW1_SE_USB_LOSPEED; 572 573 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); 574 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); 575 576 /* SE bit for Split INT transfers */ 577 if (usb_pipeint(qtd->urb->pipe) && 578 (qtd->urb->dev->speed == USB_SPEED_LOW)) 579 ptd->dw1 |= 2 << 16; 580 581 rl = 0; 582 nak = 0; 583 } else { 584 ptd->dw0 |= TO_DW0_MULTI(multi); 585 if (usb_pipecontrol(qtd->urb->pipe) || 586 usb_pipebulk(qtd->urb->pipe)) 587 ptd->dw3 |= TO_DW3_PING(qh->ping); 588 } 589 /* DW2 */ 590 ptd->dw2 = 0; 591 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); 592 ptd->dw2 |= TO_DW2_RL(rl); 593 594 /* DW3 */ 595 ptd->dw3 |= TO_DW3_NAKCOUNT(nak); 596 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); 597 if (usb_pipecontrol(qtd->urb->pipe)) { 598 if (qtd->data_buffer == qtd->urb->setup_packet) 599 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); 600 else if (last_qtd_of_urb(qtd, qh)) 601 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); 602 } 603 604 ptd->dw3 |= DW3_ACTIVE_BIT; 605 /* Cerr */ 606 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); 607 } 608 609 static void transform_add_int(struct isp1760_qh *qh, 610 struct isp1760_qtd *qtd, struct ptd *ptd) 611 { 612 u32 usof; 613 u32 period; 614 615 /* 616 * Most of this is guessing. ISP1761 datasheet is quite unclear, and 617 * the algorithm from the original Philips driver code, which was 618 * pretty much used in this driver before as well, is quite horrendous 619 * and, i believe, incorrect. The code below follows the datasheet and 620 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much 621 * more reliable this way (fingers crossed...). 622 */ 623 624 if (qtd->urb->dev->speed == USB_SPEED_HIGH) { 625 /* urb->interval is in units of microframes (1/8 ms) */ 626 period = qtd->urb->interval >> 3; 627 628 if (qtd->urb->interval > 4) 629 usof = 0x01; /* One bit set => 630 interval 1 ms * uFrame-match */ 631 else if (qtd->urb->interval > 2) 632 usof = 0x22; /* Two bits set => interval 1/2 ms */ 633 else if (qtd->urb->interval > 1) 634 usof = 0x55; /* Four bits set => interval 1/4 ms */ 635 else 636 usof = 0xff; /* All bits set => interval 1/8 ms */ 637 } else { 638 /* urb->interval is in units of frames (1 ms) */ 639 period = qtd->urb->interval; 640 usof = 0x0f; /* Execute Start Split on any of the 641 four first uFrames */ 642 643 /* 644 * First 8 bits in dw5 is uSCS and "specifies which uSOF the 645 * complete split needs to be sent. Valid only for IN." Also, 646 * "All bits can be set to one for every transfer." (p 82, 647 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did 648 * that number come from? 0xff seems to work fine... 649 */ 650 /* ptd->dw5 = 0x1c; */ 651 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ 652 } 653 654 period = period >> 1;/* Ensure equal or shorter period than requested */ 655 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ 656 657 ptd->dw2 |= period; 658 ptd->dw4 = usof; 659 } 660 661 static void create_ptd_int(struct isp1760_qh *qh, 662 struct isp1760_qtd *qtd, struct ptd *ptd) 663 { 664 create_ptd_atl(qh, qtd, ptd); 665 transform_add_int(qh, qtd, ptd); 666 } 667 668 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) 669 __releases(priv->lock) 670 __acquires(priv->lock) 671 { 672 struct isp1760_hcd *priv = hcd_to_priv(hcd); 673 674 if (!urb->unlinked) { 675 if (urb->status == -EINPROGRESS) 676 urb->status = 0; 677 } 678 679 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { 680 void *ptr; 681 for (ptr = urb->transfer_buffer; 682 ptr < urb->transfer_buffer + urb->transfer_buffer_length; 683 ptr += PAGE_SIZE) 684 flush_dcache_page(virt_to_page(ptr)); 685 } 686 687 /* complete() can reenter this HCD */ 688 usb_hcd_unlink_urb_from_ep(hcd, urb); 689 spin_unlock(&priv->lock); 690 usb_hcd_giveback_urb(hcd, urb, urb->status); 691 spin_lock(&priv->lock); 692 } 693 694 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, 695 u8 packet_type) 696 { 697 struct isp1760_qtd *qtd; 698 699 qtd = kmem_cache_zalloc(qtd_cachep, flags); 700 if (!qtd) 701 return NULL; 702 703 INIT_LIST_HEAD(&qtd->qtd_list); 704 qtd->urb = urb; 705 qtd->packet_type = packet_type; 706 qtd->status = QTD_ENQUEUED; 707 qtd->actual_length = 0; 708 709 return qtd; 710 } 711 712 static void qtd_free(struct isp1760_qtd *qtd) 713 { 714 WARN_ON(qtd->payload_addr); 715 kmem_cache_free(qtd_cachep, qtd); 716 } 717 718 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, 719 struct isp1760_slotinfo *slots, 720 struct isp1760_qtd *qtd, struct isp1760_qh *qh, 721 struct ptd *ptd) 722 { 723 struct isp1760_hcd *priv = hcd_to_priv(hcd); 724 int skip_map; 725 726 WARN_ON((slot < 0) || (slot > 31)); 727 WARN_ON(qtd->length && !qtd->payload_addr); 728 WARN_ON(slots[slot].qtd); 729 WARN_ON(slots[slot].qh); 730 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); 731 732 /* Make sure done map has not triggered from some unlinked transfer */ 733 if (ptd_offset == ATL_PTD_OFFSET) { 734 priv->atl_done_map |= reg_read32(hcd->regs, 735 HC_ATL_PTD_DONEMAP_REG); 736 priv->atl_done_map &= ~(1 << slot); 737 } else { 738 priv->int_done_map |= reg_read32(hcd->regs, 739 HC_INT_PTD_DONEMAP_REG); 740 priv->int_done_map &= ~(1 << slot); 741 } 742 743 qh->slot = slot; 744 qtd->status = QTD_XFER_STARTED; 745 slots[slot].timestamp = jiffies; 746 slots[slot].qtd = qtd; 747 slots[slot].qh = qh; 748 ptd_write(hcd->regs, ptd_offset, slot, ptd); 749 750 if (ptd_offset == ATL_PTD_OFFSET) { 751 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 752 skip_map &= ~(1 << qh->slot); 753 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); 754 } else { 755 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 756 skip_map &= ~(1 << qh->slot); 757 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); 758 } 759 } 760 761 static int is_short_bulk(struct isp1760_qtd *qtd) 762 { 763 return (usb_pipebulk(qtd->urb->pipe) && 764 (qtd->actual_length < qtd->length)); 765 } 766 767 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, 768 struct list_head *urb_list) 769 { 770 int last_qtd; 771 struct isp1760_qtd *qtd, *qtd_next; 772 struct urb_listitem *urb_listitem; 773 774 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { 775 if (qtd->status < QTD_XFER_COMPLETE) 776 break; 777 778 last_qtd = last_qtd_of_urb(qtd, qh); 779 780 if ((!last_qtd) && (qtd->status == QTD_RETIRE)) 781 qtd_next->status = QTD_RETIRE; 782 783 if (qtd->status == QTD_XFER_COMPLETE) { 784 if (qtd->actual_length) { 785 switch (qtd->packet_type) { 786 case IN_PID: 787 mem_reads8(hcd->regs, qtd->payload_addr, 788 qtd->data_buffer, 789 qtd->actual_length); 790 /* Fall through (?) */ 791 case OUT_PID: 792 qtd->urb->actual_length += 793 qtd->actual_length; 794 /* Fall through ... */ 795 case SETUP_PID: 796 break; 797 } 798 } 799 800 if (is_short_bulk(qtd)) { 801 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) 802 qtd->urb->status = -EREMOTEIO; 803 if (!last_qtd) 804 qtd_next->status = QTD_RETIRE; 805 } 806 } 807 808 if (qtd->payload_addr) 809 free_mem(hcd, qtd); 810 811 if (last_qtd) { 812 if ((qtd->status == QTD_RETIRE) && 813 (qtd->urb->status == -EINPROGRESS)) 814 qtd->urb->status = -EPIPE; 815 /* Defer calling of urb_done() since it releases lock */ 816 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, 817 GFP_ATOMIC); 818 if (unlikely(!urb_listitem)) 819 break; /* Try again on next call */ 820 urb_listitem->urb = qtd->urb; 821 list_add_tail(&urb_listitem->urb_list, urb_list); 822 } 823 824 list_del(&qtd->qtd_list); 825 qtd_free(qtd); 826 } 827 } 828 829 #define ENQUEUE_DEPTH 2 830 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) 831 { 832 struct isp1760_hcd *priv = hcd_to_priv(hcd); 833 int ptd_offset; 834 struct isp1760_slotinfo *slots; 835 int curr_slot, free_slot; 836 int n; 837 struct ptd ptd; 838 struct isp1760_qtd *qtd; 839 840 if (unlikely(list_empty(&qh->qtd_list))) { 841 WARN_ON(1); 842 return; 843 } 844 845 /* Make sure this endpoint's TT buffer is clean before queueing ptds */ 846 if (qh->tt_buffer_dirty) 847 return; 848 849 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, 850 qtd_list)->urb->pipe)) { 851 ptd_offset = INT_PTD_OFFSET; 852 slots = priv->int_slots; 853 } else { 854 ptd_offset = ATL_PTD_OFFSET; 855 slots = priv->atl_slots; 856 } 857 858 free_slot = -1; 859 for (curr_slot = 0; curr_slot < 32; curr_slot++) { 860 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) 861 free_slot = curr_slot; 862 if (slots[curr_slot].qh == qh) 863 break; 864 } 865 866 n = 0; 867 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { 868 if (qtd->status == QTD_ENQUEUED) { 869 WARN_ON(qtd->payload_addr); 870 alloc_mem(hcd, qtd); 871 if ((qtd->length) && (!qtd->payload_addr)) 872 break; 873 874 if ((qtd->length) && 875 ((qtd->packet_type == SETUP_PID) || 876 (qtd->packet_type == OUT_PID))) { 877 mem_writes8(hcd->regs, qtd->payload_addr, 878 qtd->data_buffer, qtd->length); 879 } 880 881 qtd->status = QTD_PAYLOAD_ALLOC; 882 } 883 884 if (qtd->status == QTD_PAYLOAD_ALLOC) { 885 /* 886 if ((curr_slot > 31) && (free_slot == -1)) 887 dev_dbg(hcd->self.controller, "%s: No slot " 888 "available for transfer\n", __func__); 889 */ 890 /* Start xfer for this endpoint if not already done */ 891 if ((curr_slot > 31) && (free_slot > -1)) { 892 if (usb_pipeint(qtd->urb->pipe)) 893 create_ptd_int(qh, qtd, &ptd); 894 else 895 create_ptd_atl(qh, qtd, &ptd); 896 897 start_bus_transfer(hcd, ptd_offset, free_slot, 898 slots, qtd, qh, &ptd); 899 curr_slot = free_slot; 900 } 901 902 n++; 903 if (n >= ENQUEUE_DEPTH) 904 break; 905 } 906 } 907 } 908 909 static void schedule_ptds(struct usb_hcd *hcd) 910 { 911 struct isp1760_hcd *priv; 912 struct isp1760_qh *qh, *qh_next; 913 struct list_head *ep_queue; 914 LIST_HEAD(urb_list); 915 struct urb_listitem *urb_listitem, *urb_listitem_next; 916 int i; 917 918 if (!hcd) { 919 WARN_ON(1); 920 return; 921 } 922 923 priv = hcd_to_priv(hcd); 924 925 /* 926 * check finished/retired xfers, transfer payloads, call urb_done() 927 */ 928 for (i = 0; i < QH_END; i++) { 929 ep_queue = &priv->qh_list[i]; 930 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { 931 collect_qtds(hcd, qh, &urb_list); 932 if (list_empty(&qh->qtd_list)) 933 list_del(&qh->qh_list); 934 } 935 } 936 937 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, 938 urb_list) { 939 isp1760_urb_done(hcd, urb_listitem->urb); 940 kmem_cache_free(urb_listitem_cachep, urb_listitem); 941 } 942 943 /* 944 * Schedule packets for transfer. 945 * 946 * According to USB2.0 specification: 947 * 948 * 1st prio: interrupt xfers, up to 80 % of bandwidth 949 * 2nd prio: control xfers 950 * 3rd prio: bulk xfers 951 * 952 * ... but let's use a simpler scheme here (mostly because ISP1761 doc 953 * is very unclear on how to prioritize traffic): 954 * 955 * 1) Enqueue any queued control transfers, as long as payload chip mem 956 * and PTD ATL slots are available. 957 * 2) Enqueue any queued INT transfers, as long as payload chip mem 958 * and PTD INT slots are available. 959 * 3) Enqueue any queued bulk transfers, as long as payload chip mem 960 * and PTD ATL slots are available. 961 * 962 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between 963 * conservation of chip mem and performance. 964 * 965 * I'm sure this scheme could be improved upon! 966 */ 967 for (i = 0; i < QH_END; i++) { 968 ep_queue = &priv->qh_list[i]; 969 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) 970 enqueue_qtds(hcd, qh); 971 } 972 } 973 974 #define PTD_STATE_QTD_DONE 1 975 #define PTD_STATE_QTD_RELOAD 2 976 #define PTD_STATE_URB_RETIRE 3 977 978 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, 979 struct urb *urb) 980 { 981 __dw dw4; 982 int i; 983 984 dw4 = ptd->dw4; 985 dw4 >>= 8; 986 987 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we 988 need to handle these errors? Is it done in hardware? */ 989 990 if (ptd->dw3 & DW3_HALT_BIT) { 991 992 urb->status = -EPROTO; /* Default unknown error */ 993 994 for (i = 0; i < 8; i++) { 995 switch (dw4 & 0x7) { 996 case INT_UNDERRUN: 997 dev_dbg(hcd->self.controller, "%s: underrun " 998 "during uFrame %d\n", 999 __func__, i); 1000 urb->status = -ECOMM; /* Could not write data */ 1001 break; 1002 case INT_EXACT: 1003 dev_dbg(hcd->self.controller, "%s: transaction " 1004 "error during uFrame %d\n", 1005 __func__, i); 1006 urb->status = -EPROTO; /* timeout, bad CRC, PID 1007 error etc. */ 1008 break; 1009 case INT_BABBLE: 1010 dev_dbg(hcd->self.controller, "%s: babble " 1011 "error during uFrame %d\n", 1012 __func__, i); 1013 urb->status = -EOVERFLOW; 1014 break; 1015 } 1016 dw4 >>= 3; 1017 } 1018 1019 return PTD_STATE_URB_RETIRE; 1020 } 1021 1022 return PTD_STATE_QTD_DONE; 1023 } 1024 1025 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1026 struct urb *urb) 1027 { 1028 WARN_ON(!ptd); 1029 if (ptd->dw3 & DW3_HALT_BIT) { 1030 if (ptd->dw3 & DW3_BABBLE_BIT) 1031 urb->status = -EOVERFLOW; 1032 else if (FROM_DW3_CERR(ptd->dw3)) 1033 urb->status = -EPIPE; /* Stall */ 1034 else if (ptd->dw3 & DW3_ERROR_BIT) 1035 urb->status = -EPROTO; /* XactErr */ 1036 else 1037 urb->status = -EPROTO; /* Unknown */ 1038 /* 1039 dev_dbg(hcd->self.controller, "%s: ptd error:\n" 1040 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" 1041 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", 1042 __func__, 1043 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, 1044 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); 1045 */ 1046 return PTD_STATE_URB_RETIRE; 1047 } 1048 1049 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1050 /* Transfer Error, *but* active and no HALT -> reload */ 1051 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); 1052 return PTD_STATE_QTD_RELOAD; 1053 } 1054 1055 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1056 /* 1057 * NAKs are handled in HW by the chip. Usually if the 1058 * device is not able to send data fast enough. 1059 * This happens mostly on slower hardware. 1060 */ 1061 return PTD_STATE_QTD_RELOAD; 1062 } 1063 1064 return PTD_STATE_QTD_DONE; 1065 } 1066 1067 static void handle_done_ptds(struct usb_hcd *hcd) 1068 { 1069 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1070 struct ptd ptd; 1071 struct isp1760_qh *qh; 1072 int slot; 1073 int state; 1074 struct isp1760_slotinfo *slots; 1075 u32 ptd_offset; 1076 struct isp1760_qtd *qtd; 1077 int modified; 1078 int skip_map; 1079 1080 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 1081 priv->int_done_map &= ~skip_map; 1082 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 1083 priv->atl_done_map &= ~skip_map; 1084 1085 modified = priv->int_done_map || priv->atl_done_map; 1086 1087 while (priv->int_done_map || priv->atl_done_map) { 1088 if (priv->int_done_map) { 1089 /* INT ptd */ 1090 slot = __ffs(priv->int_done_map); 1091 priv->int_done_map &= ~(1 << slot); 1092 slots = priv->int_slots; 1093 /* This should not trigger, and could be removed if 1094 noone have any problems with it triggering: */ 1095 if (!slots[slot].qh) { 1096 WARN_ON(1); 1097 continue; 1098 } 1099 ptd_offset = INT_PTD_OFFSET; 1100 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); 1101 state = check_int_transfer(hcd, &ptd, 1102 slots[slot].qtd->urb); 1103 } else { 1104 /* ATL ptd */ 1105 slot = __ffs(priv->atl_done_map); 1106 priv->atl_done_map &= ~(1 << slot); 1107 slots = priv->atl_slots; 1108 /* This should not trigger, and could be removed if 1109 noone have any problems with it triggering: */ 1110 if (!slots[slot].qh) { 1111 WARN_ON(1); 1112 continue; 1113 } 1114 ptd_offset = ATL_PTD_OFFSET; 1115 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); 1116 state = check_atl_transfer(hcd, &ptd, 1117 slots[slot].qtd->urb); 1118 } 1119 1120 qtd = slots[slot].qtd; 1121 slots[slot].qtd = NULL; 1122 qh = slots[slot].qh; 1123 slots[slot].qh = NULL; 1124 qh->slot = -1; 1125 1126 WARN_ON(qtd->status != QTD_XFER_STARTED); 1127 1128 switch (state) { 1129 case PTD_STATE_QTD_DONE: 1130 if ((usb_pipeint(qtd->urb->pipe)) && 1131 (qtd->urb->dev->speed != USB_SPEED_HIGH)) 1132 qtd->actual_length = 1133 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); 1134 else 1135 qtd->actual_length = 1136 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); 1137 1138 qtd->status = QTD_XFER_COMPLETE; 1139 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || 1140 is_short_bulk(qtd)) 1141 qtd = NULL; 1142 else 1143 qtd = list_entry(qtd->qtd_list.next, 1144 typeof(*qtd), qtd_list); 1145 1146 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1147 qh->ping = FROM_DW3_PING(ptd.dw3); 1148 break; 1149 1150 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ 1151 qtd->status = QTD_PAYLOAD_ALLOC; 1152 ptd.dw0 |= DW0_VALID_BIT; 1153 /* RL counter = ERR counter */ 1154 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); 1155 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); 1156 ptd.dw3 &= ~TO_DW3_CERR(3); 1157 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); 1158 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1159 qh->ping = FROM_DW3_PING(ptd.dw3); 1160 break; 1161 1162 case PTD_STATE_URB_RETIRE: 1163 qtd->status = QTD_RETIRE; 1164 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) && 1165 (qtd->urb->status != -EPIPE) && 1166 (qtd->urb->status != -EREMOTEIO)) { 1167 qh->tt_buffer_dirty = 1; 1168 if (usb_hub_clear_tt_buffer(qtd->urb)) 1169 /* Clear failed; let's hope things work 1170 anyway */ 1171 qh->tt_buffer_dirty = 0; 1172 } 1173 qtd = NULL; 1174 qh->toggle = 0; 1175 qh->ping = 0; 1176 break; 1177 1178 default: 1179 WARN_ON(1); 1180 continue; 1181 } 1182 1183 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { 1184 if (slots == priv->int_slots) { 1185 if (state == PTD_STATE_QTD_RELOAD) 1186 dev_err(hcd->self.controller, 1187 "%s: PTD_STATE_QTD_RELOAD on " 1188 "interrupt packet\n", __func__); 1189 if (state != PTD_STATE_QTD_RELOAD) 1190 create_ptd_int(qh, qtd, &ptd); 1191 } else { 1192 if (state != PTD_STATE_QTD_RELOAD) 1193 create_ptd_atl(qh, qtd, &ptd); 1194 } 1195 1196 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, 1197 qh, &ptd); 1198 } 1199 } 1200 1201 if (modified) 1202 schedule_ptds(hcd); 1203 } 1204 1205 static irqreturn_t isp1760_irq(struct usb_hcd *hcd) 1206 { 1207 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1208 u32 imask; 1209 irqreturn_t irqret = IRQ_NONE; 1210 1211 spin_lock(&priv->lock); 1212 1213 if (!(hcd->state & HC_STATE_RUNNING)) 1214 goto leave; 1215 1216 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); 1217 if (unlikely(!imask)) 1218 goto leave; 1219 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ 1220 1221 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); 1222 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); 1223 1224 handle_done_ptds(hcd); 1225 1226 irqret = IRQ_HANDLED; 1227 leave: 1228 spin_unlock(&priv->lock); 1229 1230 return irqret; 1231 } 1232 1233 /* 1234 * Workaround for problem described in chip errata 2: 1235 * 1236 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. 1237 * One solution suggested in the errata is to use SOF interrupts _instead_of_ 1238 * ATL done interrupts (the "instead of" might be important since it seems 1239 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" 1240 * to set the PTD's done bit in addition to not generating an interrupt!). 1241 * 1242 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their 1243 * done bit is not being set. This is bad - it blocks the endpoint until reboot. 1244 * 1245 * If we use SOF interrupts only, we get latency between ptd completion and the 1246 * actual handling. This is very noticeable in testusb runs which takes several 1247 * minutes longer without ATL interrupts. 1248 * 1249 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it 1250 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the 1251 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered 1252 * completed and its done map bit is set. 1253 * 1254 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen 1255 * not to cause too much lag when this HW bug occurs, while still hopefully 1256 * ensuring that the check does not falsely trigger. 1257 */ 1258 #define SLOT_TIMEOUT 300 1259 #define SLOT_CHECK_PERIOD 200 1260 static struct timer_list errata2_timer; 1261 1262 static void errata2_function(unsigned long data) 1263 { 1264 struct usb_hcd *hcd = (struct usb_hcd *) data; 1265 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1266 int slot; 1267 struct ptd ptd; 1268 unsigned long spinflags; 1269 1270 spin_lock_irqsave(&priv->lock, spinflags); 1271 1272 for (slot = 0; slot < 32; slot++) 1273 if (priv->atl_slots[slot].qh && time_after(jiffies, 1274 priv->atl_slots[slot].timestamp + 1275 msecs_to_jiffies(SLOT_TIMEOUT))) { 1276 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); 1277 if (!FROM_DW0_VALID(ptd.dw0) && 1278 !FROM_DW3_ACTIVE(ptd.dw3)) 1279 priv->atl_done_map |= 1 << slot; 1280 } 1281 1282 if (priv->atl_done_map) 1283 handle_done_ptds(hcd); 1284 1285 spin_unlock_irqrestore(&priv->lock, spinflags); 1286 1287 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); 1288 add_timer(&errata2_timer); 1289 } 1290 1291 static int isp1760_run(struct usb_hcd *hcd) 1292 { 1293 int retval; 1294 u32 temp; 1295 u32 command; 1296 u32 chipid; 1297 1298 hcd->uses_new_polling = 1; 1299 1300 hcd->state = HC_STATE_RUNNING; 1301 1302 /* Set PTD interrupt AND & OR maps */ 1303 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); 1304 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); 1305 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); 1306 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); 1307 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); 1308 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); 1309 /* step 23 passed */ 1310 1311 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 1312 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); 1313 1314 command = reg_read32(hcd->regs, HC_USBCMD); 1315 command &= ~(CMD_LRESET|CMD_RESET); 1316 command |= CMD_RUN; 1317 reg_write32(hcd->regs, HC_USBCMD, command); 1318 1319 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); 1320 if (retval) 1321 return retval; 1322 1323 /* 1324 * XXX 1325 * Spec says to write FLAG_CF as last config action, priv code grabs 1326 * the semaphore while doing so. 1327 */ 1328 down_write(&ehci_cf_port_reset_rwsem); 1329 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); 1330 1331 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); 1332 up_write(&ehci_cf_port_reset_rwsem); 1333 if (retval) 1334 return retval; 1335 1336 setup_timer(&errata2_timer, errata2_function, (unsigned long)hcd); 1337 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); 1338 add_timer(&errata2_timer); 1339 1340 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); 1341 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", 1342 chipid & 0xffff, chipid >> 16); 1343 1344 /* PTD Register Init Part 2, Step 28 */ 1345 1346 /* Setup registers controlling PTD checking */ 1347 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); 1348 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); 1349 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); 1350 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); 1351 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); 1352 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); 1353 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 1354 ATL_BUF_FILL | INT_BUF_FILL); 1355 1356 /* GRR this is run-once init(), being done every time the HC starts. 1357 * So long as they're part of class devices, we can't do it init() 1358 * since the class device isn't created that early. 1359 */ 1360 return 0; 1361 } 1362 1363 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) 1364 { 1365 qtd->data_buffer = databuffer; 1366 1367 if (len > MAX_PAYLOAD_SIZE) 1368 len = MAX_PAYLOAD_SIZE; 1369 qtd->length = len; 1370 1371 return qtd->length; 1372 } 1373 1374 static void qtd_list_free(struct list_head *qtd_list) 1375 { 1376 struct isp1760_qtd *qtd, *qtd_next; 1377 1378 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { 1379 list_del(&qtd->qtd_list); 1380 qtd_free(qtd); 1381 } 1382 } 1383 1384 /* 1385 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. 1386 * Also calculate the PID type (SETUP/IN/OUT) for each packet. 1387 */ 1388 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1389 static void packetize_urb(struct usb_hcd *hcd, 1390 struct urb *urb, struct list_head *head, gfp_t flags) 1391 { 1392 struct isp1760_qtd *qtd; 1393 void *buf; 1394 int len, maxpacketsize; 1395 u8 packet_type; 1396 1397 /* 1398 * URBs map to sequences of QTDs: one logical transaction 1399 */ 1400 1401 if (!urb->transfer_buffer && urb->transfer_buffer_length) { 1402 /* XXX This looks like usb storage / SCSI bug */ 1403 dev_err(hcd->self.controller, 1404 "buf is null, dma is %08lx len is %d\n", 1405 (long unsigned)urb->transfer_dma, 1406 urb->transfer_buffer_length); 1407 WARN_ON(1); 1408 } 1409 1410 if (usb_pipein(urb->pipe)) 1411 packet_type = IN_PID; 1412 else 1413 packet_type = OUT_PID; 1414 1415 if (usb_pipecontrol(urb->pipe)) { 1416 qtd = qtd_alloc(flags, urb, SETUP_PID); 1417 if (!qtd) 1418 goto cleanup; 1419 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); 1420 list_add_tail(&qtd->qtd_list, head); 1421 1422 /* for zero length DATA stages, STATUS is always IN */ 1423 if (urb->transfer_buffer_length == 0) 1424 packet_type = IN_PID; 1425 } 1426 1427 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, 1428 usb_pipeout(urb->pipe))); 1429 1430 /* 1431 * buffer gets wrapped in one or more qtds; 1432 * last one may be "short" (including zero len) 1433 * and may serve as a control status ack 1434 */ 1435 buf = urb->transfer_buffer; 1436 len = urb->transfer_buffer_length; 1437 1438 for (;;) { 1439 int this_qtd_len; 1440 1441 qtd = qtd_alloc(flags, urb, packet_type); 1442 if (!qtd) 1443 goto cleanup; 1444 this_qtd_len = qtd_fill(qtd, buf, len); 1445 list_add_tail(&qtd->qtd_list, head); 1446 1447 len -= this_qtd_len; 1448 buf += this_qtd_len; 1449 1450 if (len <= 0) 1451 break; 1452 } 1453 1454 /* 1455 * control requests may need a terminating data "status" ack; 1456 * bulk ones may need a terminating short packet (zero length). 1457 */ 1458 if (urb->transfer_buffer_length != 0) { 1459 int one_more = 0; 1460 1461 if (usb_pipecontrol(urb->pipe)) { 1462 one_more = 1; 1463 if (packet_type == IN_PID) 1464 packet_type = OUT_PID; 1465 else 1466 packet_type = IN_PID; 1467 } else if (usb_pipebulk(urb->pipe) 1468 && (urb->transfer_flags & URB_ZERO_PACKET) 1469 && !(urb->transfer_buffer_length % 1470 maxpacketsize)) { 1471 one_more = 1; 1472 } 1473 if (one_more) { 1474 qtd = qtd_alloc(flags, urb, packet_type); 1475 if (!qtd) 1476 goto cleanup; 1477 1478 /* never any data in such packets */ 1479 qtd_fill(qtd, NULL, 0); 1480 list_add_tail(&qtd->qtd_list, head); 1481 } 1482 } 1483 1484 return; 1485 1486 cleanup: 1487 qtd_list_free(head); 1488 } 1489 1490 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 1491 gfp_t mem_flags) 1492 { 1493 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1494 struct list_head *ep_queue; 1495 struct isp1760_qh *qh, *qhit; 1496 unsigned long spinflags; 1497 LIST_HEAD(new_qtds); 1498 int retval; 1499 int qh_in_queue; 1500 1501 switch (usb_pipetype(urb->pipe)) { 1502 case PIPE_CONTROL: 1503 ep_queue = &priv->qh_list[QH_CONTROL]; 1504 break; 1505 case PIPE_BULK: 1506 ep_queue = &priv->qh_list[QH_BULK]; 1507 break; 1508 case PIPE_INTERRUPT: 1509 if (urb->interval < 0) 1510 return -EINVAL; 1511 /* FIXME: Check bandwidth */ 1512 ep_queue = &priv->qh_list[QH_INTERRUPT]; 1513 break; 1514 case PIPE_ISOCHRONOUS: 1515 dev_err(hcd->self.controller, "%s: isochronous USB packets " 1516 "not yet supported\n", 1517 __func__); 1518 return -EPIPE; 1519 default: 1520 dev_err(hcd->self.controller, "%s: unknown pipe type\n", 1521 __func__); 1522 return -EPIPE; 1523 } 1524 1525 if (usb_pipein(urb->pipe)) 1526 urb->actual_length = 0; 1527 1528 packetize_urb(hcd, urb, &new_qtds, mem_flags); 1529 if (list_empty(&new_qtds)) 1530 return -ENOMEM; 1531 1532 retval = 0; 1533 spin_lock_irqsave(&priv->lock, spinflags); 1534 1535 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 1536 retval = -ESHUTDOWN; 1537 qtd_list_free(&new_qtds); 1538 goto out; 1539 } 1540 retval = usb_hcd_link_urb_to_ep(hcd, urb); 1541 if (retval) { 1542 qtd_list_free(&new_qtds); 1543 goto out; 1544 } 1545 1546 qh = urb->ep->hcpriv; 1547 if (qh) { 1548 qh_in_queue = 0; 1549 list_for_each_entry(qhit, ep_queue, qh_list) { 1550 if (qhit == qh) { 1551 qh_in_queue = 1; 1552 break; 1553 } 1554 } 1555 if (!qh_in_queue) 1556 list_add_tail(&qh->qh_list, ep_queue); 1557 } else { 1558 qh = qh_alloc(GFP_ATOMIC); 1559 if (!qh) { 1560 retval = -ENOMEM; 1561 usb_hcd_unlink_urb_from_ep(hcd, urb); 1562 qtd_list_free(&new_qtds); 1563 goto out; 1564 } 1565 list_add_tail(&qh->qh_list, ep_queue); 1566 urb->ep->hcpriv = qh; 1567 } 1568 1569 list_splice_tail(&new_qtds, &qh->qtd_list); 1570 schedule_ptds(hcd); 1571 1572 out: 1573 spin_unlock_irqrestore(&priv->lock, spinflags); 1574 return retval; 1575 } 1576 1577 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, 1578 struct isp1760_qh *qh) 1579 { 1580 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1581 int skip_map; 1582 1583 WARN_ON(qh->slot == -1); 1584 1585 /* We need to forcefully reclaim the slot since some transfers never 1586 return, e.g. interrupt transfers and NAKed bulk transfers. */ 1587 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { 1588 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 1589 skip_map |= (1 << qh->slot); 1590 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); 1591 priv->atl_slots[qh->slot].qh = NULL; 1592 priv->atl_slots[qh->slot].qtd = NULL; 1593 } else { 1594 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 1595 skip_map |= (1 << qh->slot); 1596 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); 1597 priv->int_slots[qh->slot].qh = NULL; 1598 priv->int_slots[qh->slot].qtd = NULL; 1599 } 1600 1601 qh->slot = -1; 1602 } 1603 1604 /* 1605 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing 1606 * any active transfer belonging to the urb in the process. 1607 */ 1608 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, 1609 struct isp1760_qtd *qtd) 1610 { 1611 struct urb *urb; 1612 int urb_was_running; 1613 1614 urb = qtd->urb; 1615 urb_was_running = 0; 1616 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { 1617 if (qtd->urb != urb) 1618 break; 1619 1620 if (qtd->status >= QTD_XFER_STARTED) 1621 urb_was_running = 1; 1622 if (last_qtd_of_urb(qtd, qh) && 1623 (qtd->status >= QTD_XFER_COMPLETE)) 1624 urb_was_running = 0; 1625 1626 if (qtd->status == QTD_XFER_STARTED) 1627 kill_transfer(hcd, urb, qh); 1628 qtd->status = QTD_RETIRE; 1629 } 1630 1631 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) { 1632 qh->tt_buffer_dirty = 1; 1633 if (usb_hub_clear_tt_buffer(urb)) 1634 /* Clear failed; let's hope things work anyway */ 1635 qh->tt_buffer_dirty = 0; 1636 } 1637 } 1638 1639 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 1640 int status) 1641 { 1642 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1643 unsigned long spinflags; 1644 struct isp1760_qh *qh; 1645 struct isp1760_qtd *qtd; 1646 int retval = 0; 1647 1648 spin_lock_irqsave(&priv->lock, spinflags); 1649 retval = usb_hcd_check_unlink_urb(hcd, urb, status); 1650 if (retval) 1651 goto out; 1652 1653 qh = urb->ep->hcpriv; 1654 if (!qh) { 1655 retval = -EINVAL; 1656 goto out; 1657 } 1658 1659 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) 1660 if (qtd->urb == urb) { 1661 dequeue_urb_from_qtd(hcd, qh, qtd); 1662 list_move(&qtd->qtd_list, &qh->qtd_list); 1663 break; 1664 } 1665 1666 urb->status = status; 1667 schedule_ptds(hcd); 1668 1669 out: 1670 spin_unlock_irqrestore(&priv->lock, spinflags); 1671 return retval; 1672 } 1673 1674 static void isp1760_endpoint_disable(struct usb_hcd *hcd, 1675 struct usb_host_endpoint *ep) 1676 { 1677 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1678 unsigned long spinflags; 1679 struct isp1760_qh *qh, *qh_iter; 1680 int i; 1681 1682 spin_lock_irqsave(&priv->lock, spinflags); 1683 1684 qh = ep->hcpriv; 1685 if (!qh) 1686 goto out; 1687 1688 WARN_ON(!list_empty(&qh->qtd_list)); 1689 1690 for (i = 0; i < QH_END; i++) 1691 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) 1692 if (qh_iter == qh) { 1693 list_del(&qh_iter->qh_list); 1694 i = QH_END; 1695 break; 1696 } 1697 qh_free(qh); 1698 ep->hcpriv = NULL; 1699 1700 schedule_ptds(hcd); 1701 1702 out: 1703 spin_unlock_irqrestore(&priv->lock, spinflags); 1704 } 1705 1706 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) 1707 { 1708 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1709 u32 temp, status = 0; 1710 u32 mask; 1711 int retval = 1; 1712 unsigned long flags; 1713 1714 /* if !PM, root hub timers won't get shut down ... */ 1715 if (!HC_IS_RUNNING(hcd->state)) 1716 return 0; 1717 1718 /* init status to no-changes */ 1719 buf[0] = 0; 1720 mask = PORT_CSC; 1721 1722 spin_lock_irqsave(&priv->lock, flags); 1723 temp = reg_read32(hcd->regs, HC_PORTSC1); 1724 1725 if (temp & PORT_OWNER) { 1726 if (temp & PORT_CSC) { 1727 temp &= ~PORT_CSC; 1728 reg_write32(hcd->regs, HC_PORTSC1, temp); 1729 goto done; 1730 } 1731 } 1732 1733 /* 1734 * Return status information even for ports with OWNER set. 1735 * Otherwise hub_wq wouldn't see the disconnect event when a 1736 * high-speed device is switched over to the companion 1737 * controller by the user. 1738 */ 1739 1740 if ((temp & mask) != 0 1741 || ((temp & PORT_RESUME) != 0 1742 && time_after_eq(jiffies, 1743 priv->reset_done))) { 1744 buf [0] |= 1 << (0 + 1); 1745 status = STS_PCD; 1746 } 1747 /* FIXME autosuspend idle root hubs */ 1748 done: 1749 spin_unlock_irqrestore(&priv->lock, flags); 1750 return status ? retval : 0; 1751 } 1752 1753 static void isp1760_hub_descriptor(struct isp1760_hcd *priv, 1754 struct usb_hub_descriptor *desc) 1755 { 1756 int ports = HCS_N_PORTS(priv->hcs_params); 1757 u16 temp; 1758 1759 desc->bDescriptorType = USB_DT_HUB; 1760 /* priv 1.0, 2.3.9 says 20ms max */ 1761 desc->bPwrOn2PwrGood = 10; 1762 desc->bHubContrCurrent = 0; 1763 1764 desc->bNbrPorts = ports; 1765 temp = 1 + (ports / 8); 1766 desc->bDescLength = 7 + 2 * temp; 1767 1768 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 1769 memset(&desc->u.hs.DeviceRemovable[0], 0, temp); 1770 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); 1771 1772 /* per-port overcurrent reporting */ 1773 temp = HUB_CHAR_INDV_PORT_OCPM; 1774 if (HCS_PPC(priv->hcs_params)) 1775 /* per-port power control */ 1776 temp |= HUB_CHAR_INDV_PORT_LPSM; 1777 else 1778 /* no power switching */ 1779 temp |= HUB_CHAR_NO_LPSM; 1780 desc->wHubCharacteristics = cpu_to_le16(temp); 1781 } 1782 1783 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) 1784 1785 static int check_reset_complete(struct usb_hcd *hcd, int index, 1786 int port_status) 1787 { 1788 if (!(port_status & PORT_CONNECT)) 1789 return port_status; 1790 1791 /* if reset finished and it's still not enabled -- handoff */ 1792 if (!(port_status & PORT_PE)) { 1793 1794 dev_info(hcd->self.controller, 1795 "port %d full speed --> companion\n", 1796 index + 1); 1797 1798 port_status |= PORT_OWNER; 1799 port_status &= ~PORT_RWC_BITS; 1800 reg_write32(hcd->regs, HC_PORTSC1, port_status); 1801 1802 } else 1803 dev_info(hcd->self.controller, "port %d high speed\n", 1804 index + 1); 1805 1806 return port_status; 1807 } 1808 1809 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, 1810 u16 wValue, u16 wIndex, char *buf, u16 wLength) 1811 { 1812 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1813 int ports = HCS_N_PORTS(priv->hcs_params); 1814 u32 temp, status; 1815 unsigned long flags; 1816 int retval = 0; 1817 unsigned selector; 1818 1819 /* 1820 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. 1821 * HCS_INDICATOR may say we can change LEDs to off/amber/green. 1822 * (track current state ourselves) ... blink for diagnostics, 1823 * power, "this is the one", etc. EHCI spec supports this. 1824 */ 1825 1826 spin_lock_irqsave(&priv->lock, flags); 1827 switch (typeReq) { 1828 case ClearHubFeature: 1829 switch (wValue) { 1830 case C_HUB_LOCAL_POWER: 1831 case C_HUB_OVER_CURRENT: 1832 /* no hub-wide feature/status flags */ 1833 break; 1834 default: 1835 goto error; 1836 } 1837 break; 1838 case ClearPortFeature: 1839 if (!wIndex || wIndex > ports) 1840 goto error; 1841 wIndex--; 1842 temp = reg_read32(hcd->regs, HC_PORTSC1); 1843 1844 /* 1845 * Even if OWNER is set, so the port is owned by the 1846 * companion controller, hub_wq needs to be able to clear 1847 * the port-change status bits (especially 1848 * USB_PORT_STAT_C_CONNECTION). 1849 */ 1850 1851 switch (wValue) { 1852 case USB_PORT_FEAT_ENABLE: 1853 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); 1854 break; 1855 case USB_PORT_FEAT_C_ENABLE: 1856 /* XXX error? */ 1857 break; 1858 case USB_PORT_FEAT_SUSPEND: 1859 if (temp & PORT_RESET) 1860 goto error; 1861 1862 if (temp & PORT_SUSPEND) { 1863 if ((temp & PORT_PE) == 0) 1864 goto error; 1865 /* resume signaling for 20 msec */ 1866 temp &= ~(PORT_RWC_BITS); 1867 reg_write32(hcd->regs, HC_PORTSC1, 1868 temp | PORT_RESUME); 1869 priv->reset_done = jiffies + 1870 msecs_to_jiffies(USB_RESUME_TIMEOUT); 1871 } 1872 break; 1873 case USB_PORT_FEAT_C_SUSPEND: 1874 /* we auto-clear this feature */ 1875 break; 1876 case USB_PORT_FEAT_POWER: 1877 if (HCS_PPC(priv->hcs_params)) 1878 reg_write32(hcd->regs, HC_PORTSC1, 1879 temp & ~PORT_POWER); 1880 break; 1881 case USB_PORT_FEAT_C_CONNECTION: 1882 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); 1883 break; 1884 case USB_PORT_FEAT_C_OVER_CURRENT: 1885 /* XXX error ?*/ 1886 break; 1887 case USB_PORT_FEAT_C_RESET: 1888 /* GetPortStatus clears reset */ 1889 break; 1890 default: 1891 goto error; 1892 } 1893 reg_read32(hcd->regs, HC_USBCMD); 1894 break; 1895 case GetHubDescriptor: 1896 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) 1897 buf); 1898 break; 1899 case GetHubStatus: 1900 /* no hub-wide feature/status flags */ 1901 memset(buf, 0, 4); 1902 break; 1903 case GetPortStatus: 1904 if (!wIndex || wIndex > ports) 1905 goto error; 1906 wIndex--; 1907 status = 0; 1908 temp = reg_read32(hcd->regs, HC_PORTSC1); 1909 1910 /* wPortChange bits */ 1911 if (temp & PORT_CSC) 1912 status |= USB_PORT_STAT_C_CONNECTION << 16; 1913 1914 1915 /* whoever resumes must GetPortStatus to complete it!! */ 1916 if (temp & PORT_RESUME) { 1917 dev_err(hcd->self.controller, "Port resume should be skipped.\n"); 1918 1919 /* Remote Wakeup received? */ 1920 if (!priv->reset_done) { 1921 /* resume signaling for 20 msec */ 1922 priv->reset_done = jiffies 1923 + msecs_to_jiffies(20); 1924 /* check the port again */ 1925 mod_timer(&hcd->rh_timer, priv->reset_done); 1926 } 1927 1928 /* resume completed? */ 1929 else if (time_after_eq(jiffies, 1930 priv->reset_done)) { 1931 status |= USB_PORT_STAT_C_SUSPEND << 16; 1932 priv->reset_done = 0; 1933 1934 /* stop resume signaling */ 1935 temp = reg_read32(hcd->regs, HC_PORTSC1); 1936 reg_write32(hcd->regs, HC_PORTSC1, 1937 temp & ~(PORT_RWC_BITS | PORT_RESUME)); 1938 retval = handshake(hcd, HC_PORTSC1, 1939 PORT_RESUME, 0, 2000 /* 2msec */); 1940 if (retval != 0) { 1941 dev_err(hcd->self.controller, 1942 "port %d resume error %d\n", 1943 wIndex + 1, retval); 1944 goto error; 1945 } 1946 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); 1947 } 1948 } 1949 1950 /* whoever resets must GetPortStatus to complete it!! */ 1951 if ((temp & PORT_RESET) 1952 && time_after_eq(jiffies, 1953 priv->reset_done)) { 1954 status |= USB_PORT_STAT_C_RESET << 16; 1955 priv->reset_done = 0; 1956 1957 /* force reset to complete */ 1958 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); 1959 /* REVISIT: some hardware needs 550+ usec to clear 1960 * this bit; seems too long to spin routinely... 1961 */ 1962 retval = handshake(hcd, HC_PORTSC1, 1963 PORT_RESET, 0, 750); 1964 if (retval != 0) { 1965 dev_err(hcd->self.controller, "port %d reset error %d\n", 1966 wIndex + 1, retval); 1967 goto error; 1968 } 1969 1970 /* see what we found out */ 1971 temp = check_reset_complete(hcd, wIndex, 1972 reg_read32(hcd->regs, HC_PORTSC1)); 1973 } 1974 /* 1975 * Even if OWNER is set, there's no harm letting hub_wq 1976 * see the wPortStatus values (they should all be 0 except 1977 * for PORT_POWER anyway). 1978 */ 1979 1980 if (temp & PORT_OWNER) 1981 dev_err(hcd->self.controller, "PORT_OWNER is set\n"); 1982 1983 if (temp & PORT_CONNECT) { 1984 status |= USB_PORT_STAT_CONNECTION; 1985 /* status may be from integrated TT */ 1986 status |= USB_PORT_STAT_HIGH_SPEED; 1987 } 1988 if (temp & PORT_PE) 1989 status |= USB_PORT_STAT_ENABLE; 1990 if (temp & (PORT_SUSPEND|PORT_RESUME)) 1991 status |= USB_PORT_STAT_SUSPEND; 1992 if (temp & PORT_RESET) 1993 status |= USB_PORT_STAT_RESET; 1994 if (temp & PORT_POWER) 1995 status |= USB_PORT_STAT_POWER; 1996 1997 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1998 break; 1999 case SetHubFeature: 2000 switch (wValue) { 2001 case C_HUB_LOCAL_POWER: 2002 case C_HUB_OVER_CURRENT: 2003 /* no hub-wide feature/status flags */ 2004 break; 2005 default: 2006 goto error; 2007 } 2008 break; 2009 case SetPortFeature: 2010 selector = wIndex >> 8; 2011 wIndex &= 0xff; 2012 if (!wIndex || wIndex > ports) 2013 goto error; 2014 wIndex--; 2015 temp = reg_read32(hcd->regs, HC_PORTSC1); 2016 if (temp & PORT_OWNER) 2017 break; 2018 2019 /* temp &= ~PORT_RWC_BITS; */ 2020 switch (wValue) { 2021 case USB_PORT_FEAT_ENABLE: 2022 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); 2023 break; 2024 2025 case USB_PORT_FEAT_SUSPEND: 2026 if ((temp & PORT_PE) == 0 2027 || (temp & PORT_RESET) != 0) 2028 goto error; 2029 2030 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); 2031 break; 2032 case USB_PORT_FEAT_POWER: 2033 if (HCS_PPC(priv->hcs_params)) 2034 reg_write32(hcd->regs, HC_PORTSC1, 2035 temp | PORT_POWER); 2036 break; 2037 case USB_PORT_FEAT_RESET: 2038 if (temp & PORT_RESUME) 2039 goto error; 2040 /* line status bits may report this as low speed, 2041 * which can be fine if this root hub has a 2042 * transaction translator built in. 2043 */ 2044 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT 2045 && PORT_USB11(temp)) { 2046 temp |= PORT_OWNER; 2047 } else { 2048 temp |= PORT_RESET; 2049 temp &= ~PORT_PE; 2050 2051 /* 2052 * caller must wait, then call GetPortStatus 2053 * usb 2.0 spec says 50 ms resets on root 2054 */ 2055 priv->reset_done = jiffies + 2056 msecs_to_jiffies(50); 2057 } 2058 reg_write32(hcd->regs, HC_PORTSC1, temp); 2059 break; 2060 default: 2061 goto error; 2062 } 2063 reg_read32(hcd->regs, HC_USBCMD); 2064 break; 2065 2066 default: 2067 error: 2068 /* "stall" on error */ 2069 retval = -EPIPE; 2070 } 2071 spin_unlock_irqrestore(&priv->lock, flags); 2072 return retval; 2073 } 2074 2075 static int isp1760_get_frame(struct usb_hcd *hcd) 2076 { 2077 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2078 u32 fr; 2079 2080 fr = reg_read32(hcd->regs, HC_FRINDEX); 2081 return (fr >> 3) % priv->periodic_size; 2082 } 2083 2084 static void isp1760_stop(struct usb_hcd *hcd) 2085 { 2086 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2087 u32 temp; 2088 2089 del_timer(&errata2_timer); 2090 2091 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, 2092 NULL, 0); 2093 mdelay(20); 2094 2095 spin_lock_irq(&priv->lock); 2096 ehci_reset(hcd); 2097 /* Disable IRQ */ 2098 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 2099 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); 2100 spin_unlock_irq(&priv->lock); 2101 2102 reg_write32(hcd->regs, HC_CONFIGFLAG, 0); 2103 } 2104 2105 static void isp1760_shutdown(struct usb_hcd *hcd) 2106 { 2107 u32 command, temp; 2108 2109 isp1760_stop(hcd); 2110 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 2111 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); 2112 2113 command = reg_read32(hcd->regs, HC_USBCMD); 2114 command &= ~CMD_RUN; 2115 reg_write32(hcd->regs, HC_USBCMD, command); 2116 } 2117 2118 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, 2119 struct usb_host_endpoint *ep) 2120 { 2121 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2122 struct isp1760_qh *qh = ep->hcpriv; 2123 unsigned long spinflags; 2124 2125 if (!qh) 2126 return; 2127 2128 spin_lock_irqsave(&priv->lock, spinflags); 2129 qh->tt_buffer_dirty = 0; 2130 schedule_ptds(hcd); 2131 spin_unlock_irqrestore(&priv->lock, spinflags); 2132 } 2133 2134 2135 static const struct hc_driver isp1760_hc_driver = { 2136 .description = "isp1760-hcd", 2137 .product_desc = "NXP ISP1760 USB Host Controller", 2138 .hcd_priv_size = sizeof(struct isp1760_hcd *), 2139 .irq = isp1760_irq, 2140 .flags = HCD_MEMORY | HCD_USB2, 2141 .reset = isp1760_hc_setup, 2142 .start = isp1760_run, 2143 .stop = isp1760_stop, 2144 .shutdown = isp1760_shutdown, 2145 .urb_enqueue = isp1760_urb_enqueue, 2146 .urb_dequeue = isp1760_urb_dequeue, 2147 .endpoint_disable = isp1760_endpoint_disable, 2148 .get_frame_number = isp1760_get_frame, 2149 .hub_status_data = isp1760_hub_status_data, 2150 .hub_control = isp1760_hub_control, 2151 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, 2152 }; 2153 2154 int __init isp1760_init_kmem_once(void) 2155 { 2156 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", 2157 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | 2158 SLAB_MEM_SPREAD, NULL); 2159 2160 if (!urb_listitem_cachep) 2161 return -ENOMEM; 2162 2163 qtd_cachep = kmem_cache_create("isp1760_qtd", 2164 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | 2165 SLAB_MEM_SPREAD, NULL); 2166 2167 if (!qtd_cachep) 2168 return -ENOMEM; 2169 2170 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), 2171 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); 2172 2173 if (!qh_cachep) { 2174 kmem_cache_destroy(qtd_cachep); 2175 return -ENOMEM; 2176 } 2177 2178 return 0; 2179 } 2180 2181 void isp1760_deinit_kmem_cache(void) 2182 { 2183 kmem_cache_destroy(qtd_cachep); 2184 kmem_cache_destroy(qh_cachep); 2185 kmem_cache_destroy(urb_listitem_cachep); 2186 } 2187 2188 int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs, 2189 struct resource *mem, int irq, unsigned long irqflags, 2190 struct device *dev) 2191 { 2192 struct usb_hcd *hcd; 2193 int ret; 2194 2195 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); 2196 if (!hcd) 2197 return -ENOMEM; 2198 2199 *(struct isp1760_hcd **)hcd->hcd_priv = priv; 2200 2201 priv->hcd = hcd; 2202 2203 init_memory(priv); 2204 2205 hcd->irq = irq; 2206 hcd->regs = regs; 2207 hcd->rsrc_start = mem->start; 2208 hcd->rsrc_len = resource_size(mem); 2209 2210 /* This driver doesn't support wakeup requests */ 2211 hcd->cant_recv_wakeups = 1; 2212 2213 ret = usb_add_hcd(hcd, irq, irqflags); 2214 if (ret) 2215 goto error; 2216 2217 device_wakeup_enable(hcd->self.controller); 2218 2219 return 0; 2220 2221 error: 2222 usb_put_hcd(hcd); 2223 return ret; 2224 } 2225 2226 void isp1760_hcd_unregister(struct isp1760_hcd *priv) 2227 { 2228 if (!priv->hcd) 2229 return; 2230 2231 usb_remove_hcd(priv->hcd); 2232 usb_put_hcd(priv->hcd); 2233 } 2234