1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the NXP ISP1760 chip 4 * 5 * However, the code might contain some bugs. What doesn't work for sure is: 6 * - ISO 7 * - OTG 8 e The interrupt line is configured as active low, level. 9 * 10 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> 11 * 12 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> 13 * 14 * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> 15 * 16 */ 17 #include <linux/gpio/consumer.h> 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/usb.h> 23 #include <linux/usb/hcd.h> 24 #include <linux/debugfs.h> 25 #include <linux/uaccess.h> 26 #include <linux/io.h> 27 #include <linux/iopoll.h> 28 #include <linux/mm.h> 29 #include <linux/timer.h> 30 #include <asm/unaligned.h> 31 #include <asm/cacheflush.h> 32 33 #include "isp1760-core.h" 34 #include "isp1760-hcd.h" 35 #include "isp1760-regs.h" 36 37 static struct kmem_cache *qtd_cachep; 38 static struct kmem_cache *qh_cachep; 39 static struct kmem_cache *urb_listitem_cachep; 40 41 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 42 struct isp1760_qtd *qtd); 43 44 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) 45 { 46 return *(struct isp1760_hcd **)hcd->hcd_priv; 47 } 48 49 #define dw_to_le32(x) (cpu_to_le32((__force u32)x)) 50 #define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x))) 51 52 /* urb state*/ 53 #define DELETE_URB (0x0008) 54 #define NO_TRANSFER_ACTIVE (0xffffffff) 55 56 /* Philips Proprietary Transfer Descriptor (PTD) */ 57 typedef __u32 __bitwise __dw; 58 struct ptd { 59 __dw dw0; 60 __dw dw1; 61 __dw dw2; 62 __dw dw3; 63 __dw dw4; 64 __dw dw5; 65 __dw dw6; 66 __dw dw7; 67 }; 68 69 struct ptd_le32 { 70 __le32 dw0; 71 __le32 dw1; 72 __le32 dw2; 73 __le32 dw3; 74 __le32 dw4; 75 __le32 dw5; 76 __le32 dw6; 77 __le32 dw7; 78 }; 79 80 #define PTD_OFFSET 0x0400 81 #define ISO_PTD_OFFSET 0x0400 82 #define INT_PTD_OFFSET 0x0800 83 #define ATL_PTD_OFFSET 0x0c00 84 #define PAYLOAD_OFFSET 0x1000 85 86 #define ISP_BANK_0 0x00 87 #define ISP_BANK_1 0x01 88 #define ISP_BANK_2 0x02 89 #define ISP_BANK_3 0x03 90 91 #define TO_DW(x) ((__force __dw)x) 92 #define TO_U32(x) ((__force u32)x) 93 94 /* ATL */ 95 /* DW0 */ 96 #define DW0_VALID_BIT TO_DW(1) 97 #define FROM_DW0_VALID(x) (TO_U32(x) & 0x01) 98 #define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3)) 99 #define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18)) 100 #define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29)) 101 #define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31)) 102 /* DW1 */ 103 #define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3)) 104 #define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10)) 105 #define DW1_TRANS_BULK TO_DW(((u32)2 << 12)) 106 #define DW1_TRANS_INT TO_DW(((u32)3 << 12)) 107 #define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14)) 108 #define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16)) 109 #define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18)) 110 #define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25)) 111 /* DW2 */ 112 #define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8)) 113 #define TO_DW2_RL(x) TO_DW(((x) << 25)) 114 #define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) 115 /* DW3 */ 116 #define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff) 117 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) 118 #define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) 119 #define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) 120 #define TO_DW3_CERR(x) TO_DW(((x) << 23)) 121 #define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3) 122 #define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25)) 123 #define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1) 124 #define TO_DW3_PING(x) TO_DW(((x) << 26)) 125 #define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1) 126 #define DW3_ERROR_BIT TO_DW((1 << 28)) 127 #define DW3_BABBLE_BIT TO_DW((1 << 29)) 128 #define DW3_HALT_BIT TO_DW((1 << 30)) 129 #define DW3_ACTIVE_BIT TO_DW((1 << 31)) 130 #define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01) 131 132 #define INT_UNDERRUN (1 << 2) 133 #define INT_BABBLE (1 << 1) 134 #define INT_EXACT (1 << 0) 135 136 #define SETUP_PID (2) 137 #define IN_PID (1) 138 #define OUT_PID (0) 139 140 /* Errata 1 */ 141 #define RL_COUNTER (0) 142 #define NAK_COUNTER (0) 143 #define ERR_COUNTER (3) 144 145 struct isp1760_qtd { 146 u8 packet_type; 147 void *data_buffer; 148 u32 payload_addr; 149 150 /* the rest is HCD-private */ 151 struct list_head qtd_list; 152 struct urb *urb; 153 size_t length; 154 size_t actual_length; 155 156 /* QTD_ENQUEUED: waiting for transfer (inactive) */ 157 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ 158 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only 159 interrupt handler may touch this qtd! */ 160 /* QTD_XFER_COMPLETE: payload has been transferred successfully */ 161 /* QTD_RETIRE: transfer error/abort qtd */ 162 #define QTD_ENQUEUED 0 163 #define QTD_PAYLOAD_ALLOC 1 164 #define QTD_XFER_STARTED 2 165 #define QTD_XFER_COMPLETE 3 166 #define QTD_RETIRE 4 167 u32 status; 168 }; 169 170 /* Queue head, one for each active endpoint */ 171 struct isp1760_qh { 172 struct list_head qh_list; 173 struct list_head qtd_list; 174 u32 toggle; 175 u32 ping; 176 int slot; 177 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ 178 }; 179 180 struct urb_listitem { 181 struct list_head urb_list; 182 struct urb *urb; 183 }; 184 185 static const u32 isp1763_hc_portsc1_fields[] = { 186 [PORT_OWNER] = BIT(13), 187 [PORT_POWER] = BIT(12), 188 [PORT_LSTATUS] = BIT(10), 189 [PORT_RESET] = BIT(8), 190 [PORT_SUSPEND] = BIT(7), 191 [PORT_RESUME] = BIT(6), 192 [PORT_PE] = BIT(2), 193 [PORT_CSC] = BIT(1), 194 [PORT_CONNECT] = BIT(0), 195 }; 196 197 /* 198 * Access functions for isp176x registers regmap fields 199 */ 200 static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) 201 { 202 struct isp1760_hcd *priv = hcd_to_priv(hcd); 203 204 return isp1760_field_read(priv->fields, field); 205 } 206 207 /* 208 * We need, in isp1763, to write directly the values to the portsc1 209 * register so it will make the other values to trigger. 210 */ 211 static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, 212 u32 val) 213 { 214 u32 bit = isp1763_hc_portsc1_fields[field]; 215 u32 port_status = readl(priv->base + ISP1763_HC_PORTSC1); 216 217 if (val) 218 writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); 219 else 220 writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); 221 } 222 223 static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) 224 { 225 struct isp1760_hcd *priv = hcd_to_priv(hcd); 226 227 if (unlikely(priv->is_isp1763 && 228 (field >= PORT_OWNER && field <= PORT_CONNECT))) 229 return isp1760_hcd_portsc1_set_clear(priv, field, val); 230 231 isp1760_field_write(priv->fields, field, val); 232 } 233 234 static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field) 235 { 236 isp1760_hcd_write(hcd, field, 0xFFFFFFFF); 237 } 238 239 static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) 240 { 241 isp1760_hcd_write(hcd, field, 0); 242 } 243 244 static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, 245 u32 timeout_us) 246 { 247 struct isp1760_hcd *priv = hcd_to_priv(hcd); 248 u32 val; 249 250 isp1760_hcd_set(hcd, field); 251 252 return regmap_field_read_poll_timeout(priv->fields[field], val, 253 val, 10, timeout_us); 254 } 255 256 static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, 257 u32 timeout_us) 258 { 259 struct isp1760_hcd *priv = hcd_to_priv(hcd); 260 u32 val; 261 262 isp1760_hcd_set(hcd, field); 263 264 return regmap_field_read_poll_timeout(priv->fields[field], val, 265 !val, 10, timeout_us); 266 } 267 268 static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, 269 u32 timeout_us) 270 { 271 struct isp1760_hcd *priv = hcd_to_priv(hcd); 272 u32 val; 273 274 isp1760_hcd_clear(hcd, field); 275 276 return regmap_field_read_poll_timeout(priv->fields[field], val, 277 !val, 10, timeout_us); 278 } 279 280 static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) 281 { 282 return !!isp1760_hcd_read(hcd, field); 283 } 284 285 static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd) 286 { 287 struct isp1760_hcd *priv = hcd_to_priv(hcd); 288 289 if (priv->is_isp1763) 290 return true; 291 292 return isp1760_hcd_is_set(hcd, HCS_PPC); 293 } 294 295 static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd) 296 { 297 struct isp1760_hcd *priv = hcd_to_priv(hcd); 298 299 if (priv->is_isp1763) 300 return 1; 301 302 return isp1760_hcd_read(hcd, HCS_N_PORTS); 303 } 304 305 /* 306 * Access functions for isp176x memory (offset >= 0x0400). 307 * 308 * bank_reads8() reads memory locations prefetched by an earlier write to 309 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- 310 * bank optimizations, you should use the more generic mem_read() below. 311 * 312 * For access to ptd memory, use the specialized ptd_read() and ptd_write() 313 * below. 314 * 315 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() 316 * doesn't quite work because some people have to enforce 32-bit access 317 */ 318 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, 319 __u32 *dst, u32 bytes) 320 { 321 __u32 __iomem *src; 322 u32 val; 323 __u8 *src_byteptr; 324 __u8 *dst_byteptr; 325 326 src = src_base + (bank_addr | src_offset); 327 328 if (src_offset < PAYLOAD_OFFSET) { 329 while (bytes >= 4) { 330 *dst = readl_relaxed(src); 331 bytes -= 4; 332 src++; 333 dst++; 334 } 335 } else { 336 while (bytes >= 4) { 337 *dst = __raw_readl(src); 338 bytes -= 4; 339 src++; 340 dst++; 341 } 342 } 343 344 if (!bytes) 345 return; 346 347 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully 348 * allocated. 349 */ 350 if (src_offset < PAYLOAD_OFFSET) 351 val = readl_relaxed(src); 352 else 353 val = __raw_readl(src); 354 355 dst_byteptr = (void *) dst; 356 src_byteptr = (void *) &val; 357 while (bytes > 0) { 358 *dst_byteptr = *src_byteptr; 359 dst_byteptr++; 360 src_byteptr++; 361 bytes--; 362 } 363 } 364 365 static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, 366 u32 bytes) 367 { 368 struct isp1760_hcd *priv = hcd_to_priv(hcd); 369 370 isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); 371 isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); 372 ndelay(100); 373 374 bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); 375 } 376 377 /* 378 * ISP1763 does not have the banks direct host controller memory access, 379 * needs to use the HC_DATA register. Add data read/write according to this, 380 * and also adjust 16bit access. 381 */ 382 static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr, 383 u16 *dstptr, u32 bytes) 384 { 385 struct isp1760_hcd *priv = hcd_to_priv(hcd); 386 387 /* Write the starting device address to the hcd memory register */ 388 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr); 389 ndelay(100); /* Delay between consecutive access */ 390 391 /* As long there are at least 16-bit to read ... */ 392 while (bytes >= 2) { 393 *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA); 394 bytes -= 2; 395 dstptr++; 396 } 397 398 /* If there are no more bytes to read, return */ 399 if (bytes <= 0) 400 return; 401 402 *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF); 403 } 404 405 static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst, 406 u32 bytes) 407 { 408 struct isp1760_hcd *priv = hcd_to_priv(hcd); 409 410 if (!priv->is_isp1763) 411 return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); 412 413 isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); 414 } 415 416 static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset, 417 __u32 const *src, u32 bytes) 418 { 419 __u32 __iomem *dst; 420 421 dst = dst_base + dst_offset; 422 423 if (dst_offset < PAYLOAD_OFFSET) { 424 while (bytes >= 4) { 425 writel_relaxed(*src, dst); 426 bytes -= 4; 427 src++; 428 dst++; 429 } 430 } else { 431 while (bytes >= 4) { 432 __raw_writel(*src, dst); 433 bytes -= 4; 434 src++; 435 dst++; 436 } 437 } 438 439 if (!bytes) 440 return; 441 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the 442 * extra bytes should not be read by the HW. 443 */ 444 445 if (dst_offset < PAYLOAD_OFFSET) 446 writel_relaxed(*src, dst); 447 else 448 __raw_writel(*src, dst); 449 } 450 451 static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src, 452 u32 bytes) 453 { 454 struct isp1760_hcd *priv = hcd_to_priv(hcd); 455 456 /* Write the starting device address to the hcd memory register */ 457 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr); 458 ndelay(100); /* Delay between consecutive access */ 459 460 while (bytes >= 2) { 461 /* Get and write the data; then adjust the data ptr and len */ 462 __raw_writew(*src, priv->base + ISP1763_HC_DATA); 463 bytes -= 2; 464 src++; 465 } 466 467 /* If there are no more bytes to process, return */ 468 if (bytes <= 0) 469 return; 470 471 /* 472 * The only way to get here is if there is a single byte left, 473 * get it and write it to the data reg; 474 */ 475 writew(*((u8 *)src), priv->base + ISP1763_HC_DATA); 476 } 477 478 static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src, 479 u32 bytes) 480 { 481 struct isp1760_hcd *priv = hcd_to_priv(hcd); 482 483 if (!priv->is_isp1763) 484 return isp1760_mem_write(priv->base, dst_offset, src, bytes); 485 486 isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes); 487 } 488 489 /* 490 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, 491 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. 492 */ 493 static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 494 struct ptd *ptd) 495 { 496 u16 src_offset = ptd_offset + slot * sizeof(*ptd); 497 struct isp1760_hcd *priv = hcd_to_priv(hcd); 498 499 isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); 500 isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); 501 ndelay(90); 502 503 bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, 504 sizeof(*ptd)); 505 } 506 507 static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 508 struct ptd *ptd) 509 { 510 u16 src_offset = ptd_offset + slot * sizeof(*ptd); 511 struct ptd_le32 le32_ptd; 512 513 isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd)); 514 /* Normalize the data obtained */ 515 ptd->dw0 = le32_to_dw(le32_ptd.dw0); 516 ptd->dw1 = le32_to_dw(le32_ptd.dw1); 517 ptd->dw2 = le32_to_dw(le32_ptd.dw2); 518 ptd->dw3 = le32_to_dw(le32_ptd.dw3); 519 ptd->dw4 = le32_to_dw(le32_ptd.dw4); 520 ptd->dw5 = le32_to_dw(le32_ptd.dw5); 521 ptd->dw6 = le32_to_dw(le32_ptd.dw6); 522 ptd->dw7 = le32_to_dw(le32_ptd.dw7); 523 } 524 525 static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 526 struct ptd *ptd) 527 { 528 struct isp1760_hcd *priv = hcd_to_priv(hcd); 529 530 if (!priv->is_isp1763) 531 return isp1760_ptd_read(hcd, ptd_offset, slot, ptd); 532 533 isp1763_ptd_read(hcd, ptd_offset, slot, ptd); 534 } 535 536 static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 537 struct ptd *cpu_ptd) 538 { 539 u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd); 540 struct ptd_le32 ptd; 541 542 ptd.dw0 = dw_to_le32(cpu_ptd->dw0); 543 ptd.dw1 = dw_to_le32(cpu_ptd->dw1); 544 ptd.dw2 = dw_to_le32(cpu_ptd->dw2); 545 ptd.dw3 = dw_to_le32(cpu_ptd->dw3); 546 ptd.dw4 = dw_to_le32(cpu_ptd->dw4); 547 ptd.dw5 = dw_to_le32(cpu_ptd->dw5); 548 ptd.dw6 = dw_to_le32(cpu_ptd->dw6); 549 ptd.dw7 = dw_to_le32(cpu_ptd->dw7); 550 551 isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, 552 8 * sizeof(ptd.dw0)); 553 } 554 555 static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, 556 struct ptd *ptd) 557 { 558 u32 dst_offset = ptd_offset + slot * sizeof(*ptd); 559 560 /* 561 * Make sure dw0 gets written last (after other dw's and after payload) 562 * since it contains the enable bit 563 */ 564 isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), 565 (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); 566 wmb(); 567 isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, 568 sizeof(ptd->dw0)); 569 } 570 571 static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 572 struct ptd *ptd) 573 { 574 struct isp1760_hcd *priv = hcd_to_priv(hcd); 575 576 if (!priv->is_isp1763) 577 return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd); 578 579 isp1763_ptd_write(hcd, ptd_offset, slot, ptd); 580 } 581 582 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ 583 static void init_memory(struct isp1760_hcd *priv) 584 { 585 const struct isp1760_memory_layout *mem = priv->memory_layout; 586 int i, j, curr; 587 u32 payload_addr; 588 589 payload_addr = PAYLOAD_OFFSET; 590 591 for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++) { 592 for (j = 0; j < mem->blocks[i]; j++, curr++) { 593 priv->memory_pool[curr + j].start = payload_addr; 594 priv->memory_pool[curr + j].size = mem->blocks_size[i]; 595 priv->memory_pool[curr + j].free = 1; 596 payload_addr += priv->memory_pool[curr + j].size; 597 } 598 } 599 600 WARN_ON(payload_addr - priv->memory_pool[0].start > 601 mem->payload_area_size); 602 } 603 604 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 605 { 606 struct isp1760_hcd *priv = hcd_to_priv(hcd); 607 const struct isp1760_memory_layout *mem = priv->memory_layout; 608 int i; 609 610 WARN_ON(qtd->payload_addr); 611 612 if (!qtd->length) 613 return; 614 615 for (i = 0; i < mem->payload_blocks; i++) { 616 if (priv->memory_pool[i].size >= qtd->length && 617 priv->memory_pool[i].free) { 618 priv->memory_pool[i].free = 0; 619 qtd->payload_addr = priv->memory_pool[i].start; 620 return; 621 } 622 } 623 } 624 625 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 626 { 627 struct isp1760_hcd *priv = hcd_to_priv(hcd); 628 const struct isp1760_memory_layout *mem = priv->memory_layout; 629 int i; 630 631 if (!qtd->payload_addr) 632 return; 633 634 for (i = 0; i < mem->payload_blocks; i++) { 635 if (priv->memory_pool[i].start == qtd->payload_addr) { 636 WARN_ON(priv->memory_pool[i].free); 637 priv->memory_pool[i].free = 1; 638 qtd->payload_addr = 0; 639 return; 640 } 641 } 642 643 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", 644 __func__, qtd->payload_addr); 645 WARN_ON(1); 646 qtd->payload_addr = 0; 647 } 648 649 /* reset a non-running (STS_HALT == 1) controller */ 650 static int ehci_reset(struct usb_hcd *hcd) 651 { 652 struct isp1760_hcd *priv = hcd_to_priv(hcd); 653 654 hcd->state = HC_STATE_HALT; 655 priv->next_statechange = jiffies; 656 657 return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000); 658 } 659 660 static struct isp1760_qh *qh_alloc(gfp_t flags) 661 { 662 struct isp1760_qh *qh; 663 664 qh = kmem_cache_zalloc(qh_cachep, flags); 665 if (!qh) 666 return NULL; 667 668 INIT_LIST_HEAD(&qh->qh_list); 669 INIT_LIST_HEAD(&qh->qtd_list); 670 qh->slot = -1; 671 672 return qh; 673 } 674 675 static void qh_free(struct isp1760_qh *qh) 676 { 677 WARN_ON(!list_empty(&qh->qtd_list)); 678 WARN_ON(qh->slot > -1); 679 kmem_cache_free(qh_cachep, qh); 680 } 681 682 /* one-time init, only for memory state */ 683 static int priv_init(struct usb_hcd *hcd) 684 { 685 struct isp1760_hcd *priv = hcd_to_priv(hcd); 686 u32 isoc_cache; 687 u32 isoc_thres; 688 int i; 689 690 spin_lock_init(&priv->lock); 691 692 for (i = 0; i < QH_END; i++) 693 INIT_LIST_HEAD(&priv->qh_list[i]); 694 695 /* 696 * hw default: 1K periodic list heads, one per frame. 697 * periodic_size can shrink by USBCMD update if hcc_params allows. 698 */ 699 priv->periodic_size = DEFAULT_I_TDPS; 700 701 if (priv->is_isp1763) { 702 priv->i_thresh = 2; 703 return 0; 704 } 705 706 /* controllers may cache some of the periodic schedule ... */ 707 isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); 708 isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); 709 710 /* full frame cache */ 711 if (isoc_cache) 712 priv->i_thresh = 8; 713 else /* N microframes cached */ 714 priv->i_thresh = 2 + isoc_thres; 715 716 return 0; 717 } 718 719 static int isp1760_hc_setup(struct usb_hcd *hcd) 720 { 721 struct isp1760_hcd *priv = hcd_to_priv(hcd); 722 u32 atx_reset; 723 int result; 724 u32 scratch; 725 u32 pattern; 726 727 if (priv->is_isp1763) 728 pattern = 0xcafe; 729 else 730 pattern = 0xdeadcafe; 731 732 isp1760_hcd_write(hcd, HC_SCRATCH, pattern); 733 734 /* Change bus pattern */ 735 scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); 736 dev_err(hcd->self.controller, "Scratch test 0x%08x\n", scratch); 737 scratch = isp1760_hcd_read(hcd, HC_SCRATCH); 738 if (scratch != pattern) { 739 dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n", scratch); 740 return -ENODEV; 741 } 742 743 /* 744 * The RESET_HC bit in the SW_RESET register is supposed to reset the 745 * host controller without touching the CPU interface registers, but at 746 * least on the ISP1761 it seems to behave as the RESET_ALL bit and 747 * reset the whole device. We thus can't use it here, so let's reset 748 * the host controller through the EHCI USB Command register. The device 749 * has been reset in core code anyway, so this shouldn't matter. 750 */ 751 isp1760_hcd_clear(hcd, ISO_BUF_FILL); 752 isp1760_hcd_clear(hcd, INT_BUF_FILL); 753 isp1760_hcd_clear(hcd, ATL_BUF_FILL); 754 755 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); 756 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); 757 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); 758 759 result = ehci_reset(hcd); 760 if (result) 761 return result; 762 763 /* Step 11 passed */ 764 765 /* ATL reset */ 766 if (priv->is_isp1763) 767 atx_reset = SW_RESET_RESET_ATX; 768 else 769 atx_reset = ALL_ATX_RESET; 770 771 isp1760_hcd_set(hcd, atx_reset); 772 mdelay(10); 773 isp1760_hcd_clear(hcd, atx_reset); 774 775 if (priv->is_isp1763) { 776 isp1760_hcd_set(hcd, HW_OTG_DISABLE); 777 isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR); 778 isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR); 779 mdelay(10); 780 781 isp1760_hcd_set(hcd, HW_INTF_LOCK); 782 } 783 784 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); 785 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); 786 787 return priv_init(hcd); 788 } 789 790 static u32 base_to_chip(u32 base) 791 { 792 return ((base - 0x400) >> 3); 793 } 794 795 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) 796 { 797 struct urb *urb; 798 799 if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) 800 return 1; 801 802 urb = qtd->urb; 803 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); 804 return (qtd->urb != urb); 805 } 806 807 /* magic numbers that can affect system performance */ 808 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 809 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 810 #define EHCI_TUNE_RL_TT 0 811 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 812 #define EHCI_TUNE_MULT_TT 1 813 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 814 815 static void create_ptd_atl(struct isp1760_qh *qh, 816 struct isp1760_qtd *qtd, struct ptd *ptd) 817 { 818 u32 maxpacket; 819 u32 multi; 820 u32 rl = RL_COUNTER; 821 u32 nak = NAK_COUNTER; 822 823 memset(ptd, 0, sizeof(*ptd)); 824 825 /* according to 3.6.2, max packet len can not be > 0x400 */ 826 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, 827 usb_pipeout(qtd->urb->pipe)); 828 multi = 1 + ((maxpacket >> 11) & 0x3); 829 maxpacket &= 0x7ff; 830 831 /* DW0 */ 832 ptd->dw0 = DW0_VALID_BIT; 833 ptd->dw0 |= TO_DW0_LENGTH(qtd->length); 834 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); 835 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); 836 837 /* DW1 */ 838 ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1)); 839 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); 840 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); 841 842 if (usb_pipebulk(qtd->urb->pipe)) 843 ptd->dw1 |= DW1_TRANS_BULK; 844 else if (usb_pipeint(qtd->urb->pipe)) 845 ptd->dw1 |= DW1_TRANS_INT; 846 847 if (qtd->urb->dev->speed != USB_SPEED_HIGH) { 848 /* split transaction */ 849 850 ptd->dw1 |= DW1_TRANS_SPLIT; 851 if (qtd->urb->dev->speed == USB_SPEED_LOW) 852 ptd->dw1 |= DW1_SE_USB_LOSPEED; 853 854 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); 855 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); 856 857 /* SE bit for Split INT transfers */ 858 if (usb_pipeint(qtd->urb->pipe) && 859 (qtd->urb->dev->speed == USB_SPEED_LOW)) 860 ptd->dw1 |= DW1_SE_USB_LOSPEED; 861 862 rl = 0; 863 nak = 0; 864 } else { 865 ptd->dw0 |= TO_DW0_MULTI(multi); 866 if (usb_pipecontrol(qtd->urb->pipe) || 867 usb_pipebulk(qtd->urb->pipe)) 868 ptd->dw3 |= TO_DW3_PING(qh->ping); 869 } 870 /* DW2 */ 871 ptd->dw2 = 0; 872 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); 873 ptd->dw2 |= TO_DW2_RL(rl); 874 875 /* DW3 */ 876 ptd->dw3 |= TO_DW3_NAKCOUNT(nak); 877 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); 878 if (usb_pipecontrol(qtd->urb->pipe)) { 879 if (qtd->data_buffer == qtd->urb->setup_packet) 880 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); 881 else if (last_qtd_of_urb(qtd, qh)) 882 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); 883 } 884 885 ptd->dw3 |= DW3_ACTIVE_BIT; 886 /* Cerr */ 887 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); 888 } 889 890 static void transform_add_int(struct isp1760_qh *qh, 891 struct isp1760_qtd *qtd, struct ptd *ptd) 892 { 893 u32 usof; 894 u32 period; 895 896 /* 897 * Most of this is guessing. ISP1761 datasheet is quite unclear, and 898 * the algorithm from the original Philips driver code, which was 899 * pretty much used in this driver before as well, is quite horrendous 900 * and, i believe, incorrect. The code below follows the datasheet and 901 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much 902 * more reliable this way (fingers crossed...). 903 */ 904 905 if (qtd->urb->dev->speed == USB_SPEED_HIGH) { 906 /* urb->interval is in units of microframes (1/8 ms) */ 907 period = qtd->urb->interval >> 3; 908 909 if (qtd->urb->interval > 4) 910 usof = 0x01; /* One bit set => 911 interval 1 ms * uFrame-match */ 912 else if (qtd->urb->interval > 2) 913 usof = 0x22; /* Two bits set => interval 1/2 ms */ 914 else if (qtd->urb->interval > 1) 915 usof = 0x55; /* Four bits set => interval 1/4 ms */ 916 else 917 usof = 0xff; /* All bits set => interval 1/8 ms */ 918 } else { 919 /* urb->interval is in units of frames (1 ms) */ 920 period = qtd->urb->interval; 921 usof = 0x0f; /* Execute Start Split on any of the 922 four first uFrames */ 923 924 /* 925 * First 8 bits in dw5 is uSCS and "specifies which uSOF the 926 * complete split needs to be sent. Valid only for IN." Also, 927 * "All bits can be set to one for every transfer." (p 82, 928 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did 929 * that number come from? 0xff seems to work fine... 930 */ 931 /* ptd->dw5 = 0x1c; */ 932 ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */ 933 } 934 935 period = period >> 1;/* Ensure equal or shorter period than requested */ 936 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ 937 938 ptd->dw2 |= TO_DW(period); 939 ptd->dw4 = TO_DW(usof); 940 } 941 942 static void create_ptd_int(struct isp1760_qh *qh, 943 struct isp1760_qtd *qtd, struct ptd *ptd) 944 { 945 create_ptd_atl(qh, qtd, ptd); 946 transform_add_int(qh, qtd, ptd); 947 } 948 949 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) 950 __releases(priv->lock) 951 __acquires(priv->lock) 952 { 953 struct isp1760_hcd *priv = hcd_to_priv(hcd); 954 955 if (!urb->unlinked) { 956 if (urb->status == -EINPROGRESS) 957 urb->status = 0; 958 } 959 960 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { 961 void *ptr; 962 for (ptr = urb->transfer_buffer; 963 ptr < urb->transfer_buffer + urb->transfer_buffer_length; 964 ptr += PAGE_SIZE) 965 flush_dcache_page(virt_to_page(ptr)); 966 } 967 968 /* complete() can reenter this HCD */ 969 usb_hcd_unlink_urb_from_ep(hcd, urb); 970 spin_unlock(&priv->lock); 971 usb_hcd_giveback_urb(hcd, urb, urb->status); 972 spin_lock(&priv->lock); 973 } 974 975 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, 976 u8 packet_type) 977 { 978 struct isp1760_qtd *qtd; 979 980 qtd = kmem_cache_zalloc(qtd_cachep, flags); 981 if (!qtd) 982 return NULL; 983 984 INIT_LIST_HEAD(&qtd->qtd_list); 985 qtd->urb = urb; 986 qtd->packet_type = packet_type; 987 qtd->status = QTD_ENQUEUED; 988 qtd->actual_length = 0; 989 990 return qtd; 991 } 992 993 static void qtd_free(struct isp1760_qtd *qtd) 994 { 995 WARN_ON(qtd->payload_addr); 996 kmem_cache_free(qtd_cachep, qtd); 997 } 998 999 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, 1000 struct isp1760_slotinfo *slots, 1001 struct isp1760_qtd *qtd, struct isp1760_qh *qh, 1002 struct ptd *ptd) 1003 { 1004 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1005 const struct isp1760_memory_layout *mem = priv->memory_layout; 1006 int skip_map; 1007 1008 WARN_ON((slot < 0) || (slot > mem->slot_num - 1)); 1009 WARN_ON(qtd->length && !qtd->payload_addr); 1010 WARN_ON(slots[slot].qtd); 1011 WARN_ON(slots[slot].qh); 1012 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); 1013 1014 if (priv->is_isp1763) 1015 ndelay(100); 1016 1017 /* Make sure done map has not triggered from some unlinked transfer */ 1018 if (ptd_offset == ATL_PTD_OFFSET) { 1019 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); 1020 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, 1021 skip_map | (1 << slot)); 1022 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); 1023 priv->atl_done_map &= ~(1 << slot); 1024 } else { 1025 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); 1026 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, 1027 skip_map | (1 << slot)); 1028 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); 1029 priv->int_done_map &= ~(1 << slot); 1030 } 1031 1032 skip_map &= ~(1 << slot); 1033 qh->slot = slot; 1034 qtd->status = QTD_XFER_STARTED; 1035 slots[slot].timestamp = jiffies; 1036 slots[slot].qtd = qtd; 1037 slots[slot].qh = qh; 1038 ptd_write(hcd, ptd_offset, slot, ptd); 1039 1040 if (ptd_offset == ATL_PTD_OFFSET) 1041 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); 1042 else 1043 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); 1044 } 1045 1046 static int is_short_bulk(struct isp1760_qtd *qtd) 1047 { 1048 return (usb_pipebulk(qtd->urb->pipe) && 1049 (qtd->actual_length < qtd->length)); 1050 } 1051 1052 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, 1053 struct list_head *urb_list) 1054 { 1055 struct isp1760_qtd *qtd, *qtd_next; 1056 struct urb_listitem *urb_listitem; 1057 int last_qtd; 1058 1059 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { 1060 if (qtd->status < QTD_XFER_COMPLETE) 1061 break; 1062 1063 last_qtd = last_qtd_of_urb(qtd, qh); 1064 1065 if ((!last_qtd) && (qtd->status == QTD_RETIRE)) 1066 qtd_next->status = QTD_RETIRE; 1067 1068 if (qtd->status == QTD_XFER_COMPLETE) { 1069 if (qtd->actual_length) { 1070 switch (qtd->packet_type) { 1071 case IN_PID: 1072 mem_read(hcd, qtd->payload_addr, 1073 qtd->data_buffer, 1074 qtd->actual_length); 1075 fallthrough; 1076 case OUT_PID: 1077 qtd->urb->actual_length += 1078 qtd->actual_length; 1079 fallthrough; 1080 case SETUP_PID: 1081 break; 1082 } 1083 } 1084 1085 if (is_short_bulk(qtd)) { 1086 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) 1087 qtd->urb->status = -EREMOTEIO; 1088 if (!last_qtd) 1089 qtd_next->status = QTD_RETIRE; 1090 } 1091 } 1092 1093 if (qtd->payload_addr) 1094 free_mem(hcd, qtd); 1095 1096 if (last_qtd) { 1097 if ((qtd->status == QTD_RETIRE) && 1098 (qtd->urb->status == -EINPROGRESS)) 1099 qtd->urb->status = -EPIPE; 1100 /* Defer calling of urb_done() since it releases lock */ 1101 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, 1102 GFP_ATOMIC); 1103 if (unlikely(!urb_listitem)) 1104 break; /* Try again on next call */ 1105 urb_listitem->urb = qtd->urb; 1106 list_add_tail(&urb_listitem->urb_list, urb_list); 1107 } 1108 1109 list_del(&qtd->qtd_list); 1110 qtd_free(qtd); 1111 } 1112 } 1113 1114 #define ENQUEUE_DEPTH 2 1115 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) 1116 { 1117 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1118 const struct isp1760_memory_layout *mem = priv->memory_layout; 1119 int slot_num = mem->slot_num; 1120 int ptd_offset; 1121 struct isp1760_slotinfo *slots; 1122 int curr_slot, free_slot; 1123 int n; 1124 struct ptd ptd; 1125 struct isp1760_qtd *qtd; 1126 1127 if (unlikely(list_empty(&qh->qtd_list))) { 1128 WARN_ON(1); 1129 return; 1130 } 1131 1132 /* Make sure this endpoint's TT buffer is clean before queueing ptds */ 1133 if (qh->tt_buffer_dirty) 1134 return; 1135 1136 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, 1137 qtd_list)->urb->pipe)) { 1138 ptd_offset = INT_PTD_OFFSET; 1139 slots = priv->int_slots; 1140 } else { 1141 ptd_offset = ATL_PTD_OFFSET; 1142 slots = priv->atl_slots; 1143 } 1144 1145 free_slot = -1; 1146 for (curr_slot = 0; curr_slot < slot_num; curr_slot++) { 1147 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) 1148 free_slot = curr_slot; 1149 if (slots[curr_slot].qh == qh) 1150 break; 1151 } 1152 1153 n = 0; 1154 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { 1155 if (qtd->status == QTD_ENQUEUED) { 1156 WARN_ON(qtd->payload_addr); 1157 alloc_mem(hcd, qtd); 1158 if ((qtd->length) && (!qtd->payload_addr)) 1159 break; 1160 1161 if (qtd->length && (qtd->packet_type == SETUP_PID || 1162 qtd->packet_type == OUT_PID)) { 1163 mem_write(hcd, qtd->payload_addr, 1164 qtd->data_buffer, qtd->length); 1165 } 1166 1167 qtd->status = QTD_PAYLOAD_ALLOC; 1168 } 1169 1170 if (qtd->status == QTD_PAYLOAD_ALLOC) { 1171 /* 1172 if ((curr_slot > 31) && (free_slot == -1)) 1173 dev_dbg(hcd->self.controller, "%s: No slot " 1174 "available for transfer\n", __func__); 1175 */ 1176 /* Start xfer for this endpoint if not already done */ 1177 if ((curr_slot > slot_num - 1) && (free_slot > -1)) { 1178 if (usb_pipeint(qtd->urb->pipe)) 1179 create_ptd_int(qh, qtd, &ptd); 1180 else 1181 create_ptd_atl(qh, qtd, &ptd); 1182 1183 start_bus_transfer(hcd, ptd_offset, free_slot, 1184 slots, qtd, qh, &ptd); 1185 curr_slot = free_slot; 1186 } 1187 1188 n++; 1189 if (n >= ENQUEUE_DEPTH) 1190 break; 1191 } 1192 } 1193 } 1194 1195 static void schedule_ptds(struct usb_hcd *hcd) 1196 { 1197 struct isp1760_hcd *priv; 1198 struct isp1760_qh *qh, *qh_next; 1199 struct list_head *ep_queue; 1200 LIST_HEAD(urb_list); 1201 struct urb_listitem *urb_listitem, *urb_listitem_next; 1202 int i; 1203 1204 if (!hcd) { 1205 WARN_ON(1); 1206 return; 1207 } 1208 1209 priv = hcd_to_priv(hcd); 1210 1211 /* 1212 * check finished/retired xfers, transfer payloads, call urb_done() 1213 */ 1214 for (i = 0; i < QH_END; i++) { 1215 ep_queue = &priv->qh_list[i]; 1216 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { 1217 collect_qtds(hcd, qh, &urb_list); 1218 if (list_empty(&qh->qtd_list)) 1219 list_del(&qh->qh_list); 1220 } 1221 } 1222 1223 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, 1224 urb_list) { 1225 isp1760_urb_done(hcd, urb_listitem->urb); 1226 kmem_cache_free(urb_listitem_cachep, urb_listitem); 1227 } 1228 1229 /* 1230 * Schedule packets for transfer. 1231 * 1232 * According to USB2.0 specification: 1233 * 1234 * 1st prio: interrupt xfers, up to 80 % of bandwidth 1235 * 2nd prio: control xfers 1236 * 3rd prio: bulk xfers 1237 * 1238 * ... but let's use a simpler scheme here (mostly because ISP1761 doc 1239 * is very unclear on how to prioritize traffic): 1240 * 1241 * 1) Enqueue any queued control transfers, as long as payload chip mem 1242 * and PTD ATL slots are available. 1243 * 2) Enqueue any queued INT transfers, as long as payload chip mem 1244 * and PTD INT slots are available. 1245 * 3) Enqueue any queued bulk transfers, as long as payload chip mem 1246 * and PTD ATL slots are available. 1247 * 1248 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between 1249 * conservation of chip mem and performance. 1250 * 1251 * I'm sure this scheme could be improved upon! 1252 */ 1253 for (i = 0; i < QH_END; i++) { 1254 ep_queue = &priv->qh_list[i]; 1255 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) 1256 enqueue_qtds(hcd, qh); 1257 } 1258 } 1259 1260 #define PTD_STATE_QTD_DONE 1 1261 #define PTD_STATE_QTD_RELOAD 2 1262 #define PTD_STATE_URB_RETIRE 3 1263 1264 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1265 struct urb *urb) 1266 { 1267 u32 dw4; 1268 int i; 1269 1270 dw4 = TO_U32(ptd->dw4); 1271 dw4 >>= 8; 1272 1273 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we 1274 need to handle these errors? Is it done in hardware? */ 1275 1276 if (ptd->dw3 & DW3_HALT_BIT) { 1277 1278 urb->status = -EPROTO; /* Default unknown error */ 1279 1280 for (i = 0; i < 8; i++) { 1281 switch (dw4 & 0x7) { 1282 case INT_UNDERRUN: 1283 dev_dbg(hcd->self.controller, "%s: underrun " 1284 "during uFrame %d\n", 1285 __func__, i); 1286 urb->status = -ECOMM; /* Could not write data */ 1287 break; 1288 case INT_EXACT: 1289 dev_dbg(hcd->self.controller, "%s: transaction " 1290 "error during uFrame %d\n", 1291 __func__, i); 1292 urb->status = -EPROTO; /* timeout, bad CRC, PID 1293 error etc. */ 1294 break; 1295 case INT_BABBLE: 1296 dev_dbg(hcd->self.controller, "%s: babble " 1297 "error during uFrame %d\n", 1298 __func__, i); 1299 urb->status = -EOVERFLOW; 1300 break; 1301 } 1302 dw4 >>= 3; 1303 } 1304 1305 return PTD_STATE_URB_RETIRE; 1306 } 1307 1308 return PTD_STATE_QTD_DONE; 1309 } 1310 1311 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1312 struct urb *urb) 1313 { 1314 WARN_ON(!ptd); 1315 if (ptd->dw3 & DW3_HALT_BIT) { 1316 if (ptd->dw3 & DW3_BABBLE_BIT) 1317 urb->status = -EOVERFLOW; 1318 else if (FROM_DW3_CERR(ptd->dw3)) 1319 urb->status = -EPIPE; /* Stall */ 1320 else 1321 urb->status = -EPROTO; /* Unknown */ 1322 /* 1323 dev_dbg(hcd->self.controller, "%s: ptd error:\n" 1324 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" 1325 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", 1326 __func__, 1327 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, 1328 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); 1329 */ 1330 return PTD_STATE_URB_RETIRE; 1331 } 1332 1333 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1334 /* Transfer Error, *but* active and no HALT -> reload */ 1335 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); 1336 return PTD_STATE_QTD_RELOAD; 1337 } 1338 1339 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1340 /* 1341 * NAKs are handled in HW by the chip. Usually if the 1342 * device is not able to send data fast enough. 1343 * This happens mostly on slower hardware. 1344 */ 1345 return PTD_STATE_QTD_RELOAD; 1346 } 1347 1348 return PTD_STATE_QTD_DONE; 1349 } 1350 1351 static void handle_done_ptds(struct usb_hcd *hcd) 1352 { 1353 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1354 struct ptd ptd; 1355 struct isp1760_qh *qh; 1356 int slot; 1357 int state; 1358 struct isp1760_slotinfo *slots; 1359 u32 ptd_offset; 1360 struct isp1760_qtd *qtd; 1361 int modified; 1362 int skip_map; 1363 1364 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); 1365 priv->int_done_map &= ~skip_map; 1366 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); 1367 priv->atl_done_map &= ~skip_map; 1368 1369 modified = priv->int_done_map || priv->atl_done_map; 1370 1371 while (priv->int_done_map || priv->atl_done_map) { 1372 if (priv->int_done_map) { 1373 /* INT ptd */ 1374 slot = __ffs(priv->int_done_map); 1375 priv->int_done_map &= ~(1 << slot); 1376 slots = priv->int_slots; 1377 /* This should not trigger, and could be removed if 1378 noone have any problems with it triggering: */ 1379 if (!slots[slot].qh) { 1380 WARN_ON(1); 1381 continue; 1382 } 1383 ptd_offset = INT_PTD_OFFSET; 1384 ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd); 1385 state = check_int_transfer(hcd, &ptd, 1386 slots[slot].qtd->urb); 1387 } else { 1388 /* ATL ptd */ 1389 slot = __ffs(priv->atl_done_map); 1390 priv->atl_done_map &= ~(1 << slot); 1391 slots = priv->atl_slots; 1392 /* This should not trigger, and could be removed if 1393 noone have any problems with it triggering: */ 1394 if (!slots[slot].qh) { 1395 WARN_ON(1); 1396 continue; 1397 } 1398 ptd_offset = ATL_PTD_OFFSET; 1399 ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); 1400 state = check_atl_transfer(hcd, &ptd, 1401 slots[slot].qtd->urb); 1402 } 1403 1404 qtd = slots[slot].qtd; 1405 slots[slot].qtd = NULL; 1406 qh = slots[slot].qh; 1407 slots[slot].qh = NULL; 1408 qh->slot = -1; 1409 1410 WARN_ON(qtd->status != QTD_XFER_STARTED); 1411 1412 switch (state) { 1413 case PTD_STATE_QTD_DONE: 1414 if ((usb_pipeint(qtd->urb->pipe)) && 1415 (qtd->urb->dev->speed != USB_SPEED_HIGH)) 1416 qtd->actual_length = 1417 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); 1418 else 1419 qtd->actual_length = 1420 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); 1421 1422 qtd->status = QTD_XFER_COMPLETE; 1423 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || 1424 is_short_bulk(qtd)) 1425 qtd = NULL; 1426 else 1427 qtd = list_entry(qtd->qtd_list.next, 1428 typeof(*qtd), qtd_list); 1429 1430 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1431 qh->ping = FROM_DW3_PING(ptd.dw3); 1432 break; 1433 1434 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ 1435 qtd->status = QTD_PAYLOAD_ALLOC; 1436 ptd.dw0 |= DW0_VALID_BIT; 1437 /* RL counter = ERR counter */ 1438 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); 1439 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); 1440 ptd.dw3 &= ~TO_DW3_CERR(3); 1441 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); 1442 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1443 qh->ping = FROM_DW3_PING(ptd.dw3); 1444 break; 1445 1446 case PTD_STATE_URB_RETIRE: 1447 qtd->status = QTD_RETIRE; 1448 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) && 1449 (qtd->urb->status != -EPIPE) && 1450 (qtd->urb->status != -EREMOTEIO)) { 1451 qh->tt_buffer_dirty = 1; 1452 if (usb_hub_clear_tt_buffer(qtd->urb)) 1453 /* Clear failed; let's hope things work 1454 anyway */ 1455 qh->tt_buffer_dirty = 0; 1456 } 1457 qtd = NULL; 1458 qh->toggle = 0; 1459 qh->ping = 0; 1460 break; 1461 1462 default: 1463 WARN_ON(1); 1464 continue; 1465 } 1466 1467 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { 1468 if (slots == priv->int_slots) { 1469 if (state == PTD_STATE_QTD_RELOAD) 1470 dev_err(hcd->self.controller, 1471 "%s: PTD_STATE_QTD_RELOAD on " 1472 "interrupt packet\n", __func__); 1473 if (state != PTD_STATE_QTD_RELOAD) 1474 create_ptd_int(qh, qtd, &ptd); 1475 } else { 1476 if (state != PTD_STATE_QTD_RELOAD) 1477 create_ptd_atl(qh, qtd, &ptd); 1478 } 1479 1480 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, 1481 qh, &ptd); 1482 } 1483 } 1484 1485 if (modified) 1486 schedule_ptds(hcd); 1487 } 1488 1489 static irqreturn_t isp1760_irq(struct usb_hcd *hcd) 1490 { 1491 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1492 irqreturn_t irqret = IRQ_NONE; 1493 u32 int_reg; 1494 u32 imask; 1495 1496 spin_lock(&priv->lock); 1497 1498 if (!(hcd->state & HC_STATE_RUNNING)) 1499 goto leave; 1500 1501 imask = isp1760_hcd_read(hcd, HC_INTERRUPT); 1502 if (unlikely(!imask)) 1503 goto leave; 1504 1505 int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT : 1506 ISP176x_HC_INTERRUPT; 1507 isp1760_reg_write(priv->regs, int_reg, imask); 1508 1509 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); 1510 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); 1511 1512 handle_done_ptds(hcd); 1513 1514 irqret = IRQ_HANDLED; 1515 1516 leave: 1517 spin_unlock(&priv->lock); 1518 1519 return irqret; 1520 } 1521 1522 /* 1523 * Workaround for problem described in chip errata 2: 1524 * 1525 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. 1526 * One solution suggested in the errata is to use SOF interrupts _instead_of_ 1527 * ATL done interrupts (the "instead of" might be important since it seems 1528 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" 1529 * to set the PTD's done bit in addition to not generating an interrupt!). 1530 * 1531 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their 1532 * done bit is not being set. This is bad - it blocks the endpoint until reboot. 1533 * 1534 * If we use SOF interrupts only, we get latency between ptd completion and the 1535 * actual handling. This is very noticeable in testusb runs which takes several 1536 * minutes longer without ATL interrupts. 1537 * 1538 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it 1539 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the 1540 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered 1541 * completed and its done map bit is set. 1542 * 1543 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen 1544 * not to cause too much lag when this HW bug occurs, while still hopefully 1545 * ensuring that the check does not falsely trigger. 1546 */ 1547 #define SLOT_TIMEOUT 300 1548 #define SLOT_CHECK_PERIOD 200 1549 static struct timer_list errata2_timer; 1550 static struct usb_hcd *errata2_timer_hcd; 1551 1552 static void errata2_function(struct timer_list *unused) 1553 { 1554 struct usb_hcd *hcd = errata2_timer_hcd; 1555 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1556 const struct isp1760_memory_layout *mem = priv->memory_layout; 1557 int slot; 1558 struct ptd ptd; 1559 unsigned long spinflags; 1560 1561 spin_lock_irqsave(&priv->lock, spinflags); 1562 1563 for (slot = 0; slot < mem->slot_num; slot++) 1564 if (priv->atl_slots[slot].qh && time_after(jiffies, 1565 priv->atl_slots[slot].timestamp + 1566 msecs_to_jiffies(SLOT_TIMEOUT))) { 1567 ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); 1568 if (!FROM_DW0_VALID(ptd.dw0) && 1569 !FROM_DW3_ACTIVE(ptd.dw3)) 1570 priv->atl_done_map |= 1 << slot; 1571 } 1572 1573 if (priv->atl_done_map) 1574 handle_done_ptds(hcd); 1575 1576 spin_unlock_irqrestore(&priv->lock, spinflags); 1577 1578 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); 1579 add_timer(&errata2_timer); 1580 } 1581 1582 static int isp1763_run(struct usb_hcd *hcd) 1583 { 1584 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1585 int retval; 1586 u32 chipid_h; 1587 u32 chipid_l; 1588 u32 chip_rev; 1589 u32 ptd_atl_int; 1590 u32 ptd_iso; 1591 1592 hcd->uses_new_polling = 1; 1593 hcd->state = HC_STATE_RUNNING; 1594 1595 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); 1596 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); 1597 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); 1598 dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n", 1599 chipid_h, chipid_l, chip_rev); 1600 1601 isp1760_hcd_clear(hcd, ISO_BUF_FILL); 1602 isp1760_hcd_clear(hcd, INT_BUF_FILL); 1603 isp1760_hcd_clear(hcd, ATL_BUF_FILL); 1604 1605 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); 1606 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); 1607 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); 1608 ndelay(100); 1609 isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP); 1610 isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP); 1611 isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP); 1612 1613 isp1760_hcd_set(hcd, HW_OTG_DISABLE); 1614 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7)); 1615 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15)); 1616 mdelay(10); 1617 1618 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); 1619 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); 1620 1621 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); 1622 1623 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); 1624 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); 1625 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); 1626 1627 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); 1628 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); 1629 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); 1630 1631 ptd_atl_int = 0x8000; 1632 ptd_iso = 0x0001; 1633 1634 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); 1635 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); 1636 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); 1637 1638 isp1760_hcd_set(hcd, ATL_BUF_FILL); 1639 isp1760_hcd_set(hcd, INT_BUF_FILL); 1640 1641 isp1760_hcd_clear(hcd, CMD_LRESET); 1642 isp1760_hcd_clear(hcd, CMD_RESET); 1643 1644 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); 1645 if (retval) 1646 return retval; 1647 1648 down_write(&ehci_cf_port_reset_rwsem); 1649 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); 1650 up_write(&ehci_cf_port_reset_rwsem); 1651 if (retval) 1652 return retval; 1653 1654 return 0; 1655 } 1656 1657 static int isp1760_run(struct usb_hcd *hcd) 1658 { 1659 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1660 int retval; 1661 u32 chipid_h; 1662 u32 chipid_l; 1663 u32 chip_rev; 1664 u32 ptd_atl_int; 1665 u32 ptd_iso; 1666 1667 /* 1668 * ISP1763 have some differences in the setup and order to enable 1669 * the ports, disable otg, setup buffers, and ATL, INT, ISO status. 1670 * So, just handle it a separate sequence. 1671 */ 1672 if (priv->is_isp1763) 1673 return isp1763_run(hcd); 1674 1675 hcd->uses_new_polling = 1; 1676 1677 hcd->state = HC_STATE_RUNNING; 1678 1679 /* Set PTD interrupt AND & OR maps */ 1680 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); 1681 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); 1682 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); 1683 1684 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); 1685 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); 1686 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); 1687 1688 /* step 23 passed */ 1689 1690 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); 1691 1692 isp1760_hcd_clear(hcd, CMD_LRESET); 1693 isp1760_hcd_clear(hcd, CMD_RESET); 1694 1695 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); 1696 if (retval) 1697 return retval; 1698 1699 /* 1700 * XXX 1701 * Spec says to write FLAG_CF as last config action, priv code grabs 1702 * the semaphore while doing so. 1703 */ 1704 down_write(&ehci_cf_port_reset_rwsem); 1705 1706 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); 1707 up_write(&ehci_cf_port_reset_rwsem); 1708 if (retval) 1709 return retval; 1710 1711 errata2_timer_hcd = hcd; 1712 timer_setup(&errata2_timer, errata2_function, 0); 1713 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); 1714 add_timer(&errata2_timer); 1715 1716 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); 1717 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); 1718 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); 1719 dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n", 1720 chipid_h, chipid_l, chip_rev); 1721 1722 /* PTD Register Init Part 2, Step 28 */ 1723 1724 /* Setup registers controlling PTD checking */ 1725 ptd_atl_int = 0x80000000; 1726 ptd_iso = 0x00000001; 1727 1728 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); 1729 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); 1730 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); 1731 1732 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); 1733 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); 1734 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); 1735 1736 isp1760_hcd_set(hcd, ATL_BUF_FILL); 1737 isp1760_hcd_set(hcd, INT_BUF_FILL); 1738 1739 /* GRR this is run-once init(), being done every time the HC starts. 1740 * So long as they're part of class devices, we can't do it init() 1741 * since the class device isn't created that early. 1742 */ 1743 return 0; 1744 } 1745 1746 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) 1747 { 1748 qtd->data_buffer = databuffer; 1749 1750 qtd->length = len; 1751 1752 return qtd->length; 1753 } 1754 1755 static void qtd_list_free(struct list_head *qtd_list) 1756 { 1757 struct isp1760_qtd *qtd, *qtd_next; 1758 1759 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { 1760 list_del(&qtd->qtd_list); 1761 qtd_free(qtd); 1762 } 1763 } 1764 1765 /* 1766 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. 1767 * Also calculate the PID type (SETUP/IN/OUT) for each packet. 1768 */ 1769 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1770 static void packetize_urb(struct usb_hcd *hcd, 1771 struct urb *urb, struct list_head *head, gfp_t flags) 1772 { 1773 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1774 const struct isp1760_memory_layout *mem = priv->memory_layout; 1775 struct isp1760_qtd *qtd; 1776 void *buf; 1777 int len, maxpacketsize; 1778 u8 packet_type; 1779 1780 /* 1781 * URBs map to sequences of QTDs: one logical transaction 1782 */ 1783 1784 if (!urb->transfer_buffer && urb->transfer_buffer_length) { 1785 /* XXX This looks like usb storage / SCSI bug */ 1786 dev_err(hcd->self.controller, 1787 "buf is null, dma is %08lx len is %d\n", 1788 (long unsigned)urb->transfer_dma, 1789 urb->transfer_buffer_length); 1790 WARN_ON(1); 1791 } 1792 1793 if (usb_pipein(urb->pipe)) 1794 packet_type = IN_PID; 1795 else 1796 packet_type = OUT_PID; 1797 1798 if (usb_pipecontrol(urb->pipe)) { 1799 qtd = qtd_alloc(flags, urb, SETUP_PID); 1800 if (!qtd) 1801 goto cleanup; 1802 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); 1803 list_add_tail(&qtd->qtd_list, head); 1804 1805 /* for zero length DATA stages, STATUS is always IN */ 1806 if (urb->transfer_buffer_length == 0) 1807 packet_type = IN_PID; 1808 } 1809 1810 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, 1811 usb_pipeout(urb->pipe))); 1812 1813 /* 1814 * buffer gets wrapped in one or more qtds; 1815 * last one may be "short" (including zero len) 1816 * and may serve as a control status ack 1817 */ 1818 buf = urb->transfer_buffer; 1819 len = urb->transfer_buffer_length; 1820 1821 for (;;) { 1822 int this_qtd_len; 1823 1824 qtd = qtd_alloc(flags, urb, packet_type); 1825 if (!qtd) 1826 goto cleanup; 1827 1828 if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) 1829 len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; 1830 1831 this_qtd_len = qtd_fill(qtd, buf, len); 1832 list_add_tail(&qtd->qtd_list, head); 1833 1834 len -= this_qtd_len; 1835 buf += this_qtd_len; 1836 1837 if (len <= 0) 1838 break; 1839 } 1840 1841 /* 1842 * control requests may need a terminating data "status" ack; 1843 * bulk ones may need a terminating short packet (zero length). 1844 */ 1845 if (urb->transfer_buffer_length != 0) { 1846 int one_more = 0; 1847 1848 if (usb_pipecontrol(urb->pipe)) { 1849 one_more = 1; 1850 if (packet_type == IN_PID) 1851 packet_type = OUT_PID; 1852 else 1853 packet_type = IN_PID; 1854 } else if (usb_pipebulk(urb->pipe) 1855 && (urb->transfer_flags & URB_ZERO_PACKET) 1856 && !(urb->transfer_buffer_length % 1857 maxpacketsize)) { 1858 one_more = 1; 1859 } 1860 if (one_more) { 1861 qtd = qtd_alloc(flags, urb, packet_type); 1862 if (!qtd) 1863 goto cleanup; 1864 1865 /* never any data in such packets */ 1866 qtd_fill(qtd, NULL, 0); 1867 list_add_tail(&qtd->qtd_list, head); 1868 } 1869 } 1870 1871 return; 1872 1873 cleanup: 1874 qtd_list_free(head); 1875 } 1876 1877 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 1878 gfp_t mem_flags) 1879 { 1880 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1881 struct list_head *ep_queue; 1882 struct isp1760_qh *qh, *qhit; 1883 unsigned long spinflags; 1884 LIST_HEAD(new_qtds); 1885 int retval; 1886 int qh_in_queue; 1887 1888 switch (usb_pipetype(urb->pipe)) { 1889 case PIPE_CONTROL: 1890 ep_queue = &priv->qh_list[QH_CONTROL]; 1891 break; 1892 case PIPE_BULK: 1893 ep_queue = &priv->qh_list[QH_BULK]; 1894 break; 1895 case PIPE_INTERRUPT: 1896 if (urb->interval < 0) 1897 return -EINVAL; 1898 /* FIXME: Check bandwidth */ 1899 ep_queue = &priv->qh_list[QH_INTERRUPT]; 1900 break; 1901 case PIPE_ISOCHRONOUS: 1902 dev_err(hcd->self.controller, "%s: isochronous USB packets " 1903 "not yet supported\n", 1904 __func__); 1905 return -EPIPE; 1906 default: 1907 dev_err(hcd->self.controller, "%s: unknown pipe type\n", 1908 __func__); 1909 return -EPIPE; 1910 } 1911 1912 if (usb_pipein(urb->pipe)) 1913 urb->actual_length = 0; 1914 1915 packetize_urb(hcd, urb, &new_qtds, mem_flags); 1916 if (list_empty(&new_qtds)) 1917 return -ENOMEM; 1918 1919 retval = 0; 1920 spin_lock_irqsave(&priv->lock, spinflags); 1921 1922 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 1923 retval = -ESHUTDOWN; 1924 qtd_list_free(&new_qtds); 1925 goto out; 1926 } 1927 retval = usb_hcd_link_urb_to_ep(hcd, urb); 1928 if (retval) { 1929 qtd_list_free(&new_qtds); 1930 goto out; 1931 } 1932 1933 qh = urb->ep->hcpriv; 1934 if (qh) { 1935 qh_in_queue = 0; 1936 list_for_each_entry(qhit, ep_queue, qh_list) { 1937 if (qhit == qh) { 1938 qh_in_queue = 1; 1939 break; 1940 } 1941 } 1942 if (!qh_in_queue) 1943 list_add_tail(&qh->qh_list, ep_queue); 1944 } else { 1945 qh = qh_alloc(GFP_ATOMIC); 1946 if (!qh) { 1947 retval = -ENOMEM; 1948 usb_hcd_unlink_urb_from_ep(hcd, urb); 1949 qtd_list_free(&new_qtds); 1950 goto out; 1951 } 1952 list_add_tail(&qh->qh_list, ep_queue); 1953 urb->ep->hcpriv = qh; 1954 } 1955 1956 list_splice_tail(&new_qtds, &qh->qtd_list); 1957 schedule_ptds(hcd); 1958 1959 out: 1960 spin_unlock_irqrestore(&priv->lock, spinflags); 1961 return retval; 1962 } 1963 1964 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, 1965 struct isp1760_qh *qh) 1966 { 1967 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1968 int skip_map; 1969 1970 WARN_ON(qh->slot == -1); 1971 1972 /* We need to forcefully reclaim the slot since some transfers never 1973 return, e.g. interrupt transfers and NAKed bulk transfers. */ 1974 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { 1975 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); 1976 skip_map |= (1 << qh->slot); 1977 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); 1978 ndelay(100); 1979 priv->atl_slots[qh->slot].qh = NULL; 1980 priv->atl_slots[qh->slot].qtd = NULL; 1981 } else { 1982 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); 1983 skip_map |= (1 << qh->slot); 1984 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); 1985 priv->int_slots[qh->slot].qh = NULL; 1986 priv->int_slots[qh->slot].qtd = NULL; 1987 } 1988 1989 qh->slot = -1; 1990 } 1991 1992 /* 1993 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing 1994 * any active transfer belonging to the urb in the process. 1995 */ 1996 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, 1997 struct isp1760_qtd *qtd) 1998 { 1999 struct urb *urb; 2000 int urb_was_running; 2001 2002 urb = qtd->urb; 2003 urb_was_running = 0; 2004 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { 2005 if (qtd->urb != urb) 2006 break; 2007 2008 if (qtd->status >= QTD_XFER_STARTED) 2009 urb_was_running = 1; 2010 if (last_qtd_of_urb(qtd, qh) && 2011 (qtd->status >= QTD_XFER_COMPLETE)) 2012 urb_was_running = 0; 2013 2014 if (qtd->status == QTD_XFER_STARTED) 2015 kill_transfer(hcd, urb, qh); 2016 qtd->status = QTD_RETIRE; 2017 } 2018 2019 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) { 2020 qh->tt_buffer_dirty = 1; 2021 if (usb_hub_clear_tt_buffer(urb)) 2022 /* Clear failed; let's hope things work anyway */ 2023 qh->tt_buffer_dirty = 0; 2024 } 2025 } 2026 2027 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2028 int status) 2029 { 2030 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2031 unsigned long spinflags; 2032 struct isp1760_qh *qh; 2033 struct isp1760_qtd *qtd; 2034 int retval = 0; 2035 2036 spin_lock_irqsave(&priv->lock, spinflags); 2037 retval = usb_hcd_check_unlink_urb(hcd, urb, status); 2038 if (retval) 2039 goto out; 2040 2041 qh = urb->ep->hcpriv; 2042 if (!qh) { 2043 retval = -EINVAL; 2044 goto out; 2045 } 2046 2047 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) 2048 if (qtd->urb == urb) { 2049 dequeue_urb_from_qtd(hcd, qh, qtd); 2050 list_move(&qtd->qtd_list, &qh->qtd_list); 2051 break; 2052 } 2053 2054 urb->status = status; 2055 schedule_ptds(hcd); 2056 2057 out: 2058 spin_unlock_irqrestore(&priv->lock, spinflags); 2059 return retval; 2060 } 2061 2062 static void isp1760_endpoint_disable(struct usb_hcd *hcd, 2063 struct usb_host_endpoint *ep) 2064 { 2065 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2066 unsigned long spinflags; 2067 struct isp1760_qh *qh, *qh_iter; 2068 int i; 2069 2070 spin_lock_irqsave(&priv->lock, spinflags); 2071 2072 qh = ep->hcpriv; 2073 if (!qh) 2074 goto out; 2075 2076 WARN_ON(!list_empty(&qh->qtd_list)); 2077 2078 for (i = 0; i < QH_END; i++) 2079 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) 2080 if (qh_iter == qh) { 2081 list_del(&qh_iter->qh_list); 2082 i = QH_END; 2083 break; 2084 } 2085 qh_free(qh); 2086 ep->hcpriv = NULL; 2087 2088 schedule_ptds(hcd); 2089 2090 out: 2091 spin_unlock_irqrestore(&priv->lock, spinflags); 2092 } 2093 2094 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) 2095 { 2096 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2097 u32 status = 0; 2098 int retval = 1; 2099 unsigned long flags; 2100 2101 /* if !PM, root hub timers won't get shut down ... */ 2102 if (!HC_IS_RUNNING(hcd->state)) 2103 return 0; 2104 2105 /* init status to no-changes */ 2106 buf[0] = 0; 2107 2108 spin_lock_irqsave(&priv->lock, flags); 2109 2110 if (isp1760_hcd_is_set(hcd, PORT_OWNER) && 2111 isp1760_hcd_is_set(hcd, PORT_CSC)) { 2112 isp1760_hcd_clear(hcd, PORT_CSC); 2113 goto done; 2114 } 2115 2116 /* 2117 * Return status information even for ports with OWNER set. 2118 * Otherwise hub_wq wouldn't see the disconnect event when a 2119 * high-speed device is switched over to the companion 2120 * controller by the user. 2121 */ 2122 if (isp1760_hcd_is_set(hcd, PORT_CSC) || 2123 (isp1760_hcd_is_set(hcd, PORT_RESUME) && 2124 time_after_eq(jiffies, priv->reset_done))) { 2125 buf [0] |= 1 << (0 + 1); 2126 status = STS_PCD; 2127 } 2128 /* FIXME autosuspend idle root hubs */ 2129 done: 2130 spin_unlock_irqrestore(&priv->lock, flags); 2131 return status ? retval : 0; 2132 } 2133 2134 static void isp1760_hub_descriptor(struct isp1760_hcd *priv, 2135 struct usb_hub_descriptor *desc) 2136 { 2137 int ports; 2138 u16 temp; 2139 2140 ports = isp1760_hcd_n_ports(priv->hcd); 2141 2142 desc->bDescriptorType = USB_DT_HUB; 2143 /* priv 1.0, 2.3.9 says 20ms max */ 2144 desc->bPwrOn2PwrGood = 10; 2145 desc->bHubContrCurrent = 0; 2146 2147 desc->bNbrPorts = ports; 2148 temp = 1 + (ports / 8); 2149 desc->bDescLength = 7 + 2 * temp; 2150 2151 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 2152 memset(&desc->u.hs.DeviceRemovable[0], 0, temp); 2153 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); 2154 2155 /* per-port overcurrent reporting */ 2156 temp = HUB_CHAR_INDV_PORT_OCPM; 2157 if (isp1760_hcd_ppc_is_set(priv->hcd)) 2158 /* per-port power control */ 2159 temp |= HUB_CHAR_INDV_PORT_LPSM; 2160 else 2161 /* no power switching */ 2162 temp |= HUB_CHAR_NO_LPSM; 2163 desc->wHubCharacteristics = cpu_to_le16(temp); 2164 } 2165 2166 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) 2167 2168 static void check_reset_complete(struct usb_hcd *hcd, int index) 2169 { 2170 if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT))) 2171 return; 2172 2173 /* if reset finished and it's still not enabled -- handoff */ 2174 if (!isp1760_hcd_is_set(hcd, PORT_PE)) { 2175 dev_info(hcd->self.controller, 2176 "port %d full speed --> companion\n", index + 1); 2177 2178 isp1760_hcd_set(hcd, PORT_OWNER); 2179 2180 isp1760_hcd_clear(hcd, PORT_CSC); 2181 } else { 2182 dev_info(hcd->self.controller, "port %d high speed\n", 2183 index + 1); 2184 } 2185 2186 return; 2187 } 2188 2189 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, 2190 u16 wValue, u16 wIndex, char *buf, u16 wLength) 2191 { 2192 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2193 u32 status; 2194 unsigned long flags; 2195 int retval = 0; 2196 int ports; 2197 2198 ports = isp1760_hcd_n_ports(hcd); 2199 2200 /* 2201 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. 2202 * HCS_INDICATOR may say we can change LEDs to off/amber/green. 2203 * (track current state ourselves) ... blink for diagnostics, 2204 * power, "this is the one", etc. EHCI spec supports this. 2205 */ 2206 2207 spin_lock_irqsave(&priv->lock, flags); 2208 switch (typeReq) { 2209 case ClearHubFeature: 2210 switch (wValue) { 2211 case C_HUB_LOCAL_POWER: 2212 case C_HUB_OVER_CURRENT: 2213 /* no hub-wide feature/status flags */ 2214 break; 2215 default: 2216 goto error; 2217 } 2218 break; 2219 case ClearPortFeature: 2220 if (!wIndex || wIndex > ports) 2221 goto error; 2222 wIndex--; 2223 2224 /* 2225 * Even if OWNER is set, so the port is owned by the 2226 * companion controller, hub_wq needs to be able to clear 2227 * the port-change status bits (especially 2228 * USB_PORT_STAT_C_CONNECTION). 2229 */ 2230 2231 switch (wValue) { 2232 case USB_PORT_FEAT_ENABLE: 2233 isp1760_hcd_clear(hcd, PORT_PE); 2234 break; 2235 case USB_PORT_FEAT_C_ENABLE: 2236 /* XXX error? */ 2237 break; 2238 case USB_PORT_FEAT_SUSPEND: 2239 if (isp1760_hcd_is_set(hcd, PORT_RESET)) 2240 goto error; 2241 2242 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) { 2243 if (!isp1760_hcd_is_set(hcd, PORT_PE)) 2244 goto error; 2245 /* resume signaling for 20 msec */ 2246 isp1760_hcd_clear(hcd, PORT_CSC); 2247 isp1760_hcd_set(hcd, PORT_RESUME); 2248 2249 priv->reset_done = jiffies + 2250 msecs_to_jiffies(USB_RESUME_TIMEOUT); 2251 } 2252 break; 2253 case USB_PORT_FEAT_C_SUSPEND: 2254 /* we auto-clear this feature */ 2255 break; 2256 case USB_PORT_FEAT_POWER: 2257 if (isp1760_hcd_ppc_is_set(hcd)) 2258 isp1760_hcd_clear(hcd, PORT_POWER); 2259 break; 2260 case USB_PORT_FEAT_C_CONNECTION: 2261 isp1760_hcd_set(hcd, PORT_CSC); 2262 break; 2263 case USB_PORT_FEAT_C_OVER_CURRENT: 2264 /* XXX error ?*/ 2265 break; 2266 case USB_PORT_FEAT_C_RESET: 2267 /* GetPortStatus clears reset */ 2268 break; 2269 default: 2270 goto error; 2271 } 2272 isp1760_hcd_read(hcd, CMD_RUN); 2273 break; 2274 case GetHubDescriptor: 2275 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) 2276 buf); 2277 break; 2278 case GetHubStatus: 2279 /* no hub-wide feature/status flags */ 2280 memset(buf, 0, 4); 2281 break; 2282 case GetPortStatus: 2283 if (!wIndex || wIndex > ports) 2284 goto error; 2285 wIndex--; 2286 status = 0; 2287 2288 /* wPortChange bits */ 2289 if (isp1760_hcd_is_set(hcd, PORT_CSC)) 2290 status |= USB_PORT_STAT_C_CONNECTION << 16; 2291 2292 /* whoever resumes must GetPortStatus to complete it!! */ 2293 if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { 2294 dev_err(hcd->self.controller, "Port resume should be skipped.\n"); 2295 2296 /* Remote Wakeup received? */ 2297 if (!priv->reset_done) { 2298 /* resume signaling for 20 msec */ 2299 priv->reset_done = jiffies 2300 + msecs_to_jiffies(20); 2301 /* check the port again */ 2302 mod_timer(&hcd->rh_timer, priv->reset_done); 2303 } 2304 2305 /* resume completed? */ 2306 else if (time_after_eq(jiffies, 2307 priv->reset_done)) { 2308 status |= USB_PORT_STAT_C_SUSPEND << 16; 2309 priv->reset_done = 0; 2310 2311 /* stop resume signaling */ 2312 isp1760_hcd_clear(hcd, PORT_CSC); 2313 2314 retval = isp1760_hcd_clear_and_wait(hcd, 2315 PORT_RESUME, 2000); 2316 if (retval != 0) { 2317 dev_err(hcd->self.controller, 2318 "port %d resume error %d\n", 2319 wIndex + 1, retval); 2320 goto error; 2321 } 2322 } 2323 } 2324 2325 /* whoever resets must GetPortStatus to complete it!! */ 2326 if (isp1760_hcd_is_set(hcd, PORT_RESET) && 2327 time_after_eq(jiffies, priv->reset_done)) { 2328 status |= USB_PORT_STAT_C_RESET << 16; 2329 priv->reset_done = 0; 2330 2331 /* force reset to complete */ 2332 /* REVISIT: some hardware needs 550+ usec to clear 2333 * this bit; seems too long to spin routinely... 2334 */ 2335 retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET, 2336 750); 2337 if (retval != 0) { 2338 dev_err(hcd->self.controller, "port %d reset error %d\n", 2339 wIndex + 1, retval); 2340 goto error; 2341 } 2342 2343 /* see what we found out */ 2344 check_reset_complete(hcd, wIndex); 2345 } 2346 /* 2347 * Even if OWNER is set, there's no harm letting hub_wq 2348 * see the wPortStatus values (they should all be 0 except 2349 * for PORT_POWER anyway). 2350 */ 2351 2352 if (isp1760_hcd_is_set(hcd, PORT_OWNER)) 2353 dev_err(hcd->self.controller, "PORT_OWNER is set\n"); 2354 2355 if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) { 2356 status |= USB_PORT_STAT_CONNECTION; 2357 /* status may be from integrated TT */ 2358 status |= USB_PORT_STAT_HIGH_SPEED; 2359 } 2360 if (isp1760_hcd_is_set(hcd, PORT_PE)) 2361 status |= USB_PORT_STAT_ENABLE; 2362 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) && 2363 isp1760_hcd_is_set(hcd, PORT_RESUME)) 2364 status |= USB_PORT_STAT_SUSPEND; 2365 if (isp1760_hcd_is_set(hcd, PORT_RESET)) 2366 status |= USB_PORT_STAT_RESET; 2367 if (isp1760_hcd_is_set(hcd, PORT_POWER)) 2368 status |= USB_PORT_STAT_POWER; 2369 2370 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 2371 break; 2372 case SetHubFeature: 2373 switch (wValue) { 2374 case C_HUB_LOCAL_POWER: 2375 case C_HUB_OVER_CURRENT: 2376 /* no hub-wide feature/status flags */ 2377 break; 2378 default: 2379 goto error; 2380 } 2381 break; 2382 case SetPortFeature: 2383 wIndex &= 0xff; 2384 if (!wIndex || wIndex > ports) 2385 goto error; 2386 wIndex--; 2387 2388 if (isp1760_hcd_is_set(hcd, PORT_OWNER)) 2389 break; 2390 2391 switch (wValue) { 2392 case USB_PORT_FEAT_ENABLE: 2393 isp1760_hcd_set(hcd, PORT_PE); 2394 break; 2395 2396 case USB_PORT_FEAT_SUSPEND: 2397 if (!isp1760_hcd_is_set(hcd, PORT_PE) || 2398 isp1760_hcd_is_set(hcd, PORT_RESET)) 2399 goto error; 2400 2401 isp1760_hcd_set(hcd, PORT_SUSPEND); 2402 break; 2403 case USB_PORT_FEAT_POWER: 2404 if (isp1760_hcd_ppc_is_set(hcd)) 2405 isp1760_hcd_set(hcd, PORT_POWER); 2406 break; 2407 case USB_PORT_FEAT_RESET: 2408 if (isp1760_hcd_is_set(hcd, PORT_RESUME)) 2409 goto error; 2410 /* line status bits may report this as low speed, 2411 * which can be fine if this root hub has a 2412 * transaction translator built in. 2413 */ 2414 if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) && 2415 !isp1760_hcd_is_set(hcd, PORT_PE)) && 2416 (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) { 2417 isp1760_hcd_set(hcd, PORT_OWNER); 2418 } else { 2419 isp1760_hcd_set(hcd, PORT_RESET); 2420 isp1760_hcd_clear(hcd, PORT_PE); 2421 2422 /* 2423 * caller must wait, then call GetPortStatus 2424 * usb 2.0 spec says 50 ms resets on root 2425 */ 2426 priv->reset_done = jiffies + 2427 msecs_to_jiffies(50); 2428 } 2429 break; 2430 default: 2431 goto error; 2432 } 2433 break; 2434 2435 default: 2436 error: 2437 /* "stall" on error */ 2438 retval = -EPIPE; 2439 } 2440 spin_unlock_irqrestore(&priv->lock, flags); 2441 return retval; 2442 } 2443 2444 static int isp1760_get_frame(struct usb_hcd *hcd) 2445 { 2446 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2447 u32 fr; 2448 2449 fr = isp1760_hcd_read(hcd, HC_FRINDEX); 2450 return (fr >> 3) % priv->periodic_size; 2451 } 2452 2453 static void isp1760_stop(struct usb_hcd *hcd) 2454 { 2455 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2456 2457 del_timer(&errata2_timer); 2458 2459 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, 2460 NULL, 0); 2461 msleep(20); 2462 2463 spin_lock_irq(&priv->lock); 2464 ehci_reset(hcd); 2465 /* Disable IRQ */ 2466 isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); 2467 spin_unlock_irq(&priv->lock); 2468 2469 isp1760_hcd_clear(hcd, FLAG_CF); 2470 } 2471 2472 static void isp1760_shutdown(struct usb_hcd *hcd) 2473 { 2474 isp1760_stop(hcd); 2475 2476 isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); 2477 2478 isp1760_hcd_clear(hcd, CMD_RUN); 2479 } 2480 2481 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, 2482 struct usb_host_endpoint *ep) 2483 { 2484 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2485 struct isp1760_qh *qh = ep->hcpriv; 2486 unsigned long spinflags; 2487 2488 if (!qh) 2489 return; 2490 2491 spin_lock_irqsave(&priv->lock, spinflags); 2492 qh->tt_buffer_dirty = 0; 2493 schedule_ptds(hcd); 2494 spin_unlock_irqrestore(&priv->lock, spinflags); 2495 } 2496 2497 2498 static const struct hc_driver isp1760_hc_driver = { 2499 .description = "isp1760-hcd", 2500 .product_desc = "NXP ISP1760 USB Host Controller", 2501 .hcd_priv_size = sizeof(struct isp1760_hcd *), 2502 .irq = isp1760_irq, 2503 .flags = HCD_MEMORY | HCD_USB2, 2504 .reset = isp1760_hc_setup, 2505 .start = isp1760_run, 2506 .stop = isp1760_stop, 2507 .shutdown = isp1760_shutdown, 2508 .urb_enqueue = isp1760_urb_enqueue, 2509 .urb_dequeue = isp1760_urb_dequeue, 2510 .endpoint_disable = isp1760_endpoint_disable, 2511 .get_frame_number = isp1760_get_frame, 2512 .hub_status_data = isp1760_hub_status_data, 2513 .hub_control = isp1760_hub_control, 2514 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, 2515 }; 2516 2517 int __init isp1760_init_kmem_once(void) 2518 { 2519 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", 2520 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | 2521 SLAB_MEM_SPREAD, NULL); 2522 2523 if (!urb_listitem_cachep) 2524 return -ENOMEM; 2525 2526 qtd_cachep = kmem_cache_create("isp1760_qtd", 2527 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | 2528 SLAB_MEM_SPREAD, NULL); 2529 2530 if (!qtd_cachep) 2531 return -ENOMEM; 2532 2533 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), 2534 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); 2535 2536 if (!qh_cachep) { 2537 kmem_cache_destroy(qtd_cachep); 2538 return -ENOMEM; 2539 } 2540 2541 return 0; 2542 } 2543 2544 void isp1760_deinit_kmem_cache(void) 2545 { 2546 kmem_cache_destroy(qtd_cachep); 2547 kmem_cache_destroy(qh_cachep); 2548 kmem_cache_destroy(urb_listitem_cachep); 2549 } 2550 2551 int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, 2552 int irq, unsigned long irqflags, 2553 struct device *dev) 2554 { 2555 const struct isp1760_memory_layout *mem_layout = priv->memory_layout; 2556 struct usb_hcd *hcd; 2557 int ret; 2558 2559 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); 2560 if (!hcd) 2561 return -ENOMEM; 2562 2563 *(struct isp1760_hcd **)hcd->hcd_priv = priv; 2564 2565 priv->hcd = hcd; 2566 2567 priv->atl_slots = kcalloc(mem_layout->slot_num, 2568 sizeof(struct isp1760_slotinfo), GFP_KERNEL); 2569 if (!priv->atl_slots) { 2570 ret = -ENOMEM; 2571 goto put_hcd; 2572 } 2573 2574 priv->int_slots = kcalloc(mem_layout->slot_num, 2575 sizeof(struct isp1760_slotinfo), GFP_KERNEL); 2576 if (!priv->int_slots) { 2577 ret = -ENOMEM; 2578 goto free_atl_slots; 2579 } 2580 2581 init_memory(priv); 2582 2583 hcd->irq = irq; 2584 hcd->rsrc_start = mem->start; 2585 hcd->rsrc_len = resource_size(mem); 2586 2587 /* This driver doesn't support wakeup requests */ 2588 hcd->cant_recv_wakeups = 1; 2589 2590 ret = usb_add_hcd(hcd, irq, irqflags); 2591 if (ret) 2592 goto free_int_slots; 2593 2594 device_wakeup_enable(hcd->self.controller); 2595 2596 return 0; 2597 2598 free_int_slots: 2599 kfree(priv->int_slots); 2600 free_atl_slots: 2601 kfree(priv->atl_slots); 2602 put_hcd: 2603 usb_put_hcd(hcd); 2604 return ret; 2605 } 2606 2607 void isp1760_hcd_unregister(struct isp1760_hcd *priv) 2608 { 2609 if (!priv->hcd) 2610 return; 2611 2612 usb_remove_hcd(priv->hcd); 2613 usb_put_hcd(priv->hcd); 2614 kfree(priv->atl_slots); 2615 kfree(priv->int_slots); 2616 } 2617