1 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __LINUX_XHCI_HCD_H 25 #define __LINUX_XHCI_HCD_H 26 27 #include <linux/usb.h> 28 #include <linux/timer.h> 29 #include <linux/kernel.h> 30 #include <linux/usb/hcd.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 33 /* Code sharing between pci-quirks and xhci hcd */ 34 #include "xhci-ext-caps.h" 35 #include "pci-quirks.h" 36 37 /* xHCI PCI Configuration Registers */ 38 #define XHCI_SBRN_OFFSET (0x60) 39 40 /* Max number of USB devices for any host controller - limit in section 6.1 */ 41 #define MAX_HC_SLOTS 256 42 /* Section 5.3.3 - MaxPorts */ 43 #define MAX_HC_PORTS 127 44 45 /* 46 * xHCI register interface. 47 * This corresponds to the eXtensible Host Controller Interface (xHCI) 48 * Revision 0.95 specification 49 */ 50 51 /** 52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 53 * @hc_capbase: length of the capabilities register and HC version number 54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 57 * @hcc_params: HCCPARAMS - Capability Parameters 58 * @db_off: DBOFF - Doorbell array offset 59 * @run_regs_off: RTSOFF - Runtime register space offset 60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 61 */ 62 struct xhci_cap_regs { 63 __le32 hc_capbase; 64 __le32 hcs_params1; 65 __le32 hcs_params2; 66 __le32 hcs_params3; 67 __le32 hcc_params; 68 __le32 db_off; 69 __le32 run_regs_off; 70 __le32 hcc_params2; /* xhci 1.1 */ 71 /* Reserved up to (CAPLENGTH - 0x1C) */ 72 }; 73 74 /* hc_capbase bitmasks */ 75 /* bits 7:0 - how long is the Capabilities register */ 76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 77 /* bits 31:16 */ 78 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 79 80 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 81 /* bits 0:7, Max Device Slots */ 82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 83 #define HCS_SLOTS_MASK 0xff 84 /* bits 8:18, Max Interrupters */ 85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 88 89 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 90 /* bits 0:3, frames or uframes that SW needs to queue transactions 91 * ahead of the HW to meet periodic deadlines */ 92 #define HCS_IST(p) (((p) >> 0) & 0xf) 93 /* bits 4:7, max number of Event Ring segments */ 94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 99 100 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 105 106 /* HCCPARAMS - hcc_params - bitmasks */ 107 /* true: HC can use 64-bit address pointers */ 108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 109 /* true: HC can do bandwidth negotiation */ 110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 111 /* true: HC uses 64-byte Device Context structures 112 * FIXME 64-byte context structures aren't supported yet. 113 */ 114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 115 /* true: HC has port power switches */ 116 #define HCC_PPC(p) ((p) & (1 << 3)) 117 /* true: HC has port indicators */ 118 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 119 /* true: HC has Light HC Reset Capability */ 120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 121 /* true: HC supports latency tolerance messaging */ 122 #define HCC_LTC(p) ((p) & (1 << 6)) 123 /* true: no secondary Stream ID Support */ 124 #define HCC_NSS(p) ((p) & (1 << 7)) 125 /* true: HC supports Stopped - Short Packet */ 126 #define HCC_SPC(p) ((p) & (1 << 9)) 127 /* true: HC has Contiguous Frame ID Capability */ 128 #define HCC_CFC(p) ((p) & (1 << 11)) 129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 133 134 /* db_off bitmask - bits 0:1 reserved */ 135 #define DBOFF_MASK (~0x3) 136 137 /* run_regs_off bitmask - bits 0:4 reserved */ 138 #define RTSOFF_MASK (~0x1f) 139 140 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 141 /* true: HC supports U3 entry Capability */ 142 #define HCC2_U3C(p) ((p) & (1 << 0)) 143 /* true: HC supports Configure endpoint command Max exit latency too large */ 144 #define HCC2_CMC(p) ((p) & (1 << 1)) 145 /* true: HC supports Force Save context Capability */ 146 #define HCC2_FSC(p) ((p) & (1 << 2)) 147 /* true: HC supports Compliance Transition Capability */ 148 #define HCC2_CTC(p) ((p) & (1 << 3)) 149 /* true: HC support Large ESIT payload Capability > 48k */ 150 #define HCC2_LEC(p) ((p) & (1 << 4)) 151 /* true: HC support Configuration Information Capability */ 152 #define HCC2_CIC(p) ((p) & (1 << 5)) 153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 154 #define HCC2_ETC(p) ((p) & (1 << 6)) 155 156 /* Number of registers per port */ 157 #define NUM_PORT_REGS 4 158 159 #define PORTSC 0 160 #define PORTPMSC 1 161 #define PORTLI 2 162 #define PORTHLPMC 3 163 164 /** 165 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 166 * @command: USBCMD - xHC command register 167 * @status: USBSTS - xHC status register 168 * @page_size: This indicates the page size that the host controller 169 * supports. If bit n is set, the HC supports a page size 170 * of 2^(n+12), up to a 128MB page size. 171 * 4K is the minimum page size. 172 * @cmd_ring: CRP - 64-bit Command Ring Pointer 173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 174 * @config_reg: CONFIG - Configure Register 175 * @port_status_base: PORTSCn - base address for Port Status and Control 176 * Each port has a Port Status and Control register, 177 * followed by a Port Power Management Status and Control 178 * register, a Port Link Info register, and a reserved 179 * register. 180 * @port_power_base: PORTPMSCn - base address for 181 * Port Power Management Status and Control 182 * @port_link_base: PORTLIn - base address for Port Link Info (current 183 * Link PM state and control) for USB 2.1 and USB 3.0 184 * devices. 185 */ 186 struct xhci_op_regs { 187 __le32 command; 188 __le32 status; 189 __le32 page_size; 190 __le32 reserved1; 191 __le32 reserved2; 192 __le32 dev_notification; 193 __le64 cmd_ring; 194 /* rsvd: offset 0x20-2F */ 195 __le32 reserved3[4]; 196 __le64 dcbaa_ptr; 197 __le32 config_reg; 198 /* rsvd: offset 0x3C-3FF */ 199 __le32 reserved4[241]; 200 /* port 1 registers, which serve as a base address for other ports */ 201 __le32 port_status_base; 202 __le32 port_power_base; 203 __le32 port_link_base; 204 __le32 reserved5; 205 /* registers for ports 2-255 */ 206 __le32 reserved6[NUM_PORT_REGS*254]; 207 }; 208 209 /* USBCMD - USB command - command bitmasks */ 210 /* start/stop HC execution - do not write unless HC is halted*/ 211 #define CMD_RUN XHCI_CMD_RUN 212 /* Reset HC - resets internal HC state machine and all registers (except 213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 214 * The xHCI driver must reinitialize the xHC after setting this bit. 215 */ 216 #define CMD_RESET (1 << 1) 217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 218 #define CMD_EIE XHCI_CMD_EIE 219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 220 #define CMD_HSEIE XHCI_CMD_HSEIE 221 /* bits 4:6 are reserved (and should be preserved on writes). */ 222 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 223 #define CMD_LRESET (1 << 7) 224 /* host controller save/restore state. */ 225 #define CMD_CSS (1 << 8) 226 #define CMD_CRS (1 << 9) 227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 228 #define CMD_EWE XHCI_CMD_EWE 229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 231 * '0' means the xHC can power it off if all ports are in the disconnect, 232 * disabled, or powered-off state. 233 */ 234 #define CMD_PM_INDEX (1 << 11) 235 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 236 #define CMD_ETE (1 << 14) 237 /* bits 15:31 are reserved (and should be preserved on writes). */ 238 239 /* IMAN - Interrupt Management Register */ 240 #define IMAN_IE (1 << 1) 241 #define IMAN_IP (1 << 0) 242 243 /* USBSTS - USB status - status bitmasks */ 244 /* HC not running - set to 1 when run/stop bit is cleared. */ 245 #define STS_HALT XHCI_STS_HALT 246 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 247 #define STS_FATAL (1 << 2) 248 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 249 #define STS_EINT (1 << 3) 250 /* port change detect */ 251 #define STS_PORT (1 << 4) 252 /* bits 5:7 reserved and zeroed */ 253 /* save state status - '1' means xHC is saving state */ 254 #define STS_SAVE (1 << 8) 255 /* restore state status - '1' means xHC is restoring state */ 256 #define STS_RESTORE (1 << 9) 257 /* true: save or restore error */ 258 #define STS_SRE (1 << 10) 259 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 260 #define STS_CNR XHCI_STS_CNR 261 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 262 #define STS_HCE (1 << 12) 263 /* bits 13:31 reserved and should be preserved */ 264 265 /* 266 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 267 * Generate a device notification event when the HC sees a transaction with a 268 * notification type that matches a bit set in this bit field. 269 */ 270 #define DEV_NOTE_MASK (0xffff) 271 #define ENABLE_DEV_NOTE(x) (1 << (x)) 272 /* Most of the device notification types should only be used for debug. 273 * SW does need to pay attention to function wake notifications. 274 */ 275 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 276 277 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 278 /* bit 0 is the command ring cycle state */ 279 /* stop ring operation after completion of the currently executing command */ 280 #define CMD_RING_PAUSE (1 << 1) 281 /* stop ring immediately - abort the currently executing command */ 282 #define CMD_RING_ABORT (1 << 2) 283 /* true: command ring is running */ 284 #define CMD_RING_RUNNING (1 << 3) 285 /* bits 4:5 reserved and should be preserved */ 286 /* Command Ring pointer - bit mask for the lower 32 bits. */ 287 #define CMD_RING_RSVD_BITS (0x3f) 288 289 /* CONFIG - Configure Register - config_reg bitmasks */ 290 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 291 #define MAX_DEVS(p) ((p) & 0xff) 292 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 293 #define CONFIG_U3E (1 << 8) 294 /* bit 9: Configuration Information Enable, xhci 1.1 */ 295 #define CONFIG_CIE (1 << 9) 296 /* bits 10:31 - reserved and should be preserved */ 297 298 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 299 /* true: device connected */ 300 #define PORT_CONNECT (1 << 0) 301 /* true: port enabled */ 302 #define PORT_PE (1 << 1) 303 /* bit 2 reserved and zeroed */ 304 /* true: port has an over-current condition */ 305 #define PORT_OC (1 << 3) 306 /* true: port reset signaling asserted */ 307 #define PORT_RESET (1 << 4) 308 /* Port Link State - bits 5:8 309 * A read gives the current link PM state of the port, 310 * a write with Link State Write Strobe set sets the link state. 311 */ 312 #define PORT_PLS_MASK (0xf << 5) 313 #define XDEV_U0 (0x0 << 5) 314 #define XDEV_U2 (0x2 << 5) 315 #define XDEV_U3 (0x3 << 5) 316 #define XDEV_INACTIVE (0x6 << 5) 317 #define XDEV_RESUME (0xf << 5) 318 /* true: port has power (see HCC_PPC) */ 319 #define PORT_POWER (1 << 9) 320 /* bits 10:13 indicate device speed: 321 * 0 - undefined speed - port hasn't be initialized by a reset yet 322 * 1 - full speed 323 * 2 - low speed 324 * 3 - high speed 325 * 4 - super speed 326 * 5-15 reserved 327 */ 328 #define DEV_SPEED_MASK (0xf << 10) 329 #define XDEV_FS (0x1 << 10) 330 #define XDEV_LS (0x2 << 10) 331 #define XDEV_HS (0x3 << 10) 332 #define XDEV_SS (0x4 << 10) 333 #define XDEV_SSP (0x5 << 10) 334 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 335 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 336 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 337 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 338 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 339 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 340 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 341 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 342 343 /* Bits 20:23 in the Slot Context are the speed for the device */ 344 #define SLOT_SPEED_FS (XDEV_FS << 10) 345 #define SLOT_SPEED_LS (XDEV_LS << 10) 346 #define SLOT_SPEED_HS (XDEV_HS << 10) 347 #define SLOT_SPEED_SS (XDEV_SS << 10) 348 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 349 /* Port Indicator Control */ 350 #define PORT_LED_OFF (0 << 14) 351 #define PORT_LED_AMBER (1 << 14) 352 #define PORT_LED_GREEN (2 << 14) 353 #define PORT_LED_MASK (3 << 14) 354 /* Port Link State Write Strobe - set this when changing link state */ 355 #define PORT_LINK_STROBE (1 << 16) 356 /* true: connect status change */ 357 #define PORT_CSC (1 << 17) 358 /* true: port enable change */ 359 #define PORT_PEC (1 << 18) 360 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 361 * into an enabled state, and the device into the default state. A "warm" reset 362 * also resets the link, forcing the device through the link training sequence. 363 * SW can also look at the Port Reset register to see when warm reset is done. 364 */ 365 #define PORT_WRC (1 << 19) 366 /* true: over-current change */ 367 #define PORT_OCC (1 << 20) 368 /* true: reset change - 1 to 0 transition of PORT_RESET */ 369 #define PORT_RC (1 << 21) 370 /* port link status change - set on some port link state transitions: 371 * Transition Reason 372 * ------------------------------------------------------------------------------ 373 * - U3 to Resume Wakeup signaling from a device 374 * - Resume to Recovery to U0 USB 3.0 device resume 375 * - Resume to U0 USB 2.0 device resume 376 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 377 * - U3 to U0 Software resume of USB 2.0 device complete 378 * - U2 to U0 L1 resume of USB 2.1 device complete 379 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 380 * - U0 to disabled L1 entry error with USB 2.1 device 381 * - Any state to inactive Error on USB 3.0 port 382 */ 383 #define PORT_PLC (1 << 22) 384 /* port configure error change - port failed to configure its link partner */ 385 #define PORT_CEC (1 << 23) 386 /* Cold Attach Status - xHC can set this bit to report device attached during 387 * Sx state. Warm port reset should be perfomed to clear this bit and move port 388 * to connected state. 389 */ 390 #define PORT_CAS (1 << 24) 391 /* wake on connect (enable) */ 392 #define PORT_WKCONN_E (1 << 25) 393 /* wake on disconnect (enable) */ 394 #define PORT_WKDISC_E (1 << 26) 395 /* wake on over-current (enable) */ 396 #define PORT_WKOC_E (1 << 27) 397 /* bits 28:29 reserved */ 398 /* true: device is non-removable - for USB 3.0 roothub emulation */ 399 #define PORT_DEV_REMOVE (1 << 30) 400 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 401 #define PORT_WR (1 << 31) 402 403 /* We mark duplicate entries with -1 */ 404 #define DUPLICATE_ENTRY ((u8)(-1)) 405 406 /* Port Power Management Status and Control - port_power_base bitmasks */ 407 /* Inactivity timer value for transitions into U1, in microseconds. 408 * Timeout can be up to 127us. 0xFF means an infinite timeout. 409 */ 410 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 411 #define PORT_U1_TIMEOUT_MASK 0xff 412 /* Inactivity timer value for transitions into U2 */ 413 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 414 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 415 /* Bits 24:31 for port testing */ 416 417 /* USB2 Protocol PORTSPMSC */ 418 #define PORT_L1S_MASK 7 419 #define PORT_L1S_SUCCESS 1 420 #define PORT_RWE (1 << 3) 421 #define PORT_HIRD(p) (((p) & 0xf) << 4) 422 #define PORT_HIRD_MASK (0xf << 4) 423 #define PORT_L1DS_MASK (0xff << 8) 424 #define PORT_L1DS(p) (((p) & 0xff) << 8) 425 #define PORT_HLE (1 << 16) 426 427 /* USB3 Protocol PORTLI Port Link Information */ 428 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 429 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 430 431 /* USB2 Protocol PORTHLPMC */ 432 #define PORT_HIRDM(p)((p) & 3) 433 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 434 #define PORT_BESLD(p)(((p) & 0xf) << 10) 435 436 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 437 #define XHCI_L1_TIMEOUT 512 438 439 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 440 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 441 * by other operating systems. 442 * 443 * XHCI 1.0 errata 8/14/12 Table 13 notes: 444 * "Software should choose xHC BESL/BESLD field values that do not violate a 445 * device's resume latency requirements, 446 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 447 * or not program values < '4' if BLC = '0' and a BESL device is attached. 448 */ 449 #define XHCI_DEFAULT_BESL 4 450 451 /** 452 * struct xhci_intr_reg - Interrupt Register Set 453 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 454 * interrupts and check for pending interrupts. 455 * @irq_control: IMOD - Interrupt Moderation Register. 456 * Used to throttle interrupts. 457 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 458 * @erst_base: ERST base address. 459 * @erst_dequeue: Event ring dequeue pointer. 460 * 461 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 462 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 463 * multiple segments of the same size. The HC places events on the ring and 464 * "updates the Cycle bit in the TRBs to indicate to software the current 465 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 466 * updates the dequeue pointer. 467 */ 468 struct xhci_intr_reg { 469 __le32 irq_pending; 470 __le32 irq_control; 471 __le32 erst_size; 472 __le32 rsvd; 473 __le64 erst_base; 474 __le64 erst_dequeue; 475 }; 476 477 /* irq_pending bitmasks */ 478 #define ER_IRQ_PENDING(p) ((p) & 0x1) 479 /* bits 2:31 need to be preserved */ 480 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 481 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 482 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 483 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 484 485 /* irq_control bitmasks */ 486 /* Minimum interval between interrupts (in 250ns intervals). The interval 487 * between interrupts will be longer if there are no events on the event ring. 488 * Default is 4000 (1 ms). 489 */ 490 #define ER_IRQ_INTERVAL_MASK (0xffff) 491 /* Counter used to count down the time to the next interrupt - HW use only */ 492 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 493 494 /* erst_size bitmasks */ 495 /* Preserve bits 16:31 of erst_size */ 496 #define ERST_SIZE_MASK (0xffff << 16) 497 498 /* erst_dequeue bitmasks */ 499 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 500 * where the current dequeue pointer lies. This is an optional HW hint. 501 */ 502 #define ERST_DESI_MASK (0x7) 503 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 504 * a work queue (or delayed service routine)? 505 */ 506 #define ERST_EHB (1 << 3) 507 #define ERST_PTR_MASK (0xf) 508 509 /** 510 * struct xhci_run_regs 511 * @microframe_index: 512 * MFINDEX - current microframe number 513 * 514 * Section 5.5 Host Controller Runtime Registers: 515 * "Software should read and write these registers using only Dword (32 bit) 516 * or larger accesses" 517 */ 518 struct xhci_run_regs { 519 __le32 microframe_index; 520 __le32 rsvd[7]; 521 struct xhci_intr_reg ir_set[128]; 522 }; 523 524 /** 525 * struct doorbell_array 526 * 527 * Bits 0 - 7: Endpoint target 528 * Bits 8 - 15: RsvdZ 529 * Bits 16 - 31: Stream ID 530 * 531 * Section 5.6 532 */ 533 struct xhci_doorbell_array { 534 __le32 doorbell[256]; 535 }; 536 537 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 538 #define DB_VALUE_HOST 0x00000000 539 540 /** 541 * struct xhci_protocol_caps 542 * @revision: major revision, minor revision, capability ID, 543 * and next capability pointer. 544 * @name_string: Four ASCII characters to say which spec this xHC 545 * follows, typically "USB ". 546 * @port_info: Port offset, count, and protocol-defined information. 547 */ 548 struct xhci_protocol_caps { 549 u32 revision; 550 u32 name_string; 551 u32 port_info; 552 }; 553 554 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 555 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 556 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 557 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 558 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 559 560 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 561 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 562 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 563 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 564 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 565 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 566 567 #define PLT_MASK (0x03 << 6) 568 #define PLT_SYM (0x00 << 6) 569 #define PLT_ASYM_RX (0x02 << 6) 570 #define PLT_ASYM_TX (0x03 << 6) 571 572 /** 573 * struct xhci_container_ctx 574 * @type: Type of context. Used to calculated offsets to contained contexts. 575 * @size: Size of the context data 576 * @bytes: The raw context data given to HW 577 * @dma: dma address of the bytes 578 * 579 * Represents either a Device or Input context. Holds a pointer to the raw 580 * memory used for the context (bytes) and dma address of it (dma). 581 */ 582 struct xhci_container_ctx { 583 unsigned type; 584 #define XHCI_CTX_TYPE_DEVICE 0x1 585 #define XHCI_CTX_TYPE_INPUT 0x2 586 587 int size; 588 589 u8 *bytes; 590 dma_addr_t dma; 591 }; 592 593 /** 594 * struct xhci_slot_ctx 595 * @dev_info: Route string, device speed, hub info, and last valid endpoint 596 * @dev_info2: Max exit latency for device number, root hub port number 597 * @tt_info: tt_info is used to construct split transaction tokens 598 * @dev_state: slot state and device address 599 * 600 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 601 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 602 * reserved at the end of the slot context for HC internal use. 603 */ 604 struct xhci_slot_ctx { 605 __le32 dev_info; 606 __le32 dev_info2; 607 __le32 tt_info; 608 __le32 dev_state; 609 /* offset 0x10 to 0x1f reserved for HC internal use */ 610 __le32 reserved[4]; 611 }; 612 613 /* dev_info bitmasks */ 614 /* Route String - 0:19 */ 615 #define ROUTE_STRING_MASK (0xfffff) 616 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 617 #define DEV_SPEED (0xf << 20) 618 /* bit 24 reserved */ 619 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 620 #define DEV_MTT (0x1 << 25) 621 /* Set if the device is a hub - bit 26 */ 622 #define DEV_HUB (0x1 << 26) 623 /* Index of the last valid endpoint context in this device context - 27:31 */ 624 #define LAST_CTX_MASK (0x1f << 27) 625 #define LAST_CTX(p) ((p) << 27) 626 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 627 #define SLOT_FLAG (1 << 0) 628 #define EP0_FLAG (1 << 1) 629 630 /* dev_info2 bitmasks */ 631 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 632 #define MAX_EXIT (0xffff) 633 /* Root hub port number that is needed to access the USB device */ 634 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 635 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 636 /* Maximum number of ports under a hub device */ 637 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 638 639 /* tt_info bitmasks */ 640 /* 641 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 642 * The Slot ID of the hub that isolates the high speed signaling from 643 * this low or full-speed device. '0' if attached to root hub port. 644 */ 645 #define TT_SLOT (0xff) 646 /* 647 * The number of the downstream facing port of the high-speed hub 648 * '0' if the device is not low or full speed. 649 */ 650 #define TT_PORT (0xff << 8) 651 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 652 653 /* dev_state bitmasks */ 654 /* USB device address - assigned by the HC */ 655 #define DEV_ADDR_MASK (0xff) 656 /* bits 8:26 reserved */ 657 /* Slot state */ 658 #define SLOT_STATE (0x1f << 27) 659 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 660 661 #define SLOT_STATE_DISABLED 0 662 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 663 #define SLOT_STATE_DEFAULT 1 664 #define SLOT_STATE_ADDRESSED 2 665 #define SLOT_STATE_CONFIGURED 3 666 667 /** 668 * struct xhci_ep_ctx 669 * @ep_info: endpoint state, streams, mult, and interval information. 670 * @ep_info2: information on endpoint type, max packet size, max burst size, 671 * error count, and whether the HC will force an event for all 672 * transactions. 673 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 674 * defines one stream, this points to the endpoint transfer ring. 675 * Otherwise, it points to a stream context array, which has a 676 * ring pointer for each flow. 677 * @tx_info: 678 * Average TRB lengths for the endpoint ring and 679 * max payload within an Endpoint Service Interval Time (ESIT). 680 * 681 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 682 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 683 * reserved at the end of the endpoint context for HC internal use. 684 */ 685 struct xhci_ep_ctx { 686 __le32 ep_info; 687 __le32 ep_info2; 688 __le64 deq; 689 __le32 tx_info; 690 /* offset 0x14 - 0x1f reserved for HC internal use */ 691 __le32 reserved[3]; 692 }; 693 694 /* ep_info bitmasks */ 695 /* 696 * Endpoint State - bits 0:2 697 * 0 - disabled 698 * 1 - running 699 * 2 - halted due to halt condition - ok to manipulate endpoint ring 700 * 3 - stopped 701 * 4 - TRB error 702 * 5-7 - reserved 703 */ 704 #define EP_STATE_MASK (0xf) 705 #define EP_STATE_DISABLED 0 706 #define EP_STATE_RUNNING 1 707 #define EP_STATE_HALTED 2 708 #define EP_STATE_STOPPED 3 709 #define EP_STATE_ERROR 4 710 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 711 #define EP_MULT(p) (((p) & 0x3) << 8) 712 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 713 /* bits 10:14 are Max Primary Streams */ 714 /* bit 15 is Linear Stream Array */ 715 /* Interval - period between requests to an endpoint - 125u increments. */ 716 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 717 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 718 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 719 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 720 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 721 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 722 #define EP_HAS_LSA (1 << 15) 723 724 /* ep_info2 bitmasks */ 725 /* 726 * Force Event - generate transfer events for all TRBs for this endpoint 727 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 728 */ 729 #define FORCE_EVENT (0x1) 730 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 731 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 732 #define EP_TYPE(p) ((p) << 3) 733 #define ISOC_OUT_EP 1 734 #define BULK_OUT_EP 2 735 #define INT_OUT_EP 3 736 #define CTRL_EP 4 737 #define ISOC_IN_EP 5 738 #define BULK_IN_EP 6 739 #define INT_IN_EP 7 740 /* bit 6 reserved */ 741 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 742 #define MAX_BURST(p) (((p)&0xff) << 8) 743 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 744 #define MAX_PACKET(p) (((p)&0xffff) << 16) 745 #define MAX_PACKET_MASK (0xffff << 16) 746 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 747 748 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 749 * USB2.0 spec 9.6.6. 750 */ 751 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 752 753 /* tx_info bitmasks */ 754 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 755 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 756 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 757 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 758 759 /* deq bitmasks */ 760 #define EP_CTX_CYCLE_MASK (1 << 0) 761 #define SCTX_DEQ_MASK (~0xfL) 762 763 764 /** 765 * struct xhci_input_control_context 766 * Input control context; see section 6.2.5. 767 * 768 * @drop_context: set the bit of the endpoint context you want to disable 769 * @add_context: set the bit of the endpoint context you want to enable 770 */ 771 struct xhci_input_control_ctx { 772 __le32 drop_flags; 773 __le32 add_flags; 774 __le32 rsvd2[6]; 775 }; 776 777 #define EP_IS_ADDED(ctrl_ctx, i) \ 778 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 779 #define EP_IS_DROPPED(ctrl_ctx, i) \ 780 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 781 782 /* Represents everything that is needed to issue a command on the command ring. 783 * It's useful to pre-allocate these for commands that cannot fail due to 784 * out-of-memory errors, like freeing streams. 785 */ 786 struct xhci_command { 787 /* Input context for changing device state */ 788 struct xhci_container_ctx *in_ctx; 789 u32 status; 790 /* If completion is null, no one is waiting on this command 791 * and the structure can be freed after the command completes. 792 */ 793 struct completion *completion; 794 union xhci_trb *command_trb; 795 struct list_head cmd_list; 796 }; 797 798 /* drop context bitmasks */ 799 #define DROP_EP(x) (0x1 << x) 800 /* add context bitmasks */ 801 #define ADD_EP(x) (0x1 << x) 802 803 struct xhci_stream_ctx { 804 /* 64-bit stream ring address, cycle state, and stream type */ 805 __le64 stream_ring; 806 /* offset 0x14 - 0x1f reserved for HC internal use */ 807 __le32 reserved[2]; 808 }; 809 810 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 811 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 812 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 813 #define SCT_SEC_TR 0 814 /* Primary stream array type, dequeue pointer is to a transfer ring */ 815 #define SCT_PRI_TR 1 816 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 817 #define SCT_SSA_8 2 818 #define SCT_SSA_16 3 819 #define SCT_SSA_32 4 820 #define SCT_SSA_64 5 821 #define SCT_SSA_128 6 822 #define SCT_SSA_256 7 823 824 /* Assume no secondary streams for now */ 825 struct xhci_stream_info { 826 struct xhci_ring **stream_rings; 827 /* Number of streams, including stream 0 (which drivers can't use) */ 828 unsigned int num_streams; 829 /* The stream context array may be bigger than 830 * the number of streams the driver asked for 831 */ 832 struct xhci_stream_ctx *stream_ctx_array; 833 unsigned int num_stream_ctxs; 834 dma_addr_t ctx_array_dma; 835 /* For mapping physical TRB addresses to segments in stream rings */ 836 struct radix_tree_root trb_address_map; 837 struct xhci_command *free_streams_command; 838 }; 839 840 #define SMALL_STREAM_ARRAY_SIZE 256 841 #define MEDIUM_STREAM_ARRAY_SIZE 1024 842 843 /* Some Intel xHCI host controllers need software to keep track of the bus 844 * bandwidth. Keep track of endpoint info here. Each root port is allocated 845 * the full bus bandwidth. We must also treat TTs (including each port under a 846 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 847 * (DMI) also limits the total bandwidth (across all domains) that can be used. 848 */ 849 struct xhci_bw_info { 850 /* ep_interval is zero-based */ 851 unsigned int ep_interval; 852 /* mult and num_packets are one-based */ 853 unsigned int mult; 854 unsigned int num_packets; 855 unsigned int max_packet_size; 856 unsigned int max_esit_payload; 857 unsigned int type; 858 }; 859 860 /* "Block" sizes in bytes the hardware uses for different device speeds. 861 * The logic in this part of the hardware limits the number of bits the hardware 862 * can use, so must represent bandwidth in a less precise manner to mimic what 863 * the scheduler hardware computes. 864 */ 865 #define FS_BLOCK 1 866 #define HS_BLOCK 4 867 #define SS_BLOCK 16 868 #define DMI_BLOCK 32 869 870 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 871 * with each byte transferred. SuperSpeed devices have an initial overhead to 872 * set up bursts. These are in blocks, see above. LS overhead has already been 873 * translated into FS blocks. 874 */ 875 #define DMI_OVERHEAD 8 876 #define DMI_OVERHEAD_BURST 4 877 #define SS_OVERHEAD 8 878 #define SS_OVERHEAD_BURST 32 879 #define HS_OVERHEAD 26 880 #define FS_OVERHEAD 20 881 #define LS_OVERHEAD 128 882 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 883 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 884 * of overhead associated with split transfers crossing microframe boundaries. 885 * 31 blocks is pure protocol overhead. 886 */ 887 #define TT_HS_OVERHEAD (31 + 94) 888 #define TT_DMI_OVERHEAD (25 + 12) 889 890 /* Bandwidth limits in blocks */ 891 #define FS_BW_LIMIT 1285 892 #define TT_BW_LIMIT 1320 893 #define HS_BW_LIMIT 1607 894 #define SS_BW_LIMIT_IN 3906 895 #define DMI_BW_LIMIT_IN 3906 896 #define SS_BW_LIMIT_OUT 3906 897 #define DMI_BW_LIMIT_OUT 3906 898 899 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 900 #define FS_BW_RESERVED 10 901 #define HS_BW_RESERVED 20 902 #define SS_BW_RESERVED 10 903 904 struct xhci_virt_ep { 905 struct xhci_ring *ring; 906 /* Related to endpoints that are configured to use stream IDs only */ 907 struct xhci_stream_info *stream_info; 908 /* Temporary storage in case the configure endpoint command fails and we 909 * have to restore the device state to the previous state 910 */ 911 struct xhci_ring *new_ring; 912 unsigned int ep_state; 913 #define SET_DEQ_PENDING (1 << 0) 914 #define EP_HALTED (1 << 1) /* For stall handling */ 915 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 916 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 917 #define EP_GETTING_STREAMS (1 << 3) 918 #define EP_HAS_STREAMS (1 << 4) 919 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 920 #define EP_GETTING_NO_STREAMS (1 << 5) 921 /* ---- Related to URB cancellation ---- */ 922 struct list_head cancelled_td_list; 923 struct xhci_td *stopped_td; 924 unsigned int stopped_stream; 925 /* Watchdog timer for stop endpoint command to cancel URBs */ 926 struct timer_list stop_cmd_timer; 927 int stop_cmds_pending; 928 struct xhci_hcd *xhci; 929 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 930 * command. We'll need to update the ring's dequeue segment and dequeue 931 * pointer after the command completes. 932 */ 933 struct xhci_segment *queued_deq_seg; 934 union xhci_trb *queued_deq_ptr; 935 /* 936 * Sometimes the xHC can not process isochronous endpoint ring quickly 937 * enough, and it will miss some isoc tds on the ring and generate 938 * a Missed Service Error Event. 939 * Set skip flag when receive a Missed Service Error Event and 940 * process the missed tds on the endpoint ring. 941 */ 942 bool skip; 943 /* Bandwidth checking storage */ 944 struct xhci_bw_info bw_info; 945 struct list_head bw_endpoint_list; 946 /* Isoch Frame ID checking storage */ 947 int next_frame_id; 948 /* Use new Isoch TRB layout needed for extended TBC support */ 949 bool use_extended_tbc; 950 }; 951 952 enum xhci_overhead_type { 953 LS_OVERHEAD_TYPE = 0, 954 FS_OVERHEAD_TYPE, 955 HS_OVERHEAD_TYPE, 956 }; 957 958 struct xhci_interval_bw { 959 unsigned int num_packets; 960 /* Sorted by max packet size. 961 * Head of the list is the greatest max packet size. 962 */ 963 struct list_head endpoints; 964 /* How many endpoints of each speed are present. */ 965 unsigned int overhead[3]; 966 }; 967 968 #define XHCI_MAX_INTERVAL 16 969 970 struct xhci_interval_bw_table { 971 unsigned int interval0_esit_payload; 972 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 973 /* Includes reserved bandwidth for async endpoints */ 974 unsigned int bw_used; 975 unsigned int ss_bw_in; 976 unsigned int ss_bw_out; 977 }; 978 979 980 struct xhci_virt_device { 981 struct usb_device *udev; 982 /* 983 * Commands to the hardware are passed an "input context" that 984 * tells the hardware what to change in its data structures. 985 * The hardware will return changes in an "output context" that 986 * software must allocate for the hardware. We need to keep 987 * track of input and output contexts separately because 988 * these commands might fail and we don't trust the hardware. 989 */ 990 struct xhci_container_ctx *out_ctx; 991 /* Used for addressing devices and configuration changes */ 992 struct xhci_container_ctx *in_ctx; 993 /* Rings saved to ensure old alt settings can be re-instated */ 994 struct xhci_ring **ring_cache; 995 int num_rings_cached; 996 #define XHCI_MAX_RINGS_CACHED 31 997 struct xhci_virt_ep eps[31]; 998 struct completion cmd_completion; 999 u8 fake_port; 1000 u8 real_port; 1001 struct xhci_interval_bw_table *bw_table; 1002 struct xhci_tt_bw_info *tt_info; 1003 /* The current max exit latency for the enabled USB3 link states. */ 1004 u16 current_mel; 1005 }; 1006 1007 /* 1008 * For each roothub, keep track of the bandwidth information for each periodic 1009 * interval. 1010 * 1011 * If a high speed hub is attached to the roothub, each TT associated with that 1012 * hub is a separate bandwidth domain. The interval information for the 1013 * endpoints on the devices under that TT will appear in the TT structure. 1014 */ 1015 struct xhci_root_port_bw_info { 1016 struct list_head tts; 1017 unsigned int num_active_tts; 1018 struct xhci_interval_bw_table bw_table; 1019 }; 1020 1021 struct xhci_tt_bw_info { 1022 struct list_head tt_list; 1023 int slot_id; 1024 int ttport; 1025 struct xhci_interval_bw_table bw_table; 1026 int active_eps; 1027 }; 1028 1029 1030 /** 1031 * struct xhci_device_context_array 1032 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1033 */ 1034 struct xhci_device_context_array { 1035 /* 64-bit device addresses; we only write 32-bit addresses */ 1036 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1037 /* private xHCD pointers */ 1038 dma_addr_t dma; 1039 }; 1040 /* TODO: write function to set the 64-bit device DMA address */ 1041 /* 1042 * TODO: change this to be dynamically sized at HC mem init time since the HC 1043 * might not be able to handle the maximum number of devices possible. 1044 */ 1045 1046 1047 struct xhci_transfer_event { 1048 /* 64-bit buffer address, or immediate data */ 1049 __le64 buffer; 1050 __le32 transfer_len; 1051 /* This field is interpreted differently based on the type of TRB */ 1052 __le32 flags; 1053 }; 1054 1055 /* Transfer event TRB length bit mask */ 1056 /* bits 0:23 */ 1057 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1058 1059 /** Transfer Event bit fields **/ 1060 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1061 1062 /* Completion Code - only applicable for some types of TRBs */ 1063 #define COMP_CODE_MASK (0xff << 24) 1064 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1065 #define COMP_SUCCESS 1 1066 /* Data Buffer Error */ 1067 #define COMP_DB_ERR 2 1068 /* Babble Detected Error */ 1069 #define COMP_BABBLE 3 1070 /* USB Transaction Error */ 1071 #define COMP_TX_ERR 4 1072 /* TRB Error - some TRB field is invalid */ 1073 #define COMP_TRB_ERR 5 1074 /* Stall Error - USB device is stalled */ 1075 #define COMP_STALL 6 1076 /* Resource Error - HC doesn't have memory for that device configuration */ 1077 #define COMP_ENOMEM 7 1078 /* Bandwidth Error - not enough room in schedule for this dev config */ 1079 #define COMP_BW_ERR 8 1080 /* No Slots Available Error - HC ran out of device slots */ 1081 #define COMP_ENOSLOTS 9 1082 /* Invalid Stream Type Error */ 1083 #define COMP_STREAM_ERR 10 1084 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 1085 #define COMP_EBADSLT 11 1086 /* Endpoint Not Enabled Error */ 1087 #define COMP_EBADEP 12 1088 /* Short Packet */ 1089 #define COMP_SHORT_TX 13 1090 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 1091 #define COMP_UNDERRUN 14 1092 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 1093 #define COMP_OVERRUN 15 1094 /* Virtual Function Event Ring Full Error */ 1095 #define COMP_VF_FULL 16 1096 /* Parameter Error - Context parameter is invalid */ 1097 #define COMP_EINVAL 17 1098 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 1099 #define COMP_BW_OVER 18 1100 /* Context State Error - illegal context state transition requested */ 1101 #define COMP_CTX_STATE 19 1102 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 1103 #define COMP_PING_ERR 20 1104 /* Event Ring is full */ 1105 #define COMP_ER_FULL 21 1106 /* Incompatible Device Error */ 1107 #define COMP_DEV_ERR 22 1108 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 1109 #define COMP_MISSED_INT 23 1110 /* Successfully stopped command ring */ 1111 #define COMP_CMD_STOP 24 1112 /* Successfully aborted current command and stopped command ring */ 1113 #define COMP_CMD_ABORT 25 1114 /* Stopped - transfer was terminated by a stop endpoint command */ 1115 #define COMP_STOP 26 1116 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 1117 #define COMP_STOP_INVAL 27 1118 /* Same as COMP_EP_STOPPED, but a short packet detected */ 1119 #define COMP_STOP_SHORT 28 1120 /* Max Exit Latency Too Large Error */ 1121 #define COMP_MEL_ERR 29 1122 /* TRB type 30 reserved */ 1123 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 1124 #define COMP_BUFF_OVER 31 1125 /* Event Lost Error - xHC has an "internal event overrun condition" */ 1126 #define COMP_ISSUES 32 1127 /* Undefined Error - reported when other error codes don't apply */ 1128 #define COMP_UNKNOWN 33 1129 /* Invalid Stream ID Error */ 1130 #define COMP_STRID_ERR 34 1131 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 1132 #define COMP_2ND_BW_ERR 35 1133 /* Split Transaction Error */ 1134 #define COMP_SPLIT_ERR 36 1135 1136 struct xhci_link_trb { 1137 /* 64-bit segment pointer*/ 1138 __le64 segment_ptr; 1139 __le32 intr_target; 1140 __le32 control; 1141 }; 1142 1143 /* control bitfields */ 1144 #define LINK_TOGGLE (0x1<<1) 1145 1146 /* Command completion event TRB */ 1147 struct xhci_event_cmd { 1148 /* Pointer to command TRB, or the value passed by the event data trb */ 1149 __le64 cmd_trb; 1150 __le32 status; 1151 __le32 flags; 1152 }; 1153 1154 /* flags bitmasks */ 1155 1156 /* Address device - disable SetAddress */ 1157 #define TRB_BSR (1<<9) 1158 enum xhci_setup_dev { 1159 SETUP_CONTEXT_ONLY, 1160 SETUP_CONTEXT_ADDRESS, 1161 }; 1162 1163 /* bits 16:23 are the virtual function ID */ 1164 /* bits 24:31 are the slot ID */ 1165 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1166 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1167 1168 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1169 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1170 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1171 1172 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1173 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1174 #define LAST_EP_INDEX 30 1175 1176 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1177 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1178 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1179 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1180 1181 1182 /* Port Status Change Event TRB fields */ 1183 /* Port ID - bits 31:24 */ 1184 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1185 1186 /* Normal TRB fields */ 1187 /* transfer_len bitmasks - bits 0:16 */ 1188 #define TRB_LEN(p) ((p) & 0x1ffff) 1189 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1190 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1191 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1192 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1193 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1194 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1195 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1196 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1197 #define TRB_TBC(p) (((p) & 0x3) << 7) 1198 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1199 1200 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1201 #define TRB_CYCLE (1<<0) 1202 /* 1203 * Force next event data TRB to be evaluated before task switch. 1204 * Used to pass OS data back after a TD completes. 1205 */ 1206 #define TRB_ENT (1<<1) 1207 /* Interrupt on short packet */ 1208 #define TRB_ISP (1<<2) 1209 /* Set PCIe no snoop attribute */ 1210 #define TRB_NO_SNOOP (1<<3) 1211 /* Chain multiple TRBs into a TD */ 1212 #define TRB_CHAIN (1<<4) 1213 /* Interrupt on completion */ 1214 #define TRB_IOC (1<<5) 1215 /* The buffer pointer contains immediate data */ 1216 #define TRB_IDT (1<<6) 1217 1218 /* Block Event Interrupt */ 1219 #define TRB_BEI (1<<9) 1220 1221 /* Control transfer TRB specific fields */ 1222 #define TRB_DIR_IN (1<<16) 1223 #define TRB_TX_TYPE(p) ((p) << 16) 1224 #define TRB_DATA_OUT 2 1225 #define TRB_DATA_IN 3 1226 1227 /* Isochronous TRB specific fields */ 1228 #define TRB_SIA (1<<31) 1229 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1230 1231 struct xhci_generic_trb { 1232 __le32 field[4]; 1233 }; 1234 1235 union xhci_trb { 1236 struct xhci_link_trb link; 1237 struct xhci_transfer_event trans_event; 1238 struct xhci_event_cmd event_cmd; 1239 struct xhci_generic_trb generic; 1240 }; 1241 1242 /* TRB bit mask */ 1243 #define TRB_TYPE_BITMASK (0xfc00) 1244 #define TRB_TYPE(p) ((p) << 10) 1245 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1246 /* TRB type IDs */ 1247 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1248 #define TRB_NORMAL 1 1249 /* setup stage for control transfers */ 1250 #define TRB_SETUP 2 1251 /* data stage for control transfers */ 1252 #define TRB_DATA 3 1253 /* status stage for control transfers */ 1254 #define TRB_STATUS 4 1255 /* isoc transfers */ 1256 #define TRB_ISOC 5 1257 /* TRB for linking ring segments */ 1258 #define TRB_LINK 6 1259 #define TRB_EVENT_DATA 7 1260 /* Transfer Ring No-op (not for the command ring) */ 1261 #define TRB_TR_NOOP 8 1262 /* Command TRBs */ 1263 /* Enable Slot Command */ 1264 #define TRB_ENABLE_SLOT 9 1265 /* Disable Slot Command */ 1266 #define TRB_DISABLE_SLOT 10 1267 /* Address Device Command */ 1268 #define TRB_ADDR_DEV 11 1269 /* Configure Endpoint Command */ 1270 #define TRB_CONFIG_EP 12 1271 /* Evaluate Context Command */ 1272 #define TRB_EVAL_CONTEXT 13 1273 /* Reset Endpoint Command */ 1274 #define TRB_RESET_EP 14 1275 /* Stop Transfer Ring Command */ 1276 #define TRB_STOP_RING 15 1277 /* Set Transfer Ring Dequeue Pointer Command */ 1278 #define TRB_SET_DEQ 16 1279 /* Reset Device Command */ 1280 #define TRB_RESET_DEV 17 1281 /* Force Event Command (opt) */ 1282 #define TRB_FORCE_EVENT 18 1283 /* Negotiate Bandwidth Command (opt) */ 1284 #define TRB_NEG_BANDWIDTH 19 1285 /* Set Latency Tolerance Value Command (opt) */ 1286 #define TRB_SET_LT 20 1287 /* Get port bandwidth Command */ 1288 #define TRB_GET_BW 21 1289 /* Force Header Command - generate a transaction or link management packet */ 1290 #define TRB_FORCE_HEADER 22 1291 /* No-op Command - not for transfer rings */ 1292 #define TRB_CMD_NOOP 23 1293 /* TRB IDs 24-31 reserved */ 1294 /* Event TRBS */ 1295 /* Transfer Event */ 1296 #define TRB_TRANSFER 32 1297 /* Command Completion Event */ 1298 #define TRB_COMPLETION 33 1299 /* Port Status Change Event */ 1300 #define TRB_PORT_STATUS 34 1301 /* Bandwidth Request Event (opt) */ 1302 #define TRB_BANDWIDTH_EVENT 35 1303 /* Doorbell Event (opt) */ 1304 #define TRB_DOORBELL 36 1305 /* Host Controller Event */ 1306 #define TRB_HC_EVENT 37 1307 /* Device Notification Event - device sent function wake notification */ 1308 #define TRB_DEV_NOTE 38 1309 /* MFINDEX Wrap Event - microframe counter wrapped */ 1310 #define TRB_MFINDEX_WRAP 39 1311 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1312 1313 /* Nec vendor-specific command completion event. */ 1314 #define TRB_NEC_CMD_COMP 48 1315 /* Get NEC firmware revision. */ 1316 #define TRB_NEC_GET_FW 49 1317 1318 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1319 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1320 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1321 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1322 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1323 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1324 1325 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1326 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1327 1328 /* 1329 * TRBS_PER_SEGMENT must be a multiple of 4, 1330 * since the command ring is 64-byte aligned. 1331 * It must also be greater than 16. 1332 */ 1333 #define TRBS_PER_SEGMENT 256 1334 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1335 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1336 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1337 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1338 /* TRB buffer pointers can't cross 64KB boundaries */ 1339 #define TRB_MAX_BUFF_SHIFT 16 1340 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1341 1342 struct xhci_segment { 1343 union xhci_trb *trbs; 1344 /* private to HCD */ 1345 struct xhci_segment *next; 1346 dma_addr_t dma; 1347 }; 1348 1349 struct xhci_td { 1350 struct list_head td_list; 1351 struct list_head cancelled_td_list; 1352 struct urb *urb; 1353 struct xhci_segment *start_seg; 1354 union xhci_trb *first_trb; 1355 union xhci_trb *last_trb; 1356 /* actual_length of the URB has already been set */ 1357 bool urb_length_set; 1358 }; 1359 1360 /* xHCI command default timeout value */ 1361 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1362 1363 /* command descriptor */ 1364 struct xhci_cd { 1365 struct xhci_command *command; 1366 union xhci_trb *cmd_trb; 1367 }; 1368 1369 struct xhci_dequeue_state { 1370 struct xhci_segment *new_deq_seg; 1371 union xhci_trb *new_deq_ptr; 1372 int new_cycle_state; 1373 }; 1374 1375 enum xhci_ring_type { 1376 TYPE_CTRL = 0, 1377 TYPE_ISOC, 1378 TYPE_BULK, 1379 TYPE_INTR, 1380 TYPE_STREAM, 1381 TYPE_COMMAND, 1382 TYPE_EVENT, 1383 }; 1384 1385 struct xhci_ring { 1386 struct xhci_segment *first_seg; 1387 struct xhci_segment *last_seg; 1388 union xhci_trb *enqueue; 1389 struct xhci_segment *enq_seg; 1390 unsigned int enq_updates; 1391 union xhci_trb *dequeue; 1392 struct xhci_segment *deq_seg; 1393 unsigned int deq_updates; 1394 struct list_head td_list; 1395 /* 1396 * Write the cycle state into the TRB cycle field to give ownership of 1397 * the TRB to the host controller (if we are the producer), or to check 1398 * if we own the TRB (if we are the consumer). See section 4.9.1. 1399 */ 1400 u32 cycle_state; 1401 unsigned int stream_id; 1402 unsigned int num_segs; 1403 unsigned int num_trbs_free; 1404 unsigned int num_trbs_free_temp; 1405 enum xhci_ring_type type; 1406 bool last_td_was_short; 1407 struct radix_tree_root *trb_address_map; 1408 }; 1409 1410 struct xhci_erst_entry { 1411 /* 64-bit event ring segment address */ 1412 __le64 seg_addr; 1413 __le32 seg_size; 1414 /* Set to zero */ 1415 __le32 rsvd; 1416 }; 1417 1418 struct xhci_erst { 1419 struct xhci_erst_entry *entries; 1420 unsigned int num_entries; 1421 /* xhci->event_ring keeps track of segment dma addresses */ 1422 dma_addr_t erst_dma_addr; 1423 /* Num entries the ERST can contain */ 1424 unsigned int erst_size; 1425 }; 1426 1427 struct xhci_scratchpad { 1428 u64 *sp_array; 1429 dma_addr_t sp_dma; 1430 void **sp_buffers; 1431 dma_addr_t *sp_dma_buffers; 1432 }; 1433 1434 struct urb_priv { 1435 int length; 1436 int td_cnt; 1437 struct xhci_td *td[0]; 1438 }; 1439 1440 /* 1441 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1442 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1443 * meaning 64 ring segments. 1444 * Initial allocated size of the ERST, in number of entries */ 1445 #define ERST_NUM_SEGS 1 1446 /* Initial allocated size of the ERST, in number of entries */ 1447 #define ERST_SIZE 64 1448 /* Initial number of event segment rings allocated */ 1449 #define ERST_ENTRIES 1 1450 /* Poll every 60 seconds */ 1451 #define POLL_TIMEOUT 60 1452 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1453 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1454 /* XXX: Make these module parameters */ 1455 1456 struct s3_save { 1457 u32 command; 1458 u32 dev_nt; 1459 u64 dcbaa_ptr; 1460 u32 config_reg; 1461 u32 irq_pending; 1462 u32 irq_control; 1463 u32 erst_size; 1464 u64 erst_base; 1465 u64 erst_dequeue; 1466 }; 1467 1468 /* Use for lpm */ 1469 struct dev_info { 1470 u32 dev_id; 1471 struct list_head list; 1472 }; 1473 1474 struct xhci_bus_state { 1475 unsigned long bus_suspended; 1476 unsigned long next_statechange; 1477 1478 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1479 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1480 u32 port_c_suspend; 1481 u32 suspended_ports; 1482 u32 port_remote_wakeup; 1483 unsigned long resume_done[USB_MAXCHILDREN]; 1484 /* which ports have started to resume */ 1485 unsigned long resuming_ports; 1486 /* Which ports are waiting on RExit to U0 transition. */ 1487 unsigned long rexit_ports; 1488 struct completion rexit_done[USB_MAXCHILDREN]; 1489 }; 1490 1491 1492 /* 1493 * It can take up to 20 ms to transition from RExit to U0 on the 1494 * Intel Lynx Point LP xHCI host. 1495 */ 1496 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1497 1498 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1499 { 1500 if (hcd->speed == HCD_USB3) 1501 return 0; 1502 else 1503 return 1; 1504 } 1505 1506 struct xhci_hub { 1507 u8 maj_rev; 1508 u8 min_rev; 1509 u32 *psi; /* array of protocol speed ID entries */ 1510 u8 psi_count; 1511 u8 psi_uid_count; 1512 }; 1513 1514 /* There is one xhci_hcd structure per controller */ 1515 struct xhci_hcd { 1516 struct usb_hcd *main_hcd; 1517 struct usb_hcd *shared_hcd; 1518 /* glue to PCI and HCD framework */ 1519 struct xhci_cap_regs __iomem *cap_regs; 1520 struct xhci_op_regs __iomem *op_regs; 1521 struct xhci_run_regs __iomem *run_regs; 1522 struct xhci_doorbell_array __iomem *dba; 1523 /* Our HCD's current interrupter register set */ 1524 struct xhci_intr_reg __iomem *ir_set; 1525 1526 /* Cached register copies of read-only HC data */ 1527 __u32 hcs_params1; 1528 __u32 hcs_params2; 1529 __u32 hcs_params3; 1530 __u32 hcc_params; 1531 __u32 hcc_params2; 1532 1533 spinlock_t lock; 1534 1535 /* packed release number */ 1536 u8 sbrn; 1537 u16 hci_version; 1538 u8 max_slots; 1539 u8 max_interrupters; 1540 u8 max_ports; 1541 u8 isoc_threshold; 1542 int event_ring_max; 1543 int addr_64; 1544 /* 4KB min, 128MB max */ 1545 int page_size; 1546 /* Valid values are 12 to 20, inclusive */ 1547 int page_shift; 1548 /* msi-x vectors */ 1549 int msix_count; 1550 struct msix_entry *msix_entries; 1551 /* optional clock */ 1552 struct clk *clk; 1553 /* data structures */ 1554 struct xhci_device_context_array *dcbaa; 1555 struct xhci_ring *cmd_ring; 1556 unsigned int cmd_ring_state; 1557 #define CMD_RING_STATE_RUNNING (1 << 0) 1558 #define CMD_RING_STATE_ABORTED (1 << 1) 1559 #define CMD_RING_STATE_STOPPED (1 << 2) 1560 struct list_head cmd_list; 1561 unsigned int cmd_ring_reserved_trbs; 1562 struct timer_list cmd_timer; 1563 struct xhci_command *current_cmd; 1564 struct xhci_ring *event_ring; 1565 struct xhci_erst erst; 1566 /* Scratchpad */ 1567 struct xhci_scratchpad *scratchpad; 1568 /* Store LPM test failed devices' information */ 1569 struct list_head lpm_failed_devs; 1570 1571 /* slot enabling and address device helpers */ 1572 /* these are not thread safe so use mutex */ 1573 struct mutex mutex; 1574 struct completion addr_dev; 1575 int slot_id; 1576 /* For USB 3.0 LPM enable/disable. */ 1577 struct xhci_command *lpm_command; 1578 /* Internal mirror of the HW's dcbaa */ 1579 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1580 /* For keeping track of bandwidth domains per roothub. */ 1581 struct xhci_root_port_bw_info *rh_bw; 1582 1583 /* DMA pools */ 1584 struct dma_pool *device_pool; 1585 struct dma_pool *segment_pool; 1586 struct dma_pool *small_streams_pool; 1587 struct dma_pool *medium_streams_pool; 1588 1589 /* Host controller watchdog timer structures */ 1590 unsigned int xhc_state; 1591 1592 u32 command; 1593 struct s3_save s3; 1594 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1595 * 1596 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1597 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1598 * that sees this status (other than the timer that set it) should stop touching 1599 * hardware immediately. Interrupt handlers should return immediately when 1600 * they see this status (any time they drop and re-acquire xhci->lock). 1601 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1602 * putting the TD on the canceled list, etc. 1603 * 1604 * There are no reports of xHCI host controllers that display this issue. 1605 */ 1606 #define XHCI_STATE_DYING (1 << 0) 1607 #define XHCI_STATE_HALTED (1 << 1) 1608 #define XHCI_STATE_REMOVING (1 << 2) 1609 /* Statistics */ 1610 int error_bitmask; 1611 unsigned int quirks; 1612 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1613 #define XHCI_RESET_EP_QUIRK (1 << 1) 1614 #define XHCI_NEC_HOST (1 << 2) 1615 #define XHCI_AMD_PLL_FIX (1 << 3) 1616 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1617 /* 1618 * Certain Intel host controllers have a limit to the number of endpoint 1619 * contexts they can handle. Ideally, they would signal that they can't handle 1620 * anymore endpoint contexts by returning a Resource Error for the Configure 1621 * Endpoint command, but they don't. Instead they expect software to keep track 1622 * of the number of active endpoints for them, across configure endpoint 1623 * commands, reset device commands, disable slot commands, and address device 1624 * commands. 1625 */ 1626 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1627 #define XHCI_BROKEN_MSI (1 << 6) 1628 #define XHCI_RESET_ON_RESUME (1 << 7) 1629 #define XHCI_SW_BW_CHECKING (1 << 8) 1630 #define XHCI_AMD_0x96_HOST (1 << 9) 1631 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1632 #define XHCI_LPM_SUPPORT (1 << 11) 1633 #define XHCI_INTEL_HOST (1 << 12) 1634 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1635 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1636 #define XHCI_AVOID_BEI (1 << 15) 1637 #define XHCI_PLAT (1 << 16) 1638 #define XHCI_SLOW_SUSPEND (1 << 17) 1639 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1640 /* For controllers with a broken beyond repair streams implementation */ 1641 #define XHCI_BROKEN_STREAMS (1 << 19) 1642 #define XHCI_PME_STUCK_QUIRK (1 << 20) 1643 #define XHCI_MTK_HOST (1 << 21) 1644 #define XHCI_SSIC_PORT_UNUSED (1 << 22) 1645 #define XHCI_NO_64BIT_SUPPORT (1 << 23) 1646 unsigned int num_active_eps; 1647 unsigned int limit_active_eps; 1648 /* There are two roothubs to keep track of bus suspend info for */ 1649 struct xhci_bus_state bus_state[2]; 1650 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1651 u8 *port_array; 1652 /* Array of pointers to USB 3.0 PORTSC registers */ 1653 __le32 __iomem **usb3_ports; 1654 unsigned int num_usb3_ports; 1655 /* Array of pointers to USB 2.0 PORTSC registers */ 1656 __le32 __iomem **usb2_ports; 1657 struct xhci_hub usb2_rhub; 1658 struct xhci_hub usb3_rhub; 1659 unsigned int num_usb2_ports; 1660 /* support xHCI 0.96 spec USB2 software LPM */ 1661 unsigned sw_lpm_support:1; 1662 /* support xHCI 1.0 spec USB2 hardware LPM */ 1663 unsigned hw_lpm_support:1; 1664 /* cached usb2 extened protocol capabilites */ 1665 u32 *ext_caps; 1666 unsigned int num_ext_caps; 1667 /* Compliance Mode Recovery Data */ 1668 struct timer_list comp_mode_recovery_timer; 1669 u32 port_status_u0; 1670 /* Compliance Mode Timer Triggered every 2 seconds */ 1671 #define COMP_MODE_RCVRY_MSECS 2000 1672 1673 /* platform-specific data -- must come last */ 1674 unsigned long priv[0] __aligned(sizeof(s64)); 1675 }; 1676 1677 /* Platform specific overrides to generic XHCI hc_driver ops */ 1678 struct xhci_driver_overrides { 1679 size_t extra_priv_size; 1680 int (*reset)(struct usb_hcd *hcd); 1681 int (*start)(struct usb_hcd *hcd); 1682 }; 1683 1684 #define XHCI_CFC_DELAY 10 1685 1686 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1687 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1688 { 1689 struct usb_hcd *primary_hcd; 1690 1691 if (usb_hcd_is_primary_hcd(hcd)) 1692 primary_hcd = hcd; 1693 else 1694 primary_hcd = hcd->primary_hcd; 1695 1696 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1697 } 1698 1699 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1700 { 1701 return xhci->main_hcd; 1702 } 1703 1704 #define xhci_dbg(xhci, fmt, args...) \ 1705 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1706 #define xhci_err(xhci, fmt, args...) \ 1707 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1708 #define xhci_warn(xhci, fmt, args...) \ 1709 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1710 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1711 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1712 #define xhci_info(xhci, fmt, args...) \ 1713 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1714 1715 /* 1716 * Registers should always be accessed with double word or quad word accesses. 1717 * 1718 * Some xHCI implementations may support 64-bit address pointers. Registers 1719 * with 64-bit address pointers should be written to with dword accesses by 1720 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1721 * xHCI implementations that do not support 64-bit address pointers will ignore 1722 * the high dword, and write order is irrelevant. 1723 */ 1724 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1725 __le64 __iomem *regs) 1726 { 1727 return lo_hi_readq(regs); 1728 } 1729 static inline void xhci_write_64(struct xhci_hcd *xhci, 1730 const u64 val, __le64 __iomem *regs) 1731 { 1732 lo_hi_writeq(val, regs); 1733 } 1734 1735 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1736 { 1737 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1738 } 1739 1740 /* xHCI debugging */ 1741 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1742 void xhci_print_registers(struct xhci_hcd *xhci); 1743 void xhci_dbg_regs(struct xhci_hcd *xhci); 1744 void xhci_print_run_regs(struct xhci_hcd *xhci); 1745 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1746 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1747 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1748 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1749 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1750 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1751 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1752 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1753 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1754 struct xhci_container_ctx *ctx); 1755 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1756 unsigned int slot_id, unsigned int ep_index, 1757 struct xhci_virt_ep *ep); 1758 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1759 const char *fmt, ...); 1760 1761 /* xHCI memory management */ 1762 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1763 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1764 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1765 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1766 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1767 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1768 struct usb_device *udev); 1769 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1770 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1771 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1772 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1773 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1774 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1775 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1776 struct xhci_bw_info *ep_bw, 1777 struct xhci_interval_bw_table *bw_table, 1778 struct usb_device *udev, 1779 struct xhci_virt_ep *virt_ep, 1780 struct xhci_tt_bw_info *tt_info); 1781 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1782 struct xhci_virt_device *virt_dev, 1783 int old_active_eps); 1784 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1785 void xhci_update_bw_info(struct xhci_hcd *xhci, 1786 struct xhci_container_ctx *in_ctx, 1787 struct xhci_input_control_ctx *ctrl_ctx, 1788 struct xhci_virt_device *virt_dev); 1789 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1790 struct xhci_container_ctx *in_ctx, 1791 struct xhci_container_ctx *out_ctx, 1792 unsigned int ep_index); 1793 void xhci_slot_copy(struct xhci_hcd *xhci, 1794 struct xhci_container_ctx *in_ctx, 1795 struct xhci_container_ctx *out_ctx); 1796 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1797 struct usb_device *udev, struct usb_host_endpoint *ep, 1798 gfp_t mem_flags); 1799 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1800 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1801 unsigned int num_trbs, gfp_t flags); 1802 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1803 struct xhci_virt_device *virt_dev, 1804 unsigned int ep_index); 1805 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1806 unsigned int num_stream_ctxs, 1807 unsigned int num_streams, gfp_t flags); 1808 void xhci_free_stream_info(struct xhci_hcd *xhci, 1809 struct xhci_stream_info *stream_info); 1810 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1811 struct xhci_ep_ctx *ep_ctx, 1812 struct xhci_stream_info *stream_info); 1813 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1814 struct xhci_virt_ep *ep); 1815 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1816 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1817 struct xhci_ring *xhci_dma_to_transfer_ring( 1818 struct xhci_virt_ep *ep, 1819 u64 address); 1820 struct xhci_ring *xhci_stream_id_to_ring( 1821 struct xhci_virt_device *dev, 1822 unsigned int ep_index, 1823 unsigned int stream_id); 1824 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1825 bool allocate_in_ctx, bool allocate_completion, 1826 gfp_t mem_flags); 1827 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1828 void xhci_free_command(struct xhci_hcd *xhci, 1829 struct xhci_command *command); 1830 1831 /* xHCI host controller glue */ 1832 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1833 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 1834 void xhci_quiesce(struct xhci_hcd *xhci); 1835 int xhci_halt(struct xhci_hcd *xhci); 1836 int xhci_reset(struct xhci_hcd *xhci); 1837 int xhci_init(struct usb_hcd *hcd); 1838 int xhci_run(struct usb_hcd *hcd); 1839 void xhci_stop(struct usb_hcd *hcd); 1840 void xhci_shutdown(struct usb_hcd *hcd); 1841 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1842 void xhci_init_driver(struct hc_driver *drv, 1843 const struct xhci_driver_overrides *over); 1844 1845 #ifdef CONFIG_PM 1846 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1847 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1848 #else 1849 #define xhci_suspend NULL 1850 #define xhci_resume NULL 1851 #endif 1852 1853 int xhci_get_frame(struct usb_hcd *hcd); 1854 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1855 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1856 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1857 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1858 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1859 struct xhci_virt_device *virt_dev, 1860 struct usb_device *hdev, 1861 struct usb_tt *tt, gfp_t mem_flags); 1862 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1863 struct usb_host_endpoint **eps, unsigned int num_eps, 1864 unsigned int num_streams, gfp_t mem_flags); 1865 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1866 struct usb_host_endpoint **eps, unsigned int num_eps, 1867 gfp_t mem_flags); 1868 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1869 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); 1870 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 1871 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 1872 struct usb_device *udev, int enable); 1873 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1874 struct usb_tt *tt, gfp_t mem_flags); 1875 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1876 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1877 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1878 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1879 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1880 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1881 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1882 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1883 1884 /* xHCI ring, segment, TRB, and TD functions */ 1885 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1886 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 1887 struct xhci_segment *start_seg, union xhci_trb *start_trb, 1888 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 1889 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1890 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1891 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1892 u32 trb_type, u32 slot_id); 1893 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1894 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1895 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1896 u32 field1, u32 field2, u32 field3, u32 field4); 1897 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1898 int slot_id, unsigned int ep_index, int suspend); 1899 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1900 int slot_id, unsigned int ep_index); 1901 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1902 int slot_id, unsigned int ep_index); 1903 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1904 int slot_id, unsigned int ep_index); 1905 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1906 struct urb *urb, int slot_id, unsigned int ep_index); 1907 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1908 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1909 bool command_must_succeed); 1910 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1911 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1912 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1913 int slot_id, unsigned int ep_index); 1914 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1915 u32 slot_id); 1916 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1917 unsigned int slot_id, unsigned int ep_index, 1918 unsigned int stream_id, struct xhci_td *cur_td, 1919 struct xhci_dequeue_state *state); 1920 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1921 unsigned int slot_id, unsigned int ep_index, 1922 unsigned int stream_id, 1923 struct xhci_dequeue_state *deq_state); 1924 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1925 unsigned int ep_index, struct xhci_td *td); 1926 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1927 unsigned int slot_id, unsigned int ep_index, 1928 struct xhci_dequeue_state *deq_state); 1929 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1930 void xhci_handle_command_timeout(unsigned long data); 1931 1932 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1933 unsigned int ep_index, unsigned int stream_id); 1934 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1935 1936 /* xHCI roothub code */ 1937 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1938 int port_id, u32 link_state); 1939 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, 1940 struct usb_device *udev, enum usb3_link_state state); 1941 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, 1942 struct usb_device *udev, enum usb3_link_state state); 1943 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1944 int port_id, u32 port_bit); 1945 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1946 char *buf, u16 wLength); 1947 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1948 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1949 1950 #ifdef CONFIG_PM 1951 int xhci_bus_suspend(struct usb_hcd *hcd); 1952 int xhci_bus_resume(struct usb_hcd *hcd); 1953 #else 1954 #define xhci_bus_suspend NULL 1955 #define xhci_bus_resume NULL 1956 #endif /* CONFIG_PM */ 1957 1958 u32 xhci_port_state_to_neutral(u32 state); 1959 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1960 u16 port); 1961 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1962 1963 /* xHCI contexts */ 1964 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1965 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1966 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1967 1968 #endif /* __LINUX_XHCI_HCD_H */ 1969