1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 #include <linux/kernel.h> 29 30 #include "../core/hcd.h" 31 /* Code sharing between pci-quirks and xhci hcd */ 32 #include "xhci-ext-caps.h" 33 34 /* xHCI PCI Configuration Registers */ 35 #define XHCI_SBRN_OFFSET (0x60) 36 37 /* Max number of USB devices for any host controller - limit in section 6.1 */ 38 #define MAX_HC_SLOTS 256 39 /* Section 5.3.3 - MaxPorts */ 40 #define MAX_HC_PORTS 127 41 42 /* 43 * xHCI register interface. 44 * This corresponds to the eXtensible Host Controller Interface (xHCI) 45 * Revision 0.95 specification 46 */ 47 48 /** 49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 50 * @hc_capbase: length of the capabilities register and HC version number 51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 54 * @hcc_params: HCCPARAMS - Capability Parameters 55 * @db_off: DBOFF - Doorbell array offset 56 * @run_regs_off: RTSOFF - Runtime register space offset 57 */ 58 struct xhci_cap_regs { 59 u32 hc_capbase; 60 u32 hcs_params1; 61 u32 hcs_params2; 62 u32 hcs_params3; 63 u32 hcc_params; 64 u32 db_off; 65 u32 run_regs_off; 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* hc_capbase bitmasks */ 70 /* bits 7:0 - how long is the Capabilities register */ 71 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 72 /* bits 31:16 */ 73 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 74 75 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 76 /* bits 0:7, Max Device Slots */ 77 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 78 #define HCS_SLOTS_MASK 0xff 79 /* bits 8:18, Max Interrupters */ 80 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 81 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 82 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 83 84 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 85 /* bits 0:3, frames or uframes that SW needs to queue transactions 86 * ahead of the HW to meet periodic deadlines */ 87 #define HCS_IST(p) (((p) >> 0) & 0xf) 88 /* bits 4:7, max number of Event Ring segments */ 89 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 90 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 91 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 92 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 93 94 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 95 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 96 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 97 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 98 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 99 100 /* HCCPARAMS - hcc_params - bitmasks */ 101 /* true: HC can use 64-bit address pointers */ 102 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 103 /* true: HC can do bandwidth negotiation */ 104 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 105 /* true: HC uses 64-byte Device Context structures 106 * FIXME 64-byte context structures aren't supported yet. 107 */ 108 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 109 /* true: HC has port power switches */ 110 #define HCC_PPC(p) ((p) & (1 << 3)) 111 /* true: HC has port indicators */ 112 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 113 /* true: HC has Light HC Reset Capability */ 114 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 115 /* true: HC supports latency tolerance messaging */ 116 #define HCC_LTC(p) ((p) & (1 << 6)) 117 /* true: no secondary Stream ID Support */ 118 #define HCC_NSS(p) ((p) & (1 << 7)) 119 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 120 #define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1)) 121 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 122 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 123 124 /* db_off bitmask - bits 0:1 reserved */ 125 #define DBOFF_MASK (~0x3) 126 127 /* run_regs_off bitmask - bits 0:4 reserved */ 128 #define RTSOFF_MASK (~0x1f) 129 130 131 /* Number of registers per port */ 132 #define NUM_PORT_REGS 4 133 134 /** 135 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 136 * @command: USBCMD - xHC command register 137 * @status: USBSTS - xHC status register 138 * @page_size: This indicates the page size that the host controller 139 * supports. If bit n is set, the HC supports a page size 140 * of 2^(n+12), up to a 128MB page size. 141 * 4K is the minimum page size. 142 * @cmd_ring: CRP - 64-bit Command Ring Pointer 143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 144 * @config_reg: CONFIG - Configure Register 145 * @port_status_base: PORTSCn - base address for Port Status and Control 146 * Each port has a Port Status and Control register, 147 * followed by a Port Power Management Status and Control 148 * register, a Port Link Info register, and a reserved 149 * register. 150 * @port_power_base: PORTPMSCn - base address for 151 * Port Power Management Status and Control 152 * @port_link_base: PORTLIn - base address for Port Link Info (current 153 * Link PM state and control) for USB 2.1 and USB 3.0 154 * devices. 155 */ 156 struct xhci_op_regs { 157 u32 command; 158 u32 status; 159 u32 page_size; 160 u32 reserved1; 161 u32 reserved2; 162 u32 dev_notification; 163 u64 cmd_ring; 164 /* rsvd: offset 0x20-2F */ 165 u32 reserved3[4]; 166 u64 dcbaa_ptr; 167 u32 config_reg; 168 /* rsvd: offset 0x3C-3FF */ 169 u32 reserved4[241]; 170 /* port 1 registers, which serve as a base address for other ports */ 171 u32 port_status_base; 172 u32 port_power_base; 173 u32 port_link_base; 174 u32 reserved5; 175 /* registers for ports 2-255 */ 176 u32 reserved6[NUM_PORT_REGS*254]; 177 }; 178 179 /* USBCMD - USB command - command bitmasks */ 180 /* start/stop HC execution - do not write unless HC is halted*/ 181 #define CMD_RUN XHCI_CMD_RUN 182 /* Reset HC - resets internal HC state machine and all registers (except 183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 184 * The xHCI driver must reinitialize the xHC after setting this bit. 185 */ 186 #define CMD_RESET (1 << 1) 187 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 188 #define CMD_EIE XHCI_CMD_EIE 189 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 190 #define CMD_HSEIE XHCI_CMD_HSEIE 191 /* bits 4:6 are reserved (and should be preserved on writes). */ 192 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 193 #define CMD_LRESET (1 << 7) 194 /* FIXME: ignoring host controller save/restore state for now. */ 195 #define CMD_CSS (1 << 8) 196 #define CMD_CRS (1 << 9) 197 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 198 #define CMD_EWE XHCI_CMD_EWE 199 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 201 * '0' means the xHC can power it off if all ports are in the disconnect, 202 * disabled, or powered-off state. 203 */ 204 #define CMD_PM_INDEX (1 << 11) 205 /* bits 12:31 are reserved (and should be preserved on writes). */ 206 207 /* USBSTS - USB status - status bitmasks */ 208 /* HC not running - set to 1 when run/stop bit is cleared. */ 209 #define STS_HALT XHCI_STS_HALT 210 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 211 #define STS_FATAL (1 << 2) 212 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 213 #define STS_EINT (1 << 3) 214 /* port change detect */ 215 #define STS_PORT (1 << 4) 216 /* bits 5:7 reserved and zeroed */ 217 /* save state status - '1' means xHC is saving state */ 218 #define STS_SAVE (1 << 8) 219 /* restore state status - '1' means xHC is restoring state */ 220 #define STS_RESTORE (1 << 9) 221 /* true: save or restore error */ 222 #define STS_SRE (1 << 10) 223 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 224 #define STS_CNR XHCI_STS_CNR 225 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 226 #define STS_HCE (1 << 12) 227 /* bits 13:31 reserved and should be preserved */ 228 229 /* 230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 231 * Generate a device notification event when the HC sees a transaction with a 232 * notification type that matches a bit set in this bit field. 233 */ 234 #define DEV_NOTE_MASK (0xffff) 235 #define ENABLE_DEV_NOTE(x) (1 << x) 236 /* Most of the device notification types should only be used for debug. 237 * SW does need to pay attention to function wake notifications. 238 */ 239 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 240 241 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 242 /* bit 0 is the command ring cycle state */ 243 /* stop ring operation after completion of the currently executing command */ 244 #define CMD_RING_PAUSE (1 << 1) 245 /* stop ring immediately - abort the currently executing command */ 246 #define CMD_RING_ABORT (1 << 2) 247 /* true: command ring is running */ 248 #define CMD_RING_RUNNING (1 << 3) 249 /* bits 4:5 reserved and should be preserved */ 250 /* Command Ring pointer - bit mask for the lower 32 bits. */ 251 #define CMD_RING_RSVD_BITS (0x3f) 252 253 /* CONFIG - Configure Register - config_reg bitmasks */ 254 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 255 #define MAX_DEVS(p) ((p) & 0xff) 256 /* bits 8:31 - reserved and should be preserved */ 257 258 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 259 /* true: device connected */ 260 #define PORT_CONNECT (1 << 0) 261 /* true: port enabled */ 262 #define PORT_PE (1 << 1) 263 /* bit 2 reserved and zeroed */ 264 /* true: port has an over-current condition */ 265 #define PORT_OC (1 << 3) 266 /* true: port reset signaling asserted */ 267 #define PORT_RESET (1 << 4) 268 /* Port Link State - bits 5:8 269 * A read gives the current link PM state of the port, 270 * a write with Link State Write Strobe set sets the link state. 271 */ 272 /* true: port has power (see HCC_PPC) */ 273 #define PORT_POWER (1 << 9) 274 /* bits 10:13 indicate device speed: 275 * 0 - undefined speed - port hasn't be initialized by a reset yet 276 * 1 - full speed 277 * 2 - low speed 278 * 3 - high speed 279 * 4 - super speed 280 * 5-15 reserved 281 */ 282 #define DEV_SPEED_MASK (0xf << 10) 283 #define XDEV_FS (0x1 << 10) 284 #define XDEV_LS (0x2 << 10) 285 #define XDEV_HS (0x3 << 10) 286 #define XDEV_SS (0x4 << 10) 287 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 288 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 289 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 290 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 291 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 292 /* Bits 20:23 in the Slot Context are the speed for the device */ 293 #define SLOT_SPEED_FS (XDEV_FS << 10) 294 #define SLOT_SPEED_LS (XDEV_LS << 10) 295 #define SLOT_SPEED_HS (XDEV_HS << 10) 296 #define SLOT_SPEED_SS (XDEV_SS << 10) 297 /* Port Indicator Control */ 298 #define PORT_LED_OFF (0 << 14) 299 #define PORT_LED_AMBER (1 << 14) 300 #define PORT_LED_GREEN (2 << 14) 301 #define PORT_LED_MASK (3 << 14) 302 /* Port Link State Write Strobe - set this when changing link state */ 303 #define PORT_LINK_STROBE (1 << 16) 304 /* true: connect status change */ 305 #define PORT_CSC (1 << 17) 306 /* true: port enable change */ 307 #define PORT_PEC (1 << 18) 308 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 309 * into an enabled state, and the device into the default state. A "warm" reset 310 * also resets the link, forcing the device through the link training sequence. 311 * SW can also look at the Port Reset register to see when warm reset is done. 312 */ 313 #define PORT_WRC (1 << 19) 314 /* true: over-current change */ 315 #define PORT_OCC (1 << 20) 316 /* true: reset change - 1 to 0 transition of PORT_RESET */ 317 #define PORT_RC (1 << 21) 318 /* port link status change - set on some port link state transitions: 319 * Transition Reason 320 * ------------------------------------------------------------------------------ 321 * - U3 to Resume Wakeup signaling from a device 322 * - Resume to Recovery to U0 USB 3.0 device resume 323 * - Resume to U0 USB 2.0 device resume 324 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 325 * - U3 to U0 Software resume of USB 2.0 device complete 326 * - U2 to U0 L1 resume of USB 2.1 device complete 327 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 328 * - U0 to disabled L1 entry error with USB 2.1 device 329 * - Any state to inactive Error on USB 3.0 port 330 */ 331 #define PORT_PLC (1 << 22) 332 /* port configure error change - port failed to configure its link partner */ 333 #define PORT_CEC (1 << 23) 334 /* bit 24 reserved */ 335 /* wake on connect (enable) */ 336 #define PORT_WKCONN_E (1 << 25) 337 /* wake on disconnect (enable) */ 338 #define PORT_WKDISC_E (1 << 26) 339 /* wake on over-current (enable) */ 340 #define PORT_WKOC_E (1 << 27) 341 /* bits 28:29 reserved */ 342 /* true: device is removable - for USB 3.0 roothub emulation */ 343 #define PORT_DEV_REMOVE (1 << 30) 344 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 345 #define PORT_WR (1 << 31) 346 347 /* Port Power Management Status and Control - port_power_base bitmasks */ 348 /* Inactivity timer value for transitions into U1, in microseconds. 349 * Timeout can be up to 127us. 0xFF means an infinite timeout. 350 */ 351 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 352 /* Inactivity timer value for transitions into U2 */ 353 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 354 /* Bits 24:31 for port testing */ 355 356 357 /** 358 * struct xhci_intr_reg - Interrupt Register Set 359 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 360 * interrupts and check for pending interrupts. 361 * @irq_control: IMOD - Interrupt Moderation Register. 362 * Used to throttle interrupts. 363 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 364 * @erst_base: ERST base address. 365 * @erst_dequeue: Event ring dequeue pointer. 366 * 367 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 368 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 369 * multiple segments of the same size. The HC places events on the ring and 370 * "updates the Cycle bit in the TRBs to indicate to software the current 371 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 372 * updates the dequeue pointer. 373 */ 374 struct xhci_intr_reg { 375 u32 irq_pending; 376 u32 irq_control; 377 u32 erst_size; 378 u32 rsvd; 379 u64 erst_base; 380 u64 erst_dequeue; 381 }; 382 383 /* irq_pending bitmasks */ 384 #define ER_IRQ_PENDING(p) ((p) & 0x1) 385 /* bits 2:31 need to be preserved */ 386 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 387 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 388 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 389 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 390 391 /* irq_control bitmasks */ 392 /* Minimum interval between interrupts (in 250ns intervals). The interval 393 * between interrupts will be longer if there are no events on the event ring. 394 * Default is 4000 (1 ms). 395 */ 396 #define ER_IRQ_INTERVAL_MASK (0xffff) 397 /* Counter used to count down the time to the next interrupt - HW use only */ 398 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 399 400 /* erst_size bitmasks */ 401 /* Preserve bits 16:31 of erst_size */ 402 #define ERST_SIZE_MASK (0xffff << 16) 403 404 /* erst_dequeue bitmasks */ 405 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 406 * where the current dequeue pointer lies. This is an optional HW hint. 407 */ 408 #define ERST_DESI_MASK (0x7) 409 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 410 * a work queue (or delayed service routine)? 411 */ 412 #define ERST_EHB (1 << 3) 413 #define ERST_PTR_MASK (0xf) 414 415 /** 416 * struct xhci_run_regs 417 * @microframe_index: 418 * MFINDEX - current microframe number 419 * 420 * Section 5.5 Host Controller Runtime Registers: 421 * "Software should read and write these registers using only Dword (32 bit) 422 * or larger accesses" 423 */ 424 struct xhci_run_regs { 425 u32 microframe_index; 426 u32 rsvd[7]; 427 struct xhci_intr_reg ir_set[128]; 428 }; 429 430 /** 431 * struct doorbell_array 432 * 433 * Section 5.6 434 */ 435 struct xhci_doorbell_array { 436 u32 doorbell[256]; 437 }; 438 439 #define DB_TARGET_MASK 0xFFFFFF00 440 #define DB_STREAM_ID_MASK 0x0000FFFF 441 #define DB_TARGET_HOST 0x0 442 #define DB_STREAM_ID_HOST 0x0 443 #define DB_MASK (0xff << 8) 444 445 /* Endpoint Target - bits 0:7 */ 446 #define EPI_TO_DB(p) (((p) + 1) & 0xff) 447 448 449 /** 450 * struct xhci_container_ctx 451 * @type: Type of context. Used to calculated offsets to contained contexts. 452 * @size: Size of the context data 453 * @bytes: The raw context data given to HW 454 * @dma: dma address of the bytes 455 * 456 * Represents either a Device or Input context. Holds a pointer to the raw 457 * memory used for the context (bytes) and dma address of it (dma). 458 */ 459 struct xhci_container_ctx { 460 unsigned type; 461 #define XHCI_CTX_TYPE_DEVICE 0x1 462 #define XHCI_CTX_TYPE_INPUT 0x2 463 464 int size; 465 466 u8 *bytes; 467 dma_addr_t dma; 468 }; 469 470 /** 471 * struct xhci_slot_ctx 472 * @dev_info: Route string, device speed, hub info, and last valid endpoint 473 * @dev_info2: Max exit latency for device number, root hub port number 474 * @tt_info: tt_info is used to construct split transaction tokens 475 * @dev_state: slot state and device address 476 * 477 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 478 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 479 * reserved at the end of the slot context for HC internal use. 480 */ 481 struct xhci_slot_ctx { 482 u32 dev_info; 483 u32 dev_info2; 484 u32 tt_info; 485 u32 dev_state; 486 /* offset 0x10 to 0x1f reserved for HC internal use */ 487 u32 reserved[4]; 488 }; 489 490 /* dev_info bitmasks */ 491 /* Route String - 0:19 */ 492 #define ROUTE_STRING_MASK (0xfffff) 493 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 494 #define DEV_SPEED (0xf << 20) 495 /* bit 24 reserved */ 496 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 497 #define DEV_MTT (0x1 << 25) 498 /* Set if the device is a hub - bit 26 */ 499 #define DEV_HUB (0x1 << 26) 500 /* Index of the last valid endpoint context in this device context - 27:31 */ 501 #define LAST_CTX_MASK (0x1f << 27) 502 #define LAST_CTX(p) ((p) << 27) 503 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 504 #define SLOT_FLAG (1 << 0) 505 #define EP0_FLAG (1 << 1) 506 507 /* dev_info2 bitmasks */ 508 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 509 #define MAX_EXIT (0xffff) 510 /* Root hub port number that is needed to access the USB device */ 511 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 512 /* Maximum number of ports under a hub device */ 513 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 514 515 /* tt_info bitmasks */ 516 /* 517 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 518 * The Slot ID of the hub that isolates the high speed signaling from 519 * this low or full-speed device. '0' if attached to root hub port. 520 */ 521 #define TT_SLOT (0xff) 522 /* 523 * The number of the downstream facing port of the high-speed hub 524 * '0' if the device is not low or full speed. 525 */ 526 #define TT_PORT (0xff << 8) 527 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 528 529 /* dev_state bitmasks */ 530 /* USB device address - assigned by the HC */ 531 #define DEV_ADDR_MASK (0xff) 532 /* bits 8:26 reserved */ 533 /* Slot state */ 534 #define SLOT_STATE (0x1f << 27) 535 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 536 537 538 /** 539 * struct xhci_ep_ctx 540 * @ep_info: endpoint state, streams, mult, and interval information. 541 * @ep_info2: information on endpoint type, max packet size, max burst size, 542 * error count, and whether the HC will force an event for all 543 * transactions. 544 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 545 * defines one stream, this points to the endpoint transfer ring. 546 * Otherwise, it points to a stream context array, which has a 547 * ring pointer for each flow. 548 * @tx_info: 549 * Average TRB lengths for the endpoint ring and 550 * max payload within an Endpoint Service Interval Time (ESIT). 551 * 552 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 553 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 554 * reserved at the end of the endpoint context for HC internal use. 555 */ 556 struct xhci_ep_ctx { 557 u32 ep_info; 558 u32 ep_info2; 559 u64 deq; 560 u32 tx_info; 561 /* offset 0x14 - 0x1f reserved for HC internal use */ 562 u32 reserved[3]; 563 }; 564 565 /* ep_info bitmasks */ 566 /* 567 * Endpoint State - bits 0:2 568 * 0 - disabled 569 * 1 - running 570 * 2 - halted due to halt condition - ok to manipulate endpoint ring 571 * 3 - stopped 572 * 4 - TRB error 573 * 5-7 - reserved 574 */ 575 #define EP_STATE_MASK (0xf) 576 #define EP_STATE_DISABLED 0 577 #define EP_STATE_RUNNING 1 578 #define EP_STATE_HALTED 2 579 #define EP_STATE_STOPPED 3 580 #define EP_STATE_ERROR 4 581 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 582 #define EP_MULT(p) ((p & 0x3) << 8) 583 /* bits 10:14 are Max Primary Streams */ 584 /* bit 15 is Linear Stream Array */ 585 /* Interval - period between requests to an endpoint - 125u increments. */ 586 #define EP_INTERVAL(p) ((p & 0xff) << 16) 587 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 588 589 /* ep_info2 bitmasks */ 590 /* 591 * Force Event - generate transfer events for all TRBs for this endpoint 592 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 593 */ 594 #define FORCE_EVENT (0x1) 595 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 596 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 597 #define EP_TYPE(p) ((p) << 3) 598 #define ISOC_OUT_EP 1 599 #define BULK_OUT_EP 2 600 #define INT_OUT_EP 3 601 #define CTRL_EP 4 602 #define ISOC_IN_EP 5 603 #define BULK_IN_EP 6 604 #define INT_IN_EP 7 605 /* bit 6 reserved */ 606 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 607 #define MAX_BURST(p) (((p)&0xff) << 8) 608 #define MAX_PACKET(p) (((p)&0xffff) << 16) 609 #define MAX_PACKET_MASK (0xffff << 16) 610 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 611 612 613 /** 614 * struct xhci_input_control_context 615 * Input control context; see section 6.2.5. 616 * 617 * @drop_context: set the bit of the endpoint context you want to disable 618 * @add_context: set the bit of the endpoint context you want to enable 619 */ 620 struct xhci_input_control_ctx { 621 u32 drop_flags; 622 u32 add_flags; 623 u32 rsvd2[6]; 624 }; 625 626 /* Represents everything that is needed to issue a command on the command ring. 627 * It's useful to pre-allocate these for commands that cannot fail due to 628 * out-of-memory errors, like freeing streams. 629 */ 630 struct xhci_command { 631 /* Input context for changing device state */ 632 struct xhci_container_ctx *in_ctx; 633 u32 status; 634 /* If completion is null, no one is waiting on this command 635 * and the structure can be freed after the command completes. 636 */ 637 struct completion *completion; 638 union xhci_trb *command_trb; 639 struct list_head cmd_list; 640 }; 641 642 /* drop context bitmasks */ 643 #define DROP_EP(x) (0x1 << x) 644 /* add context bitmasks */ 645 #define ADD_EP(x) (0x1 << x) 646 647 struct xhci_virt_ep { 648 struct xhci_ring *ring; 649 /* Temporary storage in case the configure endpoint command fails and we 650 * have to restore the device state to the previous state 651 */ 652 struct xhci_ring *new_ring; 653 unsigned int ep_state; 654 #define SET_DEQ_PENDING (1 << 0) 655 #define EP_HALTED (1 << 1) 656 /* ---- Related to URB cancellation ---- */ 657 struct list_head cancelled_td_list; 658 unsigned int cancels_pending; 659 /* The TRB that was last reported in a stopped endpoint ring */ 660 union xhci_trb *stopped_trb; 661 struct xhci_td *stopped_td; 662 }; 663 664 struct xhci_virt_device { 665 /* 666 * Commands to the hardware are passed an "input context" that 667 * tells the hardware what to change in its data structures. 668 * The hardware will return changes in an "output context" that 669 * software must allocate for the hardware. We need to keep 670 * track of input and output contexts separately because 671 * these commands might fail and we don't trust the hardware. 672 */ 673 struct xhci_container_ctx *out_ctx; 674 /* Used for addressing devices and configuration changes */ 675 struct xhci_container_ctx *in_ctx; 676 struct xhci_virt_ep eps[31]; 677 struct completion cmd_completion; 678 /* Status of the last command issued for this device */ 679 u32 cmd_status; 680 struct list_head cmd_list; 681 }; 682 683 684 /** 685 * struct xhci_device_context_array 686 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 687 */ 688 struct xhci_device_context_array { 689 /* 64-bit device addresses; we only write 32-bit addresses */ 690 u64 dev_context_ptrs[MAX_HC_SLOTS]; 691 /* private xHCD pointers */ 692 dma_addr_t dma; 693 }; 694 /* TODO: write function to set the 64-bit device DMA address */ 695 /* 696 * TODO: change this to be dynamically sized at HC mem init time since the HC 697 * might not be able to handle the maximum number of devices possible. 698 */ 699 700 701 struct xhci_stream_ctx { 702 /* 64-bit stream ring address, cycle state, and stream type */ 703 u64 stream_ring; 704 /* offset 0x14 - 0x1f reserved for HC internal use */ 705 u32 reserved[2]; 706 }; 707 708 709 struct xhci_transfer_event { 710 /* 64-bit buffer address, or immediate data */ 711 u64 buffer; 712 u32 transfer_len; 713 /* This field is interpreted differently based on the type of TRB */ 714 u32 flags; 715 }; 716 717 /** Transfer Event bit fields **/ 718 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 719 720 /* Completion Code - only applicable for some types of TRBs */ 721 #define COMP_CODE_MASK (0xff << 24) 722 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 723 #define COMP_SUCCESS 1 724 /* Data Buffer Error */ 725 #define COMP_DB_ERR 2 726 /* Babble Detected Error */ 727 #define COMP_BABBLE 3 728 /* USB Transaction Error */ 729 #define COMP_TX_ERR 4 730 /* TRB Error - some TRB field is invalid */ 731 #define COMP_TRB_ERR 5 732 /* Stall Error - USB device is stalled */ 733 #define COMP_STALL 6 734 /* Resource Error - HC doesn't have memory for that device configuration */ 735 #define COMP_ENOMEM 7 736 /* Bandwidth Error - not enough room in schedule for this dev config */ 737 #define COMP_BW_ERR 8 738 /* No Slots Available Error - HC ran out of device slots */ 739 #define COMP_ENOSLOTS 9 740 /* Invalid Stream Type Error */ 741 #define COMP_STREAM_ERR 10 742 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 743 #define COMP_EBADSLT 11 744 /* Endpoint Not Enabled Error */ 745 #define COMP_EBADEP 12 746 /* Short Packet */ 747 #define COMP_SHORT_TX 13 748 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 749 #define COMP_UNDERRUN 14 750 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 751 #define COMP_OVERRUN 15 752 /* Virtual Function Event Ring Full Error */ 753 #define COMP_VF_FULL 16 754 /* Parameter Error - Context parameter is invalid */ 755 #define COMP_EINVAL 17 756 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 757 #define COMP_BW_OVER 18 758 /* Context State Error - illegal context state transition requested */ 759 #define COMP_CTX_STATE 19 760 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 761 #define COMP_PING_ERR 20 762 /* Event Ring is full */ 763 #define COMP_ER_FULL 21 764 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 765 #define COMP_MISSED_INT 23 766 /* Successfully stopped command ring */ 767 #define COMP_CMD_STOP 24 768 /* Successfully aborted current command and stopped command ring */ 769 #define COMP_CMD_ABORT 25 770 /* Stopped - transfer was terminated by a stop endpoint command */ 771 #define COMP_STOP 26 772 /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ 773 #define COMP_STOP_INVAL 27 774 /* Control Abort Error - Debug Capability - control pipe aborted */ 775 #define COMP_DBG_ABORT 28 776 /* TRB type 29 and 30 reserved */ 777 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 778 #define COMP_BUFF_OVER 31 779 /* Event Lost Error - xHC has an "internal event overrun condition" */ 780 #define COMP_ISSUES 32 781 /* Undefined Error - reported when other error codes don't apply */ 782 #define COMP_UNKNOWN 33 783 /* Invalid Stream ID Error */ 784 #define COMP_STRID_ERR 34 785 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 786 /* FIXME - check for this */ 787 #define COMP_2ND_BW_ERR 35 788 /* Split Transaction Error */ 789 #define COMP_SPLIT_ERR 36 790 791 struct xhci_link_trb { 792 /* 64-bit segment pointer*/ 793 u64 segment_ptr; 794 u32 intr_target; 795 u32 control; 796 }; 797 798 /* control bitfields */ 799 #define LINK_TOGGLE (0x1<<1) 800 801 /* Command completion event TRB */ 802 struct xhci_event_cmd { 803 /* Pointer to command TRB, or the value passed by the event data trb */ 804 u64 cmd_trb; 805 u32 status; 806 u32 flags; 807 }; 808 809 /* flags bitmasks */ 810 /* bits 16:23 are the virtual function ID */ 811 /* bits 24:31 are the slot ID */ 812 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 813 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 814 815 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 816 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 817 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 818 819 820 /* Port Status Change Event TRB fields */ 821 /* Port ID - bits 31:24 */ 822 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 823 824 /* Normal TRB fields */ 825 /* transfer_len bitmasks - bits 0:16 */ 826 #define TRB_LEN(p) ((p) & 0x1ffff) 827 /* TD size - number of bytes remaining in the TD (including this TRB): 828 * bits 17 - 21. Shift the number of bytes by 10. */ 829 #define TD_REMAINDER(p) ((((p) >> 10) & 0x1f) << 17) 830 /* Interrupter Target - which MSI-X vector to target the completion event at */ 831 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 832 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 833 834 /* Cycle bit - indicates TRB ownership by HC or HCD */ 835 #define TRB_CYCLE (1<<0) 836 /* 837 * Force next event data TRB to be evaluated before task switch. 838 * Used to pass OS data back after a TD completes. 839 */ 840 #define TRB_ENT (1<<1) 841 /* Interrupt on short packet */ 842 #define TRB_ISP (1<<2) 843 /* Set PCIe no snoop attribute */ 844 #define TRB_NO_SNOOP (1<<3) 845 /* Chain multiple TRBs into a TD */ 846 #define TRB_CHAIN (1<<4) 847 /* Interrupt on completion */ 848 #define TRB_IOC (1<<5) 849 /* The buffer pointer contains immediate data */ 850 #define TRB_IDT (1<<6) 851 852 853 /* Control transfer TRB specific fields */ 854 #define TRB_DIR_IN (1<<16) 855 856 struct xhci_generic_trb { 857 u32 field[4]; 858 }; 859 860 union xhci_trb { 861 struct xhci_link_trb link; 862 struct xhci_transfer_event trans_event; 863 struct xhci_event_cmd event_cmd; 864 struct xhci_generic_trb generic; 865 }; 866 867 /* TRB bit mask */ 868 #define TRB_TYPE_BITMASK (0xfc00) 869 #define TRB_TYPE(p) ((p) << 10) 870 /* TRB type IDs */ 871 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 872 #define TRB_NORMAL 1 873 /* setup stage for control transfers */ 874 #define TRB_SETUP 2 875 /* data stage for control transfers */ 876 #define TRB_DATA 3 877 /* status stage for control transfers */ 878 #define TRB_STATUS 4 879 /* isoc transfers */ 880 #define TRB_ISOC 5 881 /* TRB for linking ring segments */ 882 #define TRB_LINK 6 883 #define TRB_EVENT_DATA 7 884 /* Transfer Ring No-op (not for the command ring) */ 885 #define TRB_TR_NOOP 8 886 /* Command TRBs */ 887 /* Enable Slot Command */ 888 #define TRB_ENABLE_SLOT 9 889 /* Disable Slot Command */ 890 #define TRB_DISABLE_SLOT 10 891 /* Address Device Command */ 892 #define TRB_ADDR_DEV 11 893 /* Configure Endpoint Command */ 894 #define TRB_CONFIG_EP 12 895 /* Evaluate Context Command */ 896 #define TRB_EVAL_CONTEXT 13 897 /* Reset Endpoint Command */ 898 #define TRB_RESET_EP 14 899 /* Stop Transfer Ring Command */ 900 #define TRB_STOP_RING 15 901 /* Set Transfer Ring Dequeue Pointer Command */ 902 #define TRB_SET_DEQ 16 903 /* Reset Device Command */ 904 #define TRB_RESET_DEV 17 905 /* Force Event Command (opt) */ 906 #define TRB_FORCE_EVENT 18 907 /* Negotiate Bandwidth Command (opt) */ 908 #define TRB_NEG_BANDWIDTH 19 909 /* Set Latency Tolerance Value Command (opt) */ 910 #define TRB_SET_LT 20 911 /* Get port bandwidth Command */ 912 #define TRB_GET_BW 21 913 /* Force Header Command - generate a transaction or link management packet */ 914 #define TRB_FORCE_HEADER 22 915 /* No-op Command - not for transfer rings */ 916 #define TRB_CMD_NOOP 23 917 /* TRB IDs 24-31 reserved */ 918 /* Event TRBS */ 919 /* Transfer Event */ 920 #define TRB_TRANSFER 32 921 /* Command Completion Event */ 922 #define TRB_COMPLETION 33 923 /* Port Status Change Event */ 924 #define TRB_PORT_STATUS 34 925 /* Bandwidth Request Event (opt) */ 926 #define TRB_BANDWIDTH_EVENT 35 927 /* Doorbell Event (opt) */ 928 #define TRB_DOORBELL 36 929 /* Host Controller Event */ 930 #define TRB_HC_EVENT 37 931 /* Device Notification Event - device sent function wake notification */ 932 #define TRB_DEV_NOTE 38 933 /* MFINDEX Wrap Event - microframe counter wrapped */ 934 #define TRB_MFINDEX_WRAP 39 935 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 936 937 /* 938 * TRBS_PER_SEGMENT must be a multiple of 4, 939 * since the command ring is 64-byte aligned. 940 * It must also be greater than 16. 941 */ 942 #define TRBS_PER_SEGMENT 64 943 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 944 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 945 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 946 /* TRB buffer pointers can't cross 64KB boundaries */ 947 #define TRB_MAX_BUFF_SHIFT 16 948 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 949 950 struct xhci_segment { 951 union xhci_trb *trbs; 952 /* private to HCD */ 953 struct xhci_segment *next; 954 dma_addr_t dma; 955 }; 956 957 struct xhci_td { 958 struct list_head td_list; 959 struct list_head cancelled_td_list; 960 struct urb *urb; 961 struct xhci_segment *start_seg; 962 union xhci_trb *first_trb; 963 union xhci_trb *last_trb; 964 }; 965 966 struct xhci_dequeue_state { 967 struct xhci_segment *new_deq_seg; 968 union xhci_trb *new_deq_ptr; 969 int new_cycle_state; 970 }; 971 972 struct xhci_ring { 973 struct xhci_segment *first_seg; 974 union xhci_trb *enqueue; 975 struct xhci_segment *enq_seg; 976 unsigned int enq_updates; 977 union xhci_trb *dequeue; 978 struct xhci_segment *deq_seg; 979 unsigned int deq_updates; 980 struct list_head td_list; 981 /* 982 * Write the cycle state into the TRB cycle field to give ownership of 983 * the TRB to the host controller (if we are the producer), or to check 984 * if we own the TRB (if we are the consumer). See section 4.9.1. 985 */ 986 u32 cycle_state; 987 }; 988 989 struct xhci_erst_entry { 990 /* 64-bit event ring segment address */ 991 u64 seg_addr; 992 u32 seg_size; 993 /* Set to zero */ 994 u32 rsvd; 995 }; 996 997 struct xhci_erst { 998 struct xhci_erst_entry *entries; 999 unsigned int num_entries; 1000 /* xhci->event_ring keeps track of segment dma addresses */ 1001 dma_addr_t erst_dma_addr; 1002 /* Num entries the ERST can contain */ 1003 unsigned int erst_size; 1004 }; 1005 1006 struct xhci_scratchpad { 1007 u64 *sp_array; 1008 dma_addr_t sp_dma; 1009 void **sp_buffers; 1010 dma_addr_t *sp_dma_buffers; 1011 }; 1012 1013 /* 1014 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1015 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1016 * meaning 64 ring segments. 1017 * Initial allocated size of the ERST, in number of entries */ 1018 #define ERST_NUM_SEGS 1 1019 /* Initial allocated size of the ERST, in number of entries */ 1020 #define ERST_SIZE 64 1021 /* Initial number of event segment rings allocated */ 1022 #define ERST_ENTRIES 1 1023 /* Poll every 60 seconds */ 1024 #define POLL_TIMEOUT 60 1025 /* XXX: Make these module parameters */ 1026 1027 1028 /* There is one ehci_hci structure per controller */ 1029 struct xhci_hcd { 1030 /* glue to PCI and HCD framework */ 1031 struct xhci_cap_regs __iomem *cap_regs; 1032 struct xhci_op_regs __iomem *op_regs; 1033 struct xhci_run_regs __iomem *run_regs; 1034 struct xhci_doorbell_array __iomem *dba; 1035 /* Our HCD's current interrupter register set */ 1036 struct xhci_intr_reg __iomem *ir_set; 1037 1038 /* Cached register copies of read-only HC data */ 1039 __u32 hcs_params1; 1040 __u32 hcs_params2; 1041 __u32 hcs_params3; 1042 __u32 hcc_params; 1043 1044 spinlock_t lock; 1045 1046 /* packed release number */ 1047 u8 sbrn; 1048 u16 hci_version; 1049 u8 max_slots; 1050 u8 max_interrupters; 1051 u8 max_ports; 1052 u8 isoc_threshold; 1053 int event_ring_max; 1054 int addr_64; 1055 /* 4KB min, 128MB max */ 1056 int page_size; 1057 /* Valid values are 12 to 20, inclusive */ 1058 int page_shift; 1059 /* only one MSI vector for now, but might need more later */ 1060 int msix_count; 1061 struct msix_entry *msix_entries; 1062 /* data structures */ 1063 struct xhci_device_context_array *dcbaa; 1064 struct xhci_ring *cmd_ring; 1065 unsigned int cmd_ring_reserved_trbs; 1066 struct xhci_ring *event_ring; 1067 struct xhci_erst erst; 1068 /* Scratchpad */ 1069 struct xhci_scratchpad *scratchpad; 1070 1071 /* slot enabling and address device helpers */ 1072 struct completion addr_dev; 1073 int slot_id; 1074 /* Internal mirror of the HW's dcbaa */ 1075 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1076 1077 /* DMA pools */ 1078 struct dma_pool *device_pool; 1079 struct dma_pool *segment_pool; 1080 1081 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1082 /* Poll the rings - for debugging */ 1083 struct timer_list event_ring_timer; 1084 int zombie; 1085 #endif 1086 /* Statistics */ 1087 int noops_submitted; 1088 int noops_handled; 1089 int error_bitmask; 1090 unsigned int quirks; 1091 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1092 #define XHCI_RESET_EP_QUIRK (1 << 1) 1093 }; 1094 1095 /* For testing purposes */ 1096 #define NUM_TEST_NOOPS 0 1097 1098 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1099 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1100 { 1101 return (struct xhci_hcd *) (hcd->hcd_priv); 1102 } 1103 1104 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1105 { 1106 return container_of((void *) xhci, struct usb_hcd, hcd_priv); 1107 } 1108 1109 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1110 #define XHCI_DEBUG 1 1111 #else 1112 #define XHCI_DEBUG 0 1113 #endif 1114 1115 #define xhci_dbg(xhci, fmt, args...) \ 1116 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1117 #define xhci_info(xhci, fmt, args...) \ 1118 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1119 #define xhci_err(xhci, fmt, args...) \ 1120 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1121 #define xhci_warn(xhci, fmt, args...) \ 1122 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1123 1124 /* TODO: copied from ehci.h - can be refactored? */ 1125 /* xHCI spec says all registers are little endian */ 1126 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1127 __u32 __iomem *regs) 1128 { 1129 return readl(regs); 1130 } 1131 static inline void xhci_writel(struct xhci_hcd *xhci, 1132 const unsigned int val, __u32 __iomem *regs) 1133 { 1134 xhci_dbg(xhci, 1135 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", 1136 regs, val); 1137 writel(val, regs); 1138 } 1139 1140 /* 1141 * Registers should always be accessed with double word or quad word accesses. 1142 * 1143 * Some xHCI implementations may support 64-bit address pointers. Registers 1144 * with 64-bit address pointers should be written to with dword accesses by 1145 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1146 * xHCI implementations that do not support 64-bit address pointers will ignore 1147 * the high dword, and write order is irrelevant. 1148 */ 1149 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1150 __u64 __iomem *regs) 1151 { 1152 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1153 u64 val_lo = readl(ptr); 1154 u64 val_hi = readl(ptr + 1); 1155 return val_lo + (val_hi << 32); 1156 } 1157 static inline void xhci_write_64(struct xhci_hcd *xhci, 1158 const u64 val, __u64 __iomem *regs) 1159 { 1160 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1161 u32 val_lo = lower_32_bits(val); 1162 u32 val_hi = upper_32_bits(val); 1163 1164 xhci_dbg(xhci, 1165 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n", 1166 regs, (long unsigned int) val); 1167 writel(val_lo, ptr); 1168 writel(val_hi, ptr + 1); 1169 } 1170 1171 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1172 { 1173 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); 1174 return ((HC_VERSION(temp) == 0x95) && 1175 (xhci->quirks & XHCI_LINK_TRB_QUIRK)); 1176 } 1177 1178 /* xHCI debugging */ 1179 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num); 1180 void xhci_print_registers(struct xhci_hcd *xhci); 1181 void xhci_dbg_regs(struct xhci_hcd *xhci); 1182 void xhci_print_run_regs(struct xhci_hcd *xhci); 1183 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1184 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1185 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1186 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1187 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1188 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1189 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1190 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1191 1192 /* xHCI memory management */ 1193 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1194 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1195 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1196 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1197 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1198 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1199 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1200 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1201 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1202 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1203 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1204 struct xhci_container_ctx *in_ctx, 1205 struct xhci_container_ctx *out_ctx, 1206 unsigned int ep_index); 1207 void xhci_slot_copy(struct xhci_hcd *xhci, 1208 struct xhci_container_ctx *in_ctx, 1209 struct xhci_container_ctx *out_ctx); 1210 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1211 struct usb_device *udev, struct usb_host_endpoint *ep, 1212 gfp_t mem_flags); 1213 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1214 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1215 bool allocate_completion, gfp_t mem_flags); 1216 void xhci_free_command(struct xhci_hcd *xhci, 1217 struct xhci_command *command); 1218 1219 #ifdef CONFIG_PCI 1220 /* xHCI PCI glue */ 1221 int xhci_register_pci(void); 1222 void xhci_unregister_pci(void); 1223 #endif 1224 1225 /* xHCI host controller glue */ 1226 int xhci_halt(struct xhci_hcd *xhci); 1227 int xhci_reset(struct xhci_hcd *xhci); 1228 int xhci_init(struct usb_hcd *hcd); 1229 int xhci_run(struct usb_hcd *hcd); 1230 void xhci_stop(struct usb_hcd *hcd); 1231 void xhci_shutdown(struct usb_hcd *hcd); 1232 int xhci_get_frame(struct usb_hcd *hcd); 1233 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1234 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1235 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1236 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1237 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1238 struct usb_tt *tt, gfp_t mem_flags); 1239 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1240 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1241 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1242 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1243 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1244 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1245 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1246 1247 /* xHCI ring, segment, TRB, and TD functions */ 1248 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1249 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1250 void *xhci_setup_one_noop(struct xhci_hcd *xhci); 1251 void xhci_handle_event(struct xhci_hcd *xhci); 1252 void xhci_set_hc_event_deq(struct xhci_hcd *xhci); 1253 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1254 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1255 u32 slot_id); 1256 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1257 unsigned int ep_index); 1258 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1259 int slot_id, unsigned int ep_index); 1260 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1261 int slot_id, unsigned int ep_index); 1262 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1263 int slot_id, unsigned int ep_index); 1264 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1265 u32 slot_id, bool command_must_succeed); 1266 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1267 u32 slot_id); 1268 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1269 unsigned int ep_index); 1270 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1271 unsigned int slot_id, unsigned int ep_index, 1272 struct xhci_td *cur_td, struct xhci_dequeue_state *state); 1273 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1274 unsigned int slot_id, unsigned int ep_index, 1275 struct xhci_dequeue_state *deq_state); 1276 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1277 struct usb_device *udev, unsigned int ep_index); 1278 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1279 unsigned int slot_id, unsigned int ep_index, 1280 struct xhci_dequeue_state *deq_state); 1281 1282 /* xHCI roothub code */ 1283 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1284 char *buf, u16 wLength); 1285 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1286 1287 /* xHCI contexts */ 1288 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1289 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1290 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1291 1292 #endif /* __LINUX_XHCI_HCD_H */ 1293