1 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __LINUX_XHCI_HCD_H 25 #define __LINUX_XHCI_HCD_H 26 27 #include <linux/usb.h> 28 #include <linux/timer.h> 29 #include <linux/kernel.h> 30 #include <linux/usb/hcd.h> 31 32 /* Code sharing between pci-quirks and xhci hcd */ 33 #include "xhci-ext-caps.h" 34 #include "pci-quirks.h" 35 36 /* xHCI PCI Configuration Registers */ 37 #define XHCI_SBRN_OFFSET (0x60) 38 39 /* Max number of USB devices for any host controller - limit in section 6.1 */ 40 #define MAX_HC_SLOTS 256 41 /* Section 5.3.3 - MaxPorts */ 42 #define MAX_HC_PORTS 127 43 44 /* 45 * xHCI register interface. 46 * This corresponds to the eXtensible Host Controller Interface (xHCI) 47 * Revision 0.95 specification 48 */ 49 50 /** 51 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 52 * @hc_capbase: length of the capabilities register and HC version number 53 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 54 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 55 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 56 * @hcc_params: HCCPARAMS - Capability Parameters 57 * @db_off: DBOFF - Doorbell array offset 58 * @run_regs_off: RTSOFF - Runtime register space offset 59 */ 60 struct xhci_cap_regs { 61 __le32 hc_capbase; 62 __le32 hcs_params1; 63 __le32 hcs_params2; 64 __le32 hcs_params3; 65 __le32 hcc_params; 66 __le32 db_off; 67 __le32 run_regs_off; 68 /* Reserved up to (CAPLENGTH - 0x1C) */ 69 }; 70 71 /* hc_capbase bitmasks */ 72 /* bits 7:0 - how long is the Capabilities register */ 73 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 74 /* bits 31:16 */ 75 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 76 77 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 78 /* bits 0:7, Max Device Slots */ 79 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 80 #define HCS_SLOTS_MASK 0xff 81 /* bits 8:18, Max Interrupters */ 82 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 83 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 84 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 85 86 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 87 /* bits 0:3, frames or uframes that SW needs to queue transactions 88 * ahead of the HW to meet periodic deadlines */ 89 #define HCS_IST(p) (((p) >> 0) & 0xf) 90 /* bits 4:7, max number of Event Ring segments */ 91 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 92 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 93 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 94 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 95 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 96 97 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 98 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 99 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 100 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 101 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 102 103 /* HCCPARAMS - hcc_params - bitmasks */ 104 /* true: HC can use 64-bit address pointers */ 105 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 106 /* true: HC can do bandwidth negotiation */ 107 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 108 /* true: HC uses 64-byte Device Context structures 109 * FIXME 64-byte context structures aren't supported yet. 110 */ 111 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 112 /* true: HC has port power switches */ 113 #define HCC_PPC(p) ((p) & (1 << 3)) 114 /* true: HC has port indicators */ 115 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 116 /* true: HC has Light HC Reset Capability */ 117 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 118 /* true: HC supports latency tolerance messaging */ 119 #define HCC_LTC(p) ((p) & (1 << 6)) 120 /* true: no secondary Stream ID Support */ 121 #define HCC_NSS(p) ((p) & (1 << 7)) 122 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 123 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 124 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 125 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 126 127 /* db_off bitmask - bits 0:1 reserved */ 128 #define DBOFF_MASK (~0x3) 129 130 /* run_regs_off bitmask - bits 0:4 reserved */ 131 #define RTSOFF_MASK (~0x1f) 132 133 134 /* Number of registers per port */ 135 #define NUM_PORT_REGS 4 136 137 #define PORTSC 0 138 #define PORTPMSC 1 139 #define PORTLI 2 140 #define PORTHLPMC 3 141 142 /** 143 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 144 * @command: USBCMD - xHC command register 145 * @status: USBSTS - xHC status register 146 * @page_size: This indicates the page size that the host controller 147 * supports. If bit n is set, the HC supports a page size 148 * of 2^(n+12), up to a 128MB page size. 149 * 4K is the minimum page size. 150 * @cmd_ring: CRP - 64-bit Command Ring Pointer 151 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 152 * @config_reg: CONFIG - Configure Register 153 * @port_status_base: PORTSCn - base address for Port Status and Control 154 * Each port has a Port Status and Control register, 155 * followed by a Port Power Management Status and Control 156 * register, a Port Link Info register, and a reserved 157 * register. 158 * @port_power_base: PORTPMSCn - base address for 159 * Port Power Management Status and Control 160 * @port_link_base: PORTLIn - base address for Port Link Info (current 161 * Link PM state and control) for USB 2.1 and USB 3.0 162 * devices. 163 */ 164 struct xhci_op_regs { 165 __le32 command; 166 __le32 status; 167 __le32 page_size; 168 __le32 reserved1; 169 __le32 reserved2; 170 __le32 dev_notification; 171 __le64 cmd_ring; 172 /* rsvd: offset 0x20-2F */ 173 __le32 reserved3[4]; 174 __le64 dcbaa_ptr; 175 __le32 config_reg; 176 /* rsvd: offset 0x3C-3FF */ 177 __le32 reserved4[241]; 178 /* port 1 registers, which serve as a base address for other ports */ 179 __le32 port_status_base; 180 __le32 port_power_base; 181 __le32 port_link_base; 182 __le32 reserved5; 183 /* registers for ports 2-255 */ 184 __le32 reserved6[NUM_PORT_REGS*254]; 185 }; 186 187 /* USBCMD - USB command - command bitmasks */ 188 /* start/stop HC execution - do not write unless HC is halted*/ 189 #define CMD_RUN XHCI_CMD_RUN 190 /* Reset HC - resets internal HC state machine and all registers (except 191 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 192 * The xHCI driver must reinitialize the xHC after setting this bit. 193 */ 194 #define CMD_RESET (1 << 1) 195 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 196 #define CMD_EIE XHCI_CMD_EIE 197 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 198 #define CMD_HSEIE XHCI_CMD_HSEIE 199 /* bits 4:6 are reserved (and should be preserved on writes). */ 200 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 201 #define CMD_LRESET (1 << 7) 202 /* host controller save/restore state. */ 203 #define CMD_CSS (1 << 8) 204 #define CMD_CRS (1 << 9) 205 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 206 #define CMD_EWE XHCI_CMD_EWE 207 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 208 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 209 * '0' means the xHC can power it off if all ports are in the disconnect, 210 * disabled, or powered-off state. 211 */ 212 #define CMD_PM_INDEX (1 << 11) 213 /* bits 12:31 are reserved (and should be preserved on writes). */ 214 215 /* IMAN - Interrupt Management Register */ 216 #define IMAN_IE (1 << 1) 217 #define IMAN_IP (1 << 0) 218 219 /* USBSTS - USB status - status bitmasks */ 220 /* HC not running - set to 1 when run/stop bit is cleared. */ 221 #define STS_HALT XHCI_STS_HALT 222 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 223 #define STS_FATAL (1 << 2) 224 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 225 #define STS_EINT (1 << 3) 226 /* port change detect */ 227 #define STS_PORT (1 << 4) 228 /* bits 5:7 reserved and zeroed */ 229 /* save state status - '1' means xHC is saving state */ 230 #define STS_SAVE (1 << 8) 231 /* restore state status - '1' means xHC is restoring state */ 232 #define STS_RESTORE (1 << 9) 233 /* true: save or restore error */ 234 #define STS_SRE (1 << 10) 235 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 236 #define STS_CNR XHCI_STS_CNR 237 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 238 #define STS_HCE (1 << 12) 239 /* bits 13:31 reserved and should be preserved */ 240 241 /* 242 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 243 * Generate a device notification event when the HC sees a transaction with a 244 * notification type that matches a bit set in this bit field. 245 */ 246 #define DEV_NOTE_MASK (0xffff) 247 #define ENABLE_DEV_NOTE(x) (1 << (x)) 248 /* Most of the device notification types should only be used for debug. 249 * SW does need to pay attention to function wake notifications. 250 */ 251 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 252 253 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 254 /* bit 0 is the command ring cycle state */ 255 /* stop ring operation after completion of the currently executing command */ 256 #define CMD_RING_PAUSE (1 << 1) 257 /* stop ring immediately - abort the currently executing command */ 258 #define CMD_RING_ABORT (1 << 2) 259 /* true: command ring is running */ 260 #define CMD_RING_RUNNING (1 << 3) 261 /* bits 4:5 reserved and should be preserved */ 262 /* Command Ring pointer - bit mask for the lower 32 bits. */ 263 #define CMD_RING_RSVD_BITS (0x3f) 264 265 /* CONFIG - Configure Register - config_reg bitmasks */ 266 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 267 #define MAX_DEVS(p) ((p) & 0xff) 268 /* bits 8:31 - reserved and should be preserved */ 269 270 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 271 /* true: device connected */ 272 #define PORT_CONNECT (1 << 0) 273 /* true: port enabled */ 274 #define PORT_PE (1 << 1) 275 /* bit 2 reserved and zeroed */ 276 /* true: port has an over-current condition */ 277 #define PORT_OC (1 << 3) 278 /* true: port reset signaling asserted */ 279 #define PORT_RESET (1 << 4) 280 /* Port Link State - bits 5:8 281 * A read gives the current link PM state of the port, 282 * a write with Link State Write Strobe set sets the link state. 283 */ 284 #define PORT_PLS_MASK (0xf << 5) 285 #define XDEV_U0 (0x0 << 5) 286 #define XDEV_U2 (0x2 << 5) 287 #define XDEV_U3 (0x3 << 5) 288 #define XDEV_RESUME (0xf << 5) 289 /* true: port has power (see HCC_PPC) */ 290 #define PORT_POWER (1 << 9) 291 /* bits 10:13 indicate device speed: 292 * 0 - undefined speed - port hasn't be initialized by a reset yet 293 * 1 - full speed 294 * 2 - low speed 295 * 3 - high speed 296 * 4 - super speed 297 * 5-15 reserved 298 */ 299 #define DEV_SPEED_MASK (0xf << 10) 300 #define XDEV_FS (0x1 << 10) 301 #define XDEV_LS (0x2 << 10) 302 #define XDEV_HS (0x3 << 10) 303 #define XDEV_SS (0x4 << 10) 304 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 305 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 306 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 307 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 308 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 309 /* Bits 20:23 in the Slot Context are the speed for the device */ 310 #define SLOT_SPEED_FS (XDEV_FS << 10) 311 #define SLOT_SPEED_LS (XDEV_LS << 10) 312 #define SLOT_SPEED_HS (XDEV_HS << 10) 313 #define SLOT_SPEED_SS (XDEV_SS << 10) 314 /* Port Indicator Control */ 315 #define PORT_LED_OFF (0 << 14) 316 #define PORT_LED_AMBER (1 << 14) 317 #define PORT_LED_GREEN (2 << 14) 318 #define PORT_LED_MASK (3 << 14) 319 /* Port Link State Write Strobe - set this when changing link state */ 320 #define PORT_LINK_STROBE (1 << 16) 321 /* true: connect status change */ 322 #define PORT_CSC (1 << 17) 323 /* true: port enable change */ 324 #define PORT_PEC (1 << 18) 325 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 326 * into an enabled state, and the device into the default state. A "warm" reset 327 * also resets the link, forcing the device through the link training sequence. 328 * SW can also look at the Port Reset register to see when warm reset is done. 329 */ 330 #define PORT_WRC (1 << 19) 331 /* true: over-current change */ 332 #define PORT_OCC (1 << 20) 333 /* true: reset change - 1 to 0 transition of PORT_RESET */ 334 #define PORT_RC (1 << 21) 335 /* port link status change - set on some port link state transitions: 336 * Transition Reason 337 * ------------------------------------------------------------------------------ 338 * - U3 to Resume Wakeup signaling from a device 339 * - Resume to Recovery to U0 USB 3.0 device resume 340 * - Resume to U0 USB 2.0 device resume 341 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 342 * - U3 to U0 Software resume of USB 2.0 device complete 343 * - U2 to U0 L1 resume of USB 2.1 device complete 344 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 345 * - U0 to disabled L1 entry error with USB 2.1 device 346 * - Any state to inactive Error on USB 3.0 port 347 */ 348 #define PORT_PLC (1 << 22) 349 /* port configure error change - port failed to configure its link partner */ 350 #define PORT_CEC (1 << 23) 351 /* Cold Attach Status - xHC can set this bit to report device attached during 352 * Sx state. Warm port reset should be perfomed to clear this bit and move port 353 * to connected state. 354 */ 355 #define PORT_CAS (1 << 24) 356 /* wake on connect (enable) */ 357 #define PORT_WKCONN_E (1 << 25) 358 /* wake on disconnect (enable) */ 359 #define PORT_WKDISC_E (1 << 26) 360 /* wake on over-current (enable) */ 361 #define PORT_WKOC_E (1 << 27) 362 /* bits 28:29 reserved */ 363 /* true: device is non-removable - for USB 3.0 roothub emulation */ 364 #define PORT_DEV_REMOVE (1 << 30) 365 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 366 #define PORT_WR (1 << 31) 367 368 /* We mark duplicate entries with -1 */ 369 #define DUPLICATE_ENTRY ((u8)(-1)) 370 371 /* Port Power Management Status and Control - port_power_base bitmasks */ 372 /* Inactivity timer value for transitions into U1, in microseconds. 373 * Timeout can be up to 127us. 0xFF means an infinite timeout. 374 */ 375 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 376 #define PORT_U1_TIMEOUT_MASK 0xff 377 /* Inactivity timer value for transitions into U2 */ 378 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 379 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 380 /* Bits 24:31 for port testing */ 381 382 /* USB2 Protocol PORTSPMSC */ 383 #define PORT_L1S_MASK 7 384 #define PORT_L1S_SUCCESS 1 385 #define PORT_RWE (1 << 3) 386 #define PORT_HIRD(p) (((p) & 0xf) << 4) 387 #define PORT_HIRD_MASK (0xf << 4) 388 #define PORT_L1DS_MASK (0xff << 8) 389 #define PORT_L1DS(p) (((p) & 0xff) << 8) 390 #define PORT_HLE (1 << 16) 391 392 393 /* USB2 Protocol PORTHLPMC */ 394 #define PORT_HIRDM(p)((p) & 3) 395 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 396 #define PORT_BESLD(p)(((p) & 0xf) << 10) 397 398 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 399 #define XHCI_L1_TIMEOUT 512 400 401 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 402 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 403 * by other operating systems. 404 * 405 * XHCI 1.0 errata 8/14/12 Table 13 notes: 406 * "Software should choose xHC BESL/BESLD field values that do not violate a 407 * device's resume latency requirements, 408 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 409 * or not program values < '4' if BLC = '0' and a BESL device is attached. 410 */ 411 #define XHCI_DEFAULT_BESL 4 412 413 /** 414 * struct xhci_intr_reg - Interrupt Register Set 415 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 416 * interrupts and check for pending interrupts. 417 * @irq_control: IMOD - Interrupt Moderation Register. 418 * Used to throttle interrupts. 419 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 420 * @erst_base: ERST base address. 421 * @erst_dequeue: Event ring dequeue pointer. 422 * 423 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 424 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 425 * multiple segments of the same size. The HC places events on the ring and 426 * "updates the Cycle bit in the TRBs to indicate to software the current 427 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 428 * updates the dequeue pointer. 429 */ 430 struct xhci_intr_reg { 431 __le32 irq_pending; 432 __le32 irq_control; 433 __le32 erst_size; 434 __le32 rsvd; 435 __le64 erst_base; 436 __le64 erst_dequeue; 437 }; 438 439 /* irq_pending bitmasks */ 440 #define ER_IRQ_PENDING(p) ((p) & 0x1) 441 /* bits 2:31 need to be preserved */ 442 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 443 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 444 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 445 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 446 447 /* irq_control bitmasks */ 448 /* Minimum interval between interrupts (in 250ns intervals). The interval 449 * between interrupts will be longer if there are no events on the event ring. 450 * Default is 4000 (1 ms). 451 */ 452 #define ER_IRQ_INTERVAL_MASK (0xffff) 453 /* Counter used to count down the time to the next interrupt - HW use only */ 454 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 455 456 /* erst_size bitmasks */ 457 /* Preserve bits 16:31 of erst_size */ 458 #define ERST_SIZE_MASK (0xffff << 16) 459 460 /* erst_dequeue bitmasks */ 461 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 462 * where the current dequeue pointer lies. This is an optional HW hint. 463 */ 464 #define ERST_DESI_MASK (0x7) 465 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 466 * a work queue (or delayed service routine)? 467 */ 468 #define ERST_EHB (1 << 3) 469 #define ERST_PTR_MASK (0xf) 470 471 /** 472 * struct xhci_run_regs 473 * @microframe_index: 474 * MFINDEX - current microframe number 475 * 476 * Section 5.5 Host Controller Runtime Registers: 477 * "Software should read and write these registers using only Dword (32 bit) 478 * or larger accesses" 479 */ 480 struct xhci_run_regs { 481 __le32 microframe_index; 482 __le32 rsvd[7]; 483 struct xhci_intr_reg ir_set[128]; 484 }; 485 486 /** 487 * struct doorbell_array 488 * 489 * Bits 0 - 7: Endpoint target 490 * Bits 8 - 15: RsvdZ 491 * Bits 16 - 31: Stream ID 492 * 493 * Section 5.6 494 */ 495 struct xhci_doorbell_array { 496 __le32 doorbell[256]; 497 }; 498 499 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 500 #define DB_VALUE_HOST 0x00000000 501 502 /** 503 * struct xhci_protocol_caps 504 * @revision: major revision, minor revision, capability ID, 505 * and next capability pointer. 506 * @name_string: Four ASCII characters to say which spec this xHC 507 * follows, typically "USB ". 508 * @port_info: Port offset, count, and protocol-defined information. 509 */ 510 struct xhci_protocol_caps { 511 u32 revision; 512 u32 name_string; 513 u32 port_info; 514 }; 515 516 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 517 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 518 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 519 520 /** 521 * struct xhci_container_ctx 522 * @type: Type of context. Used to calculated offsets to contained contexts. 523 * @size: Size of the context data 524 * @bytes: The raw context data given to HW 525 * @dma: dma address of the bytes 526 * 527 * Represents either a Device or Input context. Holds a pointer to the raw 528 * memory used for the context (bytes) and dma address of it (dma). 529 */ 530 struct xhci_container_ctx { 531 unsigned type; 532 #define XHCI_CTX_TYPE_DEVICE 0x1 533 #define XHCI_CTX_TYPE_INPUT 0x2 534 535 int size; 536 537 u8 *bytes; 538 dma_addr_t dma; 539 }; 540 541 /** 542 * struct xhci_slot_ctx 543 * @dev_info: Route string, device speed, hub info, and last valid endpoint 544 * @dev_info2: Max exit latency for device number, root hub port number 545 * @tt_info: tt_info is used to construct split transaction tokens 546 * @dev_state: slot state and device address 547 * 548 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 549 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 550 * reserved at the end of the slot context for HC internal use. 551 */ 552 struct xhci_slot_ctx { 553 __le32 dev_info; 554 __le32 dev_info2; 555 __le32 tt_info; 556 __le32 dev_state; 557 /* offset 0x10 to 0x1f reserved for HC internal use */ 558 __le32 reserved[4]; 559 }; 560 561 /* dev_info bitmasks */ 562 /* Route String - 0:19 */ 563 #define ROUTE_STRING_MASK (0xfffff) 564 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 565 #define DEV_SPEED (0xf << 20) 566 /* bit 24 reserved */ 567 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 568 #define DEV_MTT (0x1 << 25) 569 /* Set if the device is a hub - bit 26 */ 570 #define DEV_HUB (0x1 << 26) 571 /* Index of the last valid endpoint context in this device context - 27:31 */ 572 #define LAST_CTX_MASK (0x1f << 27) 573 #define LAST_CTX(p) ((p) << 27) 574 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 575 #define SLOT_FLAG (1 << 0) 576 #define EP0_FLAG (1 << 1) 577 578 /* dev_info2 bitmasks */ 579 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 580 #define MAX_EXIT (0xffff) 581 /* Root hub port number that is needed to access the USB device */ 582 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 583 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 584 /* Maximum number of ports under a hub device */ 585 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 586 587 /* tt_info bitmasks */ 588 /* 589 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 590 * The Slot ID of the hub that isolates the high speed signaling from 591 * this low or full-speed device. '0' if attached to root hub port. 592 */ 593 #define TT_SLOT (0xff) 594 /* 595 * The number of the downstream facing port of the high-speed hub 596 * '0' if the device is not low or full speed. 597 */ 598 #define TT_PORT (0xff << 8) 599 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 600 601 /* dev_state bitmasks */ 602 /* USB device address - assigned by the HC */ 603 #define DEV_ADDR_MASK (0xff) 604 /* bits 8:26 reserved */ 605 /* Slot state */ 606 #define SLOT_STATE (0x1f << 27) 607 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 608 609 #define SLOT_STATE_DISABLED 0 610 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 611 #define SLOT_STATE_DEFAULT 1 612 #define SLOT_STATE_ADDRESSED 2 613 #define SLOT_STATE_CONFIGURED 3 614 615 /** 616 * struct xhci_ep_ctx 617 * @ep_info: endpoint state, streams, mult, and interval information. 618 * @ep_info2: information on endpoint type, max packet size, max burst size, 619 * error count, and whether the HC will force an event for all 620 * transactions. 621 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 622 * defines one stream, this points to the endpoint transfer ring. 623 * Otherwise, it points to a stream context array, which has a 624 * ring pointer for each flow. 625 * @tx_info: 626 * Average TRB lengths for the endpoint ring and 627 * max payload within an Endpoint Service Interval Time (ESIT). 628 * 629 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 630 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 631 * reserved at the end of the endpoint context for HC internal use. 632 */ 633 struct xhci_ep_ctx { 634 __le32 ep_info; 635 __le32 ep_info2; 636 __le64 deq; 637 __le32 tx_info; 638 /* offset 0x14 - 0x1f reserved for HC internal use */ 639 __le32 reserved[3]; 640 }; 641 642 /* ep_info bitmasks */ 643 /* 644 * Endpoint State - bits 0:2 645 * 0 - disabled 646 * 1 - running 647 * 2 - halted due to halt condition - ok to manipulate endpoint ring 648 * 3 - stopped 649 * 4 - TRB error 650 * 5-7 - reserved 651 */ 652 #define EP_STATE_MASK (0xf) 653 #define EP_STATE_DISABLED 0 654 #define EP_STATE_RUNNING 1 655 #define EP_STATE_HALTED 2 656 #define EP_STATE_STOPPED 3 657 #define EP_STATE_ERROR 4 658 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 659 #define EP_MULT(p) (((p) & 0x3) << 8) 660 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 661 /* bits 10:14 are Max Primary Streams */ 662 /* bit 15 is Linear Stream Array */ 663 /* Interval - period between requests to an endpoint - 125u increments. */ 664 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 665 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 666 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 667 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 668 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 669 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 670 #define EP_HAS_LSA (1 << 15) 671 672 /* ep_info2 bitmasks */ 673 /* 674 * Force Event - generate transfer events for all TRBs for this endpoint 675 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 676 */ 677 #define FORCE_EVENT (0x1) 678 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 679 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 680 #define EP_TYPE(p) ((p) << 3) 681 #define ISOC_OUT_EP 1 682 #define BULK_OUT_EP 2 683 #define INT_OUT_EP 3 684 #define CTRL_EP 4 685 #define ISOC_IN_EP 5 686 #define BULK_IN_EP 6 687 #define INT_IN_EP 7 688 /* bit 6 reserved */ 689 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 690 #define MAX_BURST(p) (((p)&0xff) << 8) 691 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 692 #define MAX_PACKET(p) (((p)&0xffff) << 16) 693 #define MAX_PACKET_MASK (0xffff << 16) 694 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 695 696 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 697 * USB2.0 spec 9.6.6. 698 */ 699 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 700 701 /* tx_info bitmasks */ 702 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 703 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 704 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 705 706 /* deq bitmasks */ 707 #define EP_CTX_CYCLE_MASK (1 << 0) 708 #define SCTX_DEQ_MASK (~0xfL) 709 710 711 /** 712 * struct xhci_input_control_context 713 * Input control context; see section 6.2.5. 714 * 715 * @drop_context: set the bit of the endpoint context you want to disable 716 * @add_context: set the bit of the endpoint context you want to enable 717 */ 718 struct xhci_input_control_ctx { 719 __le32 drop_flags; 720 __le32 add_flags; 721 __le32 rsvd2[6]; 722 }; 723 724 #define EP_IS_ADDED(ctrl_ctx, i) \ 725 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 726 #define EP_IS_DROPPED(ctrl_ctx, i) \ 727 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 728 729 /* Represents everything that is needed to issue a command on the command ring. 730 * It's useful to pre-allocate these for commands that cannot fail due to 731 * out-of-memory errors, like freeing streams. 732 */ 733 struct xhci_command { 734 /* Input context for changing device state */ 735 struct xhci_container_ctx *in_ctx; 736 u32 status; 737 /* If completion is null, no one is waiting on this command 738 * and the structure can be freed after the command completes. 739 */ 740 struct completion *completion; 741 union xhci_trb *command_trb; 742 struct list_head cmd_list; 743 }; 744 745 /* drop context bitmasks */ 746 #define DROP_EP(x) (0x1 << x) 747 /* add context bitmasks */ 748 #define ADD_EP(x) (0x1 << x) 749 750 struct xhci_stream_ctx { 751 /* 64-bit stream ring address, cycle state, and stream type */ 752 __le64 stream_ring; 753 /* offset 0x14 - 0x1f reserved for HC internal use */ 754 __le32 reserved[2]; 755 }; 756 757 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 758 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 759 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 760 #define SCT_SEC_TR 0 761 /* Primary stream array type, dequeue pointer is to a transfer ring */ 762 #define SCT_PRI_TR 1 763 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 764 #define SCT_SSA_8 2 765 #define SCT_SSA_16 3 766 #define SCT_SSA_32 4 767 #define SCT_SSA_64 5 768 #define SCT_SSA_128 6 769 #define SCT_SSA_256 7 770 771 /* Assume no secondary streams for now */ 772 struct xhci_stream_info { 773 struct xhci_ring **stream_rings; 774 /* Number of streams, including stream 0 (which drivers can't use) */ 775 unsigned int num_streams; 776 /* The stream context array may be bigger than 777 * the number of streams the driver asked for 778 */ 779 struct xhci_stream_ctx *stream_ctx_array; 780 unsigned int num_stream_ctxs; 781 dma_addr_t ctx_array_dma; 782 /* For mapping physical TRB addresses to segments in stream rings */ 783 struct radix_tree_root trb_address_map; 784 struct xhci_command *free_streams_command; 785 }; 786 787 #define SMALL_STREAM_ARRAY_SIZE 256 788 #define MEDIUM_STREAM_ARRAY_SIZE 1024 789 790 /* Some Intel xHCI host controllers need software to keep track of the bus 791 * bandwidth. Keep track of endpoint info here. Each root port is allocated 792 * the full bus bandwidth. We must also treat TTs (including each port under a 793 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 794 * (DMI) also limits the total bandwidth (across all domains) that can be used. 795 */ 796 struct xhci_bw_info { 797 /* ep_interval is zero-based */ 798 unsigned int ep_interval; 799 /* mult and num_packets are one-based */ 800 unsigned int mult; 801 unsigned int num_packets; 802 unsigned int max_packet_size; 803 unsigned int max_esit_payload; 804 unsigned int type; 805 }; 806 807 /* "Block" sizes in bytes the hardware uses for different device speeds. 808 * The logic in this part of the hardware limits the number of bits the hardware 809 * can use, so must represent bandwidth in a less precise manner to mimic what 810 * the scheduler hardware computes. 811 */ 812 #define FS_BLOCK 1 813 #define HS_BLOCK 4 814 #define SS_BLOCK 16 815 #define DMI_BLOCK 32 816 817 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 818 * with each byte transferred. SuperSpeed devices have an initial overhead to 819 * set up bursts. These are in blocks, see above. LS overhead has already been 820 * translated into FS blocks. 821 */ 822 #define DMI_OVERHEAD 8 823 #define DMI_OVERHEAD_BURST 4 824 #define SS_OVERHEAD 8 825 #define SS_OVERHEAD_BURST 32 826 #define HS_OVERHEAD 26 827 #define FS_OVERHEAD 20 828 #define LS_OVERHEAD 128 829 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 830 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 831 * of overhead associated with split transfers crossing microframe boundaries. 832 * 31 blocks is pure protocol overhead. 833 */ 834 #define TT_HS_OVERHEAD (31 + 94) 835 #define TT_DMI_OVERHEAD (25 + 12) 836 837 /* Bandwidth limits in blocks */ 838 #define FS_BW_LIMIT 1285 839 #define TT_BW_LIMIT 1320 840 #define HS_BW_LIMIT 1607 841 #define SS_BW_LIMIT_IN 3906 842 #define DMI_BW_LIMIT_IN 3906 843 #define SS_BW_LIMIT_OUT 3906 844 #define DMI_BW_LIMIT_OUT 3906 845 846 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 847 #define FS_BW_RESERVED 10 848 #define HS_BW_RESERVED 20 849 #define SS_BW_RESERVED 10 850 851 struct xhci_virt_ep { 852 struct xhci_ring *ring; 853 /* Related to endpoints that are configured to use stream IDs only */ 854 struct xhci_stream_info *stream_info; 855 /* Temporary storage in case the configure endpoint command fails and we 856 * have to restore the device state to the previous state 857 */ 858 struct xhci_ring *new_ring; 859 unsigned int ep_state; 860 #define SET_DEQ_PENDING (1 << 0) 861 #define EP_HALTED (1 << 1) /* For stall handling */ 862 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 863 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 864 #define EP_GETTING_STREAMS (1 << 3) 865 #define EP_HAS_STREAMS (1 << 4) 866 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 867 #define EP_GETTING_NO_STREAMS (1 << 5) 868 #define EP_RECENTLY_HALTED (1 << 6) 869 #define EP_CONFIG_PENDING (1 << 7) 870 /* ---- Related to URB cancellation ---- */ 871 struct list_head cancelled_td_list; 872 struct xhci_td *stopped_td; 873 unsigned int stopped_stream; 874 /* Watchdog timer for stop endpoint command to cancel URBs */ 875 struct timer_list stop_cmd_timer; 876 int stop_cmds_pending; 877 struct xhci_hcd *xhci; 878 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 879 * command. We'll need to update the ring's dequeue segment and dequeue 880 * pointer after the command completes. 881 */ 882 struct xhci_segment *queued_deq_seg; 883 union xhci_trb *queued_deq_ptr; 884 /* 885 * Sometimes the xHC can not process isochronous endpoint ring quickly 886 * enough, and it will miss some isoc tds on the ring and generate 887 * a Missed Service Error Event. 888 * Set skip flag when receive a Missed Service Error Event and 889 * process the missed tds on the endpoint ring. 890 */ 891 bool skip; 892 /* Bandwidth checking storage */ 893 struct xhci_bw_info bw_info; 894 struct list_head bw_endpoint_list; 895 }; 896 897 enum xhci_overhead_type { 898 LS_OVERHEAD_TYPE = 0, 899 FS_OVERHEAD_TYPE, 900 HS_OVERHEAD_TYPE, 901 }; 902 903 struct xhci_interval_bw { 904 unsigned int num_packets; 905 /* Sorted by max packet size. 906 * Head of the list is the greatest max packet size. 907 */ 908 struct list_head endpoints; 909 /* How many endpoints of each speed are present. */ 910 unsigned int overhead[3]; 911 }; 912 913 #define XHCI_MAX_INTERVAL 16 914 915 struct xhci_interval_bw_table { 916 unsigned int interval0_esit_payload; 917 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 918 /* Includes reserved bandwidth for async endpoints */ 919 unsigned int bw_used; 920 unsigned int ss_bw_in; 921 unsigned int ss_bw_out; 922 }; 923 924 925 struct xhci_virt_device { 926 struct usb_device *udev; 927 /* 928 * Commands to the hardware are passed an "input context" that 929 * tells the hardware what to change in its data structures. 930 * The hardware will return changes in an "output context" that 931 * software must allocate for the hardware. We need to keep 932 * track of input and output contexts separately because 933 * these commands might fail and we don't trust the hardware. 934 */ 935 struct xhci_container_ctx *out_ctx; 936 /* Used for addressing devices and configuration changes */ 937 struct xhci_container_ctx *in_ctx; 938 /* Rings saved to ensure old alt settings can be re-instated */ 939 struct xhci_ring **ring_cache; 940 int num_rings_cached; 941 #define XHCI_MAX_RINGS_CACHED 31 942 struct xhci_virt_ep eps[31]; 943 struct completion cmd_completion; 944 u8 fake_port; 945 u8 real_port; 946 struct xhci_interval_bw_table *bw_table; 947 struct xhci_tt_bw_info *tt_info; 948 /* The current max exit latency for the enabled USB3 link states. */ 949 u16 current_mel; 950 }; 951 952 /* 953 * For each roothub, keep track of the bandwidth information for each periodic 954 * interval. 955 * 956 * If a high speed hub is attached to the roothub, each TT associated with that 957 * hub is a separate bandwidth domain. The interval information for the 958 * endpoints on the devices under that TT will appear in the TT structure. 959 */ 960 struct xhci_root_port_bw_info { 961 struct list_head tts; 962 unsigned int num_active_tts; 963 struct xhci_interval_bw_table bw_table; 964 }; 965 966 struct xhci_tt_bw_info { 967 struct list_head tt_list; 968 int slot_id; 969 int ttport; 970 struct xhci_interval_bw_table bw_table; 971 int active_eps; 972 }; 973 974 975 /** 976 * struct xhci_device_context_array 977 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 978 */ 979 struct xhci_device_context_array { 980 /* 64-bit device addresses; we only write 32-bit addresses */ 981 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 982 /* private xHCD pointers */ 983 dma_addr_t dma; 984 }; 985 /* TODO: write function to set the 64-bit device DMA address */ 986 /* 987 * TODO: change this to be dynamically sized at HC mem init time since the HC 988 * might not be able to handle the maximum number of devices possible. 989 */ 990 991 992 struct xhci_transfer_event { 993 /* 64-bit buffer address, or immediate data */ 994 __le64 buffer; 995 __le32 transfer_len; 996 /* This field is interpreted differently based on the type of TRB */ 997 __le32 flags; 998 }; 999 1000 /* Transfer event TRB length bit mask */ 1001 /* bits 0:23 */ 1002 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1003 1004 /** Transfer Event bit fields **/ 1005 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1006 1007 /* Completion Code - only applicable for some types of TRBs */ 1008 #define COMP_CODE_MASK (0xff << 24) 1009 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1010 #define COMP_SUCCESS 1 1011 /* Data Buffer Error */ 1012 #define COMP_DB_ERR 2 1013 /* Babble Detected Error */ 1014 #define COMP_BABBLE 3 1015 /* USB Transaction Error */ 1016 #define COMP_TX_ERR 4 1017 /* TRB Error - some TRB field is invalid */ 1018 #define COMP_TRB_ERR 5 1019 /* Stall Error - USB device is stalled */ 1020 #define COMP_STALL 6 1021 /* Resource Error - HC doesn't have memory for that device configuration */ 1022 #define COMP_ENOMEM 7 1023 /* Bandwidth Error - not enough room in schedule for this dev config */ 1024 #define COMP_BW_ERR 8 1025 /* No Slots Available Error - HC ran out of device slots */ 1026 #define COMP_ENOSLOTS 9 1027 /* Invalid Stream Type Error */ 1028 #define COMP_STREAM_ERR 10 1029 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 1030 #define COMP_EBADSLT 11 1031 /* Endpoint Not Enabled Error */ 1032 #define COMP_EBADEP 12 1033 /* Short Packet */ 1034 #define COMP_SHORT_TX 13 1035 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 1036 #define COMP_UNDERRUN 14 1037 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 1038 #define COMP_OVERRUN 15 1039 /* Virtual Function Event Ring Full Error */ 1040 #define COMP_VF_FULL 16 1041 /* Parameter Error - Context parameter is invalid */ 1042 #define COMP_EINVAL 17 1043 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 1044 #define COMP_BW_OVER 18 1045 /* Context State Error - illegal context state transition requested */ 1046 #define COMP_CTX_STATE 19 1047 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 1048 #define COMP_PING_ERR 20 1049 /* Event Ring is full */ 1050 #define COMP_ER_FULL 21 1051 /* Incompatible Device Error */ 1052 #define COMP_DEV_ERR 22 1053 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 1054 #define COMP_MISSED_INT 23 1055 /* Successfully stopped command ring */ 1056 #define COMP_CMD_STOP 24 1057 /* Successfully aborted current command and stopped command ring */ 1058 #define COMP_CMD_ABORT 25 1059 /* Stopped - transfer was terminated by a stop endpoint command */ 1060 #define COMP_STOP 26 1061 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 1062 #define COMP_STOP_INVAL 27 1063 /* Control Abort Error - Debug Capability - control pipe aborted */ 1064 #define COMP_DBG_ABORT 28 1065 /* Max Exit Latency Too Large Error */ 1066 #define COMP_MEL_ERR 29 1067 /* TRB type 30 reserved */ 1068 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 1069 #define COMP_BUFF_OVER 31 1070 /* Event Lost Error - xHC has an "internal event overrun condition" */ 1071 #define COMP_ISSUES 32 1072 /* Undefined Error - reported when other error codes don't apply */ 1073 #define COMP_UNKNOWN 33 1074 /* Invalid Stream ID Error */ 1075 #define COMP_STRID_ERR 34 1076 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 1077 #define COMP_2ND_BW_ERR 35 1078 /* Split Transaction Error */ 1079 #define COMP_SPLIT_ERR 36 1080 1081 struct xhci_link_trb { 1082 /* 64-bit segment pointer*/ 1083 __le64 segment_ptr; 1084 __le32 intr_target; 1085 __le32 control; 1086 }; 1087 1088 /* control bitfields */ 1089 #define LINK_TOGGLE (0x1<<1) 1090 1091 /* Command completion event TRB */ 1092 struct xhci_event_cmd { 1093 /* Pointer to command TRB, or the value passed by the event data trb */ 1094 __le64 cmd_trb; 1095 __le32 status; 1096 __le32 flags; 1097 }; 1098 1099 /* flags bitmasks */ 1100 1101 /* Address device - disable SetAddress */ 1102 #define TRB_BSR (1<<9) 1103 enum xhci_setup_dev { 1104 SETUP_CONTEXT_ONLY, 1105 SETUP_CONTEXT_ADDRESS, 1106 }; 1107 1108 /* bits 16:23 are the virtual function ID */ 1109 /* bits 24:31 are the slot ID */ 1110 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1111 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1112 1113 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1114 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1115 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1116 1117 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1118 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1119 #define LAST_EP_INDEX 30 1120 1121 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1122 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1123 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1124 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1125 1126 1127 /* Port Status Change Event TRB fields */ 1128 /* Port ID - bits 31:24 */ 1129 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1130 1131 /* Normal TRB fields */ 1132 /* transfer_len bitmasks - bits 0:16 */ 1133 #define TRB_LEN(p) ((p) & 0x1ffff) 1134 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1135 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1136 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1137 #define TRB_TBC(p) (((p) & 0x3) << 7) 1138 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1139 1140 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1141 #define TRB_CYCLE (1<<0) 1142 /* 1143 * Force next event data TRB to be evaluated before task switch. 1144 * Used to pass OS data back after a TD completes. 1145 */ 1146 #define TRB_ENT (1<<1) 1147 /* Interrupt on short packet */ 1148 #define TRB_ISP (1<<2) 1149 /* Set PCIe no snoop attribute */ 1150 #define TRB_NO_SNOOP (1<<3) 1151 /* Chain multiple TRBs into a TD */ 1152 #define TRB_CHAIN (1<<4) 1153 /* Interrupt on completion */ 1154 #define TRB_IOC (1<<5) 1155 /* The buffer pointer contains immediate data */ 1156 #define TRB_IDT (1<<6) 1157 1158 /* Block Event Interrupt */ 1159 #define TRB_BEI (1<<9) 1160 1161 /* Control transfer TRB specific fields */ 1162 #define TRB_DIR_IN (1<<16) 1163 #define TRB_TX_TYPE(p) ((p) << 16) 1164 #define TRB_DATA_OUT 2 1165 #define TRB_DATA_IN 3 1166 1167 /* Isochronous TRB specific fields */ 1168 #define TRB_SIA (1<<31) 1169 1170 struct xhci_generic_trb { 1171 __le32 field[4]; 1172 }; 1173 1174 union xhci_trb { 1175 struct xhci_link_trb link; 1176 struct xhci_transfer_event trans_event; 1177 struct xhci_event_cmd event_cmd; 1178 struct xhci_generic_trb generic; 1179 }; 1180 1181 /* TRB bit mask */ 1182 #define TRB_TYPE_BITMASK (0xfc00) 1183 #define TRB_TYPE(p) ((p) << 10) 1184 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1185 /* TRB type IDs */ 1186 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1187 #define TRB_NORMAL 1 1188 /* setup stage for control transfers */ 1189 #define TRB_SETUP 2 1190 /* data stage for control transfers */ 1191 #define TRB_DATA 3 1192 /* status stage for control transfers */ 1193 #define TRB_STATUS 4 1194 /* isoc transfers */ 1195 #define TRB_ISOC 5 1196 /* TRB for linking ring segments */ 1197 #define TRB_LINK 6 1198 #define TRB_EVENT_DATA 7 1199 /* Transfer Ring No-op (not for the command ring) */ 1200 #define TRB_TR_NOOP 8 1201 /* Command TRBs */ 1202 /* Enable Slot Command */ 1203 #define TRB_ENABLE_SLOT 9 1204 /* Disable Slot Command */ 1205 #define TRB_DISABLE_SLOT 10 1206 /* Address Device Command */ 1207 #define TRB_ADDR_DEV 11 1208 /* Configure Endpoint Command */ 1209 #define TRB_CONFIG_EP 12 1210 /* Evaluate Context Command */ 1211 #define TRB_EVAL_CONTEXT 13 1212 /* Reset Endpoint Command */ 1213 #define TRB_RESET_EP 14 1214 /* Stop Transfer Ring Command */ 1215 #define TRB_STOP_RING 15 1216 /* Set Transfer Ring Dequeue Pointer Command */ 1217 #define TRB_SET_DEQ 16 1218 /* Reset Device Command */ 1219 #define TRB_RESET_DEV 17 1220 /* Force Event Command (opt) */ 1221 #define TRB_FORCE_EVENT 18 1222 /* Negotiate Bandwidth Command (opt) */ 1223 #define TRB_NEG_BANDWIDTH 19 1224 /* Set Latency Tolerance Value Command (opt) */ 1225 #define TRB_SET_LT 20 1226 /* Get port bandwidth Command */ 1227 #define TRB_GET_BW 21 1228 /* Force Header Command - generate a transaction or link management packet */ 1229 #define TRB_FORCE_HEADER 22 1230 /* No-op Command - not for transfer rings */ 1231 #define TRB_CMD_NOOP 23 1232 /* TRB IDs 24-31 reserved */ 1233 /* Event TRBS */ 1234 /* Transfer Event */ 1235 #define TRB_TRANSFER 32 1236 /* Command Completion Event */ 1237 #define TRB_COMPLETION 33 1238 /* Port Status Change Event */ 1239 #define TRB_PORT_STATUS 34 1240 /* Bandwidth Request Event (opt) */ 1241 #define TRB_BANDWIDTH_EVENT 35 1242 /* Doorbell Event (opt) */ 1243 #define TRB_DOORBELL 36 1244 /* Host Controller Event */ 1245 #define TRB_HC_EVENT 37 1246 /* Device Notification Event - device sent function wake notification */ 1247 #define TRB_DEV_NOTE 38 1248 /* MFINDEX Wrap Event - microframe counter wrapped */ 1249 #define TRB_MFINDEX_WRAP 39 1250 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1251 1252 /* Nec vendor-specific command completion event. */ 1253 #define TRB_NEC_CMD_COMP 48 1254 /* Get NEC firmware revision. */ 1255 #define TRB_NEC_GET_FW 49 1256 1257 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1258 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1259 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1260 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1261 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1262 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1263 1264 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1265 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1266 1267 /* 1268 * TRBS_PER_SEGMENT must be a multiple of 4, 1269 * since the command ring is 64-byte aligned. 1270 * It must also be greater than 16. 1271 */ 1272 #define TRBS_PER_SEGMENT 64 1273 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1274 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1275 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1276 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1277 /* TRB buffer pointers can't cross 64KB boundaries */ 1278 #define TRB_MAX_BUFF_SHIFT 16 1279 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1280 1281 struct xhci_segment { 1282 union xhci_trb *trbs; 1283 /* private to HCD */ 1284 struct xhci_segment *next; 1285 dma_addr_t dma; 1286 }; 1287 1288 struct xhci_td { 1289 struct list_head td_list; 1290 struct list_head cancelled_td_list; 1291 struct urb *urb; 1292 struct xhci_segment *start_seg; 1293 union xhci_trb *first_trb; 1294 union xhci_trb *last_trb; 1295 /* actual_length of the URB has already been set */ 1296 bool urb_length_set; 1297 }; 1298 1299 /* xHCI command default timeout value */ 1300 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1301 1302 /* command descriptor */ 1303 struct xhci_cd { 1304 struct xhci_command *command; 1305 union xhci_trb *cmd_trb; 1306 }; 1307 1308 struct xhci_dequeue_state { 1309 struct xhci_segment *new_deq_seg; 1310 union xhci_trb *new_deq_ptr; 1311 int new_cycle_state; 1312 }; 1313 1314 enum xhci_ring_type { 1315 TYPE_CTRL = 0, 1316 TYPE_ISOC, 1317 TYPE_BULK, 1318 TYPE_INTR, 1319 TYPE_STREAM, 1320 TYPE_COMMAND, 1321 TYPE_EVENT, 1322 }; 1323 1324 struct xhci_ring { 1325 struct xhci_segment *first_seg; 1326 struct xhci_segment *last_seg; 1327 union xhci_trb *enqueue; 1328 struct xhci_segment *enq_seg; 1329 unsigned int enq_updates; 1330 union xhci_trb *dequeue; 1331 struct xhci_segment *deq_seg; 1332 unsigned int deq_updates; 1333 struct list_head td_list; 1334 /* 1335 * Write the cycle state into the TRB cycle field to give ownership of 1336 * the TRB to the host controller (if we are the producer), or to check 1337 * if we own the TRB (if we are the consumer). See section 4.9.1. 1338 */ 1339 u32 cycle_state; 1340 unsigned int stream_id; 1341 unsigned int num_segs; 1342 unsigned int num_trbs_free; 1343 unsigned int num_trbs_free_temp; 1344 enum xhci_ring_type type; 1345 bool last_td_was_short; 1346 struct radix_tree_root *trb_address_map; 1347 }; 1348 1349 struct xhci_erst_entry { 1350 /* 64-bit event ring segment address */ 1351 __le64 seg_addr; 1352 __le32 seg_size; 1353 /* Set to zero */ 1354 __le32 rsvd; 1355 }; 1356 1357 struct xhci_erst { 1358 struct xhci_erst_entry *entries; 1359 unsigned int num_entries; 1360 /* xhci->event_ring keeps track of segment dma addresses */ 1361 dma_addr_t erst_dma_addr; 1362 /* Num entries the ERST can contain */ 1363 unsigned int erst_size; 1364 }; 1365 1366 struct xhci_scratchpad { 1367 u64 *sp_array; 1368 dma_addr_t sp_dma; 1369 void **sp_buffers; 1370 dma_addr_t *sp_dma_buffers; 1371 }; 1372 1373 struct urb_priv { 1374 int length; 1375 int td_cnt; 1376 struct xhci_td *td[0]; 1377 }; 1378 1379 /* 1380 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1381 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1382 * meaning 64 ring segments. 1383 * Initial allocated size of the ERST, in number of entries */ 1384 #define ERST_NUM_SEGS 1 1385 /* Initial allocated size of the ERST, in number of entries */ 1386 #define ERST_SIZE 64 1387 /* Initial number of event segment rings allocated */ 1388 #define ERST_ENTRIES 1 1389 /* Poll every 60 seconds */ 1390 #define POLL_TIMEOUT 60 1391 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1392 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1393 /* XXX: Make these module parameters */ 1394 1395 struct s3_save { 1396 u32 command; 1397 u32 dev_nt; 1398 u64 dcbaa_ptr; 1399 u32 config_reg; 1400 u32 irq_pending; 1401 u32 irq_control; 1402 u32 erst_size; 1403 u64 erst_base; 1404 u64 erst_dequeue; 1405 }; 1406 1407 /* Use for lpm */ 1408 struct dev_info { 1409 u32 dev_id; 1410 struct list_head list; 1411 }; 1412 1413 struct xhci_bus_state { 1414 unsigned long bus_suspended; 1415 unsigned long next_statechange; 1416 1417 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1418 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1419 u32 port_c_suspend; 1420 u32 suspended_ports; 1421 u32 port_remote_wakeup; 1422 unsigned long resume_done[USB_MAXCHILDREN]; 1423 /* which ports have started to resume */ 1424 unsigned long resuming_ports; 1425 /* Which ports are waiting on RExit to U0 transition. */ 1426 unsigned long rexit_ports; 1427 struct completion rexit_done[USB_MAXCHILDREN]; 1428 }; 1429 1430 1431 /* 1432 * It can take up to 20 ms to transition from RExit to U0 on the 1433 * Intel Lynx Point LP xHCI host. 1434 */ 1435 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1436 1437 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1438 { 1439 if (hcd->speed == HCD_USB3) 1440 return 0; 1441 else 1442 return 1; 1443 } 1444 1445 /* There is one xhci_hcd structure per controller */ 1446 struct xhci_hcd { 1447 struct usb_hcd *main_hcd; 1448 struct usb_hcd *shared_hcd; 1449 /* glue to PCI and HCD framework */ 1450 struct xhci_cap_regs __iomem *cap_regs; 1451 struct xhci_op_regs __iomem *op_regs; 1452 struct xhci_run_regs __iomem *run_regs; 1453 struct xhci_doorbell_array __iomem *dba; 1454 /* Our HCD's current interrupter register set */ 1455 struct xhci_intr_reg __iomem *ir_set; 1456 1457 /* Cached register copies of read-only HC data */ 1458 __u32 hcs_params1; 1459 __u32 hcs_params2; 1460 __u32 hcs_params3; 1461 __u32 hcc_params; 1462 1463 spinlock_t lock; 1464 1465 /* packed release number */ 1466 u8 sbrn; 1467 u16 hci_version; 1468 u8 max_slots; 1469 u8 max_interrupters; 1470 u8 max_ports; 1471 u8 isoc_threshold; 1472 int event_ring_max; 1473 int addr_64; 1474 /* 4KB min, 128MB max */ 1475 int page_size; 1476 /* Valid values are 12 to 20, inclusive */ 1477 int page_shift; 1478 /* msi-x vectors */ 1479 int msix_count; 1480 struct msix_entry *msix_entries; 1481 /* optional clock */ 1482 struct clk *clk; 1483 /* data structures */ 1484 struct xhci_device_context_array *dcbaa; 1485 struct xhci_ring *cmd_ring; 1486 unsigned int cmd_ring_state; 1487 #define CMD_RING_STATE_RUNNING (1 << 0) 1488 #define CMD_RING_STATE_ABORTED (1 << 1) 1489 #define CMD_RING_STATE_STOPPED (1 << 2) 1490 struct list_head cmd_list; 1491 unsigned int cmd_ring_reserved_trbs; 1492 struct timer_list cmd_timer; 1493 struct xhci_command *current_cmd; 1494 struct xhci_ring *event_ring; 1495 struct xhci_erst erst; 1496 /* Scratchpad */ 1497 struct xhci_scratchpad *scratchpad; 1498 /* Store LPM test failed devices' information */ 1499 struct list_head lpm_failed_devs; 1500 1501 /* slot enabling and address device helpers */ 1502 struct completion addr_dev; 1503 int slot_id; 1504 /* For USB 3.0 LPM enable/disable. */ 1505 struct xhci_command *lpm_command; 1506 /* Internal mirror of the HW's dcbaa */ 1507 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1508 /* For keeping track of bandwidth domains per roothub. */ 1509 struct xhci_root_port_bw_info *rh_bw; 1510 1511 /* DMA pools */ 1512 struct dma_pool *device_pool; 1513 struct dma_pool *segment_pool; 1514 struct dma_pool *small_streams_pool; 1515 struct dma_pool *medium_streams_pool; 1516 1517 /* Host controller watchdog timer structures */ 1518 unsigned int xhc_state; 1519 1520 u32 command; 1521 struct s3_save s3; 1522 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1523 * 1524 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1525 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1526 * that sees this status (other than the timer that set it) should stop touching 1527 * hardware immediately. Interrupt handlers should return immediately when 1528 * they see this status (any time they drop and re-acquire xhci->lock). 1529 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1530 * putting the TD on the canceled list, etc. 1531 * 1532 * There are no reports of xHCI host controllers that display this issue. 1533 */ 1534 #define XHCI_STATE_DYING (1 << 0) 1535 #define XHCI_STATE_HALTED (1 << 1) 1536 /* Statistics */ 1537 int error_bitmask; 1538 unsigned int quirks; 1539 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1540 #define XHCI_RESET_EP_QUIRK (1 << 1) 1541 #define XHCI_NEC_HOST (1 << 2) 1542 #define XHCI_AMD_PLL_FIX (1 << 3) 1543 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1544 /* 1545 * Certain Intel host controllers have a limit to the number of endpoint 1546 * contexts they can handle. Ideally, they would signal that they can't handle 1547 * anymore endpoint contexts by returning a Resource Error for the Configure 1548 * Endpoint command, but they don't. Instead they expect software to keep track 1549 * of the number of active endpoints for them, across configure endpoint 1550 * commands, reset device commands, disable slot commands, and address device 1551 * commands. 1552 */ 1553 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1554 #define XHCI_BROKEN_MSI (1 << 6) 1555 #define XHCI_RESET_ON_RESUME (1 << 7) 1556 #define XHCI_SW_BW_CHECKING (1 << 8) 1557 #define XHCI_AMD_0x96_HOST (1 << 9) 1558 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1559 #define XHCI_LPM_SUPPORT (1 << 11) 1560 #define XHCI_INTEL_HOST (1 << 12) 1561 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1562 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1563 #define XHCI_AVOID_BEI (1 << 15) 1564 #define XHCI_PLAT (1 << 16) 1565 #define XHCI_SLOW_SUSPEND (1 << 17) 1566 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1567 /* For controllers with a broken beyond repair streams implementation */ 1568 #define XHCI_BROKEN_STREAMS (1 << 19) 1569 #define XHCI_PME_STUCK_QUIRK (1 << 20) 1570 unsigned int num_active_eps; 1571 unsigned int limit_active_eps; 1572 /* There are two roothubs to keep track of bus suspend info for */ 1573 struct xhci_bus_state bus_state[2]; 1574 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1575 u8 *port_array; 1576 /* Array of pointers to USB 3.0 PORTSC registers */ 1577 __le32 __iomem **usb3_ports; 1578 unsigned int num_usb3_ports; 1579 /* Array of pointers to USB 2.0 PORTSC registers */ 1580 __le32 __iomem **usb2_ports; 1581 unsigned int num_usb2_ports; 1582 /* support xHCI 0.96 spec USB2 software LPM */ 1583 unsigned sw_lpm_support:1; 1584 /* support xHCI 1.0 spec USB2 hardware LPM */ 1585 unsigned hw_lpm_support:1; 1586 /* cached usb2 extened protocol capabilites */ 1587 u32 *ext_caps; 1588 unsigned int num_ext_caps; 1589 /* Compliance Mode Recovery Data */ 1590 struct timer_list comp_mode_recovery_timer; 1591 u32 port_status_u0; 1592 /* Compliance Mode Timer Triggered every 2 seconds */ 1593 #define COMP_MODE_RCVRY_MSECS 2000 1594 }; 1595 1596 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1597 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1598 { 1599 return *((struct xhci_hcd **) (hcd->hcd_priv)); 1600 } 1601 1602 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1603 { 1604 return xhci->main_hcd; 1605 } 1606 1607 #define xhci_dbg(xhci, fmt, args...) \ 1608 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1609 #define xhci_err(xhci, fmt, args...) \ 1610 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1611 #define xhci_warn(xhci, fmt, args...) \ 1612 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1613 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1614 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1615 #define xhci_info(xhci, fmt, args...) \ 1616 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1617 1618 /* 1619 * Registers should always be accessed with double word or quad word accesses. 1620 * 1621 * Some xHCI implementations may support 64-bit address pointers. Registers 1622 * with 64-bit address pointers should be written to with dword accesses by 1623 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1624 * xHCI implementations that do not support 64-bit address pointers will ignore 1625 * the high dword, and write order is irrelevant. 1626 */ 1627 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1628 __le64 __iomem *regs) 1629 { 1630 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1631 u64 val_lo = readl(ptr); 1632 u64 val_hi = readl(ptr + 1); 1633 return val_lo + (val_hi << 32); 1634 } 1635 static inline void xhci_write_64(struct xhci_hcd *xhci, 1636 const u64 val, __le64 __iomem *regs) 1637 { 1638 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1639 u32 val_lo = lower_32_bits(val); 1640 u32 val_hi = upper_32_bits(val); 1641 1642 writel(val_lo, ptr); 1643 writel(val_hi, ptr + 1); 1644 } 1645 1646 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1647 { 1648 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1649 } 1650 1651 /* xHCI debugging */ 1652 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1653 void xhci_print_registers(struct xhci_hcd *xhci); 1654 void xhci_dbg_regs(struct xhci_hcd *xhci); 1655 void xhci_print_run_regs(struct xhci_hcd *xhci); 1656 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1657 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1658 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1659 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1660 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1661 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1662 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1663 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1664 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1665 struct xhci_container_ctx *ctx); 1666 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1667 unsigned int slot_id, unsigned int ep_index, 1668 struct xhci_virt_ep *ep); 1669 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1670 const char *fmt, ...); 1671 1672 /* xHCI memory management */ 1673 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1674 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1675 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1676 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1677 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1678 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1679 struct usb_device *udev); 1680 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1681 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1682 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1683 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1684 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1685 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1686 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1687 struct xhci_bw_info *ep_bw, 1688 struct xhci_interval_bw_table *bw_table, 1689 struct usb_device *udev, 1690 struct xhci_virt_ep *virt_ep, 1691 struct xhci_tt_bw_info *tt_info); 1692 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1693 struct xhci_virt_device *virt_dev, 1694 int old_active_eps); 1695 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1696 void xhci_update_bw_info(struct xhci_hcd *xhci, 1697 struct xhci_container_ctx *in_ctx, 1698 struct xhci_input_control_ctx *ctrl_ctx, 1699 struct xhci_virt_device *virt_dev); 1700 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1701 struct xhci_container_ctx *in_ctx, 1702 struct xhci_container_ctx *out_ctx, 1703 unsigned int ep_index); 1704 void xhci_slot_copy(struct xhci_hcd *xhci, 1705 struct xhci_container_ctx *in_ctx, 1706 struct xhci_container_ctx *out_ctx); 1707 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1708 struct usb_device *udev, struct usb_host_endpoint *ep, 1709 gfp_t mem_flags); 1710 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1711 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1712 unsigned int num_trbs, gfp_t flags); 1713 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1714 struct xhci_virt_device *virt_dev, 1715 unsigned int ep_index); 1716 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1717 unsigned int num_stream_ctxs, 1718 unsigned int num_streams, gfp_t flags); 1719 void xhci_free_stream_info(struct xhci_hcd *xhci, 1720 struct xhci_stream_info *stream_info); 1721 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1722 struct xhci_ep_ctx *ep_ctx, 1723 struct xhci_stream_info *stream_info); 1724 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1725 struct xhci_virt_ep *ep); 1726 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1727 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1728 struct xhci_ring *xhci_dma_to_transfer_ring( 1729 struct xhci_virt_ep *ep, 1730 u64 address); 1731 struct xhci_ring *xhci_stream_id_to_ring( 1732 struct xhci_virt_device *dev, 1733 unsigned int ep_index, 1734 unsigned int stream_id); 1735 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1736 bool allocate_in_ctx, bool allocate_completion, 1737 gfp_t mem_flags); 1738 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1739 void xhci_free_command(struct xhci_hcd *xhci, 1740 struct xhci_command *command); 1741 1742 /* xHCI host controller glue */ 1743 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1744 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 1745 void xhci_quiesce(struct xhci_hcd *xhci); 1746 int xhci_halt(struct xhci_hcd *xhci); 1747 int xhci_reset(struct xhci_hcd *xhci); 1748 int xhci_init(struct usb_hcd *hcd); 1749 int xhci_run(struct usb_hcd *hcd); 1750 void xhci_stop(struct usb_hcd *hcd); 1751 void xhci_shutdown(struct usb_hcd *hcd); 1752 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1753 void xhci_init_driver(struct hc_driver *drv, int (*setup_fn)(struct usb_hcd *)); 1754 1755 #ifdef CONFIG_PM 1756 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1757 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1758 #else 1759 #define xhci_suspend NULL 1760 #define xhci_resume NULL 1761 #endif 1762 1763 int xhci_get_frame(struct usb_hcd *hcd); 1764 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1765 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1766 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1767 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1768 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1769 struct xhci_virt_device *virt_dev, 1770 struct usb_device *hdev, 1771 struct usb_tt *tt, gfp_t mem_flags); 1772 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1773 struct usb_host_endpoint **eps, unsigned int num_eps, 1774 unsigned int num_streams, gfp_t mem_flags); 1775 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1776 struct usb_host_endpoint **eps, unsigned int num_eps, 1777 gfp_t mem_flags); 1778 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1779 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); 1780 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 1781 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 1782 struct usb_device *udev, int enable); 1783 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1784 struct usb_tt *tt, gfp_t mem_flags); 1785 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1786 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1787 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1788 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1789 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1790 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1791 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1792 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1793 1794 /* xHCI ring, segment, TRB, and TD functions */ 1795 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1796 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 1797 struct xhci_segment *start_seg, union xhci_trb *start_trb, 1798 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 1799 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1800 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1801 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1802 u32 trb_type, u32 slot_id); 1803 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1804 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1805 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1806 u32 field1, u32 field2, u32 field3, u32 field4); 1807 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1808 int slot_id, unsigned int ep_index, int suspend); 1809 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1810 int slot_id, unsigned int ep_index); 1811 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1812 int slot_id, unsigned int ep_index); 1813 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1814 int slot_id, unsigned int ep_index); 1815 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1816 struct urb *urb, int slot_id, unsigned int ep_index); 1817 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1818 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1819 bool command_must_succeed); 1820 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1821 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1822 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1823 int slot_id, unsigned int ep_index); 1824 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1825 u32 slot_id); 1826 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1827 unsigned int slot_id, unsigned int ep_index, 1828 unsigned int stream_id, struct xhci_td *cur_td, 1829 struct xhci_dequeue_state *state); 1830 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1831 unsigned int slot_id, unsigned int ep_index, 1832 unsigned int stream_id, 1833 struct xhci_dequeue_state *deq_state); 1834 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1835 unsigned int ep_index, struct xhci_td *td); 1836 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1837 unsigned int slot_id, unsigned int ep_index, 1838 struct xhci_dequeue_state *deq_state); 1839 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1840 void xhci_handle_command_timeout(unsigned long data); 1841 1842 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1843 unsigned int ep_index, unsigned int stream_id); 1844 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1845 1846 /* xHCI roothub code */ 1847 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1848 int port_id, u32 link_state); 1849 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, 1850 struct usb_device *udev, enum usb3_link_state state); 1851 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, 1852 struct usb_device *udev, enum usb3_link_state state); 1853 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1854 int port_id, u32 port_bit); 1855 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1856 char *buf, u16 wLength); 1857 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1858 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1859 1860 #ifdef CONFIG_PM 1861 int xhci_bus_suspend(struct usb_hcd *hcd); 1862 int xhci_bus_resume(struct usb_hcd *hcd); 1863 #else 1864 #define xhci_bus_suspend NULL 1865 #define xhci_bus_resume NULL 1866 #endif /* CONFIG_PM */ 1867 1868 u32 xhci_port_state_to_neutral(u32 state); 1869 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1870 u16 port); 1871 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1872 1873 /* xHCI contexts */ 1874 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1875 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1876 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1877 1878 #endif /* __LINUX_XHCI_HCD_H */ 1879