1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 #include <linux/kernel.h> 29 #include <linux/usb/hcd.h> 30 31 /* Code sharing between pci-quirks and xhci hcd */ 32 #include "xhci-ext-caps.h" 33 #include "pci-quirks.h" 34 35 /* xHCI PCI Configuration Registers */ 36 #define XHCI_SBRN_OFFSET (0x60) 37 38 /* Max number of USB devices for any host controller - limit in section 6.1 */ 39 #define MAX_HC_SLOTS 256 40 /* Section 5.3.3 - MaxPorts */ 41 #define MAX_HC_PORTS 127 42 43 /* 44 * xHCI register interface. 45 * This corresponds to the eXtensible Host Controller Interface (xHCI) 46 * Revision 0.95 specification 47 */ 48 49 /** 50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 51 * @hc_capbase: length of the capabilities register and HC version number 52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 55 * @hcc_params: HCCPARAMS - Capability Parameters 56 * @db_off: DBOFF - Doorbell array offset 57 * @run_regs_off: RTSOFF - Runtime register space offset 58 */ 59 struct xhci_cap_regs { 60 __le32 hc_capbase; 61 __le32 hcs_params1; 62 __le32 hcs_params2; 63 __le32 hcs_params3; 64 __le32 hcc_params; 65 __le32 db_off; 66 __le32 run_regs_off; 67 /* Reserved up to (CAPLENGTH - 0x1C) */ 68 }; 69 70 /* hc_capbase bitmasks */ 71 /* bits 7:0 - how long is the Capabilities register */ 72 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 73 /* bits 31:16 */ 74 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 75 76 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 77 /* bits 0:7, Max Device Slots */ 78 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 79 #define HCS_SLOTS_MASK 0xff 80 /* bits 8:18, Max Interrupters */ 81 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 83 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 84 85 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 86 /* bits 0:3, frames or uframes that SW needs to queue transactions 87 * ahead of the HW to meet periodic deadlines */ 88 #define HCS_IST(p) (((p) >> 0) & 0xf) 89 /* bits 4:7, max number of Event Ring segments */ 90 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 93 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 94 95 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 97 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 99 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 100 101 /* HCCPARAMS - hcc_params - bitmasks */ 102 /* true: HC can use 64-bit address pointers */ 103 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 104 /* true: HC can do bandwidth negotiation */ 105 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 106 /* true: HC uses 64-byte Device Context structures 107 * FIXME 64-byte context structures aren't supported yet. 108 */ 109 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 110 /* true: HC has port power switches */ 111 #define HCC_PPC(p) ((p) & (1 << 3)) 112 /* true: HC has port indicators */ 113 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 114 /* true: HC has Light HC Reset Capability */ 115 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 116 /* true: HC supports latency tolerance messaging */ 117 #define HCC_LTC(p) ((p) & (1 << 6)) 118 /* true: no secondary Stream ID Support */ 119 #define HCC_NSS(p) ((p) & (1 << 7)) 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 124 125 /* db_off bitmask - bits 0:1 reserved */ 126 #define DBOFF_MASK (~0x3) 127 128 /* run_regs_off bitmask - bits 0:4 reserved */ 129 #define RTSOFF_MASK (~0x1f) 130 131 132 /* Number of registers per port */ 133 #define NUM_PORT_REGS 4 134 135 /** 136 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 137 * @command: USBCMD - xHC command register 138 * @status: USBSTS - xHC status register 139 * @page_size: This indicates the page size that the host controller 140 * supports. If bit n is set, the HC supports a page size 141 * of 2^(n+12), up to a 128MB page size. 142 * 4K is the minimum page size. 143 * @cmd_ring: CRP - 64-bit Command Ring Pointer 144 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 145 * @config_reg: CONFIG - Configure Register 146 * @port_status_base: PORTSCn - base address for Port Status and Control 147 * Each port has a Port Status and Control register, 148 * followed by a Port Power Management Status and Control 149 * register, a Port Link Info register, and a reserved 150 * register. 151 * @port_power_base: PORTPMSCn - base address for 152 * Port Power Management Status and Control 153 * @port_link_base: PORTLIn - base address for Port Link Info (current 154 * Link PM state and control) for USB 2.1 and USB 3.0 155 * devices. 156 */ 157 struct xhci_op_regs { 158 __le32 command; 159 __le32 status; 160 __le32 page_size; 161 __le32 reserved1; 162 __le32 reserved2; 163 __le32 dev_notification; 164 __le64 cmd_ring; 165 /* rsvd: offset 0x20-2F */ 166 __le32 reserved3[4]; 167 __le64 dcbaa_ptr; 168 __le32 config_reg; 169 /* rsvd: offset 0x3C-3FF */ 170 __le32 reserved4[241]; 171 /* port 1 registers, which serve as a base address for other ports */ 172 __le32 port_status_base; 173 __le32 port_power_base; 174 __le32 port_link_base; 175 __le32 reserved5; 176 /* registers for ports 2-255 */ 177 __le32 reserved6[NUM_PORT_REGS*254]; 178 }; 179 180 /* USBCMD - USB command - command bitmasks */ 181 /* start/stop HC execution - do not write unless HC is halted*/ 182 #define CMD_RUN XHCI_CMD_RUN 183 /* Reset HC - resets internal HC state machine and all registers (except 184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 185 * The xHCI driver must reinitialize the xHC after setting this bit. 186 */ 187 #define CMD_RESET (1 << 1) 188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 189 #define CMD_EIE XHCI_CMD_EIE 190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 191 #define CMD_HSEIE XHCI_CMD_HSEIE 192 /* bits 4:6 are reserved (and should be preserved on writes). */ 193 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 194 #define CMD_LRESET (1 << 7) 195 /* host controller save/restore state. */ 196 #define CMD_CSS (1 << 8) 197 #define CMD_CRS (1 << 9) 198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 199 #define CMD_EWE XHCI_CMD_EWE 200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 202 * '0' means the xHC can power it off if all ports are in the disconnect, 203 * disabled, or powered-off state. 204 */ 205 #define CMD_PM_INDEX (1 << 11) 206 /* bits 12:31 are reserved (and should be preserved on writes). */ 207 208 /* IMAN - Interrupt Management Register */ 209 #define IMAN_IP (1 << 1) 210 #define IMAN_IE (1 << 0) 211 212 /* USBSTS - USB status - status bitmasks */ 213 /* HC not running - set to 1 when run/stop bit is cleared. */ 214 #define STS_HALT XHCI_STS_HALT 215 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 216 #define STS_FATAL (1 << 2) 217 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 218 #define STS_EINT (1 << 3) 219 /* port change detect */ 220 #define STS_PORT (1 << 4) 221 /* bits 5:7 reserved and zeroed */ 222 /* save state status - '1' means xHC is saving state */ 223 #define STS_SAVE (1 << 8) 224 /* restore state status - '1' means xHC is restoring state */ 225 #define STS_RESTORE (1 << 9) 226 /* true: save or restore error */ 227 #define STS_SRE (1 << 10) 228 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 229 #define STS_CNR XHCI_STS_CNR 230 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 231 #define STS_HCE (1 << 12) 232 /* bits 13:31 reserved and should be preserved */ 233 234 /* 235 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 236 * Generate a device notification event when the HC sees a transaction with a 237 * notification type that matches a bit set in this bit field. 238 */ 239 #define DEV_NOTE_MASK (0xffff) 240 #define ENABLE_DEV_NOTE(x) (1 << (x)) 241 /* Most of the device notification types should only be used for debug. 242 * SW does need to pay attention to function wake notifications. 243 */ 244 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 245 246 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 247 /* bit 0 is the command ring cycle state */ 248 /* stop ring operation after completion of the currently executing command */ 249 #define CMD_RING_PAUSE (1 << 1) 250 /* stop ring immediately - abort the currently executing command */ 251 #define CMD_RING_ABORT (1 << 2) 252 /* true: command ring is running */ 253 #define CMD_RING_RUNNING (1 << 3) 254 /* bits 4:5 reserved and should be preserved */ 255 /* Command Ring pointer - bit mask for the lower 32 bits. */ 256 #define CMD_RING_RSVD_BITS (0x3f) 257 258 /* CONFIG - Configure Register - config_reg bitmasks */ 259 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 260 #define MAX_DEVS(p) ((p) & 0xff) 261 /* bits 8:31 - reserved and should be preserved */ 262 263 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 264 /* true: device connected */ 265 #define PORT_CONNECT (1 << 0) 266 /* true: port enabled */ 267 #define PORT_PE (1 << 1) 268 /* bit 2 reserved and zeroed */ 269 /* true: port has an over-current condition */ 270 #define PORT_OC (1 << 3) 271 /* true: port reset signaling asserted */ 272 #define PORT_RESET (1 << 4) 273 /* Port Link State - bits 5:8 274 * A read gives the current link PM state of the port, 275 * a write with Link State Write Strobe set sets the link state. 276 */ 277 #define PORT_PLS_MASK (0xf << 5) 278 #define XDEV_U0 (0x0 << 5) 279 #define XDEV_U2 (0x2 << 5) 280 #define XDEV_U3 (0x3 << 5) 281 #define XDEV_RESUME (0xf << 5) 282 /* true: port has power (see HCC_PPC) */ 283 #define PORT_POWER (1 << 9) 284 /* bits 10:13 indicate device speed: 285 * 0 - undefined speed - port hasn't be initialized by a reset yet 286 * 1 - full speed 287 * 2 - low speed 288 * 3 - high speed 289 * 4 - super speed 290 * 5-15 reserved 291 */ 292 #define DEV_SPEED_MASK (0xf << 10) 293 #define XDEV_FS (0x1 << 10) 294 #define XDEV_LS (0x2 << 10) 295 #define XDEV_HS (0x3 << 10) 296 #define XDEV_SS (0x4 << 10) 297 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 298 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 299 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 300 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 301 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 302 /* Bits 20:23 in the Slot Context are the speed for the device */ 303 #define SLOT_SPEED_FS (XDEV_FS << 10) 304 #define SLOT_SPEED_LS (XDEV_LS << 10) 305 #define SLOT_SPEED_HS (XDEV_HS << 10) 306 #define SLOT_SPEED_SS (XDEV_SS << 10) 307 /* Port Indicator Control */ 308 #define PORT_LED_OFF (0 << 14) 309 #define PORT_LED_AMBER (1 << 14) 310 #define PORT_LED_GREEN (2 << 14) 311 #define PORT_LED_MASK (3 << 14) 312 /* Port Link State Write Strobe - set this when changing link state */ 313 #define PORT_LINK_STROBE (1 << 16) 314 /* true: connect status change */ 315 #define PORT_CSC (1 << 17) 316 /* true: port enable change */ 317 #define PORT_PEC (1 << 18) 318 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 319 * into an enabled state, and the device into the default state. A "warm" reset 320 * also resets the link, forcing the device through the link training sequence. 321 * SW can also look at the Port Reset register to see when warm reset is done. 322 */ 323 #define PORT_WRC (1 << 19) 324 /* true: over-current change */ 325 #define PORT_OCC (1 << 20) 326 /* true: reset change - 1 to 0 transition of PORT_RESET */ 327 #define PORT_RC (1 << 21) 328 /* port link status change - set on some port link state transitions: 329 * Transition Reason 330 * ------------------------------------------------------------------------------ 331 * - U3 to Resume Wakeup signaling from a device 332 * - Resume to Recovery to U0 USB 3.0 device resume 333 * - Resume to U0 USB 2.0 device resume 334 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 335 * - U3 to U0 Software resume of USB 2.0 device complete 336 * - U2 to U0 L1 resume of USB 2.1 device complete 337 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 338 * - U0 to disabled L1 entry error with USB 2.1 device 339 * - Any state to inactive Error on USB 3.0 port 340 */ 341 #define PORT_PLC (1 << 22) 342 /* port configure error change - port failed to configure its link partner */ 343 #define PORT_CEC (1 << 23) 344 /* bit 24 reserved */ 345 /* wake on connect (enable) */ 346 #define PORT_WKCONN_E (1 << 25) 347 /* wake on disconnect (enable) */ 348 #define PORT_WKDISC_E (1 << 26) 349 /* wake on over-current (enable) */ 350 #define PORT_WKOC_E (1 << 27) 351 /* bits 28:29 reserved */ 352 /* true: device is removable - for USB 3.0 roothub emulation */ 353 #define PORT_DEV_REMOVE (1 << 30) 354 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 355 #define PORT_WR (1 << 31) 356 357 /* We mark duplicate entries with -1 */ 358 #define DUPLICATE_ENTRY ((u8)(-1)) 359 360 /* Port Power Management Status and Control - port_power_base bitmasks */ 361 /* Inactivity timer value for transitions into U1, in microseconds. 362 * Timeout can be up to 127us. 0xFF means an infinite timeout. 363 */ 364 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 365 /* Inactivity timer value for transitions into U2 */ 366 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 367 /* Bits 24:31 for port testing */ 368 369 /* USB2 Protocol PORTSPMSC */ 370 #define PORT_L1S_MASK 7 371 #define PORT_L1S_SUCCESS 1 372 #define PORT_RWE (1 << 3) 373 #define PORT_HIRD(p) (((p) & 0xf) << 4) 374 #define PORT_HIRD_MASK (0xf << 4) 375 #define PORT_L1DS(p) (((p) & 0xff) << 8) 376 #define PORT_HLE (1 << 16) 377 378 /** 379 * struct xhci_intr_reg - Interrupt Register Set 380 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 381 * interrupts and check for pending interrupts. 382 * @irq_control: IMOD - Interrupt Moderation Register. 383 * Used to throttle interrupts. 384 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 385 * @erst_base: ERST base address. 386 * @erst_dequeue: Event ring dequeue pointer. 387 * 388 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 389 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 390 * multiple segments of the same size. The HC places events on the ring and 391 * "updates the Cycle bit in the TRBs to indicate to software the current 392 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 393 * updates the dequeue pointer. 394 */ 395 struct xhci_intr_reg { 396 __le32 irq_pending; 397 __le32 irq_control; 398 __le32 erst_size; 399 __le32 rsvd; 400 __le64 erst_base; 401 __le64 erst_dequeue; 402 }; 403 404 /* irq_pending bitmasks */ 405 #define ER_IRQ_PENDING(p) ((p) & 0x1) 406 /* bits 2:31 need to be preserved */ 407 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 408 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 409 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 410 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 411 412 /* irq_control bitmasks */ 413 /* Minimum interval between interrupts (in 250ns intervals). The interval 414 * between interrupts will be longer if there are no events on the event ring. 415 * Default is 4000 (1 ms). 416 */ 417 #define ER_IRQ_INTERVAL_MASK (0xffff) 418 /* Counter used to count down the time to the next interrupt - HW use only */ 419 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 420 421 /* erst_size bitmasks */ 422 /* Preserve bits 16:31 of erst_size */ 423 #define ERST_SIZE_MASK (0xffff << 16) 424 425 /* erst_dequeue bitmasks */ 426 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 427 * where the current dequeue pointer lies. This is an optional HW hint. 428 */ 429 #define ERST_DESI_MASK (0x7) 430 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 431 * a work queue (or delayed service routine)? 432 */ 433 #define ERST_EHB (1 << 3) 434 #define ERST_PTR_MASK (0xf) 435 436 /** 437 * struct xhci_run_regs 438 * @microframe_index: 439 * MFINDEX - current microframe number 440 * 441 * Section 5.5 Host Controller Runtime Registers: 442 * "Software should read and write these registers using only Dword (32 bit) 443 * or larger accesses" 444 */ 445 struct xhci_run_regs { 446 __le32 microframe_index; 447 __le32 rsvd[7]; 448 struct xhci_intr_reg ir_set[128]; 449 }; 450 451 /** 452 * struct doorbell_array 453 * 454 * Bits 0 - 7: Endpoint target 455 * Bits 8 - 15: RsvdZ 456 * Bits 16 - 31: Stream ID 457 * 458 * Section 5.6 459 */ 460 struct xhci_doorbell_array { 461 __le32 doorbell[256]; 462 }; 463 464 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 465 #define DB_VALUE_HOST 0x00000000 466 467 /** 468 * struct xhci_protocol_caps 469 * @revision: major revision, minor revision, capability ID, 470 * and next capability pointer. 471 * @name_string: Four ASCII characters to say which spec this xHC 472 * follows, typically "USB ". 473 * @port_info: Port offset, count, and protocol-defined information. 474 */ 475 struct xhci_protocol_caps { 476 u32 revision; 477 u32 name_string; 478 u32 port_info; 479 }; 480 481 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 482 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 483 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 484 485 /** 486 * struct xhci_container_ctx 487 * @type: Type of context. Used to calculated offsets to contained contexts. 488 * @size: Size of the context data 489 * @bytes: The raw context data given to HW 490 * @dma: dma address of the bytes 491 * 492 * Represents either a Device or Input context. Holds a pointer to the raw 493 * memory used for the context (bytes) and dma address of it (dma). 494 */ 495 struct xhci_container_ctx { 496 unsigned type; 497 #define XHCI_CTX_TYPE_DEVICE 0x1 498 #define XHCI_CTX_TYPE_INPUT 0x2 499 500 int size; 501 502 u8 *bytes; 503 dma_addr_t dma; 504 }; 505 506 /** 507 * struct xhci_slot_ctx 508 * @dev_info: Route string, device speed, hub info, and last valid endpoint 509 * @dev_info2: Max exit latency for device number, root hub port number 510 * @tt_info: tt_info is used to construct split transaction tokens 511 * @dev_state: slot state and device address 512 * 513 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 514 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 515 * reserved at the end of the slot context for HC internal use. 516 */ 517 struct xhci_slot_ctx { 518 __le32 dev_info; 519 __le32 dev_info2; 520 __le32 tt_info; 521 __le32 dev_state; 522 /* offset 0x10 to 0x1f reserved for HC internal use */ 523 __le32 reserved[4]; 524 }; 525 526 /* dev_info bitmasks */ 527 /* Route String - 0:19 */ 528 #define ROUTE_STRING_MASK (0xfffff) 529 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 530 #define DEV_SPEED (0xf << 20) 531 /* bit 24 reserved */ 532 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 533 #define DEV_MTT (0x1 << 25) 534 /* Set if the device is a hub - bit 26 */ 535 #define DEV_HUB (0x1 << 26) 536 /* Index of the last valid endpoint context in this device context - 27:31 */ 537 #define LAST_CTX_MASK (0x1f << 27) 538 #define LAST_CTX(p) ((p) << 27) 539 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 540 #define SLOT_FLAG (1 << 0) 541 #define EP0_FLAG (1 << 1) 542 543 /* dev_info2 bitmasks */ 544 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 545 #define MAX_EXIT (0xffff) 546 /* Root hub port number that is needed to access the USB device */ 547 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 548 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 549 /* Maximum number of ports under a hub device */ 550 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 551 552 /* tt_info bitmasks */ 553 /* 554 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 555 * The Slot ID of the hub that isolates the high speed signaling from 556 * this low or full-speed device. '0' if attached to root hub port. 557 */ 558 #define TT_SLOT (0xff) 559 /* 560 * The number of the downstream facing port of the high-speed hub 561 * '0' if the device is not low or full speed. 562 */ 563 #define TT_PORT (0xff << 8) 564 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 565 566 /* dev_state bitmasks */ 567 /* USB device address - assigned by the HC */ 568 #define DEV_ADDR_MASK (0xff) 569 /* bits 8:26 reserved */ 570 /* Slot state */ 571 #define SLOT_STATE (0x1f << 27) 572 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 573 574 #define SLOT_STATE_DISABLED 0 575 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 576 #define SLOT_STATE_DEFAULT 1 577 #define SLOT_STATE_ADDRESSED 2 578 #define SLOT_STATE_CONFIGURED 3 579 580 /** 581 * struct xhci_ep_ctx 582 * @ep_info: endpoint state, streams, mult, and interval information. 583 * @ep_info2: information on endpoint type, max packet size, max burst size, 584 * error count, and whether the HC will force an event for all 585 * transactions. 586 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 587 * defines one stream, this points to the endpoint transfer ring. 588 * Otherwise, it points to a stream context array, which has a 589 * ring pointer for each flow. 590 * @tx_info: 591 * Average TRB lengths for the endpoint ring and 592 * max payload within an Endpoint Service Interval Time (ESIT). 593 * 594 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 595 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 596 * reserved at the end of the endpoint context for HC internal use. 597 */ 598 struct xhci_ep_ctx { 599 __le32 ep_info; 600 __le32 ep_info2; 601 __le64 deq; 602 __le32 tx_info; 603 /* offset 0x14 - 0x1f reserved for HC internal use */ 604 __le32 reserved[3]; 605 }; 606 607 /* ep_info bitmasks */ 608 /* 609 * Endpoint State - bits 0:2 610 * 0 - disabled 611 * 1 - running 612 * 2 - halted due to halt condition - ok to manipulate endpoint ring 613 * 3 - stopped 614 * 4 - TRB error 615 * 5-7 - reserved 616 */ 617 #define EP_STATE_MASK (0xf) 618 #define EP_STATE_DISABLED 0 619 #define EP_STATE_RUNNING 1 620 #define EP_STATE_HALTED 2 621 #define EP_STATE_STOPPED 3 622 #define EP_STATE_ERROR 4 623 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 624 #define EP_MULT(p) (((p) & 0x3) << 8) 625 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 626 /* bits 10:14 are Max Primary Streams */ 627 /* bit 15 is Linear Stream Array */ 628 /* Interval - period between requests to an endpoint - 125u increments. */ 629 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 630 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 631 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 632 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 633 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 634 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 635 #define EP_HAS_LSA (1 << 15) 636 637 /* ep_info2 bitmasks */ 638 /* 639 * Force Event - generate transfer events for all TRBs for this endpoint 640 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 641 */ 642 #define FORCE_EVENT (0x1) 643 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 644 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 645 #define EP_TYPE(p) ((p) << 3) 646 #define ISOC_OUT_EP 1 647 #define BULK_OUT_EP 2 648 #define INT_OUT_EP 3 649 #define CTRL_EP 4 650 #define ISOC_IN_EP 5 651 #define BULK_IN_EP 6 652 #define INT_IN_EP 7 653 /* bit 6 reserved */ 654 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 655 #define MAX_BURST(p) (((p)&0xff) << 8) 656 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 657 #define MAX_PACKET(p) (((p)&0xffff) << 16) 658 #define MAX_PACKET_MASK (0xffff << 16) 659 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 660 661 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 662 * USB2.0 spec 9.6.6. 663 */ 664 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 665 666 /* tx_info bitmasks */ 667 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 668 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 669 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 670 671 /* deq bitmasks */ 672 #define EP_CTX_CYCLE_MASK (1 << 0) 673 674 675 /** 676 * struct xhci_input_control_context 677 * Input control context; see section 6.2.5. 678 * 679 * @drop_context: set the bit of the endpoint context you want to disable 680 * @add_context: set the bit of the endpoint context you want to enable 681 */ 682 struct xhci_input_control_ctx { 683 __le32 drop_flags; 684 __le32 add_flags; 685 __le32 rsvd2[6]; 686 }; 687 688 #define EP_IS_ADDED(ctrl_ctx, i) \ 689 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 690 #define EP_IS_DROPPED(ctrl_ctx, i) \ 691 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 692 693 /* Represents everything that is needed to issue a command on the command ring. 694 * It's useful to pre-allocate these for commands that cannot fail due to 695 * out-of-memory errors, like freeing streams. 696 */ 697 struct xhci_command { 698 /* Input context for changing device state */ 699 struct xhci_container_ctx *in_ctx; 700 u32 status; 701 /* If completion is null, no one is waiting on this command 702 * and the structure can be freed after the command completes. 703 */ 704 struct completion *completion; 705 union xhci_trb *command_trb; 706 struct list_head cmd_list; 707 }; 708 709 /* drop context bitmasks */ 710 #define DROP_EP(x) (0x1 << x) 711 /* add context bitmasks */ 712 #define ADD_EP(x) (0x1 << x) 713 714 struct xhci_stream_ctx { 715 /* 64-bit stream ring address, cycle state, and stream type */ 716 __le64 stream_ring; 717 /* offset 0x14 - 0x1f reserved for HC internal use */ 718 __le32 reserved[2]; 719 }; 720 721 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 722 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7) 723 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 724 #define SCT_SEC_TR 0 725 /* Primary stream array type, dequeue pointer is to a transfer ring */ 726 #define SCT_PRI_TR 1 727 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 728 #define SCT_SSA_8 2 729 #define SCT_SSA_16 3 730 #define SCT_SSA_32 4 731 #define SCT_SSA_64 5 732 #define SCT_SSA_128 6 733 #define SCT_SSA_256 7 734 735 /* Assume no secondary streams for now */ 736 struct xhci_stream_info { 737 struct xhci_ring **stream_rings; 738 /* Number of streams, including stream 0 (which drivers can't use) */ 739 unsigned int num_streams; 740 /* The stream context array may be bigger than 741 * the number of streams the driver asked for 742 */ 743 struct xhci_stream_ctx *stream_ctx_array; 744 unsigned int num_stream_ctxs; 745 dma_addr_t ctx_array_dma; 746 /* For mapping physical TRB addresses to segments in stream rings */ 747 struct radix_tree_root trb_address_map; 748 struct xhci_command *free_streams_command; 749 }; 750 751 #define SMALL_STREAM_ARRAY_SIZE 256 752 #define MEDIUM_STREAM_ARRAY_SIZE 1024 753 754 /* Some Intel xHCI host controllers need software to keep track of the bus 755 * bandwidth. Keep track of endpoint info here. Each root port is allocated 756 * the full bus bandwidth. We must also treat TTs (including each port under a 757 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 758 * (DMI) also limits the total bandwidth (across all domains) that can be used. 759 */ 760 struct xhci_bw_info { 761 /* ep_interval is zero-based */ 762 unsigned int ep_interval; 763 /* mult and num_packets are one-based */ 764 unsigned int mult; 765 unsigned int num_packets; 766 unsigned int max_packet_size; 767 unsigned int max_esit_payload; 768 unsigned int type; 769 }; 770 771 /* "Block" sizes in bytes the hardware uses for different device speeds. 772 * The logic in this part of the hardware limits the number of bits the hardware 773 * can use, so must represent bandwidth in a less precise manner to mimic what 774 * the scheduler hardware computes. 775 */ 776 #define FS_BLOCK 1 777 #define HS_BLOCK 4 778 #define SS_BLOCK 16 779 #define DMI_BLOCK 32 780 781 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 782 * with each byte transferred. SuperSpeed devices have an initial overhead to 783 * set up bursts. These are in blocks, see above. LS overhead has already been 784 * translated into FS blocks. 785 */ 786 #define DMI_OVERHEAD 8 787 #define DMI_OVERHEAD_BURST 4 788 #define SS_OVERHEAD 8 789 #define SS_OVERHEAD_BURST 32 790 #define HS_OVERHEAD 26 791 #define FS_OVERHEAD 20 792 #define LS_OVERHEAD 128 793 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 794 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 795 * of overhead associated with split transfers crossing microframe boundaries. 796 * 31 blocks is pure protocol overhead. 797 */ 798 #define TT_HS_OVERHEAD (31 + 94) 799 #define TT_DMI_OVERHEAD (25 + 12) 800 801 /* Bandwidth limits in blocks */ 802 #define FS_BW_LIMIT 1285 803 #define TT_BW_LIMIT 1320 804 #define HS_BW_LIMIT 1607 805 #define SS_BW_LIMIT_IN 3906 806 #define DMI_BW_LIMIT_IN 3906 807 #define SS_BW_LIMIT_OUT 3906 808 #define DMI_BW_LIMIT_OUT 3906 809 810 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 811 #define FS_BW_RESERVED 10 812 #define HS_BW_RESERVED 20 813 #define SS_BW_RESERVED 10 814 815 struct xhci_virt_ep { 816 struct xhci_ring *ring; 817 /* Related to endpoints that are configured to use stream IDs only */ 818 struct xhci_stream_info *stream_info; 819 /* Temporary storage in case the configure endpoint command fails and we 820 * have to restore the device state to the previous state 821 */ 822 struct xhci_ring *new_ring; 823 unsigned int ep_state; 824 #define SET_DEQ_PENDING (1 << 0) 825 #define EP_HALTED (1 << 1) /* For stall handling */ 826 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 827 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 828 #define EP_GETTING_STREAMS (1 << 3) 829 #define EP_HAS_STREAMS (1 << 4) 830 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 831 #define EP_GETTING_NO_STREAMS (1 << 5) 832 /* ---- Related to URB cancellation ---- */ 833 struct list_head cancelled_td_list; 834 /* The TRB that was last reported in a stopped endpoint ring */ 835 union xhci_trb *stopped_trb; 836 struct xhci_td *stopped_td; 837 unsigned int stopped_stream; 838 /* Watchdog timer for stop endpoint command to cancel URBs */ 839 struct timer_list stop_cmd_timer; 840 int stop_cmds_pending; 841 struct xhci_hcd *xhci; 842 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 843 * command. We'll need to update the ring's dequeue segment and dequeue 844 * pointer after the command completes. 845 */ 846 struct xhci_segment *queued_deq_seg; 847 union xhci_trb *queued_deq_ptr; 848 /* 849 * Sometimes the xHC can not process isochronous endpoint ring quickly 850 * enough, and it will miss some isoc tds on the ring and generate 851 * a Missed Service Error Event. 852 * Set skip flag when receive a Missed Service Error Event and 853 * process the missed tds on the endpoint ring. 854 */ 855 bool skip; 856 /* Bandwidth checking storage */ 857 struct xhci_bw_info bw_info; 858 struct list_head bw_endpoint_list; 859 }; 860 861 enum xhci_overhead_type { 862 LS_OVERHEAD_TYPE = 0, 863 FS_OVERHEAD_TYPE, 864 HS_OVERHEAD_TYPE, 865 }; 866 867 struct xhci_interval_bw { 868 unsigned int num_packets; 869 /* Sorted by max packet size. 870 * Head of the list is the greatest max packet size. 871 */ 872 struct list_head endpoints; 873 /* How many endpoints of each speed are present. */ 874 unsigned int overhead[3]; 875 }; 876 877 #define XHCI_MAX_INTERVAL 16 878 879 struct xhci_interval_bw_table { 880 unsigned int interval0_esit_payload; 881 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 882 /* Includes reserved bandwidth for async endpoints */ 883 unsigned int bw_used; 884 unsigned int ss_bw_in; 885 unsigned int ss_bw_out; 886 }; 887 888 889 struct xhci_virt_device { 890 struct usb_device *udev; 891 /* 892 * Commands to the hardware are passed an "input context" that 893 * tells the hardware what to change in its data structures. 894 * The hardware will return changes in an "output context" that 895 * software must allocate for the hardware. We need to keep 896 * track of input and output contexts separately because 897 * these commands might fail and we don't trust the hardware. 898 */ 899 struct xhci_container_ctx *out_ctx; 900 /* Used for addressing devices and configuration changes */ 901 struct xhci_container_ctx *in_ctx; 902 /* Rings saved to ensure old alt settings can be re-instated */ 903 struct xhci_ring **ring_cache; 904 int num_rings_cached; 905 /* Store xHC assigned device address */ 906 int address; 907 #define XHCI_MAX_RINGS_CACHED 31 908 struct xhci_virt_ep eps[31]; 909 struct completion cmd_completion; 910 /* Status of the last command issued for this device */ 911 u32 cmd_status; 912 struct list_head cmd_list; 913 u8 fake_port; 914 u8 real_port; 915 struct xhci_interval_bw_table *bw_table; 916 struct xhci_tt_bw_info *tt_info; 917 }; 918 919 /* 920 * For each roothub, keep track of the bandwidth information for each periodic 921 * interval. 922 * 923 * If a high speed hub is attached to the roothub, each TT associated with that 924 * hub is a separate bandwidth domain. The interval information for the 925 * endpoints on the devices under that TT will appear in the TT structure. 926 */ 927 struct xhci_root_port_bw_info { 928 struct list_head tts; 929 unsigned int num_active_tts; 930 struct xhci_interval_bw_table bw_table; 931 }; 932 933 struct xhci_tt_bw_info { 934 struct list_head tt_list; 935 int slot_id; 936 int ttport; 937 struct xhci_interval_bw_table bw_table; 938 int active_eps; 939 }; 940 941 942 /** 943 * struct xhci_device_context_array 944 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 945 */ 946 struct xhci_device_context_array { 947 /* 64-bit device addresses; we only write 32-bit addresses */ 948 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 949 /* private xHCD pointers */ 950 dma_addr_t dma; 951 }; 952 /* TODO: write function to set the 64-bit device DMA address */ 953 /* 954 * TODO: change this to be dynamically sized at HC mem init time since the HC 955 * might not be able to handle the maximum number of devices possible. 956 */ 957 958 959 struct xhci_transfer_event { 960 /* 64-bit buffer address, or immediate data */ 961 __le64 buffer; 962 __le32 transfer_len; 963 /* This field is interpreted differently based on the type of TRB */ 964 __le32 flags; 965 }; 966 967 /** Transfer Event bit fields **/ 968 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 969 970 /* Completion Code - only applicable for some types of TRBs */ 971 #define COMP_CODE_MASK (0xff << 24) 972 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 973 #define COMP_SUCCESS 1 974 /* Data Buffer Error */ 975 #define COMP_DB_ERR 2 976 /* Babble Detected Error */ 977 #define COMP_BABBLE 3 978 /* USB Transaction Error */ 979 #define COMP_TX_ERR 4 980 /* TRB Error - some TRB field is invalid */ 981 #define COMP_TRB_ERR 5 982 /* Stall Error - USB device is stalled */ 983 #define COMP_STALL 6 984 /* Resource Error - HC doesn't have memory for that device configuration */ 985 #define COMP_ENOMEM 7 986 /* Bandwidth Error - not enough room in schedule for this dev config */ 987 #define COMP_BW_ERR 8 988 /* No Slots Available Error - HC ran out of device slots */ 989 #define COMP_ENOSLOTS 9 990 /* Invalid Stream Type Error */ 991 #define COMP_STREAM_ERR 10 992 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 993 #define COMP_EBADSLT 11 994 /* Endpoint Not Enabled Error */ 995 #define COMP_EBADEP 12 996 /* Short Packet */ 997 #define COMP_SHORT_TX 13 998 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 999 #define COMP_UNDERRUN 14 1000 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 1001 #define COMP_OVERRUN 15 1002 /* Virtual Function Event Ring Full Error */ 1003 #define COMP_VF_FULL 16 1004 /* Parameter Error - Context parameter is invalid */ 1005 #define COMP_EINVAL 17 1006 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 1007 #define COMP_BW_OVER 18 1008 /* Context State Error - illegal context state transition requested */ 1009 #define COMP_CTX_STATE 19 1010 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 1011 #define COMP_PING_ERR 20 1012 /* Event Ring is full */ 1013 #define COMP_ER_FULL 21 1014 /* Incompatible Device Error */ 1015 #define COMP_DEV_ERR 22 1016 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 1017 #define COMP_MISSED_INT 23 1018 /* Successfully stopped command ring */ 1019 #define COMP_CMD_STOP 24 1020 /* Successfully aborted current command and stopped command ring */ 1021 #define COMP_CMD_ABORT 25 1022 /* Stopped - transfer was terminated by a stop endpoint command */ 1023 #define COMP_STOP 26 1024 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 1025 #define COMP_STOP_INVAL 27 1026 /* Control Abort Error - Debug Capability - control pipe aborted */ 1027 #define COMP_DBG_ABORT 28 1028 /* Max Exit Latency Too Large Error */ 1029 #define COMP_MEL_ERR 29 1030 /* TRB type 30 reserved */ 1031 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 1032 #define COMP_BUFF_OVER 31 1033 /* Event Lost Error - xHC has an "internal event overrun condition" */ 1034 #define COMP_ISSUES 32 1035 /* Undefined Error - reported when other error codes don't apply */ 1036 #define COMP_UNKNOWN 33 1037 /* Invalid Stream ID Error */ 1038 #define COMP_STRID_ERR 34 1039 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 1040 #define COMP_2ND_BW_ERR 35 1041 /* Split Transaction Error */ 1042 #define COMP_SPLIT_ERR 36 1043 1044 struct xhci_link_trb { 1045 /* 64-bit segment pointer*/ 1046 __le64 segment_ptr; 1047 __le32 intr_target; 1048 __le32 control; 1049 }; 1050 1051 /* control bitfields */ 1052 #define LINK_TOGGLE (0x1<<1) 1053 1054 /* Command completion event TRB */ 1055 struct xhci_event_cmd { 1056 /* Pointer to command TRB, or the value passed by the event data trb */ 1057 __le64 cmd_trb; 1058 __le32 status; 1059 __le32 flags; 1060 }; 1061 1062 /* flags bitmasks */ 1063 /* bits 16:23 are the virtual function ID */ 1064 /* bits 24:31 are the slot ID */ 1065 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1066 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1067 1068 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1069 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1070 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1071 1072 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1073 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1074 #define LAST_EP_INDEX 30 1075 1076 /* Set TR Dequeue Pointer command TRB fields */ 1077 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1078 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1079 1080 1081 /* Port Status Change Event TRB fields */ 1082 /* Port ID - bits 31:24 */ 1083 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1084 1085 /* Normal TRB fields */ 1086 /* transfer_len bitmasks - bits 0:16 */ 1087 #define TRB_LEN(p) ((p) & 0x1ffff) 1088 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1089 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1090 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1091 #define TRB_TBC(p) (((p) & 0x3) << 7) 1092 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1093 1094 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1095 #define TRB_CYCLE (1<<0) 1096 /* 1097 * Force next event data TRB to be evaluated before task switch. 1098 * Used to pass OS data back after a TD completes. 1099 */ 1100 #define TRB_ENT (1<<1) 1101 /* Interrupt on short packet */ 1102 #define TRB_ISP (1<<2) 1103 /* Set PCIe no snoop attribute */ 1104 #define TRB_NO_SNOOP (1<<3) 1105 /* Chain multiple TRBs into a TD */ 1106 #define TRB_CHAIN (1<<4) 1107 /* Interrupt on completion */ 1108 #define TRB_IOC (1<<5) 1109 /* The buffer pointer contains immediate data */ 1110 #define TRB_IDT (1<<6) 1111 1112 /* Block Event Interrupt */ 1113 #define TRB_BEI (1<<9) 1114 1115 /* Control transfer TRB specific fields */ 1116 #define TRB_DIR_IN (1<<16) 1117 #define TRB_TX_TYPE(p) ((p) << 16) 1118 #define TRB_DATA_OUT 2 1119 #define TRB_DATA_IN 3 1120 1121 /* Isochronous TRB specific fields */ 1122 #define TRB_SIA (1<<31) 1123 1124 struct xhci_generic_trb { 1125 __le32 field[4]; 1126 }; 1127 1128 union xhci_trb { 1129 struct xhci_link_trb link; 1130 struct xhci_transfer_event trans_event; 1131 struct xhci_event_cmd event_cmd; 1132 struct xhci_generic_trb generic; 1133 }; 1134 1135 /* TRB bit mask */ 1136 #define TRB_TYPE_BITMASK (0xfc00) 1137 #define TRB_TYPE(p) ((p) << 10) 1138 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1139 /* TRB type IDs */ 1140 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1141 #define TRB_NORMAL 1 1142 /* setup stage for control transfers */ 1143 #define TRB_SETUP 2 1144 /* data stage for control transfers */ 1145 #define TRB_DATA 3 1146 /* status stage for control transfers */ 1147 #define TRB_STATUS 4 1148 /* isoc transfers */ 1149 #define TRB_ISOC 5 1150 /* TRB for linking ring segments */ 1151 #define TRB_LINK 6 1152 #define TRB_EVENT_DATA 7 1153 /* Transfer Ring No-op (not for the command ring) */ 1154 #define TRB_TR_NOOP 8 1155 /* Command TRBs */ 1156 /* Enable Slot Command */ 1157 #define TRB_ENABLE_SLOT 9 1158 /* Disable Slot Command */ 1159 #define TRB_DISABLE_SLOT 10 1160 /* Address Device Command */ 1161 #define TRB_ADDR_DEV 11 1162 /* Configure Endpoint Command */ 1163 #define TRB_CONFIG_EP 12 1164 /* Evaluate Context Command */ 1165 #define TRB_EVAL_CONTEXT 13 1166 /* Reset Endpoint Command */ 1167 #define TRB_RESET_EP 14 1168 /* Stop Transfer Ring Command */ 1169 #define TRB_STOP_RING 15 1170 /* Set Transfer Ring Dequeue Pointer Command */ 1171 #define TRB_SET_DEQ 16 1172 /* Reset Device Command */ 1173 #define TRB_RESET_DEV 17 1174 /* Force Event Command (opt) */ 1175 #define TRB_FORCE_EVENT 18 1176 /* Negotiate Bandwidth Command (opt) */ 1177 #define TRB_NEG_BANDWIDTH 19 1178 /* Set Latency Tolerance Value Command (opt) */ 1179 #define TRB_SET_LT 20 1180 /* Get port bandwidth Command */ 1181 #define TRB_GET_BW 21 1182 /* Force Header Command - generate a transaction or link management packet */ 1183 #define TRB_FORCE_HEADER 22 1184 /* No-op Command - not for transfer rings */ 1185 #define TRB_CMD_NOOP 23 1186 /* TRB IDs 24-31 reserved */ 1187 /* Event TRBS */ 1188 /* Transfer Event */ 1189 #define TRB_TRANSFER 32 1190 /* Command Completion Event */ 1191 #define TRB_COMPLETION 33 1192 /* Port Status Change Event */ 1193 #define TRB_PORT_STATUS 34 1194 /* Bandwidth Request Event (opt) */ 1195 #define TRB_BANDWIDTH_EVENT 35 1196 /* Doorbell Event (opt) */ 1197 #define TRB_DOORBELL 36 1198 /* Host Controller Event */ 1199 #define TRB_HC_EVENT 37 1200 /* Device Notification Event - device sent function wake notification */ 1201 #define TRB_DEV_NOTE 38 1202 /* MFINDEX Wrap Event - microframe counter wrapped */ 1203 #define TRB_MFINDEX_WRAP 39 1204 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1205 1206 /* Nec vendor-specific command completion event. */ 1207 #define TRB_NEC_CMD_COMP 48 1208 /* Get NEC firmware revision. */ 1209 #define TRB_NEC_GET_FW 49 1210 1211 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1212 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1213 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1214 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1215 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1216 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1217 1218 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1219 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1220 1221 /* 1222 * TRBS_PER_SEGMENT must be a multiple of 4, 1223 * since the command ring is 64-byte aligned. 1224 * It must also be greater than 16. 1225 */ 1226 #define TRBS_PER_SEGMENT 64 1227 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1228 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1229 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1230 #define SEGMENT_SHIFT (__ffs(SEGMENT_SIZE)) 1231 /* TRB buffer pointers can't cross 64KB boundaries */ 1232 #define TRB_MAX_BUFF_SHIFT 16 1233 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1234 1235 struct xhci_segment { 1236 union xhci_trb *trbs; 1237 /* private to HCD */ 1238 struct xhci_segment *next; 1239 dma_addr_t dma; 1240 }; 1241 1242 struct xhci_td { 1243 struct list_head td_list; 1244 struct list_head cancelled_td_list; 1245 struct urb *urb; 1246 struct xhci_segment *start_seg; 1247 union xhci_trb *first_trb; 1248 union xhci_trb *last_trb; 1249 }; 1250 1251 struct xhci_dequeue_state { 1252 struct xhci_segment *new_deq_seg; 1253 union xhci_trb *new_deq_ptr; 1254 int new_cycle_state; 1255 }; 1256 1257 enum xhci_ring_type { 1258 TYPE_CTRL = 0, 1259 TYPE_ISOC, 1260 TYPE_BULK, 1261 TYPE_INTR, 1262 TYPE_STREAM, 1263 TYPE_COMMAND, 1264 TYPE_EVENT, 1265 }; 1266 1267 struct xhci_ring { 1268 struct xhci_segment *first_seg; 1269 struct xhci_segment *last_seg; 1270 union xhci_trb *enqueue; 1271 struct xhci_segment *enq_seg; 1272 unsigned int enq_updates; 1273 union xhci_trb *dequeue; 1274 struct xhci_segment *deq_seg; 1275 unsigned int deq_updates; 1276 struct list_head td_list; 1277 /* 1278 * Write the cycle state into the TRB cycle field to give ownership of 1279 * the TRB to the host controller (if we are the producer), or to check 1280 * if we own the TRB (if we are the consumer). See section 4.9.1. 1281 */ 1282 u32 cycle_state; 1283 unsigned int stream_id; 1284 unsigned int num_segs; 1285 unsigned int num_trbs_free; 1286 unsigned int num_trbs_free_temp; 1287 enum xhci_ring_type type; 1288 bool last_td_was_short; 1289 }; 1290 1291 struct xhci_erst_entry { 1292 /* 64-bit event ring segment address */ 1293 __le64 seg_addr; 1294 __le32 seg_size; 1295 /* Set to zero */ 1296 __le32 rsvd; 1297 }; 1298 1299 struct xhci_erst { 1300 struct xhci_erst_entry *entries; 1301 unsigned int num_entries; 1302 /* xhci->event_ring keeps track of segment dma addresses */ 1303 dma_addr_t erst_dma_addr; 1304 /* Num entries the ERST can contain */ 1305 unsigned int erst_size; 1306 }; 1307 1308 struct xhci_scratchpad { 1309 u64 *sp_array; 1310 dma_addr_t sp_dma; 1311 void **sp_buffers; 1312 dma_addr_t *sp_dma_buffers; 1313 }; 1314 1315 struct urb_priv { 1316 int length; 1317 int td_cnt; 1318 struct xhci_td *td[0]; 1319 }; 1320 1321 /* 1322 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1323 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1324 * meaning 64 ring segments. 1325 * Initial allocated size of the ERST, in number of entries */ 1326 #define ERST_NUM_SEGS 1 1327 /* Initial allocated size of the ERST, in number of entries */ 1328 #define ERST_SIZE 64 1329 /* Initial number of event segment rings allocated */ 1330 #define ERST_ENTRIES 1 1331 /* Poll every 60 seconds */ 1332 #define POLL_TIMEOUT 60 1333 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1334 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1335 /* XXX: Make these module parameters */ 1336 1337 struct s3_save { 1338 u32 command; 1339 u32 dev_nt; 1340 u64 dcbaa_ptr; 1341 u32 config_reg; 1342 u32 irq_pending; 1343 u32 irq_control; 1344 u32 erst_size; 1345 u64 erst_base; 1346 u64 erst_dequeue; 1347 }; 1348 1349 /* Use for lpm */ 1350 struct dev_info { 1351 u32 dev_id; 1352 struct list_head list; 1353 }; 1354 1355 struct xhci_bus_state { 1356 unsigned long bus_suspended; 1357 unsigned long next_statechange; 1358 1359 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1360 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1361 u32 port_c_suspend; 1362 u32 suspended_ports; 1363 u32 port_remote_wakeup; 1364 unsigned long resume_done[USB_MAXCHILDREN]; 1365 }; 1366 1367 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1368 { 1369 if (hcd->speed == HCD_USB3) 1370 return 0; 1371 else 1372 return 1; 1373 } 1374 1375 /* There is one xhci_hcd structure per controller */ 1376 struct xhci_hcd { 1377 struct usb_hcd *main_hcd; 1378 struct usb_hcd *shared_hcd; 1379 /* glue to PCI and HCD framework */ 1380 struct xhci_cap_regs __iomem *cap_regs; 1381 struct xhci_op_regs __iomem *op_regs; 1382 struct xhci_run_regs __iomem *run_regs; 1383 struct xhci_doorbell_array __iomem *dba; 1384 /* Our HCD's current interrupter register set */ 1385 struct xhci_intr_reg __iomem *ir_set; 1386 1387 /* Cached register copies of read-only HC data */ 1388 __u32 hcs_params1; 1389 __u32 hcs_params2; 1390 __u32 hcs_params3; 1391 __u32 hcc_params; 1392 1393 spinlock_t lock; 1394 1395 /* packed release number */ 1396 u8 sbrn; 1397 u16 hci_version; 1398 u8 max_slots; 1399 u8 max_interrupters; 1400 u8 max_ports; 1401 u8 isoc_threshold; 1402 int event_ring_max; 1403 int addr_64; 1404 /* 4KB min, 128MB max */ 1405 int page_size; 1406 /* Valid values are 12 to 20, inclusive */ 1407 int page_shift; 1408 /* msi-x vectors */ 1409 int msix_count; 1410 struct msix_entry *msix_entries; 1411 /* data structures */ 1412 struct xhci_device_context_array *dcbaa; 1413 struct xhci_ring *cmd_ring; 1414 unsigned int cmd_ring_reserved_trbs; 1415 struct xhci_ring *event_ring; 1416 struct xhci_erst erst; 1417 /* Scratchpad */ 1418 struct xhci_scratchpad *scratchpad; 1419 /* Store LPM test failed devices' information */ 1420 struct list_head lpm_failed_devs; 1421 1422 /* slot enabling and address device helpers */ 1423 struct completion addr_dev; 1424 int slot_id; 1425 /* Internal mirror of the HW's dcbaa */ 1426 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1427 /* For keeping track of bandwidth domains per roothub. */ 1428 struct xhci_root_port_bw_info *rh_bw; 1429 1430 /* DMA pools */ 1431 struct dma_pool *device_pool; 1432 struct dma_pool *segment_pool; 1433 struct dma_pool *small_streams_pool; 1434 struct dma_pool *medium_streams_pool; 1435 1436 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1437 /* Poll the rings - for debugging */ 1438 struct timer_list event_ring_timer; 1439 int zombie; 1440 #endif 1441 /* Host controller watchdog timer structures */ 1442 unsigned int xhc_state; 1443 1444 u32 command; 1445 struct s3_save s3; 1446 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1447 * 1448 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1449 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1450 * that sees this status (other than the timer that set it) should stop touching 1451 * hardware immediately. Interrupt handlers should return immediately when 1452 * they see this status (any time they drop and re-acquire xhci->lock). 1453 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1454 * putting the TD on the canceled list, etc. 1455 * 1456 * There are no reports of xHCI host controllers that display this issue. 1457 */ 1458 #define XHCI_STATE_DYING (1 << 0) 1459 #define XHCI_STATE_HALTED (1 << 1) 1460 /* Statistics */ 1461 int error_bitmask; 1462 unsigned int quirks; 1463 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1464 #define XHCI_RESET_EP_QUIRK (1 << 1) 1465 #define XHCI_NEC_HOST (1 << 2) 1466 #define XHCI_AMD_PLL_FIX (1 << 3) 1467 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1468 /* 1469 * Certain Intel host controllers have a limit to the number of endpoint 1470 * contexts they can handle. Ideally, they would signal that they can't handle 1471 * anymore endpoint contexts by returning a Resource Error for the Configure 1472 * Endpoint command, but they don't. Instead they expect software to keep track 1473 * of the number of active endpoints for them, across configure endpoint 1474 * commands, reset device commands, disable slot commands, and address device 1475 * commands. 1476 */ 1477 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1478 #define XHCI_BROKEN_MSI (1 << 6) 1479 #define XHCI_RESET_ON_RESUME (1 << 7) 1480 #define XHCI_SW_BW_CHECKING (1 << 8) 1481 #define XHCI_AMD_0x96_HOST (1 << 9) 1482 unsigned int num_active_eps; 1483 unsigned int limit_active_eps; 1484 /* There are two roothubs to keep track of bus suspend info for */ 1485 struct xhci_bus_state bus_state[2]; 1486 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1487 u8 *port_array; 1488 /* Array of pointers to USB 3.0 PORTSC registers */ 1489 __le32 __iomem **usb3_ports; 1490 unsigned int num_usb3_ports; 1491 /* Array of pointers to USB 2.0 PORTSC registers */ 1492 __le32 __iomem **usb2_ports; 1493 unsigned int num_usb2_ports; 1494 /* support xHCI 0.96 spec USB2 software LPM */ 1495 unsigned sw_lpm_support:1; 1496 /* support xHCI 1.0 spec USB2 hardware LPM */ 1497 unsigned hw_lpm_support:1; 1498 }; 1499 1500 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1501 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1502 { 1503 return *((struct xhci_hcd **) (hcd->hcd_priv)); 1504 } 1505 1506 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1507 { 1508 return xhci->main_hcd; 1509 } 1510 1511 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1512 #define XHCI_DEBUG 1 1513 #else 1514 #define XHCI_DEBUG 0 1515 #endif 1516 1517 #define xhci_dbg(xhci, fmt, args...) \ 1518 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1519 #define xhci_info(xhci, fmt, args...) \ 1520 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1521 #define xhci_err(xhci, fmt, args...) \ 1522 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1523 #define xhci_warn(xhci, fmt, args...) \ 1524 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1525 1526 /* TODO: copied from ehci.h - can be refactored? */ 1527 /* xHCI spec says all registers are little endian */ 1528 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1529 __le32 __iomem *regs) 1530 { 1531 return readl(regs); 1532 } 1533 static inline void xhci_writel(struct xhci_hcd *xhci, 1534 const unsigned int val, __le32 __iomem *regs) 1535 { 1536 writel(val, regs); 1537 } 1538 1539 /* 1540 * Registers should always be accessed with double word or quad word accesses. 1541 * 1542 * Some xHCI implementations may support 64-bit address pointers. Registers 1543 * with 64-bit address pointers should be written to with dword accesses by 1544 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1545 * xHCI implementations that do not support 64-bit address pointers will ignore 1546 * the high dword, and write order is irrelevant. 1547 */ 1548 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1549 __le64 __iomem *regs) 1550 { 1551 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1552 u64 val_lo = readl(ptr); 1553 u64 val_hi = readl(ptr + 1); 1554 return val_lo + (val_hi << 32); 1555 } 1556 static inline void xhci_write_64(struct xhci_hcd *xhci, 1557 const u64 val, __le64 __iomem *regs) 1558 { 1559 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1560 u32 val_lo = lower_32_bits(val); 1561 u32 val_hi = upper_32_bits(val); 1562 1563 writel(val_lo, ptr); 1564 writel(val_hi, ptr + 1); 1565 } 1566 1567 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1568 { 1569 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1570 } 1571 1572 /* xHCI debugging */ 1573 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1574 void xhci_print_registers(struct xhci_hcd *xhci); 1575 void xhci_dbg_regs(struct xhci_hcd *xhci); 1576 void xhci_print_run_regs(struct xhci_hcd *xhci); 1577 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1578 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1579 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1580 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1581 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1582 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1583 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1584 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1585 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1586 struct xhci_container_ctx *ctx); 1587 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1588 unsigned int slot_id, unsigned int ep_index, 1589 struct xhci_virt_ep *ep); 1590 1591 /* xHCI memory management */ 1592 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1593 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1594 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1595 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1596 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1597 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1598 struct usb_device *udev); 1599 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1600 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1601 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1602 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1603 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1604 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1605 struct xhci_bw_info *ep_bw, 1606 struct xhci_interval_bw_table *bw_table, 1607 struct usb_device *udev, 1608 struct xhci_virt_ep *virt_ep, 1609 struct xhci_tt_bw_info *tt_info); 1610 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1611 struct xhci_virt_device *virt_dev, 1612 int old_active_eps); 1613 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1614 void xhci_update_bw_info(struct xhci_hcd *xhci, 1615 struct xhci_container_ctx *in_ctx, 1616 struct xhci_input_control_ctx *ctrl_ctx, 1617 struct xhci_virt_device *virt_dev); 1618 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1619 struct xhci_container_ctx *in_ctx, 1620 struct xhci_container_ctx *out_ctx, 1621 unsigned int ep_index); 1622 void xhci_slot_copy(struct xhci_hcd *xhci, 1623 struct xhci_container_ctx *in_ctx, 1624 struct xhci_container_ctx *out_ctx); 1625 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1626 struct usb_device *udev, struct usb_host_endpoint *ep, 1627 gfp_t mem_flags); 1628 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1629 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1630 unsigned int num_trbs, gfp_t flags); 1631 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1632 struct xhci_virt_device *virt_dev, 1633 unsigned int ep_index); 1634 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1635 unsigned int num_stream_ctxs, 1636 unsigned int num_streams, gfp_t flags); 1637 void xhci_free_stream_info(struct xhci_hcd *xhci, 1638 struct xhci_stream_info *stream_info); 1639 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1640 struct xhci_ep_ctx *ep_ctx, 1641 struct xhci_stream_info *stream_info); 1642 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1643 struct xhci_ep_ctx *ep_ctx, 1644 struct xhci_virt_ep *ep); 1645 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1646 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1647 struct xhci_ring *xhci_dma_to_transfer_ring( 1648 struct xhci_virt_ep *ep, 1649 u64 address); 1650 struct xhci_ring *xhci_stream_id_to_ring( 1651 struct xhci_virt_device *dev, 1652 unsigned int ep_index, 1653 unsigned int stream_id); 1654 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1655 bool allocate_in_ctx, bool allocate_completion, 1656 gfp_t mem_flags); 1657 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); 1658 void xhci_free_command(struct xhci_hcd *xhci, 1659 struct xhci_command *command); 1660 1661 #ifdef CONFIG_PCI 1662 /* xHCI PCI glue */ 1663 int xhci_register_pci(void); 1664 void xhci_unregister_pci(void); 1665 #else 1666 static inline int xhci_register_pci(void) { return 0; } 1667 static inline void xhci_unregister_pci(void) {} 1668 #endif 1669 1670 #if defined(CONFIG_USB_XHCI_PLATFORM) \ 1671 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE) 1672 int xhci_register_plat(void); 1673 void xhci_unregister_plat(void); 1674 #else 1675 static inline int xhci_register_plat(void) 1676 { return 0; } 1677 static inline void xhci_unregister_plat(void) 1678 { } 1679 #endif 1680 1681 /* xHCI host controller glue */ 1682 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1683 void xhci_quiesce(struct xhci_hcd *xhci); 1684 int xhci_halt(struct xhci_hcd *xhci); 1685 int xhci_reset(struct xhci_hcd *xhci); 1686 int xhci_init(struct usb_hcd *hcd); 1687 int xhci_run(struct usb_hcd *hcd); 1688 void xhci_stop(struct usb_hcd *hcd); 1689 void xhci_shutdown(struct usb_hcd *hcd); 1690 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1691 1692 #ifdef CONFIG_PM 1693 int xhci_suspend(struct xhci_hcd *xhci); 1694 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1695 #else 1696 #define xhci_suspend NULL 1697 #define xhci_resume NULL 1698 #endif 1699 1700 int xhci_get_frame(struct usb_hcd *hcd); 1701 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1702 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); 1703 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1704 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1705 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1706 struct xhci_virt_device *virt_dev, 1707 struct usb_device *hdev, 1708 struct usb_tt *tt, gfp_t mem_flags); 1709 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1710 struct usb_host_endpoint **eps, unsigned int num_eps, 1711 unsigned int num_streams, gfp_t mem_flags); 1712 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1713 struct usb_host_endpoint **eps, unsigned int num_eps, 1714 gfp_t mem_flags); 1715 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1716 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 1717 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 1718 struct usb_device *udev, int enable); 1719 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1720 struct usb_tt *tt, gfp_t mem_flags); 1721 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1722 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1723 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1724 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1725 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1726 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1727 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1728 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1729 1730 /* xHCI ring, segment, TRB, and TD functions */ 1731 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1732 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1733 union xhci_trb *start_trb, union xhci_trb *end_trb, 1734 dma_addr_t suspect_dma); 1735 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1736 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1737 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1738 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1739 u32 slot_id); 1740 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 1741 u32 field1, u32 field2, u32 field3, u32 field4); 1742 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1743 unsigned int ep_index, int suspend); 1744 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1745 int slot_id, unsigned int ep_index); 1746 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1747 int slot_id, unsigned int ep_index); 1748 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1749 int slot_id, unsigned int ep_index); 1750 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1751 struct urb *urb, int slot_id, unsigned int ep_index); 1752 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1753 u32 slot_id, bool command_must_succeed); 1754 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1755 u32 slot_id); 1756 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1757 unsigned int ep_index); 1758 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); 1759 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1760 unsigned int slot_id, unsigned int ep_index, 1761 unsigned int stream_id, struct xhci_td *cur_td, 1762 struct xhci_dequeue_state *state); 1763 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1764 unsigned int slot_id, unsigned int ep_index, 1765 unsigned int stream_id, 1766 struct xhci_dequeue_state *deq_state); 1767 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1768 struct usb_device *udev, unsigned int ep_index); 1769 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1770 unsigned int slot_id, unsigned int ep_index, 1771 struct xhci_dequeue_state *deq_state); 1772 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1773 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1774 unsigned int ep_index, unsigned int stream_id); 1775 1776 /* xHCI roothub code */ 1777 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1778 int port_id, u32 link_state); 1779 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1780 int port_id, u32 port_bit); 1781 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1782 char *buf, u16 wLength); 1783 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1784 1785 #ifdef CONFIG_PM 1786 int xhci_bus_suspend(struct usb_hcd *hcd); 1787 int xhci_bus_resume(struct usb_hcd *hcd); 1788 #else 1789 #define xhci_bus_suspend NULL 1790 #define xhci_bus_resume NULL 1791 #endif /* CONFIG_PM */ 1792 1793 u32 xhci_port_state_to_neutral(u32 state); 1794 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1795 u16 port); 1796 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1797 1798 /* xHCI contexts */ 1799 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1800 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1801 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1802 1803 #endif /* __LINUX_XHCI_HCD_H */ 1804