1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 #include <linux/kernel.h> 29 #include <linux/usb/hcd.h> 30 31 /* Code sharing between pci-quirks and xhci hcd */ 32 #include "xhci-ext-caps.h" 33 34 /* xHCI PCI Configuration Registers */ 35 #define XHCI_SBRN_OFFSET (0x60) 36 37 /* Max number of USB devices for any host controller - limit in section 6.1 */ 38 #define MAX_HC_SLOTS 256 39 /* Section 5.3.3 - MaxPorts */ 40 #define MAX_HC_PORTS 127 41 42 /* 43 * xHCI register interface. 44 * This corresponds to the eXtensible Host Controller Interface (xHCI) 45 * Revision 0.95 specification 46 */ 47 48 /** 49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 50 * @hc_capbase: length of the capabilities register and HC version number 51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 54 * @hcc_params: HCCPARAMS - Capability Parameters 55 * @db_off: DBOFF - Doorbell array offset 56 * @run_regs_off: RTSOFF - Runtime register space offset 57 */ 58 struct xhci_cap_regs { 59 u32 hc_capbase; 60 u32 hcs_params1; 61 u32 hcs_params2; 62 u32 hcs_params3; 63 u32 hcc_params; 64 u32 db_off; 65 u32 run_regs_off; 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* hc_capbase bitmasks */ 70 /* bits 7:0 - how long is the Capabilities register */ 71 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 72 /* bits 31:16 */ 73 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 74 75 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 76 /* bits 0:7, Max Device Slots */ 77 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 78 #define HCS_SLOTS_MASK 0xff 79 /* bits 8:18, Max Interrupters */ 80 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 81 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 82 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 83 84 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 85 /* bits 0:3, frames or uframes that SW needs to queue transactions 86 * ahead of the HW to meet periodic deadlines */ 87 #define HCS_IST(p) (((p) >> 0) & 0xf) 88 /* bits 4:7, max number of Event Ring segments */ 89 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 90 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 91 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 92 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 93 94 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 95 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 96 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 97 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 98 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 99 100 /* HCCPARAMS - hcc_params - bitmasks */ 101 /* true: HC can use 64-bit address pointers */ 102 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 103 /* true: HC can do bandwidth negotiation */ 104 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 105 /* true: HC uses 64-byte Device Context structures 106 * FIXME 64-byte context structures aren't supported yet. 107 */ 108 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 109 /* true: HC has port power switches */ 110 #define HCC_PPC(p) ((p) & (1 << 3)) 111 /* true: HC has port indicators */ 112 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 113 /* true: HC has Light HC Reset Capability */ 114 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 115 /* true: HC supports latency tolerance messaging */ 116 #define HCC_LTC(p) ((p) & (1 << 6)) 117 /* true: no secondary Stream ID Support */ 118 #define HCC_NSS(p) ((p) & (1 << 7)) 119 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 120 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 121 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 122 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 123 124 /* db_off bitmask - bits 0:1 reserved */ 125 #define DBOFF_MASK (~0x3) 126 127 /* run_regs_off bitmask - bits 0:4 reserved */ 128 #define RTSOFF_MASK (~0x1f) 129 130 131 /* Number of registers per port */ 132 #define NUM_PORT_REGS 4 133 134 /** 135 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 136 * @command: USBCMD - xHC command register 137 * @status: USBSTS - xHC status register 138 * @page_size: This indicates the page size that the host controller 139 * supports. If bit n is set, the HC supports a page size 140 * of 2^(n+12), up to a 128MB page size. 141 * 4K is the minimum page size. 142 * @cmd_ring: CRP - 64-bit Command Ring Pointer 143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 144 * @config_reg: CONFIG - Configure Register 145 * @port_status_base: PORTSCn - base address for Port Status and Control 146 * Each port has a Port Status and Control register, 147 * followed by a Port Power Management Status and Control 148 * register, a Port Link Info register, and a reserved 149 * register. 150 * @port_power_base: PORTPMSCn - base address for 151 * Port Power Management Status and Control 152 * @port_link_base: PORTLIn - base address for Port Link Info (current 153 * Link PM state and control) for USB 2.1 and USB 3.0 154 * devices. 155 */ 156 struct xhci_op_regs { 157 u32 command; 158 u32 status; 159 u32 page_size; 160 u32 reserved1; 161 u32 reserved2; 162 u32 dev_notification; 163 u64 cmd_ring; 164 /* rsvd: offset 0x20-2F */ 165 u32 reserved3[4]; 166 u64 dcbaa_ptr; 167 u32 config_reg; 168 /* rsvd: offset 0x3C-3FF */ 169 u32 reserved4[241]; 170 /* port 1 registers, which serve as a base address for other ports */ 171 u32 port_status_base; 172 u32 port_power_base; 173 u32 port_link_base; 174 u32 reserved5; 175 /* registers for ports 2-255 */ 176 u32 reserved6[NUM_PORT_REGS*254]; 177 }; 178 179 /* USBCMD - USB command - command bitmasks */ 180 /* start/stop HC execution - do not write unless HC is halted*/ 181 #define CMD_RUN XHCI_CMD_RUN 182 /* Reset HC - resets internal HC state machine and all registers (except 183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 184 * The xHCI driver must reinitialize the xHC after setting this bit. 185 */ 186 #define CMD_RESET (1 << 1) 187 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 188 #define CMD_EIE XHCI_CMD_EIE 189 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 190 #define CMD_HSEIE XHCI_CMD_HSEIE 191 /* bits 4:6 are reserved (and should be preserved on writes). */ 192 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 193 #define CMD_LRESET (1 << 7) 194 /* host controller save/restore state. */ 195 #define CMD_CSS (1 << 8) 196 #define CMD_CRS (1 << 9) 197 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 198 #define CMD_EWE XHCI_CMD_EWE 199 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 201 * '0' means the xHC can power it off if all ports are in the disconnect, 202 * disabled, or powered-off state. 203 */ 204 #define CMD_PM_INDEX (1 << 11) 205 /* bits 12:31 are reserved (and should be preserved on writes). */ 206 207 /* USBSTS - USB status - status bitmasks */ 208 /* HC not running - set to 1 when run/stop bit is cleared. */ 209 #define STS_HALT XHCI_STS_HALT 210 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 211 #define STS_FATAL (1 << 2) 212 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 213 #define STS_EINT (1 << 3) 214 /* port change detect */ 215 #define STS_PORT (1 << 4) 216 /* bits 5:7 reserved and zeroed */ 217 /* save state status - '1' means xHC is saving state */ 218 #define STS_SAVE (1 << 8) 219 /* restore state status - '1' means xHC is restoring state */ 220 #define STS_RESTORE (1 << 9) 221 /* true: save or restore error */ 222 #define STS_SRE (1 << 10) 223 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 224 #define STS_CNR XHCI_STS_CNR 225 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 226 #define STS_HCE (1 << 12) 227 /* bits 13:31 reserved and should be preserved */ 228 229 /* 230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 231 * Generate a device notification event when the HC sees a transaction with a 232 * notification type that matches a bit set in this bit field. 233 */ 234 #define DEV_NOTE_MASK (0xffff) 235 #define ENABLE_DEV_NOTE(x) (1 << x) 236 /* Most of the device notification types should only be used for debug. 237 * SW does need to pay attention to function wake notifications. 238 */ 239 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 240 241 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 242 /* bit 0 is the command ring cycle state */ 243 /* stop ring operation after completion of the currently executing command */ 244 #define CMD_RING_PAUSE (1 << 1) 245 /* stop ring immediately - abort the currently executing command */ 246 #define CMD_RING_ABORT (1 << 2) 247 /* true: command ring is running */ 248 #define CMD_RING_RUNNING (1 << 3) 249 /* bits 4:5 reserved and should be preserved */ 250 /* Command Ring pointer - bit mask for the lower 32 bits. */ 251 #define CMD_RING_RSVD_BITS (0x3f) 252 253 /* CONFIG - Configure Register - config_reg bitmasks */ 254 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 255 #define MAX_DEVS(p) ((p) & 0xff) 256 /* bits 8:31 - reserved and should be preserved */ 257 258 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 259 /* true: device connected */ 260 #define PORT_CONNECT (1 << 0) 261 /* true: port enabled */ 262 #define PORT_PE (1 << 1) 263 /* bit 2 reserved and zeroed */ 264 /* true: port has an over-current condition */ 265 #define PORT_OC (1 << 3) 266 /* true: port reset signaling asserted */ 267 #define PORT_RESET (1 << 4) 268 /* Port Link State - bits 5:8 269 * A read gives the current link PM state of the port, 270 * a write with Link State Write Strobe set sets the link state. 271 */ 272 #define PORT_PLS_MASK (0xf << 5) 273 #define XDEV_U0 (0x0 << 5) 274 #define XDEV_U3 (0x3 << 5) 275 #define XDEV_RESUME (0xf << 5) 276 /* true: port has power (see HCC_PPC) */ 277 #define PORT_POWER (1 << 9) 278 /* bits 10:13 indicate device speed: 279 * 0 - undefined speed - port hasn't be initialized by a reset yet 280 * 1 - full speed 281 * 2 - low speed 282 * 3 - high speed 283 * 4 - super speed 284 * 5-15 reserved 285 */ 286 #define DEV_SPEED_MASK (0xf << 10) 287 #define XDEV_FS (0x1 << 10) 288 #define XDEV_LS (0x2 << 10) 289 #define XDEV_HS (0x3 << 10) 290 #define XDEV_SS (0x4 << 10) 291 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 292 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 293 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 294 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 295 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 296 /* Bits 20:23 in the Slot Context are the speed for the device */ 297 #define SLOT_SPEED_FS (XDEV_FS << 10) 298 #define SLOT_SPEED_LS (XDEV_LS << 10) 299 #define SLOT_SPEED_HS (XDEV_HS << 10) 300 #define SLOT_SPEED_SS (XDEV_SS << 10) 301 /* Port Indicator Control */ 302 #define PORT_LED_OFF (0 << 14) 303 #define PORT_LED_AMBER (1 << 14) 304 #define PORT_LED_GREEN (2 << 14) 305 #define PORT_LED_MASK (3 << 14) 306 /* Port Link State Write Strobe - set this when changing link state */ 307 #define PORT_LINK_STROBE (1 << 16) 308 /* true: connect status change */ 309 #define PORT_CSC (1 << 17) 310 /* true: port enable change */ 311 #define PORT_PEC (1 << 18) 312 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 313 * into an enabled state, and the device into the default state. A "warm" reset 314 * also resets the link, forcing the device through the link training sequence. 315 * SW can also look at the Port Reset register to see when warm reset is done. 316 */ 317 #define PORT_WRC (1 << 19) 318 /* true: over-current change */ 319 #define PORT_OCC (1 << 20) 320 /* true: reset change - 1 to 0 transition of PORT_RESET */ 321 #define PORT_RC (1 << 21) 322 /* port link status change - set on some port link state transitions: 323 * Transition Reason 324 * ------------------------------------------------------------------------------ 325 * - U3 to Resume Wakeup signaling from a device 326 * - Resume to Recovery to U0 USB 3.0 device resume 327 * - Resume to U0 USB 2.0 device resume 328 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 329 * - U3 to U0 Software resume of USB 2.0 device complete 330 * - U2 to U0 L1 resume of USB 2.1 device complete 331 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 332 * - U0 to disabled L1 entry error with USB 2.1 device 333 * - Any state to inactive Error on USB 3.0 port 334 */ 335 #define PORT_PLC (1 << 22) 336 /* port configure error change - port failed to configure its link partner */ 337 #define PORT_CEC (1 << 23) 338 /* bit 24 reserved */ 339 /* wake on connect (enable) */ 340 #define PORT_WKCONN_E (1 << 25) 341 /* wake on disconnect (enable) */ 342 #define PORT_WKDISC_E (1 << 26) 343 /* wake on over-current (enable) */ 344 #define PORT_WKOC_E (1 << 27) 345 /* bits 28:29 reserved */ 346 /* true: device is removable - for USB 3.0 roothub emulation */ 347 #define PORT_DEV_REMOVE (1 << 30) 348 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 349 #define PORT_WR (1 << 31) 350 351 /* Port Power Management Status and Control - port_power_base bitmasks */ 352 /* Inactivity timer value for transitions into U1, in microseconds. 353 * Timeout can be up to 127us. 0xFF means an infinite timeout. 354 */ 355 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 356 /* Inactivity timer value for transitions into U2 */ 357 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 358 /* Bits 24:31 for port testing */ 359 360 /* USB2 Protocol PORTSPMSC */ 361 #define PORT_RWE (1 << 0x3) 362 363 /** 364 * struct xhci_intr_reg - Interrupt Register Set 365 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 366 * interrupts and check for pending interrupts. 367 * @irq_control: IMOD - Interrupt Moderation Register. 368 * Used to throttle interrupts. 369 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 370 * @erst_base: ERST base address. 371 * @erst_dequeue: Event ring dequeue pointer. 372 * 373 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 374 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 375 * multiple segments of the same size. The HC places events on the ring and 376 * "updates the Cycle bit in the TRBs to indicate to software the current 377 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 378 * updates the dequeue pointer. 379 */ 380 struct xhci_intr_reg { 381 u32 irq_pending; 382 u32 irq_control; 383 u32 erst_size; 384 u32 rsvd; 385 u64 erst_base; 386 u64 erst_dequeue; 387 }; 388 389 /* irq_pending bitmasks */ 390 #define ER_IRQ_PENDING(p) ((p) & 0x1) 391 /* bits 2:31 need to be preserved */ 392 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 393 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 394 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 395 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 396 397 /* irq_control bitmasks */ 398 /* Minimum interval between interrupts (in 250ns intervals). The interval 399 * between interrupts will be longer if there are no events on the event ring. 400 * Default is 4000 (1 ms). 401 */ 402 #define ER_IRQ_INTERVAL_MASK (0xffff) 403 /* Counter used to count down the time to the next interrupt - HW use only */ 404 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 405 406 /* erst_size bitmasks */ 407 /* Preserve bits 16:31 of erst_size */ 408 #define ERST_SIZE_MASK (0xffff << 16) 409 410 /* erst_dequeue bitmasks */ 411 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 412 * where the current dequeue pointer lies. This is an optional HW hint. 413 */ 414 #define ERST_DESI_MASK (0x7) 415 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 416 * a work queue (or delayed service routine)? 417 */ 418 #define ERST_EHB (1 << 3) 419 #define ERST_PTR_MASK (0xf) 420 421 /** 422 * struct xhci_run_regs 423 * @microframe_index: 424 * MFINDEX - current microframe number 425 * 426 * Section 5.5 Host Controller Runtime Registers: 427 * "Software should read and write these registers using only Dword (32 bit) 428 * or larger accesses" 429 */ 430 struct xhci_run_regs { 431 u32 microframe_index; 432 u32 rsvd[7]; 433 struct xhci_intr_reg ir_set[128]; 434 }; 435 436 /** 437 * struct doorbell_array 438 * 439 * Section 5.6 440 */ 441 struct xhci_doorbell_array { 442 u32 doorbell[256]; 443 }; 444 445 #define DB_TARGET_MASK 0xFFFFFF00 446 #define DB_STREAM_ID_MASK 0x0000FFFF 447 #define DB_TARGET_HOST 0x0 448 #define DB_STREAM_ID_HOST 0x0 449 #define DB_MASK (0xff << 8) 450 451 /* Endpoint Target - bits 0:7 */ 452 #define EPI_TO_DB(p) (((p) + 1) & 0xff) 453 #define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16) 454 455 456 /** 457 * struct xhci_protocol_caps 458 * @revision: major revision, minor revision, capability ID, 459 * and next capability pointer. 460 * @name_string: Four ASCII characters to say which spec this xHC 461 * follows, typically "USB ". 462 * @port_info: Port offset, count, and protocol-defined information. 463 */ 464 struct xhci_protocol_caps { 465 u32 revision; 466 u32 name_string; 467 u32 port_info; 468 }; 469 470 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 471 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 472 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 473 474 /** 475 * struct xhci_container_ctx 476 * @type: Type of context. Used to calculated offsets to contained contexts. 477 * @size: Size of the context data 478 * @bytes: The raw context data given to HW 479 * @dma: dma address of the bytes 480 * 481 * Represents either a Device or Input context. Holds a pointer to the raw 482 * memory used for the context (bytes) and dma address of it (dma). 483 */ 484 struct xhci_container_ctx { 485 unsigned type; 486 #define XHCI_CTX_TYPE_DEVICE 0x1 487 #define XHCI_CTX_TYPE_INPUT 0x2 488 489 int size; 490 491 u8 *bytes; 492 dma_addr_t dma; 493 }; 494 495 /** 496 * struct xhci_slot_ctx 497 * @dev_info: Route string, device speed, hub info, and last valid endpoint 498 * @dev_info2: Max exit latency for device number, root hub port number 499 * @tt_info: tt_info is used to construct split transaction tokens 500 * @dev_state: slot state and device address 501 * 502 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 503 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 504 * reserved at the end of the slot context for HC internal use. 505 */ 506 struct xhci_slot_ctx { 507 u32 dev_info; 508 u32 dev_info2; 509 u32 tt_info; 510 u32 dev_state; 511 /* offset 0x10 to 0x1f reserved for HC internal use */ 512 u32 reserved[4]; 513 }; 514 515 /* dev_info bitmasks */ 516 /* Route String - 0:19 */ 517 #define ROUTE_STRING_MASK (0xfffff) 518 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 519 #define DEV_SPEED (0xf << 20) 520 /* bit 24 reserved */ 521 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 522 #define DEV_MTT (0x1 << 25) 523 /* Set if the device is a hub - bit 26 */ 524 #define DEV_HUB (0x1 << 26) 525 /* Index of the last valid endpoint context in this device context - 27:31 */ 526 #define LAST_CTX_MASK (0x1f << 27) 527 #define LAST_CTX(p) ((p) << 27) 528 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 529 #define SLOT_FLAG (1 << 0) 530 #define EP0_FLAG (1 << 1) 531 532 /* dev_info2 bitmasks */ 533 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 534 #define MAX_EXIT (0xffff) 535 /* Root hub port number that is needed to access the USB device */ 536 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 537 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 538 /* Maximum number of ports under a hub device */ 539 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 540 541 /* tt_info bitmasks */ 542 /* 543 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 544 * The Slot ID of the hub that isolates the high speed signaling from 545 * this low or full-speed device. '0' if attached to root hub port. 546 */ 547 #define TT_SLOT (0xff) 548 /* 549 * The number of the downstream facing port of the high-speed hub 550 * '0' if the device is not low or full speed. 551 */ 552 #define TT_PORT (0xff << 8) 553 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 554 555 /* dev_state bitmasks */ 556 /* USB device address - assigned by the HC */ 557 #define DEV_ADDR_MASK (0xff) 558 /* bits 8:26 reserved */ 559 /* Slot state */ 560 #define SLOT_STATE (0x1f << 27) 561 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 562 563 564 /** 565 * struct xhci_ep_ctx 566 * @ep_info: endpoint state, streams, mult, and interval information. 567 * @ep_info2: information on endpoint type, max packet size, max burst size, 568 * error count, and whether the HC will force an event for all 569 * transactions. 570 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 571 * defines one stream, this points to the endpoint transfer ring. 572 * Otherwise, it points to a stream context array, which has a 573 * ring pointer for each flow. 574 * @tx_info: 575 * Average TRB lengths for the endpoint ring and 576 * max payload within an Endpoint Service Interval Time (ESIT). 577 * 578 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 579 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 580 * reserved at the end of the endpoint context for HC internal use. 581 */ 582 struct xhci_ep_ctx { 583 u32 ep_info; 584 u32 ep_info2; 585 u64 deq; 586 u32 tx_info; 587 /* offset 0x14 - 0x1f reserved for HC internal use */ 588 u32 reserved[3]; 589 }; 590 591 /* ep_info bitmasks */ 592 /* 593 * Endpoint State - bits 0:2 594 * 0 - disabled 595 * 1 - running 596 * 2 - halted due to halt condition - ok to manipulate endpoint ring 597 * 3 - stopped 598 * 4 - TRB error 599 * 5-7 - reserved 600 */ 601 #define EP_STATE_MASK (0xf) 602 #define EP_STATE_DISABLED 0 603 #define EP_STATE_RUNNING 1 604 #define EP_STATE_HALTED 2 605 #define EP_STATE_STOPPED 3 606 #define EP_STATE_ERROR 4 607 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 608 #define EP_MULT(p) ((p & 0x3) << 8) 609 /* bits 10:14 are Max Primary Streams */ 610 /* bit 15 is Linear Stream Array */ 611 /* Interval - period between requests to an endpoint - 125u increments. */ 612 #define EP_INTERVAL(p) ((p & 0xff) << 16) 613 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 614 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 615 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 616 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 617 #define EP_HAS_LSA (1 << 15) 618 619 /* ep_info2 bitmasks */ 620 /* 621 * Force Event - generate transfer events for all TRBs for this endpoint 622 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 623 */ 624 #define FORCE_EVENT (0x1) 625 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 626 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 627 #define EP_TYPE(p) ((p) << 3) 628 #define ISOC_OUT_EP 1 629 #define BULK_OUT_EP 2 630 #define INT_OUT_EP 3 631 #define CTRL_EP 4 632 #define ISOC_IN_EP 5 633 #define BULK_IN_EP 6 634 #define INT_IN_EP 7 635 /* bit 6 reserved */ 636 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 637 #define MAX_BURST(p) (((p)&0xff) << 8) 638 #define MAX_PACKET(p) (((p)&0xffff) << 16) 639 #define MAX_PACKET_MASK (0xffff << 16) 640 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 641 642 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 643 * USB2.0 spec 9.6.6. 644 */ 645 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 646 647 /* tx_info bitmasks */ 648 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 649 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 650 651 652 /** 653 * struct xhci_input_control_context 654 * Input control context; see section 6.2.5. 655 * 656 * @drop_context: set the bit of the endpoint context you want to disable 657 * @add_context: set the bit of the endpoint context you want to enable 658 */ 659 struct xhci_input_control_ctx { 660 u32 drop_flags; 661 u32 add_flags; 662 u32 rsvd2[6]; 663 }; 664 665 /* Represents everything that is needed to issue a command on the command ring. 666 * It's useful to pre-allocate these for commands that cannot fail due to 667 * out-of-memory errors, like freeing streams. 668 */ 669 struct xhci_command { 670 /* Input context for changing device state */ 671 struct xhci_container_ctx *in_ctx; 672 u32 status; 673 /* If completion is null, no one is waiting on this command 674 * and the structure can be freed after the command completes. 675 */ 676 struct completion *completion; 677 union xhci_trb *command_trb; 678 struct list_head cmd_list; 679 }; 680 681 /* drop context bitmasks */ 682 #define DROP_EP(x) (0x1 << x) 683 /* add context bitmasks */ 684 #define ADD_EP(x) (0x1 << x) 685 686 struct xhci_stream_ctx { 687 /* 64-bit stream ring address, cycle state, and stream type */ 688 u64 stream_ring; 689 /* offset 0x14 - 0x1f reserved for HC internal use */ 690 u32 reserved[2]; 691 }; 692 693 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 694 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7) 695 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 696 #define SCT_SEC_TR 0 697 /* Primary stream array type, dequeue pointer is to a transfer ring */ 698 #define SCT_PRI_TR 1 699 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 700 #define SCT_SSA_8 2 701 #define SCT_SSA_16 3 702 #define SCT_SSA_32 4 703 #define SCT_SSA_64 5 704 #define SCT_SSA_128 6 705 #define SCT_SSA_256 7 706 707 /* Assume no secondary streams for now */ 708 struct xhci_stream_info { 709 struct xhci_ring **stream_rings; 710 /* Number of streams, including stream 0 (which drivers can't use) */ 711 unsigned int num_streams; 712 /* The stream context array may be bigger than 713 * the number of streams the driver asked for 714 */ 715 struct xhci_stream_ctx *stream_ctx_array; 716 unsigned int num_stream_ctxs; 717 dma_addr_t ctx_array_dma; 718 /* For mapping physical TRB addresses to segments in stream rings */ 719 struct radix_tree_root trb_address_map; 720 struct xhci_command *free_streams_command; 721 }; 722 723 #define SMALL_STREAM_ARRAY_SIZE 256 724 #define MEDIUM_STREAM_ARRAY_SIZE 1024 725 726 struct xhci_virt_ep { 727 struct xhci_ring *ring; 728 /* Related to endpoints that are configured to use stream IDs only */ 729 struct xhci_stream_info *stream_info; 730 /* Temporary storage in case the configure endpoint command fails and we 731 * have to restore the device state to the previous state 732 */ 733 struct xhci_ring *new_ring; 734 unsigned int ep_state; 735 #define SET_DEQ_PENDING (1 << 0) 736 #define EP_HALTED (1 << 1) /* For stall handling */ 737 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 738 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 739 #define EP_GETTING_STREAMS (1 << 3) 740 #define EP_HAS_STREAMS (1 << 4) 741 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 742 #define EP_GETTING_NO_STREAMS (1 << 5) 743 /* ---- Related to URB cancellation ---- */ 744 struct list_head cancelled_td_list; 745 /* The TRB that was last reported in a stopped endpoint ring */ 746 union xhci_trb *stopped_trb; 747 struct xhci_td *stopped_td; 748 unsigned int stopped_stream; 749 /* Watchdog timer for stop endpoint command to cancel URBs */ 750 struct timer_list stop_cmd_timer; 751 int stop_cmds_pending; 752 struct xhci_hcd *xhci; 753 /* 754 * Sometimes the xHC can not process isochronous endpoint ring quickly 755 * enough, and it will miss some isoc tds on the ring and generate 756 * a Missed Service Error Event. 757 * Set skip flag when receive a Missed Service Error Event and 758 * process the missed tds on the endpoint ring. 759 */ 760 bool skip; 761 }; 762 763 struct xhci_virt_device { 764 struct usb_device *udev; 765 /* 766 * Commands to the hardware are passed an "input context" that 767 * tells the hardware what to change in its data structures. 768 * The hardware will return changes in an "output context" that 769 * software must allocate for the hardware. We need to keep 770 * track of input and output contexts separately because 771 * these commands might fail and we don't trust the hardware. 772 */ 773 struct xhci_container_ctx *out_ctx; 774 /* Used for addressing devices and configuration changes */ 775 struct xhci_container_ctx *in_ctx; 776 /* Rings saved to ensure old alt settings can be re-instated */ 777 struct xhci_ring **ring_cache; 778 int num_rings_cached; 779 /* Store xHC assigned device address */ 780 int address; 781 #define XHCI_MAX_RINGS_CACHED 31 782 struct xhci_virt_ep eps[31]; 783 struct completion cmd_completion; 784 /* Status of the last command issued for this device */ 785 u32 cmd_status; 786 struct list_head cmd_list; 787 u8 port; 788 }; 789 790 791 /** 792 * struct xhci_device_context_array 793 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 794 */ 795 struct xhci_device_context_array { 796 /* 64-bit device addresses; we only write 32-bit addresses */ 797 u64 dev_context_ptrs[MAX_HC_SLOTS]; 798 /* private xHCD pointers */ 799 dma_addr_t dma; 800 }; 801 /* TODO: write function to set the 64-bit device DMA address */ 802 /* 803 * TODO: change this to be dynamically sized at HC mem init time since the HC 804 * might not be able to handle the maximum number of devices possible. 805 */ 806 807 808 struct xhci_transfer_event { 809 /* 64-bit buffer address, or immediate data */ 810 u64 buffer; 811 u32 transfer_len; 812 /* This field is interpreted differently based on the type of TRB */ 813 u32 flags; 814 }; 815 816 /** Transfer Event bit fields **/ 817 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 818 819 /* Completion Code - only applicable for some types of TRBs */ 820 #define COMP_CODE_MASK (0xff << 24) 821 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 822 #define COMP_SUCCESS 1 823 /* Data Buffer Error */ 824 #define COMP_DB_ERR 2 825 /* Babble Detected Error */ 826 #define COMP_BABBLE 3 827 /* USB Transaction Error */ 828 #define COMP_TX_ERR 4 829 /* TRB Error - some TRB field is invalid */ 830 #define COMP_TRB_ERR 5 831 /* Stall Error - USB device is stalled */ 832 #define COMP_STALL 6 833 /* Resource Error - HC doesn't have memory for that device configuration */ 834 #define COMP_ENOMEM 7 835 /* Bandwidth Error - not enough room in schedule for this dev config */ 836 #define COMP_BW_ERR 8 837 /* No Slots Available Error - HC ran out of device slots */ 838 #define COMP_ENOSLOTS 9 839 /* Invalid Stream Type Error */ 840 #define COMP_STREAM_ERR 10 841 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 842 #define COMP_EBADSLT 11 843 /* Endpoint Not Enabled Error */ 844 #define COMP_EBADEP 12 845 /* Short Packet */ 846 #define COMP_SHORT_TX 13 847 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 848 #define COMP_UNDERRUN 14 849 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 850 #define COMP_OVERRUN 15 851 /* Virtual Function Event Ring Full Error */ 852 #define COMP_VF_FULL 16 853 /* Parameter Error - Context parameter is invalid */ 854 #define COMP_EINVAL 17 855 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 856 #define COMP_BW_OVER 18 857 /* Context State Error - illegal context state transition requested */ 858 #define COMP_CTX_STATE 19 859 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 860 #define COMP_PING_ERR 20 861 /* Event Ring is full */ 862 #define COMP_ER_FULL 21 863 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 864 #define COMP_MISSED_INT 23 865 /* Successfully stopped command ring */ 866 #define COMP_CMD_STOP 24 867 /* Successfully aborted current command and stopped command ring */ 868 #define COMP_CMD_ABORT 25 869 /* Stopped - transfer was terminated by a stop endpoint command */ 870 #define COMP_STOP 26 871 /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ 872 #define COMP_STOP_INVAL 27 873 /* Control Abort Error - Debug Capability - control pipe aborted */ 874 #define COMP_DBG_ABORT 28 875 /* TRB type 29 and 30 reserved */ 876 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 877 #define COMP_BUFF_OVER 31 878 /* Event Lost Error - xHC has an "internal event overrun condition" */ 879 #define COMP_ISSUES 32 880 /* Undefined Error - reported when other error codes don't apply */ 881 #define COMP_UNKNOWN 33 882 /* Invalid Stream ID Error */ 883 #define COMP_STRID_ERR 34 884 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 885 /* FIXME - check for this */ 886 #define COMP_2ND_BW_ERR 35 887 /* Split Transaction Error */ 888 #define COMP_SPLIT_ERR 36 889 890 struct xhci_link_trb { 891 /* 64-bit segment pointer*/ 892 u64 segment_ptr; 893 u32 intr_target; 894 u32 control; 895 }; 896 897 /* control bitfields */ 898 #define LINK_TOGGLE (0x1<<1) 899 900 /* Command completion event TRB */ 901 struct xhci_event_cmd { 902 /* Pointer to command TRB, or the value passed by the event data trb */ 903 u64 cmd_trb; 904 u32 status; 905 u32 flags; 906 }; 907 908 /* flags bitmasks */ 909 /* bits 16:23 are the virtual function ID */ 910 /* bits 24:31 are the slot ID */ 911 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 912 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 913 914 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 915 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 916 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 917 918 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 919 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 920 #define LAST_EP_INDEX 30 921 922 /* Set TR Dequeue Pointer command TRB fields */ 923 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 924 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 925 926 927 /* Port Status Change Event TRB fields */ 928 /* Port ID - bits 31:24 */ 929 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 930 931 /* Normal TRB fields */ 932 /* transfer_len bitmasks - bits 0:16 */ 933 #define TRB_LEN(p) ((p) & 0x1ffff) 934 /* Interrupter Target - which MSI-X vector to target the completion event at */ 935 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 936 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 937 938 /* Cycle bit - indicates TRB ownership by HC or HCD */ 939 #define TRB_CYCLE (1<<0) 940 /* 941 * Force next event data TRB to be evaluated before task switch. 942 * Used to pass OS data back after a TD completes. 943 */ 944 #define TRB_ENT (1<<1) 945 /* Interrupt on short packet */ 946 #define TRB_ISP (1<<2) 947 /* Set PCIe no snoop attribute */ 948 #define TRB_NO_SNOOP (1<<3) 949 /* Chain multiple TRBs into a TD */ 950 #define TRB_CHAIN (1<<4) 951 /* Interrupt on completion */ 952 #define TRB_IOC (1<<5) 953 /* The buffer pointer contains immediate data */ 954 #define TRB_IDT (1<<6) 955 956 957 /* Control transfer TRB specific fields */ 958 #define TRB_DIR_IN (1<<16) 959 960 /* Isochronous TRB specific fields */ 961 #define TRB_SIA (1<<31) 962 963 struct xhci_generic_trb { 964 u32 field[4]; 965 }; 966 967 union xhci_trb { 968 struct xhci_link_trb link; 969 struct xhci_transfer_event trans_event; 970 struct xhci_event_cmd event_cmd; 971 struct xhci_generic_trb generic; 972 }; 973 974 /* TRB bit mask */ 975 #define TRB_TYPE_BITMASK (0xfc00) 976 #define TRB_TYPE(p) ((p) << 10) 977 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 978 /* TRB type IDs */ 979 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 980 #define TRB_NORMAL 1 981 /* setup stage for control transfers */ 982 #define TRB_SETUP 2 983 /* data stage for control transfers */ 984 #define TRB_DATA 3 985 /* status stage for control transfers */ 986 #define TRB_STATUS 4 987 /* isoc transfers */ 988 #define TRB_ISOC 5 989 /* TRB for linking ring segments */ 990 #define TRB_LINK 6 991 #define TRB_EVENT_DATA 7 992 /* Transfer Ring No-op (not for the command ring) */ 993 #define TRB_TR_NOOP 8 994 /* Command TRBs */ 995 /* Enable Slot Command */ 996 #define TRB_ENABLE_SLOT 9 997 /* Disable Slot Command */ 998 #define TRB_DISABLE_SLOT 10 999 /* Address Device Command */ 1000 #define TRB_ADDR_DEV 11 1001 /* Configure Endpoint Command */ 1002 #define TRB_CONFIG_EP 12 1003 /* Evaluate Context Command */ 1004 #define TRB_EVAL_CONTEXT 13 1005 /* Reset Endpoint Command */ 1006 #define TRB_RESET_EP 14 1007 /* Stop Transfer Ring Command */ 1008 #define TRB_STOP_RING 15 1009 /* Set Transfer Ring Dequeue Pointer Command */ 1010 #define TRB_SET_DEQ 16 1011 /* Reset Device Command */ 1012 #define TRB_RESET_DEV 17 1013 /* Force Event Command (opt) */ 1014 #define TRB_FORCE_EVENT 18 1015 /* Negotiate Bandwidth Command (opt) */ 1016 #define TRB_NEG_BANDWIDTH 19 1017 /* Set Latency Tolerance Value Command (opt) */ 1018 #define TRB_SET_LT 20 1019 /* Get port bandwidth Command */ 1020 #define TRB_GET_BW 21 1021 /* Force Header Command - generate a transaction or link management packet */ 1022 #define TRB_FORCE_HEADER 22 1023 /* No-op Command - not for transfer rings */ 1024 #define TRB_CMD_NOOP 23 1025 /* TRB IDs 24-31 reserved */ 1026 /* Event TRBS */ 1027 /* Transfer Event */ 1028 #define TRB_TRANSFER 32 1029 /* Command Completion Event */ 1030 #define TRB_COMPLETION 33 1031 /* Port Status Change Event */ 1032 #define TRB_PORT_STATUS 34 1033 /* Bandwidth Request Event (opt) */ 1034 #define TRB_BANDWIDTH_EVENT 35 1035 /* Doorbell Event (opt) */ 1036 #define TRB_DOORBELL 36 1037 /* Host Controller Event */ 1038 #define TRB_HC_EVENT 37 1039 /* Device Notification Event - device sent function wake notification */ 1040 #define TRB_DEV_NOTE 38 1041 /* MFINDEX Wrap Event - microframe counter wrapped */ 1042 #define TRB_MFINDEX_WRAP 39 1043 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1044 1045 /* Nec vendor-specific command completion event. */ 1046 #define TRB_NEC_CMD_COMP 48 1047 /* Get NEC firmware revision. */ 1048 #define TRB_NEC_GET_FW 49 1049 1050 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1051 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1052 1053 /* 1054 * TRBS_PER_SEGMENT must be a multiple of 4, 1055 * since the command ring is 64-byte aligned. 1056 * It must also be greater than 16. 1057 */ 1058 #define TRBS_PER_SEGMENT 64 1059 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1060 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1061 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1062 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 1063 * Change this if you change TRBS_PER_SEGMENT! 1064 */ 1065 #define SEGMENT_SHIFT 10 1066 /* TRB buffer pointers can't cross 64KB boundaries */ 1067 #define TRB_MAX_BUFF_SHIFT 16 1068 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1069 1070 struct xhci_segment { 1071 union xhci_trb *trbs; 1072 /* private to HCD */ 1073 struct xhci_segment *next; 1074 dma_addr_t dma; 1075 }; 1076 1077 struct xhci_td { 1078 struct list_head td_list; 1079 struct list_head cancelled_td_list; 1080 struct urb *urb; 1081 struct xhci_segment *start_seg; 1082 union xhci_trb *first_trb; 1083 union xhci_trb *last_trb; 1084 }; 1085 1086 struct xhci_dequeue_state { 1087 struct xhci_segment *new_deq_seg; 1088 union xhci_trb *new_deq_ptr; 1089 int new_cycle_state; 1090 }; 1091 1092 struct xhci_ring { 1093 struct xhci_segment *first_seg; 1094 union xhci_trb *enqueue; 1095 struct xhci_segment *enq_seg; 1096 unsigned int enq_updates; 1097 union xhci_trb *dequeue; 1098 struct xhci_segment *deq_seg; 1099 unsigned int deq_updates; 1100 struct list_head td_list; 1101 /* 1102 * Write the cycle state into the TRB cycle field to give ownership of 1103 * the TRB to the host controller (if we are the producer), or to check 1104 * if we own the TRB (if we are the consumer). See section 4.9.1. 1105 */ 1106 u32 cycle_state; 1107 unsigned int stream_id; 1108 }; 1109 1110 struct xhci_erst_entry { 1111 /* 64-bit event ring segment address */ 1112 u64 seg_addr; 1113 u32 seg_size; 1114 /* Set to zero */ 1115 u32 rsvd; 1116 }; 1117 1118 struct xhci_erst { 1119 struct xhci_erst_entry *entries; 1120 unsigned int num_entries; 1121 /* xhci->event_ring keeps track of segment dma addresses */ 1122 dma_addr_t erst_dma_addr; 1123 /* Num entries the ERST can contain */ 1124 unsigned int erst_size; 1125 }; 1126 1127 struct xhci_scratchpad { 1128 u64 *sp_array; 1129 dma_addr_t sp_dma; 1130 void **sp_buffers; 1131 dma_addr_t *sp_dma_buffers; 1132 }; 1133 1134 struct urb_priv { 1135 int length; 1136 int td_cnt; 1137 struct xhci_td *td[0]; 1138 }; 1139 1140 /* 1141 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1142 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1143 * meaning 64 ring segments. 1144 * Initial allocated size of the ERST, in number of entries */ 1145 #define ERST_NUM_SEGS 1 1146 /* Initial allocated size of the ERST, in number of entries */ 1147 #define ERST_SIZE 64 1148 /* Initial number of event segment rings allocated */ 1149 #define ERST_ENTRIES 1 1150 /* Poll every 60 seconds */ 1151 #define POLL_TIMEOUT 60 1152 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1153 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1154 /* XXX: Make these module parameters */ 1155 1156 struct s3_save { 1157 u32 command; 1158 u32 dev_nt; 1159 u64 dcbaa_ptr; 1160 u32 config_reg; 1161 u32 irq_pending; 1162 u32 irq_control; 1163 u32 erst_size; 1164 u64 erst_base; 1165 u64 erst_dequeue; 1166 }; 1167 1168 /* There is one ehci_hci structure per controller */ 1169 struct xhci_hcd { 1170 /* glue to PCI and HCD framework */ 1171 struct xhci_cap_regs __iomem *cap_regs; 1172 struct xhci_op_regs __iomem *op_regs; 1173 struct xhci_run_regs __iomem *run_regs; 1174 struct xhci_doorbell_array __iomem *dba; 1175 /* Our HCD's current interrupter register set */ 1176 struct xhci_intr_reg __iomem *ir_set; 1177 1178 /* Cached register copies of read-only HC data */ 1179 __u32 hcs_params1; 1180 __u32 hcs_params2; 1181 __u32 hcs_params3; 1182 __u32 hcc_params; 1183 1184 spinlock_t lock; 1185 1186 /* packed release number */ 1187 u8 sbrn; 1188 u16 hci_version; 1189 u8 max_slots; 1190 u8 max_interrupters; 1191 u8 max_ports; 1192 u8 isoc_threshold; 1193 int event_ring_max; 1194 int addr_64; 1195 /* 4KB min, 128MB max */ 1196 int page_size; 1197 /* Valid values are 12 to 20, inclusive */ 1198 int page_shift; 1199 /* msi-x vectors */ 1200 int msix_count; 1201 struct msix_entry *msix_entries; 1202 /* data structures */ 1203 struct xhci_device_context_array *dcbaa; 1204 struct xhci_ring *cmd_ring; 1205 unsigned int cmd_ring_reserved_trbs; 1206 struct xhci_ring *event_ring; 1207 struct xhci_erst erst; 1208 /* Scratchpad */ 1209 struct xhci_scratchpad *scratchpad; 1210 1211 /* slot enabling and address device helpers */ 1212 struct completion addr_dev; 1213 int slot_id; 1214 /* Internal mirror of the HW's dcbaa */ 1215 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1216 1217 /* DMA pools */ 1218 struct dma_pool *device_pool; 1219 struct dma_pool *segment_pool; 1220 struct dma_pool *small_streams_pool; 1221 struct dma_pool *medium_streams_pool; 1222 1223 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1224 /* Poll the rings - for debugging */ 1225 struct timer_list event_ring_timer; 1226 int zombie; 1227 #endif 1228 /* Host controller watchdog timer structures */ 1229 unsigned int xhc_state; 1230 1231 unsigned long bus_suspended; 1232 unsigned long next_statechange; 1233 1234 u32 command; 1235 struct s3_save s3; 1236 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1237 * 1238 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1239 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1240 * that sees this status (other than the timer that set it) should stop touching 1241 * hardware immediately. Interrupt handlers should return immediately when 1242 * they see this status (any time they drop and re-acquire xhci->lock). 1243 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1244 * putting the TD on the canceled list, etc. 1245 * 1246 * There are no reports of xHCI host controllers that display this issue. 1247 */ 1248 #define XHCI_STATE_DYING (1 << 0) 1249 /* Statistics */ 1250 int noops_submitted; 1251 int noops_handled; 1252 int error_bitmask; 1253 unsigned int quirks; 1254 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1255 #define XHCI_RESET_EP_QUIRK (1 << 1) 1256 #define XHCI_NEC_HOST (1 << 2) 1257 u32 port_c_suspend[8]; /* port suspend change*/ 1258 u32 suspended_ports[8]; /* which ports are 1259 suspended */ 1260 unsigned long resume_done[MAX_HC_PORTS]; 1261 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1262 u8 *port_array; 1263 /* Array of pointers to USB 3.0 PORTSC registers */ 1264 u32 __iomem **usb3_ports; 1265 unsigned int num_usb3_ports; 1266 /* Array of pointers to USB 2.0 PORTSC registers */ 1267 u32 __iomem **usb2_ports; 1268 unsigned int num_usb2_ports; 1269 }; 1270 1271 /* For testing purposes */ 1272 #define NUM_TEST_NOOPS 0 1273 1274 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1275 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1276 { 1277 return (struct xhci_hcd *) (hcd->hcd_priv); 1278 } 1279 1280 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1281 { 1282 return container_of((void *) xhci, struct usb_hcd, hcd_priv); 1283 } 1284 1285 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1286 #define XHCI_DEBUG 1 1287 #else 1288 #define XHCI_DEBUG 0 1289 #endif 1290 1291 #define xhci_dbg(xhci, fmt, args...) \ 1292 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1293 #define xhci_info(xhci, fmt, args...) \ 1294 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1295 #define xhci_err(xhci, fmt, args...) \ 1296 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1297 #define xhci_warn(xhci, fmt, args...) \ 1298 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1299 1300 /* TODO: copied from ehci.h - can be refactored? */ 1301 /* xHCI spec says all registers are little endian */ 1302 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1303 __u32 __iomem *regs) 1304 { 1305 return readl(regs); 1306 } 1307 static inline void xhci_writel(struct xhci_hcd *xhci, 1308 const unsigned int val, __u32 __iomem *regs) 1309 { 1310 xhci_dbg(xhci, 1311 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", 1312 regs, val); 1313 writel(val, regs); 1314 } 1315 1316 /* 1317 * Registers should always be accessed with double word or quad word accesses. 1318 * 1319 * Some xHCI implementations may support 64-bit address pointers. Registers 1320 * with 64-bit address pointers should be written to with dword accesses by 1321 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1322 * xHCI implementations that do not support 64-bit address pointers will ignore 1323 * the high dword, and write order is irrelevant. 1324 */ 1325 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1326 __u64 __iomem *regs) 1327 { 1328 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1329 u64 val_lo = readl(ptr); 1330 u64 val_hi = readl(ptr + 1); 1331 return val_lo + (val_hi << 32); 1332 } 1333 static inline void xhci_write_64(struct xhci_hcd *xhci, 1334 const u64 val, __u64 __iomem *regs) 1335 { 1336 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1337 u32 val_lo = lower_32_bits(val); 1338 u32 val_hi = upper_32_bits(val); 1339 1340 xhci_dbg(xhci, 1341 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n", 1342 regs, (long unsigned int) val); 1343 writel(val_lo, ptr); 1344 writel(val_hi, ptr + 1); 1345 } 1346 1347 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1348 { 1349 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); 1350 return ((HC_VERSION(temp) == 0x95) && 1351 (xhci->quirks & XHCI_LINK_TRB_QUIRK)); 1352 } 1353 1354 /* xHCI debugging */ 1355 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num); 1356 void xhci_print_registers(struct xhci_hcd *xhci); 1357 void xhci_dbg_regs(struct xhci_hcd *xhci); 1358 void xhci_print_run_regs(struct xhci_hcd *xhci); 1359 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1360 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1361 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1362 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1363 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1364 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1365 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1366 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1367 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1368 struct xhci_container_ctx *ctx); 1369 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1370 unsigned int slot_id, unsigned int ep_index, 1371 struct xhci_virt_ep *ep); 1372 1373 /* xHCI memory management */ 1374 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1375 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1376 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1377 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1378 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1379 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1380 struct usb_device *udev); 1381 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1382 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1383 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1384 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1385 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1386 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1387 struct xhci_container_ctx *in_ctx, 1388 struct xhci_container_ctx *out_ctx, 1389 unsigned int ep_index); 1390 void xhci_slot_copy(struct xhci_hcd *xhci, 1391 struct xhci_container_ctx *in_ctx, 1392 struct xhci_container_ctx *out_ctx); 1393 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1394 struct usb_device *udev, struct usb_host_endpoint *ep, 1395 gfp_t mem_flags); 1396 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1397 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1398 struct xhci_virt_device *virt_dev, 1399 unsigned int ep_index); 1400 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1401 unsigned int num_stream_ctxs, 1402 unsigned int num_streams, gfp_t flags); 1403 void xhci_free_stream_info(struct xhci_hcd *xhci, 1404 struct xhci_stream_info *stream_info); 1405 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1406 struct xhci_ep_ctx *ep_ctx, 1407 struct xhci_stream_info *stream_info); 1408 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1409 struct xhci_ep_ctx *ep_ctx, 1410 struct xhci_virt_ep *ep); 1411 struct xhci_ring *xhci_dma_to_transfer_ring( 1412 struct xhci_virt_ep *ep, 1413 u64 address); 1414 struct xhci_ring *xhci_stream_id_to_ring( 1415 struct xhci_virt_device *dev, 1416 unsigned int ep_index, 1417 unsigned int stream_id); 1418 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1419 bool allocate_in_ctx, bool allocate_completion, 1420 gfp_t mem_flags); 1421 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); 1422 void xhci_free_command(struct xhci_hcd *xhci, 1423 struct xhci_command *command); 1424 1425 #ifdef CONFIG_PCI 1426 /* xHCI PCI glue */ 1427 int xhci_register_pci(void); 1428 void xhci_unregister_pci(void); 1429 #endif 1430 1431 /* xHCI host controller glue */ 1432 void xhci_quiesce(struct xhci_hcd *xhci); 1433 int xhci_halt(struct xhci_hcd *xhci); 1434 int xhci_reset(struct xhci_hcd *xhci); 1435 int xhci_init(struct usb_hcd *hcd); 1436 int xhci_run(struct usb_hcd *hcd); 1437 void xhci_stop(struct usb_hcd *hcd); 1438 void xhci_shutdown(struct usb_hcd *hcd); 1439 1440 #ifdef CONFIG_PM 1441 int xhci_suspend(struct xhci_hcd *xhci); 1442 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1443 #else 1444 #define xhci_suspend NULL 1445 #define xhci_resume NULL 1446 #endif 1447 1448 int xhci_get_frame(struct usb_hcd *hcd); 1449 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1450 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); 1451 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1452 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1453 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1454 struct usb_host_endpoint **eps, unsigned int num_eps, 1455 unsigned int num_streams, gfp_t mem_flags); 1456 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1457 struct usb_host_endpoint **eps, unsigned int num_eps, 1458 gfp_t mem_flags); 1459 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1460 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1461 struct usb_tt *tt, gfp_t mem_flags); 1462 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1463 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1464 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1465 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1466 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1467 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1468 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1469 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1470 1471 /* xHCI ring, segment, TRB, and TD functions */ 1472 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1473 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1474 union xhci_trb *start_trb, union xhci_trb *end_trb, 1475 dma_addr_t suspect_dma); 1476 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1477 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1478 void *xhci_setup_one_noop(struct xhci_hcd *xhci); 1479 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1480 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1481 u32 slot_id); 1482 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 1483 u32 field1, u32 field2, u32 field3, u32 field4); 1484 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1485 unsigned int ep_index, int suspend); 1486 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1487 int slot_id, unsigned int ep_index); 1488 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1489 int slot_id, unsigned int ep_index); 1490 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1491 int slot_id, unsigned int ep_index); 1492 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1493 struct urb *urb, int slot_id, unsigned int ep_index); 1494 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1495 u32 slot_id, bool command_must_succeed); 1496 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1497 u32 slot_id); 1498 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1499 unsigned int ep_index); 1500 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); 1501 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1502 unsigned int slot_id, unsigned int ep_index, 1503 unsigned int stream_id, struct xhci_td *cur_td, 1504 struct xhci_dequeue_state *state); 1505 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1506 unsigned int slot_id, unsigned int ep_index, 1507 unsigned int stream_id, 1508 struct xhci_dequeue_state *deq_state); 1509 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1510 struct usb_device *udev, unsigned int ep_index); 1511 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1512 unsigned int slot_id, unsigned int ep_index, 1513 struct xhci_dequeue_state *deq_state); 1514 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1515 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1516 unsigned int ep_index, unsigned int stream_id); 1517 1518 /* xHCI roothub code */ 1519 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1520 char *buf, u16 wLength); 1521 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1522 1523 #ifdef CONFIG_PM 1524 int xhci_bus_suspend(struct usb_hcd *hcd); 1525 int xhci_bus_resume(struct usb_hcd *hcd); 1526 #else 1527 #define xhci_bus_suspend NULL 1528 #define xhci_bus_resume NULL 1529 #endif /* CONFIG_PM */ 1530 1531 u32 xhci_port_state_to_neutral(u32 state); 1532 int xhci_find_slot_id_by_port(struct xhci_hcd *xhci, u16 port); 1533 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1534 1535 /* xHCI contexts */ 1536 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1537 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1538 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1539 1540 #endif /* __LINUX_XHCI_HCD_H */ 1541