1 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __LINUX_XHCI_HCD_H 25 #define __LINUX_XHCI_HCD_H 26 27 #include <linux/usb.h> 28 #include <linux/timer.h> 29 #include <linux/kernel.h> 30 #include <linux/usb/hcd.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 33 /* Code sharing between pci-quirks and xhci hcd */ 34 #include "xhci-ext-caps.h" 35 #include "pci-quirks.h" 36 37 /* xHCI PCI Configuration Registers */ 38 #define XHCI_SBRN_OFFSET (0x60) 39 40 /* Max number of USB devices for any host controller - limit in section 6.1 */ 41 #define MAX_HC_SLOTS 256 42 /* Section 5.3.3 - MaxPorts */ 43 #define MAX_HC_PORTS 127 44 45 /* 46 * xHCI register interface. 47 * This corresponds to the eXtensible Host Controller Interface (xHCI) 48 * Revision 0.95 specification 49 */ 50 51 /** 52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 53 * @hc_capbase: length of the capabilities register and HC version number 54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 57 * @hcc_params: HCCPARAMS - Capability Parameters 58 * @db_off: DBOFF - Doorbell array offset 59 * @run_regs_off: RTSOFF - Runtime register space offset 60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 61 */ 62 struct xhci_cap_regs { 63 __le32 hc_capbase; 64 __le32 hcs_params1; 65 __le32 hcs_params2; 66 __le32 hcs_params3; 67 __le32 hcc_params; 68 __le32 db_off; 69 __le32 run_regs_off; 70 __le32 hcc_params2; /* xhci 1.1 */ 71 /* Reserved up to (CAPLENGTH - 0x1C) */ 72 }; 73 74 /* hc_capbase bitmasks */ 75 /* bits 7:0 - how long is the Capabilities register */ 76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 77 /* bits 31:16 */ 78 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 79 80 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 81 /* bits 0:7, Max Device Slots */ 82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 83 #define HCS_SLOTS_MASK 0xff 84 /* bits 8:18, Max Interrupters */ 85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 88 89 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 90 /* bits 0:3, frames or uframes that SW needs to queue transactions 91 * ahead of the HW to meet periodic deadlines */ 92 #define HCS_IST(p) (((p) >> 0) & 0xf) 93 /* bits 4:7, max number of Event Ring segments */ 94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 99 100 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 105 106 /* HCCPARAMS - hcc_params - bitmasks */ 107 /* true: HC can use 64-bit address pointers */ 108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 109 /* true: HC can do bandwidth negotiation */ 110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 111 /* true: HC uses 64-byte Device Context structures 112 * FIXME 64-byte context structures aren't supported yet. 113 */ 114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 115 /* true: HC has port power switches */ 116 #define HCC_PPC(p) ((p) & (1 << 3)) 117 /* true: HC has port indicators */ 118 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 119 /* true: HC has Light HC Reset Capability */ 120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 121 /* true: HC supports latency tolerance messaging */ 122 #define HCC_LTC(p) ((p) & (1 << 6)) 123 /* true: no secondary Stream ID Support */ 124 #define HCC_NSS(p) ((p) & (1 << 7)) 125 /* true: HC supports Stopped - Short Packet */ 126 #define HCC_SPC(p) ((p) & (1 << 9)) 127 /* true: HC has Contiguous Frame ID Capability */ 128 #define HCC_CFC(p) ((p) & (1 << 11)) 129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 133 134 /* db_off bitmask - bits 0:1 reserved */ 135 #define DBOFF_MASK (~0x3) 136 137 /* run_regs_off bitmask - bits 0:4 reserved */ 138 #define RTSOFF_MASK (~0x1f) 139 140 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 141 /* true: HC supports U3 entry Capability */ 142 #define HCC2_U3C(p) ((p) & (1 << 0)) 143 /* true: HC supports Configure endpoint command Max exit latency too large */ 144 #define HCC2_CMC(p) ((p) & (1 << 1)) 145 /* true: HC supports Force Save context Capability */ 146 #define HCC2_FSC(p) ((p) & (1 << 2)) 147 /* true: HC supports Compliance Transition Capability */ 148 #define HCC2_CTC(p) ((p) & (1 << 3)) 149 /* true: HC support Large ESIT payload Capability > 48k */ 150 #define HCC2_LEC(p) ((p) & (1 << 4)) 151 /* true: HC support Configuration Information Capability */ 152 #define HCC2_CIC(p) ((p) & (1 << 5)) 153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 154 #define HCC2_ETC(p) ((p) & (1 << 6)) 155 156 /* Number of registers per port */ 157 #define NUM_PORT_REGS 4 158 159 #define PORTSC 0 160 #define PORTPMSC 1 161 #define PORTLI 2 162 #define PORTHLPMC 3 163 164 /** 165 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 166 * @command: USBCMD - xHC command register 167 * @status: USBSTS - xHC status register 168 * @page_size: This indicates the page size that the host controller 169 * supports. If bit n is set, the HC supports a page size 170 * of 2^(n+12), up to a 128MB page size. 171 * 4K is the minimum page size. 172 * @cmd_ring: CRP - 64-bit Command Ring Pointer 173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 174 * @config_reg: CONFIG - Configure Register 175 * @port_status_base: PORTSCn - base address for Port Status and Control 176 * Each port has a Port Status and Control register, 177 * followed by a Port Power Management Status and Control 178 * register, a Port Link Info register, and a reserved 179 * register. 180 * @port_power_base: PORTPMSCn - base address for 181 * Port Power Management Status and Control 182 * @port_link_base: PORTLIn - base address for Port Link Info (current 183 * Link PM state and control) for USB 2.1 and USB 3.0 184 * devices. 185 */ 186 struct xhci_op_regs { 187 __le32 command; 188 __le32 status; 189 __le32 page_size; 190 __le32 reserved1; 191 __le32 reserved2; 192 __le32 dev_notification; 193 __le64 cmd_ring; 194 /* rsvd: offset 0x20-2F */ 195 __le32 reserved3[4]; 196 __le64 dcbaa_ptr; 197 __le32 config_reg; 198 /* rsvd: offset 0x3C-3FF */ 199 __le32 reserved4[241]; 200 /* port 1 registers, which serve as a base address for other ports */ 201 __le32 port_status_base; 202 __le32 port_power_base; 203 __le32 port_link_base; 204 __le32 reserved5; 205 /* registers for ports 2-255 */ 206 __le32 reserved6[NUM_PORT_REGS*254]; 207 }; 208 209 /* USBCMD - USB command - command bitmasks */ 210 /* start/stop HC execution - do not write unless HC is halted*/ 211 #define CMD_RUN XHCI_CMD_RUN 212 /* Reset HC - resets internal HC state machine and all registers (except 213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 214 * The xHCI driver must reinitialize the xHC after setting this bit. 215 */ 216 #define CMD_RESET (1 << 1) 217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 218 #define CMD_EIE XHCI_CMD_EIE 219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 220 #define CMD_HSEIE XHCI_CMD_HSEIE 221 /* bits 4:6 are reserved (and should be preserved on writes). */ 222 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 223 #define CMD_LRESET (1 << 7) 224 /* host controller save/restore state. */ 225 #define CMD_CSS (1 << 8) 226 #define CMD_CRS (1 << 9) 227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 228 #define CMD_EWE XHCI_CMD_EWE 229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 231 * '0' means the xHC can power it off if all ports are in the disconnect, 232 * disabled, or powered-off state. 233 */ 234 #define CMD_PM_INDEX (1 << 11) 235 /* bits 12:31 are reserved (and should be preserved on writes). */ 236 237 /* IMAN - Interrupt Management Register */ 238 #define IMAN_IE (1 << 1) 239 #define IMAN_IP (1 << 0) 240 241 /* USBSTS - USB status - status bitmasks */ 242 /* HC not running - set to 1 when run/stop bit is cleared. */ 243 #define STS_HALT XHCI_STS_HALT 244 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 245 #define STS_FATAL (1 << 2) 246 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 247 #define STS_EINT (1 << 3) 248 /* port change detect */ 249 #define STS_PORT (1 << 4) 250 /* bits 5:7 reserved and zeroed */ 251 /* save state status - '1' means xHC is saving state */ 252 #define STS_SAVE (1 << 8) 253 /* restore state status - '1' means xHC is restoring state */ 254 #define STS_RESTORE (1 << 9) 255 /* true: save or restore error */ 256 #define STS_SRE (1 << 10) 257 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 258 #define STS_CNR XHCI_STS_CNR 259 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 260 #define STS_HCE (1 << 12) 261 /* bits 13:31 reserved and should be preserved */ 262 263 /* 264 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 265 * Generate a device notification event when the HC sees a transaction with a 266 * notification type that matches a bit set in this bit field. 267 */ 268 #define DEV_NOTE_MASK (0xffff) 269 #define ENABLE_DEV_NOTE(x) (1 << (x)) 270 /* Most of the device notification types should only be used for debug. 271 * SW does need to pay attention to function wake notifications. 272 */ 273 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 274 275 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 276 /* bit 0 is the command ring cycle state */ 277 /* stop ring operation after completion of the currently executing command */ 278 #define CMD_RING_PAUSE (1 << 1) 279 /* stop ring immediately - abort the currently executing command */ 280 #define CMD_RING_ABORT (1 << 2) 281 /* true: command ring is running */ 282 #define CMD_RING_RUNNING (1 << 3) 283 /* bits 4:5 reserved and should be preserved */ 284 /* Command Ring pointer - bit mask for the lower 32 bits. */ 285 #define CMD_RING_RSVD_BITS (0x3f) 286 287 /* CONFIG - Configure Register - config_reg bitmasks */ 288 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 289 #define MAX_DEVS(p) ((p) & 0xff) 290 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 291 #define CONFIG_U3E (1 << 8) 292 /* bit 9: Configuration Information Enable, xhci 1.1 */ 293 #define CONFIG_CIE (1 << 9) 294 /* bits 10:31 - reserved and should be preserved */ 295 296 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 297 /* true: device connected */ 298 #define PORT_CONNECT (1 << 0) 299 /* true: port enabled */ 300 #define PORT_PE (1 << 1) 301 /* bit 2 reserved and zeroed */ 302 /* true: port has an over-current condition */ 303 #define PORT_OC (1 << 3) 304 /* true: port reset signaling asserted */ 305 #define PORT_RESET (1 << 4) 306 /* Port Link State - bits 5:8 307 * A read gives the current link PM state of the port, 308 * a write with Link State Write Strobe set sets the link state. 309 */ 310 #define PORT_PLS_MASK (0xf << 5) 311 #define XDEV_U0 (0x0 << 5) 312 #define XDEV_U2 (0x2 << 5) 313 #define XDEV_U3 (0x3 << 5) 314 #define XDEV_INACTIVE (0x6 << 5) 315 #define XDEV_RESUME (0xf << 5) 316 /* true: port has power (see HCC_PPC) */ 317 #define PORT_POWER (1 << 9) 318 /* bits 10:13 indicate device speed: 319 * 0 - undefined speed - port hasn't be initialized by a reset yet 320 * 1 - full speed 321 * 2 - low speed 322 * 3 - high speed 323 * 4 - super speed 324 * 5-15 reserved 325 */ 326 #define DEV_SPEED_MASK (0xf << 10) 327 #define XDEV_FS (0x1 << 10) 328 #define XDEV_LS (0x2 << 10) 329 #define XDEV_HS (0x3 << 10) 330 #define XDEV_SS (0x4 << 10) 331 #define XDEV_SSP (0x5 << 10) 332 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 333 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 334 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 335 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 336 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 337 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 338 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 339 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 340 341 /* Bits 20:23 in the Slot Context are the speed for the device */ 342 #define SLOT_SPEED_FS (XDEV_FS << 10) 343 #define SLOT_SPEED_LS (XDEV_LS << 10) 344 #define SLOT_SPEED_HS (XDEV_HS << 10) 345 #define SLOT_SPEED_SS (XDEV_SS << 10) 346 /* Port Indicator Control */ 347 #define PORT_LED_OFF (0 << 14) 348 #define PORT_LED_AMBER (1 << 14) 349 #define PORT_LED_GREEN (2 << 14) 350 #define PORT_LED_MASK (3 << 14) 351 /* Port Link State Write Strobe - set this when changing link state */ 352 #define PORT_LINK_STROBE (1 << 16) 353 /* true: connect status change */ 354 #define PORT_CSC (1 << 17) 355 /* true: port enable change */ 356 #define PORT_PEC (1 << 18) 357 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 358 * into an enabled state, and the device into the default state. A "warm" reset 359 * also resets the link, forcing the device through the link training sequence. 360 * SW can also look at the Port Reset register to see when warm reset is done. 361 */ 362 #define PORT_WRC (1 << 19) 363 /* true: over-current change */ 364 #define PORT_OCC (1 << 20) 365 /* true: reset change - 1 to 0 transition of PORT_RESET */ 366 #define PORT_RC (1 << 21) 367 /* port link status change - set on some port link state transitions: 368 * Transition Reason 369 * ------------------------------------------------------------------------------ 370 * - U3 to Resume Wakeup signaling from a device 371 * - Resume to Recovery to U0 USB 3.0 device resume 372 * - Resume to U0 USB 2.0 device resume 373 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 374 * - U3 to U0 Software resume of USB 2.0 device complete 375 * - U2 to U0 L1 resume of USB 2.1 device complete 376 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 377 * - U0 to disabled L1 entry error with USB 2.1 device 378 * - Any state to inactive Error on USB 3.0 port 379 */ 380 #define PORT_PLC (1 << 22) 381 /* port configure error change - port failed to configure its link partner */ 382 #define PORT_CEC (1 << 23) 383 /* Cold Attach Status - xHC can set this bit to report device attached during 384 * Sx state. Warm port reset should be perfomed to clear this bit and move port 385 * to connected state. 386 */ 387 #define PORT_CAS (1 << 24) 388 /* wake on connect (enable) */ 389 #define PORT_WKCONN_E (1 << 25) 390 /* wake on disconnect (enable) */ 391 #define PORT_WKDISC_E (1 << 26) 392 /* wake on over-current (enable) */ 393 #define PORT_WKOC_E (1 << 27) 394 /* bits 28:29 reserved */ 395 /* true: device is non-removable - for USB 3.0 roothub emulation */ 396 #define PORT_DEV_REMOVE (1 << 30) 397 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 398 #define PORT_WR (1 << 31) 399 400 /* We mark duplicate entries with -1 */ 401 #define DUPLICATE_ENTRY ((u8)(-1)) 402 403 /* Port Power Management Status and Control - port_power_base bitmasks */ 404 /* Inactivity timer value for transitions into U1, in microseconds. 405 * Timeout can be up to 127us. 0xFF means an infinite timeout. 406 */ 407 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 408 #define PORT_U1_TIMEOUT_MASK 0xff 409 /* Inactivity timer value for transitions into U2 */ 410 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 411 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 412 /* Bits 24:31 for port testing */ 413 414 /* USB2 Protocol PORTSPMSC */ 415 #define PORT_L1S_MASK 7 416 #define PORT_L1S_SUCCESS 1 417 #define PORT_RWE (1 << 3) 418 #define PORT_HIRD(p) (((p) & 0xf) << 4) 419 #define PORT_HIRD_MASK (0xf << 4) 420 #define PORT_L1DS_MASK (0xff << 8) 421 #define PORT_L1DS(p) (((p) & 0xff) << 8) 422 #define PORT_HLE (1 << 16) 423 424 /* USB3 Protocol PORTLI Port Link Information */ 425 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 426 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 427 428 /* USB2 Protocol PORTHLPMC */ 429 #define PORT_HIRDM(p)((p) & 3) 430 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 431 #define PORT_BESLD(p)(((p) & 0xf) << 10) 432 433 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 434 #define XHCI_L1_TIMEOUT 512 435 436 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 437 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 438 * by other operating systems. 439 * 440 * XHCI 1.0 errata 8/14/12 Table 13 notes: 441 * "Software should choose xHC BESL/BESLD field values that do not violate a 442 * device's resume latency requirements, 443 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 444 * or not program values < '4' if BLC = '0' and a BESL device is attached. 445 */ 446 #define XHCI_DEFAULT_BESL 4 447 448 /** 449 * struct xhci_intr_reg - Interrupt Register Set 450 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 451 * interrupts and check for pending interrupts. 452 * @irq_control: IMOD - Interrupt Moderation Register. 453 * Used to throttle interrupts. 454 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 455 * @erst_base: ERST base address. 456 * @erst_dequeue: Event ring dequeue pointer. 457 * 458 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 459 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 460 * multiple segments of the same size. The HC places events on the ring and 461 * "updates the Cycle bit in the TRBs to indicate to software the current 462 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 463 * updates the dequeue pointer. 464 */ 465 struct xhci_intr_reg { 466 __le32 irq_pending; 467 __le32 irq_control; 468 __le32 erst_size; 469 __le32 rsvd; 470 __le64 erst_base; 471 __le64 erst_dequeue; 472 }; 473 474 /* irq_pending bitmasks */ 475 #define ER_IRQ_PENDING(p) ((p) & 0x1) 476 /* bits 2:31 need to be preserved */ 477 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 478 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 479 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 480 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 481 482 /* irq_control bitmasks */ 483 /* Minimum interval between interrupts (in 250ns intervals). The interval 484 * between interrupts will be longer if there are no events on the event ring. 485 * Default is 4000 (1 ms). 486 */ 487 #define ER_IRQ_INTERVAL_MASK (0xffff) 488 /* Counter used to count down the time to the next interrupt - HW use only */ 489 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 490 491 /* erst_size bitmasks */ 492 /* Preserve bits 16:31 of erst_size */ 493 #define ERST_SIZE_MASK (0xffff << 16) 494 495 /* erst_dequeue bitmasks */ 496 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 497 * where the current dequeue pointer lies. This is an optional HW hint. 498 */ 499 #define ERST_DESI_MASK (0x7) 500 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 501 * a work queue (or delayed service routine)? 502 */ 503 #define ERST_EHB (1 << 3) 504 #define ERST_PTR_MASK (0xf) 505 506 /** 507 * struct xhci_run_regs 508 * @microframe_index: 509 * MFINDEX - current microframe number 510 * 511 * Section 5.5 Host Controller Runtime Registers: 512 * "Software should read and write these registers using only Dword (32 bit) 513 * or larger accesses" 514 */ 515 struct xhci_run_regs { 516 __le32 microframe_index; 517 __le32 rsvd[7]; 518 struct xhci_intr_reg ir_set[128]; 519 }; 520 521 /** 522 * struct doorbell_array 523 * 524 * Bits 0 - 7: Endpoint target 525 * Bits 8 - 15: RsvdZ 526 * Bits 16 - 31: Stream ID 527 * 528 * Section 5.6 529 */ 530 struct xhci_doorbell_array { 531 __le32 doorbell[256]; 532 }; 533 534 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 535 #define DB_VALUE_HOST 0x00000000 536 537 /** 538 * struct xhci_protocol_caps 539 * @revision: major revision, minor revision, capability ID, 540 * and next capability pointer. 541 * @name_string: Four ASCII characters to say which spec this xHC 542 * follows, typically "USB ". 543 * @port_info: Port offset, count, and protocol-defined information. 544 */ 545 struct xhci_protocol_caps { 546 u32 revision; 547 u32 name_string; 548 u32 port_info; 549 }; 550 551 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 552 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 553 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 554 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 555 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 556 557 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 558 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 559 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 560 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 561 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 562 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 563 564 #define PLT_MASK (0x03 << 6) 565 #define PLT_SYM (0x00 << 6) 566 #define PLT_ASYM_RX (0x02 << 6) 567 #define PLT_ASYM_TX (0x03 << 6) 568 569 /** 570 * struct xhci_container_ctx 571 * @type: Type of context. Used to calculated offsets to contained contexts. 572 * @size: Size of the context data 573 * @bytes: The raw context data given to HW 574 * @dma: dma address of the bytes 575 * 576 * Represents either a Device or Input context. Holds a pointer to the raw 577 * memory used for the context (bytes) and dma address of it (dma). 578 */ 579 struct xhci_container_ctx { 580 unsigned type; 581 #define XHCI_CTX_TYPE_DEVICE 0x1 582 #define XHCI_CTX_TYPE_INPUT 0x2 583 584 int size; 585 586 u8 *bytes; 587 dma_addr_t dma; 588 }; 589 590 /** 591 * struct xhci_slot_ctx 592 * @dev_info: Route string, device speed, hub info, and last valid endpoint 593 * @dev_info2: Max exit latency for device number, root hub port number 594 * @tt_info: tt_info is used to construct split transaction tokens 595 * @dev_state: slot state and device address 596 * 597 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 598 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 599 * reserved at the end of the slot context for HC internal use. 600 */ 601 struct xhci_slot_ctx { 602 __le32 dev_info; 603 __le32 dev_info2; 604 __le32 tt_info; 605 __le32 dev_state; 606 /* offset 0x10 to 0x1f reserved for HC internal use */ 607 __le32 reserved[4]; 608 }; 609 610 /* dev_info bitmasks */ 611 /* Route String - 0:19 */ 612 #define ROUTE_STRING_MASK (0xfffff) 613 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 614 #define DEV_SPEED (0xf << 20) 615 /* bit 24 reserved */ 616 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 617 #define DEV_MTT (0x1 << 25) 618 /* Set if the device is a hub - bit 26 */ 619 #define DEV_HUB (0x1 << 26) 620 /* Index of the last valid endpoint context in this device context - 27:31 */ 621 #define LAST_CTX_MASK (0x1f << 27) 622 #define LAST_CTX(p) ((p) << 27) 623 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 624 #define SLOT_FLAG (1 << 0) 625 #define EP0_FLAG (1 << 1) 626 627 /* dev_info2 bitmasks */ 628 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 629 #define MAX_EXIT (0xffff) 630 /* Root hub port number that is needed to access the USB device */ 631 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 632 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 633 /* Maximum number of ports under a hub device */ 634 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 635 636 /* tt_info bitmasks */ 637 /* 638 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 639 * The Slot ID of the hub that isolates the high speed signaling from 640 * this low or full-speed device. '0' if attached to root hub port. 641 */ 642 #define TT_SLOT (0xff) 643 /* 644 * The number of the downstream facing port of the high-speed hub 645 * '0' if the device is not low or full speed. 646 */ 647 #define TT_PORT (0xff << 8) 648 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 649 650 /* dev_state bitmasks */ 651 /* USB device address - assigned by the HC */ 652 #define DEV_ADDR_MASK (0xff) 653 /* bits 8:26 reserved */ 654 /* Slot state */ 655 #define SLOT_STATE (0x1f << 27) 656 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 657 658 #define SLOT_STATE_DISABLED 0 659 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 660 #define SLOT_STATE_DEFAULT 1 661 #define SLOT_STATE_ADDRESSED 2 662 #define SLOT_STATE_CONFIGURED 3 663 664 /** 665 * struct xhci_ep_ctx 666 * @ep_info: endpoint state, streams, mult, and interval information. 667 * @ep_info2: information on endpoint type, max packet size, max burst size, 668 * error count, and whether the HC will force an event for all 669 * transactions. 670 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 671 * defines one stream, this points to the endpoint transfer ring. 672 * Otherwise, it points to a stream context array, which has a 673 * ring pointer for each flow. 674 * @tx_info: 675 * Average TRB lengths for the endpoint ring and 676 * max payload within an Endpoint Service Interval Time (ESIT). 677 * 678 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 679 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 680 * reserved at the end of the endpoint context for HC internal use. 681 */ 682 struct xhci_ep_ctx { 683 __le32 ep_info; 684 __le32 ep_info2; 685 __le64 deq; 686 __le32 tx_info; 687 /* offset 0x14 - 0x1f reserved for HC internal use */ 688 __le32 reserved[3]; 689 }; 690 691 /* ep_info bitmasks */ 692 /* 693 * Endpoint State - bits 0:2 694 * 0 - disabled 695 * 1 - running 696 * 2 - halted due to halt condition - ok to manipulate endpoint ring 697 * 3 - stopped 698 * 4 - TRB error 699 * 5-7 - reserved 700 */ 701 #define EP_STATE_MASK (0xf) 702 #define EP_STATE_DISABLED 0 703 #define EP_STATE_RUNNING 1 704 #define EP_STATE_HALTED 2 705 #define EP_STATE_STOPPED 3 706 #define EP_STATE_ERROR 4 707 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 708 #define EP_MULT(p) (((p) & 0x3) << 8) 709 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 710 /* bits 10:14 are Max Primary Streams */ 711 /* bit 15 is Linear Stream Array */ 712 /* Interval - period between requests to an endpoint - 125u increments. */ 713 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 714 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 715 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 716 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 717 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 718 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 719 #define EP_HAS_LSA (1 << 15) 720 721 /* ep_info2 bitmasks */ 722 /* 723 * Force Event - generate transfer events for all TRBs for this endpoint 724 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 725 */ 726 #define FORCE_EVENT (0x1) 727 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 728 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 729 #define EP_TYPE(p) ((p) << 3) 730 #define ISOC_OUT_EP 1 731 #define BULK_OUT_EP 2 732 #define INT_OUT_EP 3 733 #define CTRL_EP 4 734 #define ISOC_IN_EP 5 735 #define BULK_IN_EP 6 736 #define INT_IN_EP 7 737 /* bit 6 reserved */ 738 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 739 #define MAX_BURST(p) (((p)&0xff) << 8) 740 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 741 #define MAX_PACKET(p) (((p)&0xffff) << 16) 742 #define MAX_PACKET_MASK (0xffff << 16) 743 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 744 745 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 746 * USB2.0 spec 9.6.6. 747 */ 748 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 749 750 /* tx_info bitmasks */ 751 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 752 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 753 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 754 755 /* deq bitmasks */ 756 #define EP_CTX_CYCLE_MASK (1 << 0) 757 #define SCTX_DEQ_MASK (~0xfL) 758 759 760 /** 761 * struct xhci_input_control_context 762 * Input control context; see section 6.2.5. 763 * 764 * @drop_context: set the bit of the endpoint context you want to disable 765 * @add_context: set the bit of the endpoint context you want to enable 766 */ 767 struct xhci_input_control_ctx { 768 __le32 drop_flags; 769 __le32 add_flags; 770 __le32 rsvd2[6]; 771 }; 772 773 #define EP_IS_ADDED(ctrl_ctx, i) \ 774 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 775 #define EP_IS_DROPPED(ctrl_ctx, i) \ 776 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 777 778 /* Represents everything that is needed to issue a command on the command ring. 779 * It's useful to pre-allocate these for commands that cannot fail due to 780 * out-of-memory errors, like freeing streams. 781 */ 782 struct xhci_command { 783 /* Input context for changing device state */ 784 struct xhci_container_ctx *in_ctx; 785 u32 status; 786 /* If completion is null, no one is waiting on this command 787 * and the structure can be freed after the command completes. 788 */ 789 struct completion *completion; 790 union xhci_trb *command_trb; 791 struct list_head cmd_list; 792 }; 793 794 /* drop context bitmasks */ 795 #define DROP_EP(x) (0x1 << x) 796 /* add context bitmasks */ 797 #define ADD_EP(x) (0x1 << x) 798 799 struct xhci_stream_ctx { 800 /* 64-bit stream ring address, cycle state, and stream type */ 801 __le64 stream_ring; 802 /* offset 0x14 - 0x1f reserved for HC internal use */ 803 __le32 reserved[2]; 804 }; 805 806 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 807 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 808 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 809 #define SCT_SEC_TR 0 810 /* Primary stream array type, dequeue pointer is to a transfer ring */ 811 #define SCT_PRI_TR 1 812 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 813 #define SCT_SSA_8 2 814 #define SCT_SSA_16 3 815 #define SCT_SSA_32 4 816 #define SCT_SSA_64 5 817 #define SCT_SSA_128 6 818 #define SCT_SSA_256 7 819 820 /* Assume no secondary streams for now */ 821 struct xhci_stream_info { 822 struct xhci_ring **stream_rings; 823 /* Number of streams, including stream 0 (which drivers can't use) */ 824 unsigned int num_streams; 825 /* The stream context array may be bigger than 826 * the number of streams the driver asked for 827 */ 828 struct xhci_stream_ctx *stream_ctx_array; 829 unsigned int num_stream_ctxs; 830 dma_addr_t ctx_array_dma; 831 /* For mapping physical TRB addresses to segments in stream rings */ 832 struct radix_tree_root trb_address_map; 833 struct xhci_command *free_streams_command; 834 }; 835 836 #define SMALL_STREAM_ARRAY_SIZE 256 837 #define MEDIUM_STREAM_ARRAY_SIZE 1024 838 839 /* Some Intel xHCI host controllers need software to keep track of the bus 840 * bandwidth. Keep track of endpoint info here. Each root port is allocated 841 * the full bus bandwidth. We must also treat TTs (including each port under a 842 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 843 * (DMI) also limits the total bandwidth (across all domains) that can be used. 844 */ 845 struct xhci_bw_info { 846 /* ep_interval is zero-based */ 847 unsigned int ep_interval; 848 /* mult and num_packets are one-based */ 849 unsigned int mult; 850 unsigned int num_packets; 851 unsigned int max_packet_size; 852 unsigned int max_esit_payload; 853 unsigned int type; 854 }; 855 856 /* "Block" sizes in bytes the hardware uses for different device speeds. 857 * The logic in this part of the hardware limits the number of bits the hardware 858 * can use, so must represent bandwidth in a less precise manner to mimic what 859 * the scheduler hardware computes. 860 */ 861 #define FS_BLOCK 1 862 #define HS_BLOCK 4 863 #define SS_BLOCK 16 864 #define DMI_BLOCK 32 865 866 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 867 * with each byte transferred. SuperSpeed devices have an initial overhead to 868 * set up bursts. These are in blocks, see above. LS overhead has already been 869 * translated into FS blocks. 870 */ 871 #define DMI_OVERHEAD 8 872 #define DMI_OVERHEAD_BURST 4 873 #define SS_OVERHEAD 8 874 #define SS_OVERHEAD_BURST 32 875 #define HS_OVERHEAD 26 876 #define FS_OVERHEAD 20 877 #define LS_OVERHEAD 128 878 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 879 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 880 * of overhead associated with split transfers crossing microframe boundaries. 881 * 31 blocks is pure protocol overhead. 882 */ 883 #define TT_HS_OVERHEAD (31 + 94) 884 #define TT_DMI_OVERHEAD (25 + 12) 885 886 /* Bandwidth limits in blocks */ 887 #define FS_BW_LIMIT 1285 888 #define TT_BW_LIMIT 1320 889 #define HS_BW_LIMIT 1607 890 #define SS_BW_LIMIT_IN 3906 891 #define DMI_BW_LIMIT_IN 3906 892 #define SS_BW_LIMIT_OUT 3906 893 #define DMI_BW_LIMIT_OUT 3906 894 895 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 896 #define FS_BW_RESERVED 10 897 #define HS_BW_RESERVED 20 898 #define SS_BW_RESERVED 10 899 900 struct xhci_virt_ep { 901 struct xhci_ring *ring; 902 /* Related to endpoints that are configured to use stream IDs only */ 903 struct xhci_stream_info *stream_info; 904 /* Temporary storage in case the configure endpoint command fails and we 905 * have to restore the device state to the previous state 906 */ 907 struct xhci_ring *new_ring; 908 unsigned int ep_state; 909 #define SET_DEQ_PENDING (1 << 0) 910 #define EP_HALTED (1 << 1) /* For stall handling */ 911 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 912 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 913 #define EP_GETTING_STREAMS (1 << 3) 914 #define EP_HAS_STREAMS (1 << 4) 915 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 916 #define EP_GETTING_NO_STREAMS (1 << 5) 917 /* ---- Related to URB cancellation ---- */ 918 struct list_head cancelled_td_list; 919 struct xhci_td *stopped_td; 920 unsigned int stopped_stream; 921 /* Watchdog timer for stop endpoint command to cancel URBs */ 922 struct timer_list stop_cmd_timer; 923 int stop_cmds_pending; 924 struct xhci_hcd *xhci; 925 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 926 * command. We'll need to update the ring's dequeue segment and dequeue 927 * pointer after the command completes. 928 */ 929 struct xhci_segment *queued_deq_seg; 930 union xhci_trb *queued_deq_ptr; 931 /* 932 * Sometimes the xHC can not process isochronous endpoint ring quickly 933 * enough, and it will miss some isoc tds on the ring and generate 934 * a Missed Service Error Event. 935 * Set skip flag when receive a Missed Service Error Event and 936 * process the missed tds on the endpoint ring. 937 */ 938 bool skip; 939 /* Bandwidth checking storage */ 940 struct xhci_bw_info bw_info; 941 struct list_head bw_endpoint_list; 942 /* Isoch Frame ID checking storage */ 943 int next_frame_id; 944 }; 945 946 enum xhci_overhead_type { 947 LS_OVERHEAD_TYPE = 0, 948 FS_OVERHEAD_TYPE, 949 HS_OVERHEAD_TYPE, 950 }; 951 952 struct xhci_interval_bw { 953 unsigned int num_packets; 954 /* Sorted by max packet size. 955 * Head of the list is the greatest max packet size. 956 */ 957 struct list_head endpoints; 958 /* How many endpoints of each speed are present. */ 959 unsigned int overhead[3]; 960 }; 961 962 #define XHCI_MAX_INTERVAL 16 963 964 struct xhci_interval_bw_table { 965 unsigned int interval0_esit_payload; 966 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 967 /* Includes reserved bandwidth for async endpoints */ 968 unsigned int bw_used; 969 unsigned int ss_bw_in; 970 unsigned int ss_bw_out; 971 }; 972 973 974 struct xhci_virt_device { 975 struct usb_device *udev; 976 /* 977 * Commands to the hardware are passed an "input context" that 978 * tells the hardware what to change in its data structures. 979 * The hardware will return changes in an "output context" that 980 * software must allocate for the hardware. We need to keep 981 * track of input and output contexts separately because 982 * these commands might fail and we don't trust the hardware. 983 */ 984 struct xhci_container_ctx *out_ctx; 985 /* Used for addressing devices and configuration changes */ 986 struct xhci_container_ctx *in_ctx; 987 /* Rings saved to ensure old alt settings can be re-instated */ 988 struct xhci_ring **ring_cache; 989 int num_rings_cached; 990 #define XHCI_MAX_RINGS_CACHED 31 991 struct xhci_virt_ep eps[31]; 992 struct completion cmd_completion; 993 u8 fake_port; 994 u8 real_port; 995 struct xhci_interval_bw_table *bw_table; 996 struct xhci_tt_bw_info *tt_info; 997 /* The current max exit latency for the enabled USB3 link states. */ 998 u16 current_mel; 999 }; 1000 1001 /* 1002 * For each roothub, keep track of the bandwidth information for each periodic 1003 * interval. 1004 * 1005 * If a high speed hub is attached to the roothub, each TT associated with that 1006 * hub is a separate bandwidth domain. The interval information for the 1007 * endpoints on the devices under that TT will appear in the TT structure. 1008 */ 1009 struct xhci_root_port_bw_info { 1010 struct list_head tts; 1011 unsigned int num_active_tts; 1012 struct xhci_interval_bw_table bw_table; 1013 }; 1014 1015 struct xhci_tt_bw_info { 1016 struct list_head tt_list; 1017 int slot_id; 1018 int ttport; 1019 struct xhci_interval_bw_table bw_table; 1020 int active_eps; 1021 }; 1022 1023 1024 /** 1025 * struct xhci_device_context_array 1026 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1027 */ 1028 struct xhci_device_context_array { 1029 /* 64-bit device addresses; we only write 32-bit addresses */ 1030 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1031 /* private xHCD pointers */ 1032 dma_addr_t dma; 1033 }; 1034 /* TODO: write function to set the 64-bit device DMA address */ 1035 /* 1036 * TODO: change this to be dynamically sized at HC mem init time since the HC 1037 * might not be able to handle the maximum number of devices possible. 1038 */ 1039 1040 1041 struct xhci_transfer_event { 1042 /* 64-bit buffer address, or immediate data */ 1043 __le64 buffer; 1044 __le32 transfer_len; 1045 /* This field is interpreted differently based on the type of TRB */ 1046 __le32 flags; 1047 }; 1048 1049 /* Transfer event TRB length bit mask */ 1050 /* bits 0:23 */ 1051 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1052 1053 /** Transfer Event bit fields **/ 1054 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1055 1056 /* Completion Code - only applicable for some types of TRBs */ 1057 #define COMP_CODE_MASK (0xff << 24) 1058 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1059 #define COMP_SUCCESS 1 1060 /* Data Buffer Error */ 1061 #define COMP_DB_ERR 2 1062 /* Babble Detected Error */ 1063 #define COMP_BABBLE 3 1064 /* USB Transaction Error */ 1065 #define COMP_TX_ERR 4 1066 /* TRB Error - some TRB field is invalid */ 1067 #define COMP_TRB_ERR 5 1068 /* Stall Error - USB device is stalled */ 1069 #define COMP_STALL 6 1070 /* Resource Error - HC doesn't have memory for that device configuration */ 1071 #define COMP_ENOMEM 7 1072 /* Bandwidth Error - not enough room in schedule for this dev config */ 1073 #define COMP_BW_ERR 8 1074 /* No Slots Available Error - HC ran out of device slots */ 1075 #define COMP_ENOSLOTS 9 1076 /* Invalid Stream Type Error */ 1077 #define COMP_STREAM_ERR 10 1078 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 1079 #define COMP_EBADSLT 11 1080 /* Endpoint Not Enabled Error */ 1081 #define COMP_EBADEP 12 1082 /* Short Packet */ 1083 #define COMP_SHORT_TX 13 1084 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 1085 #define COMP_UNDERRUN 14 1086 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 1087 #define COMP_OVERRUN 15 1088 /* Virtual Function Event Ring Full Error */ 1089 #define COMP_VF_FULL 16 1090 /* Parameter Error - Context parameter is invalid */ 1091 #define COMP_EINVAL 17 1092 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 1093 #define COMP_BW_OVER 18 1094 /* Context State Error - illegal context state transition requested */ 1095 #define COMP_CTX_STATE 19 1096 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 1097 #define COMP_PING_ERR 20 1098 /* Event Ring is full */ 1099 #define COMP_ER_FULL 21 1100 /* Incompatible Device Error */ 1101 #define COMP_DEV_ERR 22 1102 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 1103 #define COMP_MISSED_INT 23 1104 /* Successfully stopped command ring */ 1105 #define COMP_CMD_STOP 24 1106 /* Successfully aborted current command and stopped command ring */ 1107 #define COMP_CMD_ABORT 25 1108 /* Stopped - transfer was terminated by a stop endpoint command */ 1109 #define COMP_STOP 26 1110 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 1111 #define COMP_STOP_INVAL 27 1112 /* Same as COMP_EP_STOPPED, but a short packet detected */ 1113 #define COMP_STOP_SHORT 28 1114 /* Max Exit Latency Too Large Error */ 1115 #define COMP_MEL_ERR 29 1116 /* TRB type 30 reserved */ 1117 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 1118 #define COMP_BUFF_OVER 31 1119 /* Event Lost Error - xHC has an "internal event overrun condition" */ 1120 #define COMP_ISSUES 32 1121 /* Undefined Error - reported when other error codes don't apply */ 1122 #define COMP_UNKNOWN 33 1123 /* Invalid Stream ID Error */ 1124 #define COMP_STRID_ERR 34 1125 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 1126 #define COMP_2ND_BW_ERR 35 1127 /* Split Transaction Error */ 1128 #define COMP_SPLIT_ERR 36 1129 1130 struct xhci_link_trb { 1131 /* 64-bit segment pointer*/ 1132 __le64 segment_ptr; 1133 __le32 intr_target; 1134 __le32 control; 1135 }; 1136 1137 /* control bitfields */ 1138 #define LINK_TOGGLE (0x1<<1) 1139 1140 /* Command completion event TRB */ 1141 struct xhci_event_cmd { 1142 /* Pointer to command TRB, or the value passed by the event data trb */ 1143 __le64 cmd_trb; 1144 __le32 status; 1145 __le32 flags; 1146 }; 1147 1148 /* flags bitmasks */ 1149 1150 /* Address device - disable SetAddress */ 1151 #define TRB_BSR (1<<9) 1152 enum xhci_setup_dev { 1153 SETUP_CONTEXT_ONLY, 1154 SETUP_CONTEXT_ADDRESS, 1155 }; 1156 1157 /* bits 16:23 are the virtual function ID */ 1158 /* bits 24:31 are the slot ID */ 1159 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1160 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1161 1162 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1163 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1164 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1165 1166 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1167 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1168 #define LAST_EP_INDEX 30 1169 1170 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1171 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1172 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1173 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1174 1175 1176 /* Port Status Change Event TRB fields */ 1177 /* Port ID - bits 31:24 */ 1178 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1179 1180 /* Normal TRB fields */ 1181 /* transfer_len bitmasks - bits 0:16 */ 1182 #define TRB_LEN(p) ((p) & 0x1ffff) 1183 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1184 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1185 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1186 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1187 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1188 #define TRB_TBC(p) (((p) & 0x3) << 7) 1189 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1190 1191 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1192 #define TRB_CYCLE (1<<0) 1193 /* 1194 * Force next event data TRB to be evaluated before task switch. 1195 * Used to pass OS data back after a TD completes. 1196 */ 1197 #define TRB_ENT (1<<1) 1198 /* Interrupt on short packet */ 1199 #define TRB_ISP (1<<2) 1200 /* Set PCIe no snoop attribute */ 1201 #define TRB_NO_SNOOP (1<<3) 1202 /* Chain multiple TRBs into a TD */ 1203 #define TRB_CHAIN (1<<4) 1204 /* Interrupt on completion */ 1205 #define TRB_IOC (1<<5) 1206 /* The buffer pointer contains immediate data */ 1207 #define TRB_IDT (1<<6) 1208 1209 /* Block Event Interrupt */ 1210 #define TRB_BEI (1<<9) 1211 1212 /* Control transfer TRB specific fields */ 1213 #define TRB_DIR_IN (1<<16) 1214 #define TRB_TX_TYPE(p) ((p) << 16) 1215 #define TRB_DATA_OUT 2 1216 #define TRB_DATA_IN 3 1217 1218 /* Isochronous TRB specific fields */ 1219 #define TRB_SIA (1<<31) 1220 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1221 1222 struct xhci_generic_trb { 1223 __le32 field[4]; 1224 }; 1225 1226 union xhci_trb { 1227 struct xhci_link_trb link; 1228 struct xhci_transfer_event trans_event; 1229 struct xhci_event_cmd event_cmd; 1230 struct xhci_generic_trb generic; 1231 }; 1232 1233 /* TRB bit mask */ 1234 #define TRB_TYPE_BITMASK (0xfc00) 1235 #define TRB_TYPE(p) ((p) << 10) 1236 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1237 /* TRB type IDs */ 1238 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1239 #define TRB_NORMAL 1 1240 /* setup stage for control transfers */ 1241 #define TRB_SETUP 2 1242 /* data stage for control transfers */ 1243 #define TRB_DATA 3 1244 /* status stage for control transfers */ 1245 #define TRB_STATUS 4 1246 /* isoc transfers */ 1247 #define TRB_ISOC 5 1248 /* TRB for linking ring segments */ 1249 #define TRB_LINK 6 1250 #define TRB_EVENT_DATA 7 1251 /* Transfer Ring No-op (not for the command ring) */ 1252 #define TRB_TR_NOOP 8 1253 /* Command TRBs */ 1254 /* Enable Slot Command */ 1255 #define TRB_ENABLE_SLOT 9 1256 /* Disable Slot Command */ 1257 #define TRB_DISABLE_SLOT 10 1258 /* Address Device Command */ 1259 #define TRB_ADDR_DEV 11 1260 /* Configure Endpoint Command */ 1261 #define TRB_CONFIG_EP 12 1262 /* Evaluate Context Command */ 1263 #define TRB_EVAL_CONTEXT 13 1264 /* Reset Endpoint Command */ 1265 #define TRB_RESET_EP 14 1266 /* Stop Transfer Ring Command */ 1267 #define TRB_STOP_RING 15 1268 /* Set Transfer Ring Dequeue Pointer Command */ 1269 #define TRB_SET_DEQ 16 1270 /* Reset Device Command */ 1271 #define TRB_RESET_DEV 17 1272 /* Force Event Command (opt) */ 1273 #define TRB_FORCE_EVENT 18 1274 /* Negotiate Bandwidth Command (opt) */ 1275 #define TRB_NEG_BANDWIDTH 19 1276 /* Set Latency Tolerance Value Command (opt) */ 1277 #define TRB_SET_LT 20 1278 /* Get port bandwidth Command */ 1279 #define TRB_GET_BW 21 1280 /* Force Header Command - generate a transaction or link management packet */ 1281 #define TRB_FORCE_HEADER 22 1282 /* No-op Command - not for transfer rings */ 1283 #define TRB_CMD_NOOP 23 1284 /* TRB IDs 24-31 reserved */ 1285 /* Event TRBS */ 1286 /* Transfer Event */ 1287 #define TRB_TRANSFER 32 1288 /* Command Completion Event */ 1289 #define TRB_COMPLETION 33 1290 /* Port Status Change Event */ 1291 #define TRB_PORT_STATUS 34 1292 /* Bandwidth Request Event (opt) */ 1293 #define TRB_BANDWIDTH_EVENT 35 1294 /* Doorbell Event (opt) */ 1295 #define TRB_DOORBELL 36 1296 /* Host Controller Event */ 1297 #define TRB_HC_EVENT 37 1298 /* Device Notification Event - device sent function wake notification */ 1299 #define TRB_DEV_NOTE 38 1300 /* MFINDEX Wrap Event - microframe counter wrapped */ 1301 #define TRB_MFINDEX_WRAP 39 1302 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1303 1304 /* Nec vendor-specific command completion event. */ 1305 #define TRB_NEC_CMD_COMP 48 1306 /* Get NEC firmware revision. */ 1307 #define TRB_NEC_GET_FW 49 1308 1309 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1310 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1311 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1312 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1313 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1314 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1315 1316 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1317 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1318 1319 /* 1320 * TRBS_PER_SEGMENT must be a multiple of 4, 1321 * since the command ring is 64-byte aligned. 1322 * It must also be greater than 16. 1323 */ 1324 #define TRBS_PER_SEGMENT 256 1325 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1326 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1327 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1328 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1329 /* TRB buffer pointers can't cross 64KB boundaries */ 1330 #define TRB_MAX_BUFF_SHIFT 16 1331 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1332 1333 struct xhci_segment { 1334 union xhci_trb *trbs; 1335 /* private to HCD */ 1336 struct xhci_segment *next; 1337 dma_addr_t dma; 1338 }; 1339 1340 struct xhci_td { 1341 struct list_head td_list; 1342 struct list_head cancelled_td_list; 1343 struct urb *urb; 1344 struct xhci_segment *start_seg; 1345 union xhci_trb *first_trb; 1346 union xhci_trb *last_trb; 1347 /* actual_length of the URB has already been set */ 1348 bool urb_length_set; 1349 }; 1350 1351 /* xHCI command default timeout value */ 1352 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1353 1354 /* command descriptor */ 1355 struct xhci_cd { 1356 struct xhci_command *command; 1357 union xhci_trb *cmd_trb; 1358 }; 1359 1360 struct xhci_dequeue_state { 1361 struct xhci_segment *new_deq_seg; 1362 union xhci_trb *new_deq_ptr; 1363 int new_cycle_state; 1364 }; 1365 1366 enum xhci_ring_type { 1367 TYPE_CTRL = 0, 1368 TYPE_ISOC, 1369 TYPE_BULK, 1370 TYPE_INTR, 1371 TYPE_STREAM, 1372 TYPE_COMMAND, 1373 TYPE_EVENT, 1374 }; 1375 1376 struct xhci_ring { 1377 struct xhci_segment *first_seg; 1378 struct xhci_segment *last_seg; 1379 union xhci_trb *enqueue; 1380 struct xhci_segment *enq_seg; 1381 unsigned int enq_updates; 1382 union xhci_trb *dequeue; 1383 struct xhci_segment *deq_seg; 1384 unsigned int deq_updates; 1385 struct list_head td_list; 1386 /* 1387 * Write the cycle state into the TRB cycle field to give ownership of 1388 * the TRB to the host controller (if we are the producer), or to check 1389 * if we own the TRB (if we are the consumer). See section 4.9.1. 1390 */ 1391 u32 cycle_state; 1392 unsigned int stream_id; 1393 unsigned int num_segs; 1394 unsigned int num_trbs_free; 1395 unsigned int num_trbs_free_temp; 1396 enum xhci_ring_type type; 1397 bool last_td_was_short; 1398 struct radix_tree_root *trb_address_map; 1399 }; 1400 1401 struct xhci_erst_entry { 1402 /* 64-bit event ring segment address */ 1403 __le64 seg_addr; 1404 __le32 seg_size; 1405 /* Set to zero */ 1406 __le32 rsvd; 1407 }; 1408 1409 struct xhci_erst { 1410 struct xhci_erst_entry *entries; 1411 unsigned int num_entries; 1412 /* xhci->event_ring keeps track of segment dma addresses */ 1413 dma_addr_t erst_dma_addr; 1414 /* Num entries the ERST can contain */ 1415 unsigned int erst_size; 1416 }; 1417 1418 struct xhci_scratchpad { 1419 u64 *sp_array; 1420 dma_addr_t sp_dma; 1421 void **sp_buffers; 1422 dma_addr_t *sp_dma_buffers; 1423 }; 1424 1425 struct urb_priv { 1426 int length; 1427 int td_cnt; 1428 struct xhci_td *td[0]; 1429 }; 1430 1431 /* 1432 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1433 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1434 * meaning 64 ring segments. 1435 * Initial allocated size of the ERST, in number of entries */ 1436 #define ERST_NUM_SEGS 1 1437 /* Initial allocated size of the ERST, in number of entries */ 1438 #define ERST_SIZE 64 1439 /* Initial number of event segment rings allocated */ 1440 #define ERST_ENTRIES 1 1441 /* Poll every 60 seconds */ 1442 #define POLL_TIMEOUT 60 1443 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1444 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1445 /* XXX: Make these module parameters */ 1446 1447 struct s3_save { 1448 u32 command; 1449 u32 dev_nt; 1450 u64 dcbaa_ptr; 1451 u32 config_reg; 1452 u32 irq_pending; 1453 u32 irq_control; 1454 u32 erst_size; 1455 u64 erst_base; 1456 u64 erst_dequeue; 1457 }; 1458 1459 /* Use for lpm */ 1460 struct dev_info { 1461 u32 dev_id; 1462 struct list_head list; 1463 }; 1464 1465 struct xhci_bus_state { 1466 unsigned long bus_suspended; 1467 unsigned long next_statechange; 1468 1469 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1470 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1471 u32 port_c_suspend; 1472 u32 suspended_ports; 1473 u32 port_remote_wakeup; 1474 unsigned long resume_done[USB_MAXCHILDREN]; 1475 /* which ports have started to resume */ 1476 unsigned long resuming_ports; 1477 /* Which ports are waiting on RExit to U0 transition. */ 1478 unsigned long rexit_ports; 1479 struct completion rexit_done[USB_MAXCHILDREN]; 1480 }; 1481 1482 1483 /* 1484 * It can take up to 20 ms to transition from RExit to U0 on the 1485 * Intel Lynx Point LP xHCI host. 1486 */ 1487 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1488 1489 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1490 { 1491 if (hcd->speed == HCD_USB3) 1492 return 0; 1493 else 1494 return 1; 1495 } 1496 1497 struct xhci_hub { 1498 u8 maj_rev; 1499 u8 min_rev; 1500 u32 *psi; /* array of protocol speed ID entries */ 1501 u8 psi_count; 1502 u8 psi_uid_count; 1503 }; 1504 1505 /* There is one xhci_hcd structure per controller */ 1506 struct xhci_hcd { 1507 struct usb_hcd *main_hcd; 1508 struct usb_hcd *shared_hcd; 1509 /* glue to PCI and HCD framework */ 1510 struct xhci_cap_regs __iomem *cap_regs; 1511 struct xhci_op_regs __iomem *op_regs; 1512 struct xhci_run_regs __iomem *run_regs; 1513 struct xhci_doorbell_array __iomem *dba; 1514 /* Our HCD's current interrupter register set */ 1515 struct xhci_intr_reg __iomem *ir_set; 1516 1517 /* Cached register copies of read-only HC data */ 1518 __u32 hcs_params1; 1519 __u32 hcs_params2; 1520 __u32 hcs_params3; 1521 __u32 hcc_params; 1522 __u32 hcc_params2; 1523 1524 spinlock_t lock; 1525 1526 /* packed release number */ 1527 u8 sbrn; 1528 u16 hci_version; 1529 u8 max_slots; 1530 u8 max_interrupters; 1531 u8 max_ports; 1532 u8 isoc_threshold; 1533 int event_ring_max; 1534 int addr_64; 1535 /* 4KB min, 128MB max */ 1536 int page_size; 1537 /* Valid values are 12 to 20, inclusive */ 1538 int page_shift; 1539 /* msi-x vectors */ 1540 int msix_count; 1541 struct msix_entry *msix_entries; 1542 /* optional clock */ 1543 struct clk *clk; 1544 /* data structures */ 1545 struct xhci_device_context_array *dcbaa; 1546 struct xhci_ring *cmd_ring; 1547 unsigned int cmd_ring_state; 1548 #define CMD_RING_STATE_RUNNING (1 << 0) 1549 #define CMD_RING_STATE_ABORTED (1 << 1) 1550 #define CMD_RING_STATE_STOPPED (1 << 2) 1551 struct list_head cmd_list; 1552 unsigned int cmd_ring_reserved_trbs; 1553 struct timer_list cmd_timer; 1554 struct xhci_command *current_cmd; 1555 struct xhci_ring *event_ring; 1556 struct xhci_erst erst; 1557 /* Scratchpad */ 1558 struct xhci_scratchpad *scratchpad; 1559 /* Store LPM test failed devices' information */ 1560 struct list_head lpm_failed_devs; 1561 1562 /* slot enabling and address device helpers */ 1563 /* these are not thread safe so use mutex */ 1564 struct mutex mutex; 1565 struct completion addr_dev; 1566 int slot_id; 1567 /* For USB 3.0 LPM enable/disable. */ 1568 struct xhci_command *lpm_command; 1569 /* Internal mirror of the HW's dcbaa */ 1570 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1571 /* For keeping track of bandwidth domains per roothub. */ 1572 struct xhci_root_port_bw_info *rh_bw; 1573 1574 /* DMA pools */ 1575 struct dma_pool *device_pool; 1576 struct dma_pool *segment_pool; 1577 struct dma_pool *small_streams_pool; 1578 struct dma_pool *medium_streams_pool; 1579 1580 /* Host controller watchdog timer structures */ 1581 unsigned int xhc_state; 1582 1583 u32 command; 1584 struct s3_save s3; 1585 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1586 * 1587 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1588 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1589 * that sees this status (other than the timer that set it) should stop touching 1590 * hardware immediately. Interrupt handlers should return immediately when 1591 * they see this status (any time they drop and re-acquire xhci->lock). 1592 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1593 * putting the TD on the canceled list, etc. 1594 * 1595 * There are no reports of xHCI host controllers that display this issue. 1596 */ 1597 #define XHCI_STATE_DYING (1 << 0) 1598 #define XHCI_STATE_HALTED (1 << 1) 1599 /* Statistics */ 1600 int error_bitmask; 1601 unsigned int quirks; 1602 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1603 #define XHCI_RESET_EP_QUIRK (1 << 1) 1604 #define XHCI_NEC_HOST (1 << 2) 1605 #define XHCI_AMD_PLL_FIX (1 << 3) 1606 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1607 /* 1608 * Certain Intel host controllers have a limit to the number of endpoint 1609 * contexts they can handle. Ideally, they would signal that they can't handle 1610 * anymore endpoint contexts by returning a Resource Error for the Configure 1611 * Endpoint command, but they don't. Instead they expect software to keep track 1612 * of the number of active endpoints for them, across configure endpoint 1613 * commands, reset device commands, disable slot commands, and address device 1614 * commands. 1615 */ 1616 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1617 #define XHCI_BROKEN_MSI (1 << 6) 1618 #define XHCI_RESET_ON_RESUME (1 << 7) 1619 #define XHCI_SW_BW_CHECKING (1 << 8) 1620 #define XHCI_AMD_0x96_HOST (1 << 9) 1621 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1622 #define XHCI_LPM_SUPPORT (1 << 11) 1623 #define XHCI_INTEL_HOST (1 << 12) 1624 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1625 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1626 #define XHCI_AVOID_BEI (1 << 15) 1627 #define XHCI_PLAT (1 << 16) 1628 #define XHCI_SLOW_SUSPEND (1 << 17) 1629 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1630 /* For controllers with a broken beyond repair streams implementation */ 1631 #define XHCI_BROKEN_STREAMS (1 << 19) 1632 #define XHCI_PME_STUCK_QUIRK (1 << 20) 1633 unsigned int num_active_eps; 1634 unsigned int limit_active_eps; 1635 /* There are two roothubs to keep track of bus suspend info for */ 1636 struct xhci_bus_state bus_state[2]; 1637 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1638 u8 *port_array; 1639 /* Array of pointers to USB 3.0 PORTSC registers */ 1640 __le32 __iomem **usb3_ports; 1641 unsigned int num_usb3_ports; 1642 /* Array of pointers to USB 2.0 PORTSC registers */ 1643 __le32 __iomem **usb2_ports; 1644 struct xhci_hub usb2_rhub; 1645 struct xhci_hub usb3_rhub; 1646 unsigned int num_usb2_ports; 1647 /* support xHCI 0.96 spec USB2 software LPM */ 1648 unsigned sw_lpm_support:1; 1649 /* support xHCI 1.0 spec USB2 hardware LPM */ 1650 unsigned hw_lpm_support:1; 1651 /* cached usb2 extened protocol capabilites */ 1652 u32 *ext_caps; 1653 unsigned int num_ext_caps; 1654 /* Compliance Mode Recovery Data */ 1655 struct timer_list comp_mode_recovery_timer; 1656 u32 port_status_u0; 1657 /* Compliance Mode Timer Triggered every 2 seconds */ 1658 #define COMP_MODE_RCVRY_MSECS 2000 1659 }; 1660 1661 /* Platform specific overrides to generic XHCI hc_driver ops */ 1662 struct xhci_driver_overrides { 1663 size_t extra_priv_size; 1664 int (*reset)(struct usb_hcd *hcd); 1665 int (*start)(struct usb_hcd *hcd); 1666 }; 1667 1668 #define XHCI_CFC_DELAY 10 1669 1670 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1671 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1672 { 1673 struct usb_hcd *primary_hcd; 1674 1675 if (usb_hcd_is_primary_hcd(hcd)) 1676 primary_hcd = hcd; 1677 else 1678 primary_hcd = hcd->primary_hcd; 1679 1680 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1681 } 1682 1683 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1684 { 1685 return xhci->main_hcd; 1686 } 1687 1688 #define xhci_dbg(xhci, fmt, args...) \ 1689 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1690 #define xhci_err(xhci, fmt, args...) \ 1691 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1692 #define xhci_warn(xhci, fmt, args...) \ 1693 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1694 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1695 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1696 #define xhci_info(xhci, fmt, args...) \ 1697 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1698 1699 /* 1700 * Registers should always be accessed with double word or quad word accesses. 1701 * 1702 * Some xHCI implementations may support 64-bit address pointers. Registers 1703 * with 64-bit address pointers should be written to with dword accesses by 1704 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1705 * xHCI implementations that do not support 64-bit address pointers will ignore 1706 * the high dword, and write order is irrelevant. 1707 */ 1708 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1709 __le64 __iomem *regs) 1710 { 1711 return lo_hi_readq(regs); 1712 } 1713 static inline void xhci_write_64(struct xhci_hcd *xhci, 1714 const u64 val, __le64 __iomem *regs) 1715 { 1716 lo_hi_writeq(val, regs); 1717 } 1718 1719 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1720 { 1721 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1722 } 1723 1724 /* xHCI debugging */ 1725 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1726 void xhci_print_registers(struct xhci_hcd *xhci); 1727 void xhci_dbg_regs(struct xhci_hcd *xhci); 1728 void xhci_print_run_regs(struct xhci_hcd *xhci); 1729 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1730 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1731 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1732 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1733 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1734 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1735 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1736 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1737 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1738 struct xhci_container_ctx *ctx); 1739 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1740 unsigned int slot_id, unsigned int ep_index, 1741 struct xhci_virt_ep *ep); 1742 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1743 const char *fmt, ...); 1744 1745 /* xHCI memory management */ 1746 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1747 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1748 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1749 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1750 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1751 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1752 struct usb_device *udev); 1753 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1754 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1755 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1756 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1757 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1758 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1759 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1760 struct xhci_bw_info *ep_bw, 1761 struct xhci_interval_bw_table *bw_table, 1762 struct usb_device *udev, 1763 struct xhci_virt_ep *virt_ep, 1764 struct xhci_tt_bw_info *tt_info); 1765 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1766 struct xhci_virt_device *virt_dev, 1767 int old_active_eps); 1768 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1769 void xhci_update_bw_info(struct xhci_hcd *xhci, 1770 struct xhci_container_ctx *in_ctx, 1771 struct xhci_input_control_ctx *ctrl_ctx, 1772 struct xhci_virt_device *virt_dev); 1773 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1774 struct xhci_container_ctx *in_ctx, 1775 struct xhci_container_ctx *out_ctx, 1776 unsigned int ep_index); 1777 void xhci_slot_copy(struct xhci_hcd *xhci, 1778 struct xhci_container_ctx *in_ctx, 1779 struct xhci_container_ctx *out_ctx); 1780 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1781 struct usb_device *udev, struct usb_host_endpoint *ep, 1782 gfp_t mem_flags); 1783 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1784 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1785 unsigned int num_trbs, gfp_t flags); 1786 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1787 struct xhci_virt_device *virt_dev, 1788 unsigned int ep_index); 1789 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1790 unsigned int num_stream_ctxs, 1791 unsigned int num_streams, gfp_t flags); 1792 void xhci_free_stream_info(struct xhci_hcd *xhci, 1793 struct xhci_stream_info *stream_info); 1794 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1795 struct xhci_ep_ctx *ep_ctx, 1796 struct xhci_stream_info *stream_info); 1797 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1798 struct xhci_virt_ep *ep); 1799 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1800 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1801 struct xhci_ring *xhci_dma_to_transfer_ring( 1802 struct xhci_virt_ep *ep, 1803 u64 address); 1804 struct xhci_ring *xhci_stream_id_to_ring( 1805 struct xhci_virt_device *dev, 1806 unsigned int ep_index, 1807 unsigned int stream_id); 1808 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1809 bool allocate_in_ctx, bool allocate_completion, 1810 gfp_t mem_flags); 1811 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1812 void xhci_free_command(struct xhci_hcd *xhci, 1813 struct xhci_command *command); 1814 1815 /* xHCI host controller glue */ 1816 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1817 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 1818 void xhci_quiesce(struct xhci_hcd *xhci); 1819 int xhci_halt(struct xhci_hcd *xhci); 1820 int xhci_reset(struct xhci_hcd *xhci); 1821 int xhci_init(struct usb_hcd *hcd); 1822 int xhci_run(struct usb_hcd *hcd); 1823 void xhci_stop(struct usb_hcd *hcd); 1824 void xhci_shutdown(struct usb_hcd *hcd); 1825 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1826 void xhci_init_driver(struct hc_driver *drv, 1827 const struct xhci_driver_overrides *over); 1828 1829 #ifdef CONFIG_PM 1830 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1831 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1832 #else 1833 #define xhci_suspend NULL 1834 #define xhci_resume NULL 1835 #endif 1836 1837 int xhci_get_frame(struct usb_hcd *hcd); 1838 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1839 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1840 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1841 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1842 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1843 struct xhci_virt_device *virt_dev, 1844 struct usb_device *hdev, 1845 struct usb_tt *tt, gfp_t mem_flags); 1846 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1847 struct usb_host_endpoint **eps, unsigned int num_eps, 1848 unsigned int num_streams, gfp_t mem_flags); 1849 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1850 struct usb_host_endpoint **eps, unsigned int num_eps, 1851 gfp_t mem_flags); 1852 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1853 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); 1854 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 1855 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 1856 struct usb_device *udev, int enable); 1857 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1858 struct usb_tt *tt, gfp_t mem_flags); 1859 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1860 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1861 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1862 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1863 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1864 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1865 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1866 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1867 1868 /* xHCI ring, segment, TRB, and TD functions */ 1869 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1870 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 1871 struct xhci_segment *start_seg, union xhci_trb *start_trb, 1872 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 1873 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1874 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1875 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1876 u32 trb_type, u32 slot_id); 1877 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1878 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1879 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1880 u32 field1, u32 field2, u32 field3, u32 field4); 1881 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1882 int slot_id, unsigned int ep_index, int suspend); 1883 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1884 int slot_id, unsigned int ep_index); 1885 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1886 int slot_id, unsigned int ep_index); 1887 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1888 int slot_id, unsigned int ep_index); 1889 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1890 struct urb *urb, int slot_id, unsigned int ep_index); 1891 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1892 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1893 bool command_must_succeed); 1894 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1895 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1896 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1897 int slot_id, unsigned int ep_index); 1898 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1899 u32 slot_id); 1900 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1901 unsigned int slot_id, unsigned int ep_index, 1902 unsigned int stream_id, struct xhci_td *cur_td, 1903 struct xhci_dequeue_state *state); 1904 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1905 unsigned int slot_id, unsigned int ep_index, 1906 unsigned int stream_id, 1907 struct xhci_dequeue_state *deq_state); 1908 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1909 unsigned int ep_index, struct xhci_td *td); 1910 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1911 unsigned int slot_id, unsigned int ep_index, 1912 struct xhci_dequeue_state *deq_state); 1913 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1914 void xhci_handle_command_timeout(unsigned long data); 1915 1916 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1917 unsigned int ep_index, unsigned int stream_id); 1918 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1919 1920 /* xHCI roothub code */ 1921 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1922 int port_id, u32 link_state); 1923 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, 1924 struct usb_device *udev, enum usb3_link_state state); 1925 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, 1926 struct usb_device *udev, enum usb3_link_state state); 1927 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1928 int port_id, u32 port_bit); 1929 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1930 char *buf, u16 wLength); 1931 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1932 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1933 1934 #ifdef CONFIG_PM 1935 int xhci_bus_suspend(struct usb_hcd *hcd); 1936 int xhci_bus_resume(struct usb_hcd *hcd); 1937 #else 1938 #define xhci_bus_suspend NULL 1939 #define xhci_bus_resume NULL 1940 #endif /* CONFIG_PM */ 1941 1942 u32 xhci_port_state_to_neutral(u32 state); 1943 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1944 u16 port); 1945 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1946 1947 /* xHCI contexts */ 1948 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1949 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1950 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1951 1952 #endif /* __LINUX_XHCI_HCD_H */ 1953