1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 21 /* Code sharing between pci-quirks and xhci hcd */ 22 #include "xhci-ext-caps.h" 23 #include "pci-quirks.h" 24 25 /* max buffer size for trace and debug messages */ 26 #define XHCI_MSG_MAX 500 27 28 /* xHCI PCI Configuration Registers */ 29 #define XHCI_SBRN_OFFSET (0x60) 30 31 /* Max number of USB devices for any host controller - limit in section 6.1 */ 32 #define MAX_HC_SLOTS 256 33 /* Section 5.3.3 - MaxPorts */ 34 #define MAX_HC_PORTS 127 35 36 /* 37 * xHCI register interface. 38 * This corresponds to the eXtensible Host Controller Interface (xHCI) 39 * Revision 0.95 specification 40 */ 41 42 /** 43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 44 * @hc_capbase: length of the capabilities register and HC version number 45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 48 * @hcc_params: HCCPARAMS - Capability Parameters 49 * @db_off: DBOFF - Doorbell array offset 50 * @run_regs_off: RTSOFF - Runtime register space offset 51 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 52 */ 53 struct xhci_cap_regs { 54 __le32 hc_capbase; 55 __le32 hcs_params1; 56 __le32 hcs_params2; 57 __le32 hcs_params3; 58 __le32 hcc_params; 59 __le32 db_off; 60 __le32 run_regs_off; 61 __le32 hcc_params2; /* xhci 1.1 */ 62 /* Reserved up to (CAPLENGTH - 0x1C) */ 63 }; 64 65 /* hc_capbase bitmasks */ 66 /* bits 7:0 - how long is the Capabilities register */ 67 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 68 /* bits 31:16 */ 69 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 70 71 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 72 /* bits 0:7, Max Device Slots */ 73 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 74 #define HCS_SLOTS_MASK 0xff 75 /* bits 8:18, Max Interrupters */ 76 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 77 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 78 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 79 80 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 81 /* bits 0:3, frames or uframes that SW needs to queue transactions 82 * ahead of the HW to meet periodic deadlines */ 83 #define HCS_IST(p) (((p) >> 0) & 0xf) 84 /* bits 4:7, max number of Event Ring segments */ 85 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 86 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 87 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 88 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 89 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 90 91 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 92 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 93 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 94 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 95 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 96 97 /* HCCPARAMS - hcc_params - bitmasks */ 98 /* true: HC can use 64-bit address pointers */ 99 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 100 /* true: HC can do bandwidth negotiation */ 101 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 102 /* true: HC uses 64-byte Device Context structures 103 * FIXME 64-byte context structures aren't supported yet. 104 */ 105 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 106 /* true: HC has port power switches */ 107 #define HCC_PPC(p) ((p) & (1 << 3)) 108 /* true: HC has port indicators */ 109 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 110 /* true: HC has Light HC Reset Capability */ 111 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 112 /* true: HC supports latency tolerance messaging */ 113 #define HCC_LTC(p) ((p) & (1 << 6)) 114 /* true: no secondary Stream ID Support */ 115 #define HCC_NSS(p) ((p) & (1 << 7)) 116 /* true: HC supports Stopped - Short Packet */ 117 #define HCC_SPC(p) ((p) & (1 << 9)) 118 /* true: HC has Contiguous Frame ID Capability */ 119 #define HCC_CFC(p) ((p) & (1 << 11)) 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 124 125 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 126 127 /* db_off bitmask - bits 0:1 reserved */ 128 #define DBOFF_MASK (~0x3) 129 130 /* run_regs_off bitmask - bits 0:4 reserved */ 131 #define RTSOFF_MASK (~0x1f) 132 133 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 134 /* true: HC supports U3 entry Capability */ 135 #define HCC2_U3C(p) ((p) & (1 << 0)) 136 /* true: HC supports Configure endpoint command Max exit latency too large */ 137 #define HCC2_CMC(p) ((p) & (1 << 1)) 138 /* true: HC supports Force Save context Capability */ 139 #define HCC2_FSC(p) ((p) & (1 << 2)) 140 /* true: HC supports Compliance Transition Capability */ 141 #define HCC2_CTC(p) ((p) & (1 << 3)) 142 /* true: HC support Large ESIT payload Capability > 48k */ 143 #define HCC2_LEC(p) ((p) & (1 << 4)) 144 /* true: HC support Configuration Information Capability */ 145 #define HCC2_CIC(p) ((p) & (1 << 5)) 146 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 147 #define HCC2_ETC(p) ((p) & (1 << 6)) 148 149 /* Number of registers per port */ 150 #define NUM_PORT_REGS 4 151 152 #define PORTSC 0 153 #define PORTPMSC 1 154 #define PORTLI 2 155 #define PORTHLPMC 3 156 157 /** 158 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 159 * @command: USBCMD - xHC command register 160 * @status: USBSTS - xHC status register 161 * @page_size: This indicates the page size that the host controller 162 * supports. If bit n is set, the HC supports a page size 163 * of 2^(n+12), up to a 128MB page size. 164 * 4K is the minimum page size. 165 * @cmd_ring: CRP - 64-bit Command Ring Pointer 166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 167 * @config_reg: CONFIG - Configure Register 168 * @port_status_base: PORTSCn - base address for Port Status and Control 169 * Each port has a Port Status and Control register, 170 * followed by a Port Power Management Status and Control 171 * register, a Port Link Info register, and a reserved 172 * register. 173 * @port_power_base: PORTPMSCn - base address for 174 * Port Power Management Status and Control 175 * @port_link_base: PORTLIn - base address for Port Link Info (current 176 * Link PM state and control) for USB 2.1 and USB 3.0 177 * devices. 178 */ 179 struct xhci_op_regs { 180 __le32 command; 181 __le32 status; 182 __le32 page_size; 183 __le32 reserved1; 184 __le32 reserved2; 185 __le32 dev_notification; 186 __le64 cmd_ring; 187 /* rsvd: offset 0x20-2F */ 188 __le32 reserved3[4]; 189 __le64 dcbaa_ptr; 190 __le32 config_reg; 191 /* rsvd: offset 0x3C-3FF */ 192 __le32 reserved4[241]; 193 /* port 1 registers, which serve as a base address for other ports */ 194 __le32 port_status_base; 195 __le32 port_power_base; 196 __le32 port_link_base; 197 __le32 reserved5; 198 /* registers for ports 2-255 */ 199 __le32 reserved6[NUM_PORT_REGS*254]; 200 }; 201 202 /* USBCMD - USB command - command bitmasks */ 203 /* start/stop HC execution - do not write unless HC is halted*/ 204 #define CMD_RUN XHCI_CMD_RUN 205 /* Reset HC - resets internal HC state machine and all registers (except 206 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 207 * The xHCI driver must reinitialize the xHC after setting this bit. 208 */ 209 #define CMD_RESET (1 << 1) 210 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 211 #define CMD_EIE XHCI_CMD_EIE 212 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 213 #define CMD_HSEIE XHCI_CMD_HSEIE 214 /* bits 4:6 are reserved (and should be preserved on writes). */ 215 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 216 #define CMD_LRESET (1 << 7) 217 /* host controller save/restore state. */ 218 #define CMD_CSS (1 << 8) 219 #define CMD_CRS (1 << 9) 220 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 221 #define CMD_EWE XHCI_CMD_EWE 222 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 224 * '0' means the xHC can power it off if all ports are in the disconnect, 225 * disabled, or powered-off state. 226 */ 227 #define CMD_PM_INDEX (1 << 11) 228 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 229 #define CMD_ETE (1 << 14) 230 /* bits 15:31 are reserved (and should be preserved on writes). */ 231 232 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 233 #define XHCI_RESET_SHORT_USEC (250 * 1000) 234 235 /* IMAN - Interrupt Management Register */ 236 #define IMAN_IE (1 << 1) 237 #define IMAN_IP (1 << 0) 238 239 /* USBSTS - USB status - status bitmasks */ 240 /* HC not running - set to 1 when run/stop bit is cleared. */ 241 #define STS_HALT XHCI_STS_HALT 242 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 243 #define STS_FATAL (1 << 2) 244 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 245 #define STS_EINT (1 << 3) 246 /* port change detect */ 247 #define STS_PORT (1 << 4) 248 /* bits 5:7 reserved and zeroed */ 249 /* save state status - '1' means xHC is saving state */ 250 #define STS_SAVE (1 << 8) 251 /* restore state status - '1' means xHC is restoring state */ 252 #define STS_RESTORE (1 << 9) 253 /* true: save or restore error */ 254 #define STS_SRE (1 << 10) 255 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 256 #define STS_CNR XHCI_STS_CNR 257 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 258 #define STS_HCE (1 << 12) 259 /* bits 13:31 reserved and should be preserved */ 260 261 /* 262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 263 * Generate a device notification event when the HC sees a transaction with a 264 * notification type that matches a bit set in this bit field. 265 */ 266 #define DEV_NOTE_MASK (0xffff) 267 #define ENABLE_DEV_NOTE(x) (1 << (x)) 268 /* Most of the device notification types should only be used for debug. 269 * SW does need to pay attention to function wake notifications. 270 */ 271 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 272 273 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 274 /* bit 0 is the command ring cycle state */ 275 /* stop ring operation after completion of the currently executing command */ 276 #define CMD_RING_PAUSE (1 << 1) 277 /* stop ring immediately - abort the currently executing command */ 278 #define CMD_RING_ABORT (1 << 2) 279 /* true: command ring is running */ 280 #define CMD_RING_RUNNING (1 << 3) 281 /* bits 4:5 reserved and should be preserved */ 282 /* Command Ring pointer - bit mask for the lower 32 bits. */ 283 #define CMD_RING_RSVD_BITS (0x3f) 284 285 /* CONFIG - Configure Register - config_reg bitmasks */ 286 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 287 #define MAX_DEVS(p) ((p) & 0xff) 288 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 289 #define CONFIG_U3E (1 << 8) 290 /* bit 9: Configuration Information Enable, xhci 1.1 */ 291 #define CONFIG_CIE (1 << 9) 292 /* bits 10:31 - reserved and should be preserved */ 293 294 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 295 /* true: device connected */ 296 #define PORT_CONNECT (1 << 0) 297 /* true: port enabled */ 298 #define PORT_PE (1 << 1) 299 /* bit 2 reserved and zeroed */ 300 /* true: port has an over-current condition */ 301 #define PORT_OC (1 << 3) 302 /* true: port reset signaling asserted */ 303 #define PORT_RESET (1 << 4) 304 /* Port Link State - bits 5:8 305 * A read gives the current link PM state of the port, 306 * a write with Link State Write Strobe set sets the link state. 307 */ 308 #define PORT_PLS_MASK (0xf << 5) 309 #define XDEV_U0 (0x0 << 5) 310 #define XDEV_U1 (0x1 << 5) 311 #define XDEV_U2 (0x2 << 5) 312 #define XDEV_U3 (0x3 << 5) 313 #define XDEV_DISABLED (0x4 << 5) 314 #define XDEV_RXDETECT (0x5 << 5) 315 #define XDEV_INACTIVE (0x6 << 5) 316 #define XDEV_POLLING (0x7 << 5) 317 #define XDEV_RECOVERY (0x8 << 5) 318 #define XDEV_HOT_RESET (0x9 << 5) 319 #define XDEV_COMP_MODE (0xa << 5) 320 #define XDEV_TEST_MODE (0xb << 5) 321 #define XDEV_RESUME (0xf << 5) 322 323 /* true: port has power (see HCC_PPC) */ 324 #define PORT_POWER (1 << 9) 325 /* bits 10:13 indicate device speed: 326 * 0 - undefined speed - port hasn't be initialized by a reset yet 327 * 1 - full speed 328 * 2 - low speed 329 * 3 - high speed 330 * 4 - super speed 331 * 5-15 reserved 332 */ 333 #define DEV_SPEED_MASK (0xf << 10) 334 #define XDEV_FS (0x1 << 10) 335 #define XDEV_LS (0x2 << 10) 336 #define XDEV_HS (0x3 << 10) 337 #define XDEV_SS (0x4 << 10) 338 #define XDEV_SSP (0x5 << 10) 339 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 340 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 341 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 342 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 343 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 344 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 345 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 346 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 347 348 /* Bits 20:23 in the Slot Context are the speed for the device */ 349 #define SLOT_SPEED_FS (XDEV_FS << 10) 350 #define SLOT_SPEED_LS (XDEV_LS << 10) 351 #define SLOT_SPEED_HS (XDEV_HS << 10) 352 #define SLOT_SPEED_SS (XDEV_SS << 10) 353 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 354 /* Port Indicator Control */ 355 #define PORT_LED_OFF (0 << 14) 356 #define PORT_LED_AMBER (1 << 14) 357 #define PORT_LED_GREEN (2 << 14) 358 #define PORT_LED_MASK (3 << 14) 359 /* Port Link State Write Strobe - set this when changing link state */ 360 #define PORT_LINK_STROBE (1 << 16) 361 /* true: connect status change */ 362 #define PORT_CSC (1 << 17) 363 /* true: port enable change */ 364 #define PORT_PEC (1 << 18) 365 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 366 * into an enabled state, and the device into the default state. A "warm" reset 367 * also resets the link, forcing the device through the link training sequence. 368 * SW can also look at the Port Reset register to see when warm reset is done. 369 */ 370 #define PORT_WRC (1 << 19) 371 /* true: over-current change */ 372 #define PORT_OCC (1 << 20) 373 /* true: reset change - 1 to 0 transition of PORT_RESET */ 374 #define PORT_RC (1 << 21) 375 /* port link status change - set on some port link state transitions: 376 * Transition Reason 377 * ------------------------------------------------------------------------------ 378 * - U3 to Resume Wakeup signaling from a device 379 * - Resume to Recovery to U0 USB 3.0 device resume 380 * - Resume to U0 USB 2.0 device resume 381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 382 * - U3 to U0 Software resume of USB 2.0 device complete 383 * - U2 to U0 L1 resume of USB 2.1 device complete 384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 385 * - U0 to disabled L1 entry error with USB 2.1 device 386 * - Any state to inactive Error on USB 3.0 port 387 */ 388 #define PORT_PLC (1 << 22) 389 /* port configure error change - port failed to configure its link partner */ 390 #define PORT_CEC (1 << 23) 391 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 392 PORT_RC | PORT_PLC | PORT_CEC) 393 394 395 /* Cold Attach Status - xHC can set this bit to report device attached during 396 * Sx state. Warm port reset should be perfomed to clear this bit and move port 397 * to connected state. 398 */ 399 #define PORT_CAS (1 << 24) 400 /* wake on connect (enable) */ 401 #define PORT_WKCONN_E (1 << 25) 402 /* wake on disconnect (enable) */ 403 #define PORT_WKDISC_E (1 << 26) 404 /* wake on over-current (enable) */ 405 #define PORT_WKOC_E (1 << 27) 406 /* bits 28:29 reserved */ 407 /* true: device is non-removable - for USB 3.0 roothub emulation */ 408 #define PORT_DEV_REMOVE (1 << 30) 409 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 410 #define PORT_WR (1 << 31) 411 412 /* We mark duplicate entries with -1 */ 413 #define DUPLICATE_ENTRY ((u8)(-1)) 414 415 /* Port Power Management Status and Control - port_power_base bitmasks */ 416 /* Inactivity timer value for transitions into U1, in microseconds. 417 * Timeout can be up to 127us. 0xFF means an infinite timeout. 418 */ 419 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 420 #define PORT_U1_TIMEOUT_MASK 0xff 421 /* Inactivity timer value for transitions into U2 */ 422 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 423 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 424 /* Bits 24:31 for port testing */ 425 426 /* USB2 Protocol PORTSPMSC */ 427 #define PORT_L1S_MASK 7 428 #define PORT_L1S_SUCCESS 1 429 #define PORT_RWE (1 << 3) 430 #define PORT_HIRD(p) (((p) & 0xf) << 4) 431 #define PORT_HIRD_MASK (0xf << 4) 432 #define PORT_L1DS_MASK (0xff << 8) 433 #define PORT_L1DS(p) (((p) & 0xff) << 8) 434 #define PORT_HLE (1 << 16) 435 #define PORT_TEST_MODE_SHIFT 28 436 437 /* USB3 Protocol PORTLI Port Link Information */ 438 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 439 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 440 441 /* USB2 Protocol PORTHLPMC */ 442 #define PORT_HIRDM(p)((p) & 3) 443 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 444 #define PORT_BESLD(p)(((p) & 0xf) << 10) 445 446 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 447 #define XHCI_L1_TIMEOUT 512 448 449 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 451 * by other operating systems. 452 * 453 * XHCI 1.0 errata 8/14/12 Table 13 notes: 454 * "Software should choose xHC BESL/BESLD field values that do not violate a 455 * device's resume latency requirements, 456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 457 * or not program values < '4' if BLC = '0' and a BESL device is attached. 458 */ 459 #define XHCI_DEFAULT_BESL 4 460 461 /* 462 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports 463 * to complete link training. usually link trainig completes much faster 464 * so check status 10 times with 36ms sleep in places we need to wait for 465 * polling to complete. 466 */ 467 #define XHCI_PORT_POLLING_LFPS_TIME 36 468 469 /** 470 * struct xhci_intr_reg - Interrupt Register Set 471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 472 * interrupts and check for pending interrupts. 473 * @irq_control: IMOD - Interrupt Moderation Register. 474 * Used to throttle interrupts. 475 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 476 * @erst_base: ERST base address. 477 * @erst_dequeue: Event ring dequeue pointer. 478 * 479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 480 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 481 * multiple segments of the same size. The HC places events on the ring and 482 * "updates the Cycle bit in the TRBs to indicate to software the current 483 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 484 * updates the dequeue pointer. 485 */ 486 struct xhci_intr_reg { 487 __le32 irq_pending; 488 __le32 irq_control; 489 __le32 erst_size; 490 __le32 rsvd; 491 __le64 erst_base; 492 __le64 erst_dequeue; 493 }; 494 495 /* irq_pending bitmasks */ 496 #define ER_IRQ_PENDING(p) ((p) & 0x1) 497 /* bits 2:31 need to be preserved */ 498 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 499 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 500 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 501 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 502 503 /* irq_control bitmasks */ 504 /* Minimum interval between interrupts (in 250ns intervals). The interval 505 * between interrupts will be longer if there are no events on the event ring. 506 * Default is 4000 (1 ms). 507 */ 508 #define ER_IRQ_INTERVAL_MASK (0xffff) 509 /* Counter used to count down the time to the next interrupt - HW use only */ 510 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 511 512 /* erst_size bitmasks */ 513 /* Preserve bits 16:31 of erst_size */ 514 #define ERST_SIZE_MASK (0xffff << 16) 515 516 /* erst_dequeue bitmasks */ 517 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 518 * where the current dequeue pointer lies. This is an optional HW hint. 519 */ 520 #define ERST_DESI_MASK (0x7) 521 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 522 * a work queue (or delayed service routine)? 523 */ 524 #define ERST_EHB (1 << 3) 525 #define ERST_PTR_MASK (0xf) 526 527 /** 528 * struct xhci_run_regs 529 * @microframe_index: 530 * MFINDEX - current microframe number 531 * 532 * Section 5.5 Host Controller Runtime Registers: 533 * "Software should read and write these registers using only Dword (32 bit) 534 * or larger accesses" 535 */ 536 struct xhci_run_regs { 537 __le32 microframe_index; 538 __le32 rsvd[7]; 539 struct xhci_intr_reg ir_set[128]; 540 }; 541 542 /** 543 * struct doorbell_array 544 * 545 * Bits 0 - 7: Endpoint target 546 * Bits 8 - 15: RsvdZ 547 * Bits 16 - 31: Stream ID 548 * 549 * Section 5.6 550 */ 551 struct xhci_doorbell_array { 552 __le32 doorbell[256]; 553 }; 554 555 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 556 #define DB_VALUE_HOST 0x00000000 557 558 /** 559 * struct xhci_protocol_caps 560 * @revision: major revision, minor revision, capability ID, 561 * and next capability pointer. 562 * @name_string: Four ASCII characters to say which spec this xHC 563 * follows, typically "USB ". 564 * @port_info: Port offset, count, and protocol-defined information. 565 */ 566 struct xhci_protocol_caps { 567 u32 revision; 568 u32 name_string; 569 u32 port_info; 570 }; 571 572 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 573 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 574 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 575 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 576 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 577 578 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 579 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 580 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 581 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 582 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 583 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 584 585 #define PLT_MASK (0x03 << 6) 586 #define PLT_SYM (0x00 << 6) 587 #define PLT_ASYM_RX (0x02 << 6) 588 #define PLT_ASYM_TX (0x03 << 6) 589 590 /** 591 * struct xhci_container_ctx 592 * @type: Type of context. Used to calculated offsets to contained contexts. 593 * @size: Size of the context data 594 * @bytes: The raw context data given to HW 595 * @dma: dma address of the bytes 596 * 597 * Represents either a Device or Input context. Holds a pointer to the raw 598 * memory used for the context (bytes) and dma address of it (dma). 599 */ 600 struct xhci_container_ctx { 601 unsigned type; 602 #define XHCI_CTX_TYPE_DEVICE 0x1 603 #define XHCI_CTX_TYPE_INPUT 0x2 604 605 int size; 606 607 u8 *bytes; 608 dma_addr_t dma; 609 }; 610 611 /** 612 * struct xhci_slot_ctx 613 * @dev_info: Route string, device speed, hub info, and last valid endpoint 614 * @dev_info2: Max exit latency for device number, root hub port number 615 * @tt_info: tt_info is used to construct split transaction tokens 616 * @dev_state: slot state and device address 617 * 618 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 619 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 620 * reserved at the end of the slot context for HC internal use. 621 */ 622 struct xhci_slot_ctx { 623 __le32 dev_info; 624 __le32 dev_info2; 625 __le32 tt_info; 626 __le32 dev_state; 627 /* offset 0x10 to 0x1f reserved for HC internal use */ 628 __le32 reserved[4]; 629 }; 630 631 /* dev_info bitmasks */ 632 /* Route String - 0:19 */ 633 #define ROUTE_STRING_MASK (0xfffff) 634 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 635 #define DEV_SPEED (0xf << 20) 636 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 637 /* bit 24 reserved */ 638 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 639 #define DEV_MTT (0x1 << 25) 640 /* Set if the device is a hub - bit 26 */ 641 #define DEV_HUB (0x1 << 26) 642 /* Index of the last valid endpoint context in this device context - 27:31 */ 643 #define LAST_CTX_MASK (0x1f << 27) 644 #define LAST_CTX(p) ((p) << 27) 645 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 646 #define SLOT_FLAG (1 << 0) 647 #define EP0_FLAG (1 << 1) 648 649 /* dev_info2 bitmasks */ 650 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 651 #define MAX_EXIT (0xffff) 652 /* Root hub port number that is needed to access the USB device */ 653 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 654 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 655 /* Maximum number of ports under a hub device */ 656 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 657 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 658 659 /* tt_info bitmasks */ 660 /* 661 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 662 * The Slot ID of the hub that isolates the high speed signaling from 663 * this low or full-speed device. '0' if attached to root hub port. 664 */ 665 #define TT_SLOT (0xff) 666 /* 667 * The number of the downstream facing port of the high-speed hub 668 * '0' if the device is not low or full speed. 669 */ 670 #define TT_PORT (0xff << 8) 671 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 672 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 673 674 /* dev_state bitmasks */ 675 /* USB device address - assigned by the HC */ 676 #define DEV_ADDR_MASK (0xff) 677 /* bits 8:26 reserved */ 678 /* Slot state */ 679 #define SLOT_STATE (0x1f << 27) 680 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 681 682 #define SLOT_STATE_DISABLED 0 683 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 684 #define SLOT_STATE_DEFAULT 1 685 #define SLOT_STATE_ADDRESSED 2 686 #define SLOT_STATE_CONFIGURED 3 687 688 /** 689 * struct xhci_ep_ctx 690 * @ep_info: endpoint state, streams, mult, and interval information. 691 * @ep_info2: information on endpoint type, max packet size, max burst size, 692 * error count, and whether the HC will force an event for all 693 * transactions. 694 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 695 * defines one stream, this points to the endpoint transfer ring. 696 * Otherwise, it points to a stream context array, which has a 697 * ring pointer for each flow. 698 * @tx_info: 699 * Average TRB lengths for the endpoint ring and 700 * max payload within an Endpoint Service Interval Time (ESIT). 701 * 702 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 703 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 704 * reserved at the end of the endpoint context for HC internal use. 705 */ 706 struct xhci_ep_ctx { 707 __le32 ep_info; 708 __le32 ep_info2; 709 __le64 deq; 710 __le32 tx_info; 711 /* offset 0x14 - 0x1f reserved for HC internal use */ 712 __le32 reserved[3]; 713 }; 714 715 /* ep_info bitmasks */ 716 /* 717 * Endpoint State - bits 0:2 718 * 0 - disabled 719 * 1 - running 720 * 2 - halted due to halt condition - ok to manipulate endpoint ring 721 * 3 - stopped 722 * 4 - TRB error 723 * 5-7 - reserved 724 */ 725 #define EP_STATE_MASK (0x7) 726 #define EP_STATE_DISABLED 0 727 #define EP_STATE_RUNNING 1 728 #define EP_STATE_HALTED 2 729 #define EP_STATE_STOPPED 3 730 #define EP_STATE_ERROR 4 731 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 732 733 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 734 #define EP_MULT(p) (((p) & 0x3) << 8) 735 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 736 /* bits 10:14 are Max Primary Streams */ 737 /* bit 15 is Linear Stream Array */ 738 /* Interval - period between requests to an endpoint - 125u increments. */ 739 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 740 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 741 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 742 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 743 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 744 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 745 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 746 #define EP_HAS_LSA (1 << 15) 747 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 748 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 749 750 /* ep_info2 bitmasks */ 751 /* 752 * Force Event - generate transfer events for all TRBs for this endpoint 753 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 754 */ 755 #define FORCE_EVENT (0x1) 756 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 757 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 758 #define EP_TYPE(p) ((p) << 3) 759 #define ISOC_OUT_EP 1 760 #define BULK_OUT_EP 2 761 #define INT_OUT_EP 3 762 #define CTRL_EP 4 763 #define ISOC_IN_EP 5 764 #define BULK_IN_EP 6 765 #define INT_IN_EP 7 766 /* bit 6 reserved */ 767 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 768 #define MAX_BURST(p) (((p)&0xff) << 8) 769 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 770 #define MAX_PACKET(p) (((p)&0xffff) << 16) 771 #define MAX_PACKET_MASK (0xffff << 16) 772 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 773 774 /* tx_info bitmasks */ 775 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 776 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 777 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 778 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 779 780 /* deq bitmasks */ 781 #define EP_CTX_CYCLE_MASK (1 << 0) 782 #define SCTX_DEQ_MASK (~0xfL) 783 784 785 /** 786 * struct xhci_input_control_context 787 * Input control context; see section 6.2.5. 788 * 789 * @drop_context: set the bit of the endpoint context you want to disable 790 * @add_context: set the bit of the endpoint context you want to enable 791 */ 792 struct xhci_input_control_ctx { 793 __le32 drop_flags; 794 __le32 add_flags; 795 __le32 rsvd2[6]; 796 }; 797 798 #define EP_IS_ADDED(ctrl_ctx, i) \ 799 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 800 #define EP_IS_DROPPED(ctrl_ctx, i) \ 801 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 802 803 /* Represents everything that is needed to issue a command on the command ring. 804 * It's useful to pre-allocate these for commands that cannot fail due to 805 * out-of-memory errors, like freeing streams. 806 */ 807 struct xhci_command { 808 /* Input context for changing device state */ 809 struct xhci_container_ctx *in_ctx; 810 u32 status; 811 int slot_id; 812 /* If completion is null, no one is waiting on this command 813 * and the structure can be freed after the command completes. 814 */ 815 struct completion *completion; 816 union xhci_trb *command_trb; 817 struct list_head cmd_list; 818 }; 819 820 /* drop context bitmasks */ 821 #define DROP_EP(x) (0x1 << x) 822 /* add context bitmasks */ 823 #define ADD_EP(x) (0x1 << x) 824 825 struct xhci_stream_ctx { 826 /* 64-bit stream ring address, cycle state, and stream type */ 827 __le64 stream_ring; 828 /* offset 0x14 - 0x1f reserved for HC internal use */ 829 __le32 reserved[2]; 830 }; 831 832 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 833 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 834 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 835 #define SCT_SEC_TR 0 836 /* Primary stream array type, dequeue pointer is to a transfer ring */ 837 #define SCT_PRI_TR 1 838 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 839 #define SCT_SSA_8 2 840 #define SCT_SSA_16 3 841 #define SCT_SSA_32 4 842 #define SCT_SSA_64 5 843 #define SCT_SSA_128 6 844 #define SCT_SSA_256 7 845 846 /* Assume no secondary streams for now */ 847 struct xhci_stream_info { 848 struct xhci_ring **stream_rings; 849 /* Number of streams, including stream 0 (which drivers can't use) */ 850 unsigned int num_streams; 851 /* The stream context array may be bigger than 852 * the number of streams the driver asked for 853 */ 854 struct xhci_stream_ctx *stream_ctx_array; 855 unsigned int num_stream_ctxs; 856 dma_addr_t ctx_array_dma; 857 /* For mapping physical TRB addresses to segments in stream rings */ 858 struct radix_tree_root trb_address_map; 859 struct xhci_command *free_streams_command; 860 }; 861 862 #define SMALL_STREAM_ARRAY_SIZE 256 863 #define MEDIUM_STREAM_ARRAY_SIZE 1024 864 865 /* Some Intel xHCI host controllers need software to keep track of the bus 866 * bandwidth. Keep track of endpoint info here. Each root port is allocated 867 * the full bus bandwidth. We must also treat TTs (including each port under a 868 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 869 * (DMI) also limits the total bandwidth (across all domains) that can be used. 870 */ 871 struct xhci_bw_info { 872 /* ep_interval is zero-based */ 873 unsigned int ep_interval; 874 /* mult and num_packets are one-based */ 875 unsigned int mult; 876 unsigned int num_packets; 877 unsigned int max_packet_size; 878 unsigned int max_esit_payload; 879 unsigned int type; 880 }; 881 882 /* "Block" sizes in bytes the hardware uses for different device speeds. 883 * The logic in this part of the hardware limits the number of bits the hardware 884 * can use, so must represent bandwidth in a less precise manner to mimic what 885 * the scheduler hardware computes. 886 */ 887 #define FS_BLOCK 1 888 #define HS_BLOCK 4 889 #define SS_BLOCK 16 890 #define DMI_BLOCK 32 891 892 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 893 * with each byte transferred. SuperSpeed devices have an initial overhead to 894 * set up bursts. These are in blocks, see above. LS overhead has already been 895 * translated into FS blocks. 896 */ 897 #define DMI_OVERHEAD 8 898 #define DMI_OVERHEAD_BURST 4 899 #define SS_OVERHEAD 8 900 #define SS_OVERHEAD_BURST 32 901 #define HS_OVERHEAD 26 902 #define FS_OVERHEAD 20 903 #define LS_OVERHEAD 128 904 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 905 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 906 * of overhead associated with split transfers crossing microframe boundaries. 907 * 31 blocks is pure protocol overhead. 908 */ 909 #define TT_HS_OVERHEAD (31 + 94) 910 #define TT_DMI_OVERHEAD (25 + 12) 911 912 /* Bandwidth limits in blocks */ 913 #define FS_BW_LIMIT 1285 914 #define TT_BW_LIMIT 1320 915 #define HS_BW_LIMIT 1607 916 #define SS_BW_LIMIT_IN 3906 917 #define DMI_BW_LIMIT_IN 3906 918 #define SS_BW_LIMIT_OUT 3906 919 #define DMI_BW_LIMIT_OUT 3906 920 921 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 922 #define FS_BW_RESERVED 10 923 #define HS_BW_RESERVED 20 924 #define SS_BW_RESERVED 10 925 926 struct xhci_virt_ep { 927 struct xhci_virt_device *vdev; /* parent */ 928 unsigned int ep_index; 929 struct xhci_ring *ring; 930 /* Related to endpoints that are configured to use stream IDs only */ 931 struct xhci_stream_info *stream_info; 932 /* Temporary storage in case the configure endpoint command fails and we 933 * have to restore the device state to the previous state 934 */ 935 struct xhci_ring *new_ring; 936 unsigned int ep_state; 937 #define SET_DEQ_PENDING (1 << 0) 938 #define EP_HALTED (1 << 1) /* For stall handling */ 939 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 940 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 941 #define EP_GETTING_STREAMS (1 << 3) 942 #define EP_HAS_STREAMS (1 << 4) 943 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 944 #define EP_GETTING_NO_STREAMS (1 << 5) 945 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 946 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 947 /* usb_hub_clear_tt_buffer is in progress */ 948 #define EP_CLEARING_TT (1 << 8) 949 /* ---- Related to URB cancellation ---- */ 950 struct list_head cancelled_td_list; 951 /* Watchdog timer for stop endpoint command to cancel URBs */ 952 struct timer_list stop_cmd_timer; 953 struct xhci_hcd *xhci; 954 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 955 * command. We'll need to update the ring's dequeue segment and dequeue 956 * pointer after the command completes. 957 */ 958 struct xhci_segment *queued_deq_seg; 959 union xhci_trb *queued_deq_ptr; 960 /* 961 * Sometimes the xHC can not process isochronous endpoint ring quickly 962 * enough, and it will miss some isoc tds on the ring and generate 963 * a Missed Service Error Event. 964 * Set skip flag when receive a Missed Service Error Event and 965 * process the missed tds on the endpoint ring. 966 */ 967 bool skip; 968 /* Bandwidth checking storage */ 969 struct xhci_bw_info bw_info; 970 struct list_head bw_endpoint_list; 971 /* Isoch Frame ID checking storage */ 972 int next_frame_id; 973 /* Use new Isoch TRB layout needed for extended TBC support */ 974 bool use_extended_tbc; 975 }; 976 977 enum xhci_overhead_type { 978 LS_OVERHEAD_TYPE = 0, 979 FS_OVERHEAD_TYPE, 980 HS_OVERHEAD_TYPE, 981 }; 982 983 struct xhci_interval_bw { 984 unsigned int num_packets; 985 /* Sorted by max packet size. 986 * Head of the list is the greatest max packet size. 987 */ 988 struct list_head endpoints; 989 /* How many endpoints of each speed are present. */ 990 unsigned int overhead[3]; 991 }; 992 993 #define XHCI_MAX_INTERVAL 16 994 995 struct xhci_interval_bw_table { 996 unsigned int interval0_esit_payload; 997 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 998 /* Includes reserved bandwidth for async endpoints */ 999 unsigned int bw_used; 1000 unsigned int ss_bw_in; 1001 unsigned int ss_bw_out; 1002 }; 1003 1004 #define EP_CTX_PER_DEV 31 1005 1006 struct xhci_virt_device { 1007 int slot_id; 1008 struct usb_device *udev; 1009 /* 1010 * Commands to the hardware are passed an "input context" that 1011 * tells the hardware what to change in its data structures. 1012 * The hardware will return changes in an "output context" that 1013 * software must allocate for the hardware. We need to keep 1014 * track of input and output contexts separately because 1015 * these commands might fail and we don't trust the hardware. 1016 */ 1017 struct xhci_container_ctx *out_ctx; 1018 /* Used for addressing devices and configuration changes */ 1019 struct xhci_container_ctx *in_ctx; 1020 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 1021 u8 fake_port; 1022 u8 real_port; 1023 struct xhci_interval_bw_table *bw_table; 1024 struct xhci_tt_bw_info *tt_info; 1025 /* 1026 * flags for state tracking based on events and issued commands. 1027 * Software can not rely on states from output contexts because of 1028 * latency between events and xHC updating output context values. 1029 * See xhci 1.1 section 4.8.3 for more details 1030 */ 1031 unsigned long flags; 1032 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 1033 1034 /* The current max exit latency for the enabled USB3 link states. */ 1035 u16 current_mel; 1036 /* Used for the debugfs interfaces. */ 1037 void *debugfs_private; 1038 }; 1039 1040 /* 1041 * For each roothub, keep track of the bandwidth information for each periodic 1042 * interval. 1043 * 1044 * If a high speed hub is attached to the roothub, each TT associated with that 1045 * hub is a separate bandwidth domain. The interval information for the 1046 * endpoints on the devices under that TT will appear in the TT structure. 1047 */ 1048 struct xhci_root_port_bw_info { 1049 struct list_head tts; 1050 unsigned int num_active_tts; 1051 struct xhci_interval_bw_table bw_table; 1052 }; 1053 1054 struct xhci_tt_bw_info { 1055 struct list_head tt_list; 1056 int slot_id; 1057 int ttport; 1058 struct xhci_interval_bw_table bw_table; 1059 int active_eps; 1060 }; 1061 1062 1063 /** 1064 * struct xhci_device_context_array 1065 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1066 */ 1067 struct xhci_device_context_array { 1068 /* 64-bit device addresses; we only write 32-bit addresses */ 1069 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1070 /* private xHCD pointers */ 1071 dma_addr_t dma; 1072 }; 1073 /* TODO: write function to set the 64-bit device DMA address */ 1074 /* 1075 * TODO: change this to be dynamically sized at HC mem init time since the HC 1076 * might not be able to handle the maximum number of devices possible. 1077 */ 1078 1079 1080 struct xhci_transfer_event { 1081 /* 64-bit buffer address, or immediate data */ 1082 __le64 buffer; 1083 __le32 transfer_len; 1084 /* This field is interpreted differently based on the type of TRB */ 1085 __le32 flags; 1086 }; 1087 1088 /* Transfer event TRB length bit mask */ 1089 /* bits 0:23 */ 1090 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1091 1092 /** Transfer Event bit fields **/ 1093 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1094 1095 /* Completion Code - only applicable for some types of TRBs */ 1096 #define COMP_CODE_MASK (0xff << 24) 1097 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1098 #define COMP_INVALID 0 1099 #define COMP_SUCCESS 1 1100 #define COMP_DATA_BUFFER_ERROR 2 1101 #define COMP_BABBLE_DETECTED_ERROR 3 1102 #define COMP_USB_TRANSACTION_ERROR 4 1103 #define COMP_TRB_ERROR 5 1104 #define COMP_STALL_ERROR 6 1105 #define COMP_RESOURCE_ERROR 7 1106 #define COMP_BANDWIDTH_ERROR 8 1107 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1108 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1109 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1110 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1111 #define COMP_SHORT_PACKET 13 1112 #define COMP_RING_UNDERRUN 14 1113 #define COMP_RING_OVERRUN 15 1114 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1115 #define COMP_PARAMETER_ERROR 17 1116 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1117 #define COMP_CONTEXT_STATE_ERROR 19 1118 #define COMP_NO_PING_RESPONSE_ERROR 20 1119 #define COMP_EVENT_RING_FULL_ERROR 21 1120 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1121 #define COMP_MISSED_SERVICE_ERROR 23 1122 #define COMP_COMMAND_RING_STOPPED 24 1123 #define COMP_COMMAND_ABORTED 25 1124 #define COMP_STOPPED 26 1125 #define COMP_STOPPED_LENGTH_INVALID 27 1126 #define COMP_STOPPED_SHORT_PACKET 28 1127 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1128 #define COMP_ISOCH_BUFFER_OVERRUN 31 1129 #define COMP_EVENT_LOST_ERROR 32 1130 #define COMP_UNDEFINED_ERROR 33 1131 #define COMP_INVALID_STREAM_ID_ERROR 34 1132 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1133 #define COMP_SPLIT_TRANSACTION_ERROR 36 1134 1135 static inline const char *xhci_trb_comp_code_string(u8 status) 1136 { 1137 switch (status) { 1138 case COMP_INVALID: 1139 return "Invalid"; 1140 case COMP_SUCCESS: 1141 return "Success"; 1142 case COMP_DATA_BUFFER_ERROR: 1143 return "Data Buffer Error"; 1144 case COMP_BABBLE_DETECTED_ERROR: 1145 return "Babble Detected"; 1146 case COMP_USB_TRANSACTION_ERROR: 1147 return "USB Transaction Error"; 1148 case COMP_TRB_ERROR: 1149 return "TRB Error"; 1150 case COMP_STALL_ERROR: 1151 return "Stall Error"; 1152 case COMP_RESOURCE_ERROR: 1153 return "Resource Error"; 1154 case COMP_BANDWIDTH_ERROR: 1155 return "Bandwidth Error"; 1156 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1157 return "No Slots Available Error"; 1158 case COMP_INVALID_STREAM_TYPE_ERROR: 1159 return "Invalid Stream Type Error"; 1160 case COMP_SLOT_NOT_ENABLED_ERROR: 1161 return "Slot Not Enabled Error"; 1162 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1163 return "Endpoint Not Enabled Error"; 1164 case COMP_SHORT_PACKET: 1165 return "Short Packet"; 1166 case COMP_RING_UNDERRUN: 1167 return "Ring Underrun"; 1168 case COMP_RING_OVERRUN: 1169 return "Ring Overrun"; 1170 case COMP_VF_EVENT_RING_FULL_ERROR: 1171 return "VF Event Ring Full Error"; 1172 case COMP_PARAMETER_ERROR: 1173 return "Parameter Error"; 1174 case COMP_BANDWIDTH_OVERRUN_ERROR: 1175 return "Bandwidth Overrun Error"; 1176 case COMP_CONTEXT_STATE_ERROR: 1177 return "Context State Error"; 1178 case COMP_NO_PING_RESPONSE_ERROR: 1179 return "No Ping Response Error"; 1180 case COMP_EVENT_RING_FULL_ERROR: 1181 return "Event Ring Full Error"; 1182 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1183 return "Incompatible Device Error"; 1184 case COMP_MISSED_SERVICE_ERROR: 1185 return "Missed Service Error"; 1186 case COMP_COMMAND_RING_STOPPED: 1187 return "Command Ring Stopped"; 1188 case COMP_COMMAND_ABORTED: 1189 return "Command Aborted"; 1190 case COMP_STOPPED: 1191 return "Stopped"; 1192 case COMP_STOPPED_LENGTH_INVALID: 1193 return "Stopped - Length Invalid"; 1194 case COMP_STOPPED_SHORT_PACKET: 1195 return "Stopped - Short Packet"; 1196 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1197 return "Max Exit Latency Too Large Error"; 1198 case COMP_ISOCH_BUFFER_OVERRUN: 1199 return "Isoch Buffer Overrun"; 1200 case COMP_EVENT_LOST_ERROR: 1201 return "Event Lost Error"; 1202 case COMP_UNDEFINED_ERROR: 1203 return "Undefined Error"; 1204 case COMP_INVALID_STREAM_ID_ERROR: 1205 return "Invalid Stream ID Error"; 1206 case COMP_SECONDARY_BANDWIDTH_ERROR: 1207 return "Secondary Bandwidth Error"; 1208 case COMP_SPLIT_TRANSACTION_ERROR: 1209 return "Split Transaction Error"; 1210 default: 1211 return "Unknown!!"; 1212 } 1213 } 1214 1215 struct xhci_link_trb { 1216 /* 64-bit segment pointer*/ 1217 __le64 segment_ptr; 1218 __le32 intr_target; 1219 __le32 control; 1220 }; 1221 1222 /* control bitfields */ 1223 #define LINK_TOGGLE (0x1<<1) 1224 1225 /* Command completion event TRB */ 1226 struct xhci_event_cmd { 1227 /* Pointer to command TRB, or the value passed by the event data trb */ 1228 __le64 cmd_trb; 1229 __le32 status; 1230 __le32 flags; 1231 }; 1232 1233 /* flags bitmasks */ 1234 1235 /* Address device - disable SetAddress */ 1236 #define TRB_BSR (1<<9) 1237 1238 /* Configure Endpoint - Deconfigure */ 1239 #define TRB_DC (1<<9) 1240 1241 /* Stop Ring - Transfer State Preserve */ 1242 #define TRB_TSP (1<<9) 1243 1244 enum xhci_ep_reset_type { 1245 EP_HARD_RESET, 1246 EP_SOFT_RESET, 1247 }; 1248 1249 /* Force Event */ 1250 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1251 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1252 1253 /* Set Latency Tolerance Value */ 1254 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1255 1256 /* Get Port Bandwidth */ 1257 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1258 1259 /* Force Header */ 1260 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1261 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1262 1263 enum xhci_setup_dev { 1264 SETUP_CONTEXT_ONLY, 1265 SETUP_CONTEXT_ADDRESS, 1266 }; 1267 1268 /* bits 16:23 are the virtual function ID */ 1269 /* bits 24:31 are the slot ID */ 1270 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1271 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1272 1273 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1274 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1275 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1276 1277 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1278 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1279 #define LAST_EP_INDEX 30 1280 1281 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1282 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1283 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1284 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1285 1286 /* Link TRB specific fields */ 1287 #define TRB_TC (1<<1) 1288 1289 /* Port Status Change Event TRB fields */ 1290 /* Port ID - bits 31:24 */ 1291 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1292 1293 #define EVENT_DATA (1 << 2) 1294 1295 /* Normal TRB fields */ 1296 /* transfer_len bitmasks - bits 0:16 */ 1297 #define TRB_LEN(p) ((p) & 0x1ffff) 1298 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1299 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1300 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1301 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1302 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1303 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1304 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1305 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1306 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1307 #define TRB_TBC(p) (((p) & 0x3) << 7) 1308 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1309 1310 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1311 #define TRB_CYCLE (1<<0) 1312 /* 1313 * Force next event data TRB to be evaluated before task switch. 1314 * Used to pass OS data back after a TD completes. 1315 */ 1316 #define TRB_ENT (1<<1) 1317 /* Interrupt on short packet */ 1318 #define TRB_ISP (1<<2) 1319 /* Set PCIe no snoop attribute */ 1320 #define TRB_NO_SNOOP (1<<3) 1321 /* Chain multiple TRBs into a TD */ 1322 #define TRB_CHAIN (1<<4) 1323 /* Interrupt on completion */ 1324 #define TRB_IOC (1<<5) 1325 /* The buffer pointer contains immediate data */ 1326 #define TRB_IDT (1<<6) 1327 /* TDs smaller than this might use IDT */ 1328 #define TRB_IDT_MAX_SIZE 8 1329 1330 /* Block Event Interrupt */ 1331 #define TRB_BEI (1<<9) 1332 1333 /* Control transfer TRB specific fields */ 1334 #define TRB_DIR_IN (1<<16) 1335 #define TRB_TX_TYPE(p) ((p) << 16) 1336 #define TRB_DATA_OUT 2 1337 #define TRB_DATA_IN 3 1338 1339 /* Isochronous TRB specific fields */ 1340 #define TRB_SIA (1<<31) 1341 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1342 1343 /* TRB cache size for xHC with TRB cache */ 1344 #define TRB_CACHE_SIZE_HS 8 1345 #define TRB_CACHE_SIZE_SS 16 1346 1347 struct xhci_generic_trb { 1348 __le32 field[4]; 1349 }; 1350 1351 union xhci_trb { 1352 struct xhci_link_trb link; 1353 struct xhci_transfer_event trans_event; 1354 struct xhci_event_cmd event_cmd; 1355 struct xhci_generic_trb generic; 1356 }; 1357 1358 /* TRB bit mask */ 1359 #define TRB_TYPE_BITMASK (0xfc00) 1360 #define TRB_TYPE(p) ((p) << 10) 1361 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1362 /* TRB type IDs */ 1363 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1364 #define TRB_NORMAL 1 1365 /* setup stage for control transfers */ 1366 #define TRB_SETUP 2 1367 /* data stage for control transfers */ 1368 #define TRB_DATA 3 1369 /* status stage for control transfers */ 1370 #define TRB_STATUS 4 1371 /* isoc transfers */ 1372 #define TRB_ISOC 5 1373 /* TRB for linking ring segments */ 1374 #define TRB_LINK 6 1375 #define TRB_EVENT_DATA 7 1376 /* Transfer Ring No-op (not for the command ring) */ 1377 #define TRB_TR_NOOP 8 1378 /* Command TRBs */ 1379 /* Enable Slot Command */ 1380 #define TRB_ENABLE_SLOT 9 1381 /* Disable Slot Command */ 1382 #define TRB_DISABLE_SLOT 10 1383 /* Address Device Command */ 1384 #define TRB_ADDR_DEV 11 1385 /* Configure Endpoint Command */ 1386 #define TRB_CONFIG_EP 12 1387 /* Evaluate Context Command */ 1388 #define TRB_EVAL_CONTEXT 13 1389 /* Reset Endpoint Command */ 1390 #define TRB_RESET_EP 14 1391 /* Stop Transfer Ring Command */ 1392 #define TRB_STOP_RING 15 1393 /* Set Transfer Ring Dequeue Pointer Command */ 1394 #define TRB_SET_DEQ 16 1395 /* Reset Device Command */ 1396 #define TRB_RESET_DEV 17 1397 /* Force Event Command (opt) */ 1398 #define TRB_FORCE_EVENT 18 1399 /* Negotiate Bandwidth Command (opt) */ 1400 #define TRB_NEG_BANDWIDTH 19 1401 /* Set Latency Tolerance Value Command (opt) */ 1402 #define TRB_SET_LT 20 1403 /* Get port bandwidth Command */ 1404 #define TRB_GET_BW 21 1405 /* Force Header Command - generate a transaction or link management packet */ 1406 #define TRB_FORCE_HEADER 22 1407 /* No-op Command - not for transfer rings */ 1408 #define TRB_CMD_NOOP 23 1409 /* TRB IDs 24-31 reserved */ 1410 /* Event TRBS */ 1411 /* Transfer Event */ 1412 #define TRB_TRANSFER 32 1413 /* Command Completion Event */ 1414 #define TRB_COMPLETION 33 1415 /* Port Status Change Event */ 1416 #define TRB_PORT_STATUS 34 1417 /* Bandwidth Request Event (opt) */ 1418 #define TRB_BANDWIDTH_EVENT 35 1419 /* Doorbell Event (opt) */ 1420 #define TRB_DOORBELL 36 1421 /* Host Controller Event */ 1422 #define TRB_HC_EVENT 37 1423 /* Device Notification Event - device sent function wake notification */ 1424 #define TRB_DEV_NOTE 38 1425 /* MFINDEX Wrap Event - microframe counter wrapped */ 1426 #define TRB_MFINDEX_WRAP 39 1427 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1428 #define TRB_VENDOR_DEFINED_LOW 48 1429 /* Nec vendor-specific command completion event. */ 1430 #define TRB_NEC_CMD_COMP 48 1431 /* Get NEC firmware revision. */ 1432 #define TRB_NEC_GET_FW 49 1433 1434 static inline const char *xhci_trb_type_string(u8 type) 1435 { 1436 switch (type) { 1437 case TRB_NORMAL: 1438 return "Normal"; 1439 case TRB_SETUP: 1440 return "Setup Stage"; 1441 case TRB_DATA: 1442 return "Data Stage"; 1443 case TRB_STATUS: 1444 return "Status Stage"; 1445 case TRB_ISOC: 1446 return "Isoch"; 1447 case TRB_LINK: 1448 return "Link"; 1449 case TRB_EVENT_DATA: 1450 return "Event Data"; 1451 case TRB_TR_NOOP: 1452 return "No-Op"; 1453 case TRB_ENABLE_SLOT: 1454 return "Enable Slot Command"; 1455 case TRB_DISABLE_SLOT: 1456 return "Disable Slot Command"; 1457 case TRB_ADDR_DEV: 1458 return "Address Device Command"; 1459 case TRB_CONFIG_EP: 1460 return "Configure Endpoint Command"; 1461 case TRB_EVAL_CONTEXT: 1462 return "Evaluate Context Command"; 1463 case TRB_RESET_EP: 1464 return "Reset Endpoint Command"; 1465 case TRB_STOP_RING: 1466 return "Stop Ring Command"; 1467 case TRB_SET_DEQ: 1468 return "Set TR Dequeue Pointer Command"; 1469 case TRB_RESET_DEV: 1470 return "Reset Device Command"; 1471 case TRB_FORCE_EVENT: 1472 return "Force Event Command"; 1473 case TRB_NEG_BANDWIDTH: 1474 return "Negotiate Bandwidth Command"; 1475 case TRB_SET_LT: 1476 return "Set Latency Tolerance Value Command"; 1477 case TRB_GET_BW: 1478 return "Get Port Bandwidth Command"; 1479 case TRB_FORCE_HEADER: 1480 return "Force Header Command"; 1481 case TRB_CMD_NOOP: 1482 return "No-Op Command"; 1483 case TRB_TRANSFER: 1484 return "Transfer Event"; 1485 case TRB_COMPLETION: 1486 return "Command Completion Event"; 1487 case TRB_PORT_STATUS: 1488 return "Port Status Change Event"; 1489 case TRB_BANDWIDTH_EVENT: 1490 return "Bandwidth Request Event"; 1491 case TRB_DOORBELL: 1492 return "Doorbell Event"; 1493 case TRB_HC_EVENT: 1494 return "Host Controller Event"; 1495 case TRB_DEV_NOTE: 1496 return "Device Notification Event"; 1497 case TRB_MFINDEX_WRAP: 1498 return "MFINDEX Wrap Event"; 1499 case TRB_NEC_CMD_COMP: 1500 return "NEC Command Completion Event"; 1501 case TRB_NEC_GET_FW: 1502 return "NET Get Firmware Revision Command"; 1503 default: 1504 return "UNKNOWN"; 1505 } 1506 } 1507 1508 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1509 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1510 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1511 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1512 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1513 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1514 1515 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1516 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1517 1518 /* 1519 * TRBS_PER_SEGMENT must be a multiple of 4, 1520 * since the command ring is 64-byte aligned. 1521 * It must also be greater than 16. 1522 */ 1523 #define TRBS_PER_SEGMENT 256 1524 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1525 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1526 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1527 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1528 /* TRB buffer pointers can't cross 64KB boundaries */ 1529 #define TRB_MAX_BUFF_SHIFT 16 1530 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1531 /* How much data is left before the 64KB boundary? */ 1532 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1533 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1534 #define MAX_SOFT_RETRY 3 1535 /* 1536 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1537 * XHCI_AVOID_BEI quirk is in use. 1538 */ 1539 #define AVOID_BEI_INTERVAL_MIN 8 1540 #define AVOID_BEI_INTERVAL_MAX 32 1541 1542 struct xhci_segment { 1543 union xhci_trb *trbs; 1544 /* private to HCD */ 1545 struct xhci_segment *next; 1546 dma_addr_t dma; 1547 /* Max packet sized bounce buffer for td-fragmant alignment */ 1548 dma_addr_t bounce_dma; 1549 void *bounce_buf; 1550 unsigned int bounce_offs; 1551 unsigned int bounce_len; 1552 }; 1553 1554 enum xhci_cancelled_td_status { 1555 TD_DIRTY = 0, 1556 TD_HALTED, 1557 TD_CLEARING_CACHE, 1558 TD_CLEARED, 1559 }; 1560 1561 struct xhci_td { 1562 struct list_head td_list; 1563 struct list_head cancelled_td_list; 1564 int status; 1565 enum xhci_cancelled_td_status cancel_status; 1566 struct urb *urb; 1567 struct xhci_segment *start_seg; 1568 union xhci_trb *first_trb; 1569 union xhci_trb *last_trb; 1570 struct xhci_segment *last_trb_seg; 1571 struct xhci_segment *bounce_seg; 1572 /* actual_length of the URB has already been set */ 1573 bool urb_length_set; 1574 unsigned int num_trbs; 1575 }; 1576 1577 /* xHCI command default timeout value */ 1578 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1579 1580 /* command descriptor */ 1581 struct xhci_cd { 1582 struct xhci_command *command; 1583 union xhci_trb *cmd_trb; 1584 }; 1585 1586 enum xhci_ring_type { 1587 TYPE_CTRL = 0, 1588 TYPE_ISOC, 1589 TYPE_BULK, 1590 TYPE_INTR, 1591 TYPE_STREAM, 1592 TYPE_COMMAND, 1593 TYPE_EVENT, 1594 }; 1595 1596 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1597 { 1598 switch (type) { 1599 case TYPE_CTRL: 1600 return "CTRL"; 1601 case TYPE_ISOC: 1602 return "ISOC"; 1603 case TYPE_BULK: 1604 return "BULK"; 1605 case TYPE_INTR: 1606 return "INTR"; 1607 case TYPE_STREAM: 1608 return "STREAM"; 1609 case TYPE_COMMAND: 1610 return "CMD"; 1611 case TYPE_EVENT: 1612 return "EVENT"; 1613 } 1614 1615 return "UNKNOWN"; 1616 } 1617 1618 struct xhci_ring { 1619 struct xhci_segment *first_seg; 1620 struct xhci_segment *last_seg; 1621 union xhci_trb *enqueue; 1622 struct xhci_segment *enq_seg; 1623 union xhci_trb *dequeue; 1624 struct xhci_segment *deq_seg; 1625 struct list_head td_list; 1626 /* 1627 * Write the cycle state into the TRB cycle field to give ownership of 1628 * the TRB to the host controller (if we are the producer), or to check 1629 * if we own the TRB (if we are the consumer). See section 4.9.1. 1630 */ 1631 u32 cycle_state; 1632 unsigned int err_count; 1633 unsigned int stream_id; 1634 unsigned int num_segs; 1635 unsigned int num_trbs_free; 1636 unsigned int num_trbs_free_temp; 1637 unsigned int bounce_buf_len; 1638 enum xhci_ring_type type; 1639 bool last_td_was_short; 1640 struct radix_tree_root *trb_address_map; 1641 }; 1642 1643 struct xhci_erst_entry { 1644 /* 64-bit event ring segment address */ 1645 __le64 seg_addr; 1646 __le32 seg_size; 1647 /* Set to zero */ 1648 __le32 rsvd; 1649 }; 1650 1651 struct xhci_erst { 1652 struct xhci_erst_entry *entries; 1653 unsigned int num_entries; 1654 /* xhci->event_ring keeps track of segment dma addresses */ 1655 dma_addr_t erst_dma_addr; 1656 /* Num entries the ERST can contain */ 1657 unsigned int erst_size; 1658 }; 1659 1660 struct xhci_scratchpad { 1661 u64 *sp_array; 1662 dma_addr_t sp_dma; 1663 void **sp_buffers; 1664 }; 1665 1666 struct urb_priv { 1667 int num_tds; 1668 int num_tds_done; 1669 struct xhci_td td[]; 1670 }; 1671 1672 /* 1673 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1674 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1675 * meaning 64 ring segments. 1676 * Initial allocated size of the ERST, in number of entries */ 1677 #define ERST_NUM_SEGS 1 1678 /* Poll every 60 seconds */ 1679 #define POLL_TIMEOUT 60 1680 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1681 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1682 /* XXX: Make these module parameters */ 1683 1684 struct s3_save { 1685 u32 command; 1686 u32 dev_nt; 1687 u64 dcbaa_ptr; 1688 u32 config_reg; 1689 u32 irq_pending; 1690 u32 irq_control; 1691 u32 erst_size; 1692 u64 erst_base; 1693 u64 erst_dequeue; 1694 }; 1695 1696 /* Use for lpm */ 1697 struct dev_info { 1698 u32 dev_id; 1699 struct list_head list; 1700 }; 1701 1702 struct xhci_bus_state { 1703 unsigned long bus_suspended; 1704 unsigned long next_statechange; 1705 1706 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1707 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1708 u32 port_c_suspend; 1709 u32 suspended_ports; 1710 u32 port_remote_wakeup; 1711 unsigned long resume_done[USB_MAXCHILDREN]; 1712 /* which ports have started to resume */ 1713 unsigned long resuming_ports; 1714 /* Which ports are waiting on RExit to U0 transition. */ 1715 unsigned long rexit_ports; 1716 struct completion rexit_done[USB_MAXCHILDREN]; 1717 struct completion u3exit_done[USB_MAXCHILDREN]; 1718 }; 1719 1720 1721 /* 1722 * It can take up to 20 ms to transition from RExit to U0 on the 1723 * Intel Lynx Point LP xHCI host. 1724 */ 1725 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1726 struct xhci_port_cap { 1727 u32 *psi; /* array of protocol speed ID entries */ 1728 u8 psi_count; 1729 u8 psi_uid_count; 1730 u8 maj_rev; 1731 u8 min_rev; 1732 }; 1733 1734 struct xhci_port { 1735 __le32 __iomem *addr; 1736 int hw_portnum; 1737 int hcd_portnum; 1738 struct xhci_hub *rhub; 1739 struct xhci_port_cap *port_cap; 1740 }; 1741 1742 struct xhci_hub { 1743 struct xhci_port **ports; 1744 unsigned int num_ports; 1745 struct usb_hcd *hcd; 1746 /* keep track of bus suspend info */ 1747 struct xhci_bus_state bus_state; 1748 /* supported prococol extended capabiliy values */ 1749 u8 maj_rev; 1750 u8 min_rev; 1751 }; 1752 1753 /* There is one xhci_hcd structure per controller */ 1754 struct xhci_hcd { 1755 struct usb_hcd *main_hcd; 1756 struct usb_hcd *shared_hcd; 1757 /* glue to PCI and HCD framework */ 1758 struct xhci_cap_regs __iomem *cap_regs; 1759 struct xhci_op_regs __iomem *op_regs; 1760 struct xhci_run_regs __iomem *run_regs; 1761 struct xhci_doorbell_array __iomem *dba; 1762 /* Our HCD's current interrupter register set */ 1763 struct xhci_intr_reg __iomem *ir_set; 1764 1765 /* Cached register copies of read-only HC data */ 1766 __u32 hcs_params1; 1767 __u32 hcs_params2; 1768 __u32 hcs_params3; 1769 __u32 hcc_params; 1770 __u32 hcc_params2; 1771 1772 spinlock_t lock; 1773 1774 /* packed release number */ 1775 u8 sbrn; 1776 u16 hci_version; 1777 u8 max_slots; 1778 u8 max_interrupters; 1779 u8 max_ports; 1780 u8 isoc_threshold; 1781 /* imod_interval in ns (I * 250ns) */ 1782 u32 imod_interval; 1783 u32 isoc_bei_interval; 1784 int event_ring_max; 1785 /* 4KB min, 128MB max */ 1786 int page_size; 1787 /* Valid values are 12 to 20, inclusive */ 1788 int page_shift; 1789 /* msi-x vectors */ 1790 int msix_count; 1791 /* optional clocks */ 1792 struct clk *clk; 1793 struct clk *reg_clk; 1794 /* optional reset controller */ 1795 struct reset_control *reset; 1796 /* data structures */ 1797 struct xhci_device_context_array *dcbaa; 1798 struct xhci_ring *cmd_ring; 1799 unsigned int cmd_ring_state; 1800 #define CMD_RING_STATE_RUNNING (1 << 0) 1801 #define CMD_RING_STATE_ABORTED (1 << 1) 1802 #define CMD_RING_STATE_STOPPED (1 << 2) 1803 struct list_head cmd_list; 1804 unsigned int cmd_ring_reserved_trbs; 1805 struct delayed_work cmd_timer; 1806 struct completion cmd_ring_stop_completion; 1807 struct xhci_command *current_cmd; 1808 struct xhci_ring *event_ring; 1809 struct xhci_erst erst; 1810 /* Scratchpad */ 1811 struct xhci_scratchpad *scratchpad; 1812 /* Store LPM test failed devices' information */ 1813 struct list_head lpm_failed_devs; 1814 1815 /* slot enabling and address device helpers */ 1816 /* these are not thread safe so use mutex */ 1817 struct mutex mutex; 1818 /* Internal mirror of the HW's dcbaa */ 1819 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1820 /* For keeping track of bandwidth domains per roothub. */ 1821 struct xhci_root_port_bw_info *rh_bw; 1822 1823 /* DMA pools */ 1824 struct dma_pool *device_pool; 1825 struct dma_pool *segment_pool; 1826 struct dma_pool *small_streams_pool; 1827 struct dma_pool *medium_streams_pool; 1828 1829 /* Host controller watchdog timer structures */ 1830 unsigned int xhc_state; 1831 1832 u32 command; 1833 struct s3_save s3; 1834 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1835 * 1836 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1837 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1838 * that sees this status (other than the timer that set it) should stop touching 1839 * hardware immediately. Interrupt handlers should return immediately when 1840 * they see this status (any time they drop and re-acquire xhci->lock). 1841 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1842 * putting the TD on the canceled list, etc. 1843 * 1844 * There are no reports of xHCI host controllers that display this issue. 1845 */ 1846 #define XHCI_STATE_DYING (1 << 0) 1847 #define XHCI_STATE_HALTED (1 << 1) 1848 #define XHCI_STATE_REMOVING (1 << 2) 1849 unsigned long long quirks; 1850 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1851 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) 1852 #define XHCI_NEC_HOST BIT_ULL(2) 1853 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1854 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1855 /* 1856 * Certain Intel host controllers have a limit to the number of endpoint 1857 * contexts they can handle. Ideally, they would signal that they can't handle 1858 * anymore endpoint contexts by returning a Resource Error for the Configure 1859 * Endpoint command, but they don't. Instead they expect software to keep track 1860 * of the number of active endpoints for them, across configure endpoint 1861 * commands, reset device commands, disable slot commands, and address device 1862 * commands. 1863 */ 1864 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1865 #define XHCI_BROKEN_MSI BIT_ULL(6) 1866 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1867 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1868 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1869 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) 1870 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1871 #define XHCI_INTEL_HOST BIT_ULL(12) 1872 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1873 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1874 #define XHCI_AVOID_BEI BIT_ULL(15) 1875 #define XHCI_PLAT BIT_ULL(16) 1876 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1877 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1878 /* For controllers with a broken beyond repair streams implementation */ 1879 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1880 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1881 #define XHCI_MTK_HOST BIT_ULL(21) 1882 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1883 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1884 #define XHCI_MISSING_CAS BIT_ULL(24) 1885 /* For controller with a broken Port Disable implementation */ 1886 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1887 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1888 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1889 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1890 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1891 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1892 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1893 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1894 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1895 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1896 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1897 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36) 1898 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1899 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1900 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1901 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1902 #define XHCI_BROKEN_D3COLD BIT_ULL(41) 1903 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1904 1905 unsigned int num_active_eps; 1906 unsigned int limit_active_eps; 1907 struct xhci_port *hw_ports; 1908 struct xhci_hub usb2_rhub; 1909 struct xhci_hub usb3_rhub; 1910 /* support xHCI 1.0 spec USB2 hardware LPM */ 1911 unsigned hw_lpm_support:1; 1912 /* Broken Suspend flag for SNPS Suspend resume issue */ 1913 unsigned broken_suspend:1; 1914 /* cached usb2 extened protocol capabilites */ 1915 u32 *ext_caps; 1916 unsigned int num_ext_caps; 1917 /* cached extended protocol port capabilities */ 1918 struct xhci_port_cap *port_caps; 1919 unsigned int num_port_caps; 1920 /* Compliance Mode Recovery Data */ 1921 struct timer_list comp_mode_recovery_timer; 1922 u32 port_status_u0; 1923 u16 test_mode; 1924 /* Compliance Mode Timer Triggered every 2 seconds */ 1925 #define COMP_MODE_RCVRY_MSECS 2000 1926 1927 struct dentry *debugfs_root; 1928 struct dentry *debugfs_slots; 1929 struct list_head regset_list; 1930 1931 void *dbc; 1932 /* platform-specific data -- must come last */ 1933 unsigned long priv[] __aligned(sizeof(s64)); 1934 }; 1935 1936 /* Platform specific overrides to generic XHCI hc_driver ops */ 1937 struct xhci_driver_overrides { 1938 size_t extra_priv_size; 1939 int (*reset)(struct usb_hcd *hcd); 1940 int (*start)(struct usb_hcd *hcd); 1941 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1942 struct usb_host_endpoint *ep); 1943 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1944 struct usb_host_endpoint *ep); 1945 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1946 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1947 }; 1948 1949 #define XHCI_CFC_DELAY 10 1950 1951 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1952 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1953 { 1954 struct usb_hcd *primary_hcd; 1955 1956 if (usb_hcd_is_primary_hcd(hcd)) 1957 primary_hcd = hcd; 1958 else 1959 primary_hcd = hcd->primary_hcd; 1960 1961 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1962 } 1963 1964 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1965 { 1966 return xhci->main_hcd; 1967 } 1968 1969 #define xhci_dbg(xhci, fmt, args...) \ 1970 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1971 #define xhci_err(xhci, fmt, args...) \ 1972 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1973 #define xhci_warn(xhci, fmt, args...) \ 1974 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1975 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1976 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1977 #define xhci_info(xhci, fmt, args...) \ 1978 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1979 1980 /* 1981 * Registers should always be accessed with double word or quad word accesses. 1982 * 1983 * Some xHCI implementations may support 64-bit address pointers. Registers 1984 * with 64-bit address pointers should be written to with dword accesses by 1985 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1986 * xHCI implementations that do not support 64-bit address pointers will ignore 1987 * the high dword, and write order is irrelevant. 1988 */ 1989 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1990 __le64 __iomem *regs) 1991 { 1992 return lo_hi_readq(regs); 1993 } 1994 static inline void xhci_write_64(struct xhci_hcd *xhci, 1995 const u64 val, __le64 __iomem *regs) 1996 { 1997 lo_hi_writeq(val, regs); 1998 } 1999 2000 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 2001 { 2002 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 2003 } 2004 2005 /* xHCI debugging */ 2006 char *xhci_get_slot_state(struct xhci_hcd *xhci, 2007 struct xhci_container_ctx *ctx); 2008 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 2009 const char *fmt, ...); 2010 2011 /* xHCI memory management */ 2012 void xhci_mem_cleanup(struct xhci_hcd *xhci); 2013 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 2014 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 2015 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 2016 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 2017 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 2018 struct usb_device *udev); 2019 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 2020 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 2021 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 2022 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 2023 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 2024 struct xhci_virt_device *virt_dev, 2025 int old_active_eps); 2026 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 2027 void xhci_update_bw_info(struct xhci_hcd *xhci, 2028 struct xhci_container_ctx *in_ctx, 2029 struct xhci_input_control_ctx *ctrl_ctx, 2030 struct xhci_virt_device *virt_dev); 2031 void xhci_endpoint_copy(struct xhci_hcd *xhci, 2032 struct xhci_container_ctx *in_ctx, 2033 struct xhci_container_ctx *out_ctx, 2034 unsigned int ep_index); 2035 void xhci_slot_copy(struct xhci_hcd *xhci, 2036 struct xhci_container_ctx *in_ctx, 2037 struct xhci_container_ctx *out_ctx); 2038 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 2039 struct usb_device *udev, struct usb_host_endpoint *ep, 2040 gfp_t mem_flags); 2041 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, 2042 unsigned int num_segs, unsigned int cycle_state, 2043 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 2044 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 2045 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 2046 unsigned int num_trbs, gfp_t flags); 2047 int xhci_alloc_erst(struct xhci_hcd *xhci, 2048 struct xhci_ring *evt_ring, 2049 struct xhci_erst *erst, 2050 gfp_t flags); 2051 void xhci_initialize_ring_info(struct xhci_ring *ring, 2052 unsigned int cycle_state); 2053 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 2054 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 2055 struct xhci_virt_device *virt_dev, 2056 unsigned int ep_index); 2057 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 2058 unsigned int num_stream_ctxs, 2059 unsigned int num_streams, 2060 unsigned int max_packet, gfp_t flags); 2061 void xhci_free_stream_info(struct xhci_hcd *xhci, 2062 struct xhci_stream_info *stream_info); 2063 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 2064 struct xhci_ep_ctx *ep_ctx, 2065 struct xhci_stream_info *stream_info); 2066 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 2067 struct xhci_virt_ep *ep); 2068 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 2069 struct xhci_virt_device *virt_dev, bool drop_control_ep); 2070 struct xhci_ring *xhci_dma_to_transfer_ring( 2071 struct xhci_virt_ep *ep, 2072 u64 address); 2073 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 2074 bool allocate_completion, gfp_t mem_flags); 2075 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 2076 bool allocate_completion, gfp_t mem_flags); 2077 void xhci_urb_free_priv(struct urb_priv *urb_priv); 2078 void xhci_free_command(struct xhci_hcd *xhci, 2079 struct xhci_command *command); 2080 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 2081 int type, gfp_t flags); 2082 void xhci_free_container_ctx(struct xhci_hcd *xhci, 2083 struct xhci_container_ctx *ctx); 2084 2085 /* xHCI host controller glue */ 2086 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 2087 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 2088 void xhci_quiesce(struct xhci_hcd *xhci); 2089 int xhci_halt(struct xhci_hcd *xhci); 2090 int xhci_start(struct xhci_hcd *xhci); 2091 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 2092 int xhci_run(struct usb_hcd *hcd); 2093 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2094 void xhci_shutdown(struct usb_hcd *hcd); 2095 void xhci_init_driver(struct hc_driver *drv, 2096 const struct xhci_driver_overrides *over); 2097 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 2098 struct usb_host_endpoint *ep); 2099 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 2100 struct usb_host_endpoint *ep); 2101 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2102 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2103 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 2104 int xhci_ext_cap_init(struct xhci_hcd *xhci); 2105 2106 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2107 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 2108 2109 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2110 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2111 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2112 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2113 struct xhci_virt_device *virt_dev, 2114 struct usb_device *hdev, 2115 struct usb_tt *tt, gfp_t mem_flags); 2116 2117 /* xHCI ring, segment, TRB, and TD functions */ 2118 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2119 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2120 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2121 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2122 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2123 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2124 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2125 u32 trb_type, u32 slot_id); 2126 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2127 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2128 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2129 u32 field1, u32 field2, u32 field3, u32 field4); 2130 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2131 int slot_id, unsigned int ep_index, int suspend); 2132 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2133 int slot_id, unsigned int ep_index); 2134 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2135 int slot_id, unsigned int ep_index); 2136 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2137 int slot_id, unsigned int ep_index); 2138 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2139 struct urb *urb, int slot_id, unsigned int ep_index); 2140 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2141 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2142 bool command_must_succeed); 2143 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2144 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2145 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2146 int slot_id, unsigned int ep_index, 2147 enum xhci_ep_reset_type reset_type); 2148 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2149 u32 slot_id); 2150 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id, 2151 unsigned int ep_index, unsigned int stream_id, 2152 struct xhci_td *td); 2153 void xhci_stop_endpoint_command_watchdog(struct timer_list *t); 2154 void xhci_handle_command_timeout(struct work_struct *work); 2155 2156 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2157 unsigned int ep_index, unsigned int stream_id); 2158 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 2159 unsigned int slot_id, 2160 unsigned int ep_index); 2161 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2162 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 2163 unsigned int count_trbs(u64 addr, u64 len); 2164 2165 /* xHCI roothub code */ 2166 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 2167 u32 link_state); 2168 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 2169 u32 port_bit); 2170 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2171 char *buf, u16 wLength); 2172 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2173 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2174 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 2175 2176 void xhci_hc_died(struct xhci_hcd *xhci); 2177 2178 #ifdef CONFIG_PM 2179 int xhci_bus_suspend(struct usb_hcd *hcd); 2180 int xhci_bus_resume(struct usb_hcd *hcd); 2181 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 2182 #else 2183 #define xhci_bus_suspend NULL 2184 #define xhci_bus_resume NULL 2185 #define xhci_get_resuming_ports NULL 2186 #endif /* CONFIG_PM */ 2187 2188 u32 xhci_port_state_to_neutral(u32 state); 2189 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2190 u16 port); 2191 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2192 2193 /* xHCI contexts */ 2194 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2195 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2196 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2197 2198 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2199 unsigned int slot_id, unsigned int ep_index, 2200 unsigned int stream_id); 2201 2202 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2203 struct urb *urb) 2204 { 2205 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2206 xhci_get_endpoint_index(&urb->ep->desc), 2207 urb->stream_id); 2208 } 2209 2210 /* 2211 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 2212 * them anyways as we where unable to find a device that matches the 2213 * constraints. 2214 */ 2215 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 2216 { 2217 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 2218 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 2219 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 2220 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 2221 !urb->num_sgs) 2222 return true; 2223 2224 return false; 2225 } 2226 2227 static inline char *xhci_slot_state_string(u32 state) 2228 { 2229 switch (state) { 2230 case SLOT_STATE_ENABLED: 2231 return "enabled/disabled"; 2232 case SLOT_STATE_DEFAULT: 2233 return "default"; 2234 case SLOT_STATE_ADDRESSED: 2235 return "addressed"; 2236 case SLOT_STATE_CONFIGURED: 2237 return "configured"; 2238 default: 2239 return "reserved"; 2240 } 2241 } 2242 2243 static inline const char *xhci_decode_trb(char *str, size_t size, 2244 u32 field0, u32 field1, u32 field2, u32 field3) 2245 { 2246 int type = TRB_FIELD_TO_TYPE(field3); 2247 2248 switch (type) { 2249 case TRB_LINK: 2250 snprintf(str, size, 2251 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2252 field1, field0, GET_INTR_TARGET(field2), 2253 xhci_trb_type_string(type), 2254 field3 & TRB_IOC ? 'I' : 'i', 2255 field3 & TRB_CHAIN ? 'C' : 'c', 2256 field3 & TRB_TC ? 'T' : 't', 2257 field3 & TRB_CYCLE ? 'C' : 'c'); 2258 break; 2259 case TRB_TRANSFER: 2260 case TRB_COMPLETION: 2261 case TRB_PORT_STATUS: 2262 case TRB_BANDWIDTH_EVENT: 2263 case TRB_DOORBELL: 2264 case TRB_HC_EVENT: 2265 case TRB_DEV_NOTE: 2266 case TRB_MFINDEX_WRAP: 2267 snprintf(str, size, 2268 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2269 field1, field0, 2270 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2271 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2272 /* Macro decrements 1, maybe it shouldn't?!? */ 2273 TRB_TO_EP_INDEX(field3) + 1, 2274 xhci_trb_type_string(type), 2275 field3 & EVENT_DATA ? 'E' : 'e', 2276 field3 & TRB_CYCLE ? 'C' : 'c'); 2277 2278 break; 2279 case TRB_SETUP: 2280 snprintf(str, size, 2281 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2282 field0 & 0xff, 2283 (field0 & 0xff00) >> 8, 2284 (field0 & 0xff000000) >> 24, 2285 (field0 & 0xff0000) >> 16, 2286 (field1 & 0xff00) >> 8, 2287 field1 & 0xff, 2288 (field1 & 0xff000000) >> 16 | 2289 (field1 & 0xff0000) >> 16, 2290 TRB_LEN(field2), GET_TD_SIZE(field2), 2291 GET_INTR_TARGET(field2), 2292 xhci_trb_type_string(type), 2293 field3 & TRB_IDT ? 'I' : 'i', 2294 field3 & TRB_IOC ? 'I' : 'i', 2295 field3 & TRB_CYCLE ? 'C' : 'c'); 2296 break; 2297 case TRB_DATA: 2298 snprintf(str, size, 2299 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2300 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2301 GET_INTR_TARGET(field2), 2302 xhci_trb_type_string(type), 2303 field3 & TRB_IDT ? 'I' : 'i', 2304 field3 & TRB_IOC ? 'I' : 'i', 2305 field3 & TRB_CHAIN ? 'C' : 'c', 2306 field3 & TRB_NO_SNOOP ? 'S' : 's', 2307 field3 & TRB_ISP ? 'I' : 'i', 2308 field3 & TRB_ENT ? 'E' : 'e', 2309 field3 & TRB_CYCLE ? 'C' : 'c'); 2310 break; 2311 case TRB_STATUS: 2312 snprintf(str, size, 2313 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2314 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2315 GET_INTR_TARGET(field2), 2316 xhci_trb_type_string(type), 2317 field3 & TRB_IOC ? 'I' : 'i', 2318 field3 & TRB_CHAIN ? 'C' : 'c', 2319 field3 & TRB_ENT ? 'E' : 'e', 2320 field3 & TRB_CYCLE ? 'C' : 'c'); 2321 break; 2322 case TRB_NORMAL: 2323 case TRB_ISOC: 2324 case TRB_EVENT_DATA: 2325 case TRB_TR_NOOP: 2326 snprintf(str, size, 2327 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2328 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2329 GET_INTR_TARGET(field2), 2330 xhci_trb_type_string(type), 2331 field3 & TRB_BEI ? 'B' : 'b', 2332 field3 & TRB_IDT ? 'I' : 'i', 2333 field3 & TRB_IOC ? 'I' : 'i', 2334 field3 & TRB_CHAIN ? 'C' : 'c', 2335 field3 & TRB_NO_SNOOP ? 'S' : 's', 2336 field3 & TRB_ISP ? 'I' : 'i', 2337 field3 & TRB_ENT ? 'E' : 'e', 2338 field3 & TRB_CYCLE ? 'C' : 'c'); 2339 break; 2340 2341 case TRB_CMD_NOOP: 2342 case TRB_ENABLE_SLOT: 2343 snprintf(str, size, 2344 "%s: flags %c", 2345 xhci_trb_type_string(type), 2346 field3 & TRB_CYCLE ? 'C' : 'c'); 2347 break; 2348 case TRB_DISABLE_SLOT: 2349 case TRB_NEG_BANDWIDTH: 2350 snprintf(str, size, 2351 "%s: slot %d flags %c", 2352 xhci_trb_type_string(type), 2353 TRB_TO_SLOT_ID(field3), 2354 field3 & TRB_CYCLE ? 'C' : 'c'); 2355 break; 2356 case TRB_ADDR_DEV: 2357 snprintf(str, size, 2358 "%s: ctx %08x%08x slot %d flags %c:%c", 2359 xhci_trb_type_string(type), 2360 field1, field0, 2361 TRB_TO_SLOT_ID(field3), 2362 field3 & TRB_BSR ? 'B' : 'b', 2363 field3 & TRB_CYCLE ? 'C' : 'c'); 2364 break; 2365 case TRB_CONFIG_EP: 2366 snprintf(str, size, 2367 "%s: ctx %08x%08x slot %d flags %c:%c", 2368 xhci_trb_type_string(type), 2369 field1, field0, 2370 TRB_TO_SLOT_ID(field3), 2371 field3 & TRB_DC ? 'D' : 'd', 2372 field3 & TRB_CYCLE ? 'C' : 'c'); 2373 break; 2374 case TRB_EVAL_CONTEXT: 2375 snprintf(str, size, 2376 "%s: ctx %08x%08x slot %d flags %c", 2377 xhci_trb_type_string(type), 2378 field1, field0, 2379 TRB_TO_SLOT_ID(field3), 2380 field3 & TRB_CYCLE ? 'C' : 'c'); 2381 break; 2382 case TRB_RESET_EP: 2383 snprintf(str, size, 2384 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2385 xhci_trb_type_string(type), 2386 field1, field0, 2387 TRB_TO_SLOT_ID(field3), 2388 /* Macro decrements 1, maybe it shouldn't?!? */ 2389 TRB_TO_EP_INDEX(field3) + 1, 2390 field3 & TRB_TSP ? 'T' : 't', 2391 field3 & TRB_CYCLE ? 'C' : 'c'); 2392 break; 2393 case TRB_STOP_RING: 2394 sprintf(str, 2395 "%s: slot %d sp %d ep %d flags %c", 2396 xhci_trb_type_string(type), 2397 TRB_TO_SLOT_ID(field3), 2398 TRB_TO_SUSPEND_PORT(field3), 2399 /* Macro decrements 1, maybe it shouldn't?!? */ 2400 TRB_TO_EP_INDEX(field3) + 1, 2401 field3 & TRB_CYCLE ? 'C' : 'c'); 2402 break; 2403 case TRB_SET_DEQ: 2404 snprintf(str, size, 2405 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2406 xhci_trb_type_string(type), 2407 field1, field0, 2408 TRB_TO_STREAM_ID(field2), 2409 TRB_TO_SLOT_ID(field3), 2410 /* Macro decrements 1, maybe it shouldn't?!? */ 2411 TRB_TO_EP_INDEX(field3) + 1, 2412 field3 & TRB_CYCLE ? 'C' : 'c'); 2413 break; 2414 case TRB_RESET_DEV: 2415 snprintf(str, size, 2416 "%s: slot %d flags %c", 2417 xhci_trb_type_string(type), 2418 TRB_TO_SLOT_ID(field3), 2419 field3 & TRB_CYCLE ? 'C' : 'c'); 2420 break; 2421 case TRB_FORCE_EVENT: 2422 snprintf(str, size, 2423 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2424 xhci_trb_type_string(type), 2425 field1, field0, 2426 TRB_TO_VF_INTR_TARGET(field2), 2427 TRB_TO_VF_ID(field3), 2428 field3 & TRB_CYCLE ? 'C' : 'c'); 2429 break; 2430 case TRB_SET_LT: 2431 snprintf(str, size, 2432 "%s: belt %d flags %c", 2433 xhci_trb_type_string(type), 2434 TRB_TO_BELT(field3), 2435 field3 & TRB_CYCLE ? 'C' : 'c'); 2436 break; 2437 case TRB_GET_BW: 2438 snprintf(str, size, 2439 "%s: ctx %08x%08x slot %d speed %d flags %c", 2440 xhci_trb_type_string(type), 2441 field1, field0, 2442 TRB_TO_SLOT_ID(field3), 2443 TRB_TO_DEV_SPEED(field3), 2444 field3 & TRB_CYCLE ? 'C' : 'c'); 2445 break; 2446 case TRB_FORCE_HEADER: 2447 snprintf(str, size, 2448 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2449 xhci_trb_type_string(type), 2450 field2, field1, field0 & 0xffffffe0, 2451 TRB_TO_PACKET_TYPE(field0), 2452 TRB_TO_ROOTHUB_PORT(field3), 2453 field3 & TRB_CYCLE ? 'C' : 'c'); 2454 break; 2455 default: 2456 snprintf(str, size, 2457 "type '%s' -> raw %08x %08x %08x %08x", 2458 xhci_trb_type_string(type), 2459 field0, field1, field2, field3); 2460 } 2461 2462 return str; 2463 } 2464 2465 static inline const char *xhci_decode_ctrl_ctx(char *str, 2466 unsigned long drop, unsigned long add) 2467 { 2468 unsigned int bit; 2469 int ret = 0; 2470 2471 str[0] = '\0'; 2472 2473 if (drop) { 2474 ret = sprintf(str, "Drop:"); 2475 for_each_set_bit(bit, &drop, 32) 2476 ret += sprintf(str + ret, " %d%s", 2477 bit / 2, 2478 bit % 2 ? "in":"out"); 2479 ret += sprintf(str + ret, ", "); 2480 } 2481 2482 if (add) { 2483 ret += sprintf(str + ret, "Add:%s%s", 2484 (add & SLOT_FLAG) ? " slot":"", 2485 (add & EP0_FLAG) ? " ep0":""); 2486 add &= ~(SLOT_FLAG | EP0_FLAG); 2487 for_each_set_bit(bit, &add, 32) 2488 ret += sprintf(str + ret, " %d%s", 2489 bit / 2, 2490 bit % 2 ? "in":"out"); 2491 } 2492 return str; 2493 } 2494 2495 static inline const char *xhci_decode_slot_context(char *str, 2496 u32 info, u32 info2, u32 tt_info, u32 state) 2497 { 2498 u32 speed; 2499 u32 hub; 2500 u32 mtt; 2501 int ret = 0; 2502 2503 speed = info & DEV_SPEED; 2504 hub = info & DEV_HUB; 2505 mtt = info & DEV_MTT; 2506 2507 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2508 info & ROUTE_STRING_MASK, 2509 ({ char *s; 2510 switch (speed) { 2511 case SLOT_SPEED_FS: 2512 s = "full-speed"; 2513 break; 2514 case SLOT_SPEED_LS: 2515 s = "low-speed"; 2516 break; 2517 case SLOT_SPEED_HS: 2518 s = "high-speed"; 2519 break; 2520 case SLOT_SPEED_SS: 2521 s = "super-speed"; 2522 break; 2523 case SLOT_SPEED_SSP: 2524 s = "super-speed plus"; 2525 break; 2526 default: 2527 s = "UNKNOWN speed"; 2528 } s; }), 2529 mtt ? " multi-TT" : "", 2530 hub ? " Hub" : "", 2531 (info & LAST_CTX_MASK) >> 27, 2532 info2 & MAX_EXIT, 2533 DEVINFO_TO_ROOT_HUB_PORT(info2), 2534 DEVINFO_TO_MAX_PORTS(info2)); 2535 2536 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2537 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2538 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2539 state & DEV_ADDR_MASK, 2540 xhci_slot_state_string(GET_SLOT_STATE(state))); 2541 2542 return str; 2543 } 2544 2545 2546 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2547 { 2548 switch (portsc & PORT_PLS_MASK) { 2549 case XDEV_U0: 2550 return "U0"; 2551 case XDEV_U1: 2552 return "U1"; 2553 case XDEV_U2: 2554 return "U2"; 2555 case XDEV_U3: 2556 return "U3"; 2557 case XDEV_DISABLED: 2558 return "Disabled"; 2559 case XDEV_RXDETECT: 2560 return "RxDetect"; 2561 case XDEV_INACTIVE: 2562 return "Inactive"; 2563 case XDEV_POLLING: 2564 return "Polling"; 2565 case XDEV_RECOVERY: 2566 return "Recovery"; 2567 case XDEV_HOT_RESET: 2568 return "Hot Reset"; 2569 case XDEV_COMP_MODE: 2570 return "Compliance mode"; 2571 case XDEV_TEST_MODE: 2572 return "Test mode"; 2573 case XDEV_RESUME: 2574 return "Resume"; 2575 default: 2576 break; 2577 } 2578 return "Unknown"; 2579 } 2580 2581 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2582 { 2583 int ret; 2584 2585 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ", 2586 portsc & PORT_POWER ? "Powered" : "Powered-off", 2587 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2588 portsc & PORT_PE ? "Enabled" : "Disabled", 2589 xhci_portsc_link_state_string(portsc), 2590 DEV_PORT_SPEED(portsc)); 2591 2592 if (portsc & PORT_OC) 2593 ret += sprintf(str + ret, "OverCurrent "); 2594 if (portsc & PORT_RESET) 2595 ret += sprintf(str + ret, "In-Reset "); 2596 2597 ret += sprintf(str + ret, "Change: "); 2598 if (portsc & PORT_CSC) 2599 ret += sprintf(str + ret, "CSC "); 2600 if (portsc & PORT_PEC) 2601 ret += sprintf(str + ret, "PEC "); 2602 if (portsc & PORT_WRC) 2603 ret += sprintf(str + ret, "WRC "); 2604 if (portsc & PORT_OCC) 2605 ret += sprintf(str + ret, "OCC "); 2606 if (portsc & PORT_RC) 2607 ret += sprintf(str + ret, "PRC "); 2608 if (portsc & PORT_PLC) 2609 ret += sprintf(str + ret, "PLC "); 2610 if (portsc & PORT_CEC) 2611 ret += sprintf(str + ret, "CEC "); 2612 if (portsc & PORT_CAS) 2613 ret += sprintf(str + ret, "CAS "); 2614 2615 ret += sprintf(str + ret, "Wake: "); 2616 if (portsc & PORT_WKCONN_E) 2617 ret += sprintf(str + ret, "WCE "); 2618 if (portsc & PORT_WKDISC_E) 2619 ret += sprintf(str + ret, "WDE "); 2620 if (portsc & PORT_WKOC_E) 2621 ret += sprintf(str + ret, "WOE "); 2622 2623 return str; 2624 } 2625 2626 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2627 { 2628 int ret = 0; 2629 2630 ret = sprintf(str, " 0x%08x", usbsts); 2631 2632 if (usbsts == ~(u32)0) 2633 return str; 2634 2635 if (usbsts & STS_HALT) 2636 ret += sprintf(str + ret, " HCHalted"); 2637 if (usbsts & STS_FATAL) 2638 ret += sprintf(str + ret, " HSE"); 2639 if (usbsts & STS_EINT) 2640 ret += sprintf(str + ret, " EINT"); 2641 if (usbsts & STS_PORT) 2642 ret += sprintf(str + ret, " PCD"); 2643 if (usbsts & STS_SAVE) 2644 ret += sprintf(str + ret, " SSS"); 2645 if (usbsts & STS_RESTORE) 2646 ret += sprintf(str + ret, " RSS"); 2647 if (usbsts & STS_SRE) 2648 ret += sprintf(str + ret, " SRE"); 2649 if (usbsts & STS_CNR) 2650 ret += sprintf(str + ret, " CNR"); 2651 if (usbsts & STS_HCE) 2652 ret += sprintf(str + ret, " HCE"); 2653 2654 return str; 2655 } 2656 2657 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2658 { 2659 u8 ep; 2660 u16 stream; 2661 int ret; 2662 2663 ep = (doorbell & 0xff); 2664 stream = doorbell >> 16; 2665 2666 if (slot == 0) { 2667 sprintf(str, "Command Ring %d", doorbell); 2668 return str; 2669 } 2670 ret = sprintf(str, "Slot %d ", slot); 2671 if (ep > 0 && ep < 32) 2672 ret = sprintf(str + ret, "ep%d%s", 2673 ep / 2, 2674 ep % 2 ? "in" : "out"); 2675 else if (ep == 0 || ep < 248) 2676 ret = sprintf(str + ret, "Reserved %d", ep); 2677 else 2678 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2679 if (stream) 2680 ret = sprintf(str + ret, " Stream %d", stream); 2681 2682 return str; 2683 } 2684 2685 static inline const char *xhci_ep_state_string(u8 state) 2686 { 2687 switch (state) { 2688 case EP_STATE_DISABLED: 2689 return "disabled"; 2690 case EP_STATE_RUNNING: 2691 return "running"; 2692 case EP_STATE_HALTED: 2693 return "halted"; 2694 case EP_STATE_STOPPED: 2695 return "stopped"; 2696 case EP_STATE_ERROR: 2697 return "error"; 2698 default: 2699 return "INVALID"; 2700 } 2701 } 2702 2703 static inline const char *xhci_ep_type_string(u8 type) 2704 { 2705 switch (type) { 2706 case ISOC_OUT_EP: 2707 return "Isoc OUT"; 2708 case BULK_OUT_EP: 2709 return "Bulk OUT"; 2710 case INT_OUT_EP: 2711 return "Int OUT"; 2712 case CTRL_EP: 2713 return "Ctrl"; 2714 case ISOC_IN_EP: 2715 return "Isoc IN"; 2716 case BULK_IN_EP: 2717 return "Bulk IN"; 2718 case INT_IN_EP: 2719 return "Int IN"; 2720 default: 2721 return "INVALID"; 2722 } 2723 } 2724 2725 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2726 u32 info2, u64 deq, u32 tx_info) 2727 { 2728 int ret; 2729 2730 u32 esit; 2731 u16 maxp; 2732 u16 avg; 2733 2734 u8 max_pstr; 2735 u8 ep_state; 2736 u8 interval; 2737 u8 ep_type; 2738 u8 burst; 2739 u8 cerr; 2740 u8 mult; 2741 2742 bool lsa; 2743 bool hid; 2744 2745 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2746 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2747 2748 ep_state = info & EP_STATE_MASK; 2749 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2750 interval = CTX_TO_EP_INTERVAL(info); 2751 mult = CTX_TO_EP_MULT(info) + 1; 2752 lsa = !!(info & EP_HAS_LSA); 2753 2754 cerr = (info2 & (3 << 1)) >> 1; 2755 ep_type = CTX_TO_EP_TYPE(info2); 2756 hid = !!(info2 & (1 << 7)); 2757 burst = CTX_TO_MAX_BURST(info2); 2758 maxp = MAX_PACKET_DECODED(info2); 2759 2760 avg = EP_AVG_TRB_LENGTH(tx_info); 2761 2762 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2763 xhci_ep_state_string(ep_state), mult, 2764 max_pstr, lsa ? "LSA " : ""); 2765 2766 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2767 (1 << interval) * 125, esit, cerr); 2768 2769 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2770 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2771 burst, maxp, deq); 2772 2773 ret += sprintf(str + ret, "avg trb len %d", avg); 2774 2775 return str; 2776 } 2777 2778 #endif /* __LINUX_XHCI_HCD_H */ 2779