1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 #include <linux/kernel.h> 29 #include <linux/usb/hcd.h> 30 31 /* Code sharing between pci-quirks and xhci hcd */ 32 #include "xhci-ext-caps.h" 33 #include "pci-quirks.h" 34 35 /* xHCI PCI Configuration Registers */ 36 #define XHCI_SBRN_OFFSET (0x60) 37 38 /* Max number of USB devices for any host controller - limit in section 6.1 */ 39 #define MAX_HC_SLOTS 256 40 /* Section 5.3.3 - MaxPorts */ 41 #define MAX_HC_PORTS 127 42 43 /* 44 * xHCI register interface. 45 * This corresponds to the eXtensible Host Controller Interface (xHCI) 46 * Revision 0.95 specification 47 */ 48 49 /** 50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 51 * @hc_capbase: length of the capabilities register and HC version number 52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 55 * @hcc_params: HCCPARAMS - Capability Parameters 56 * @db_off: DBOFF - Doorbell array offset 57 * @run_regs_off: RTSOFF - Runtime register space offset 58 */ 59 struct xhci_cap_regs { 60 __le32 hc_capbase; 61 __le32 hcs_params1; 62 __le32 hcs_params2; 63 __le32 hcs_params3; 64 __le32 hcc_params; 65 __le32 db_off; 66 __le32 run_regs_off; 67 /* Reserved up to (CAPLENGTH - 0x1C) */ 68 }; 69 70 /* hc_capbase bitmasks */ 71 /* bits 7:0 - how long is the Capabilities register */ 72 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 73 /* bits 31:16 */ 74 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 75 76 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 77 /* bits 0:7, Max Device Slots */ 78 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 79 #define HCS_SLOTS_MASK 0xff 80 /* bits 8:18, Max Interrupters */ 81 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 83 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 84 85 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 86 /* bits 0:3, frames or uframes that SW needs to queue transactions 87 * ahead of the HW to meet periodic deadlines */ 88 #define HCS_IST(p) (((p) >> 0) & 0xf) 89 /* bits 4:7, max number of Event Ring segments */ 90 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 93 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 94 95 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 97 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 99 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 100 101 /* HCCPARAMS - hcc_params - bitmasks */ 102 /* true: HC can use 64-bit address pointers */ 103 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 104 /* true: HC can do bandwidth negotiation */ 105 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 106 /* true: HC uses 64-byte Device Context structures 107 * FIXME 64-byte context structures aren't supported yet. 108 */ 109 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 110 /* true: HC has port power switches */ 111 #define HCC_PPC(p) ((p) & (1 << 3)) 112 /* true: HC has port indicators */ 113 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 114 /* true: HC has Light HC Reset Capability */ 115 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 116 /* true: HC supports latency tolerance messaging */ 117 #define HCC_LTC(p) ((p) & (1 << 6)) 118 /* true: no secondary Stream ID Support */ 119 #define HCC_NSS(p) ((p) & (1 << 7)) 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 124 125 /* db_off bitmask - bits 0:1 reserved */ 126 #define DBOFF_MASK (~0x3) 127 128 /* run_regs_off bitmask - bits 0:4 reserved */ 129 #define RTSOFF_MASK (~0x1f) 130 131 132 /* Number of registers per port */ 133 #define NUM_PORT_REGS 4 134 135 /** 136 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 137 * @command: USBCMD - xHC command register 138 * @status: USBSTS - xHC status register 139 * @page_size: This indicates the page size that the host controller 140 * supports. If bit n is set, the HC supports a page size 141 * of 2^(n+12), up to a 128MB page size. 142 * 4K is the minimum page size. 143 * @cmd_ring: CRP - 64-bit Command Ring Pointer 144 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 145 * @config_reg: CONFIG - Configure Register 146 * @port_status_base: PORTSCn - base address for Port Status and Control 147 * Each port has a Port Status and Control register, 148 * followed by a Port Power Management Status and Control 149 * register, a Port Link Info register, and a reserved 150 * register. 151 * @port_power_base: PORTPMSCn - base address for 152 * Port Power Management Status and Control 153 * @port_link_base: PORTLIn - base address for Port Link Info (current 154 * Link PM state and control) for USB 2.1 and USB 3.0 155 * devices. 156 */ 157 struct xhci_op_regs { 158 __le32 command; 159 __le32 status; 160 __le32 page_size; 161 __le32 reserved1; 162 __le32 reserved2; 163 __le32 dev_notification; 164 __le64 cmd_ring; 165 /* rsvd: offset 0x20-2F */ 166 __le32 reserved3[4]; 167 __le64 dcbaa_ptr; 168 __le32 config_reg; 169 /* rsvd: offset 0x3C-3FF */ 170 __le32 reserved4[241]; 171 /* port 1 registers, which serve as a base address for other ports */ 172 __le32 port_status_base; 173 __le32 port_power_base; 174 __le32 port_link_base; 175 __le32 reserved5; 176 /* registers for ports 2-255 */ 177 __le32 reserved6[NUM_PORT_REGS*254]; 178 }; 179 180 /* USBCMD - USB command - command bitmasks */ 181 /* start/stop HC execution - do not write unless HC is halted*/ 182 #define CMD_RUN XHCI_CMD_RUN 183 /* Reset HC - resets internal HC state machine and all registers (except 184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 185 * The xHCI driver must reinitialize the xHC after setting this bit. 186 */ 187 #define CMD_RESET (1 << 1) 188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 189 #define CMD_EIE XHCI_CMD_EIE 190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 191 #define CMD_HSEIE XHCI_CMD_HSEIE 192 /* bits 4:6 are reserved (and should be preserved on writes). */ 193 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 194 #define CMD_LRESET (1 << 7) 195 /* host controller save/restore state. */ 196 #define CMD_CSS (1 << 8) 197 #define CMD_CRS (1 << 9) 198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 199 #define CMD_EWE XHCI_CMD_EWE 200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 202 * '0' means the xHC can power it off if all ports are in the disconnect, 203 * disabled, or powered-off state. 204 */ 205 #define CMD_PM_INDEX (1 << 11) 206 /* bits 12:31 are reserved (and should be preserved on writes). */ 207 208 /* USBSTS - USB status - status bitmasks */ 209 /* HC not running - set to 1 when run/stop bit is cleared. */ 210 #define STS_HALT XHCI_STS_HALT 211 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 212 #define STS_FATAL (1 << 2) 213 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 214 #define STS_EINT (1 << 3) 215 /* port change detect */ 216 #define STS_PORT (1 << 4) 217 /* bits 5:7 reserved and zeroed */ 218 /* save state status - '1' means xHC is saving state */ 219 #define STS_SAVE (1 << 8) 220 /* restore state status - '1' means xHC is restoring state */ 221 #define STS_RESTORE (1 << 9) 222 /* true: save or restore error */ 223 #define STS_SRE (1 << 10) 224 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 225 #define STS_CNR XHCI_STS_CNR 226 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 227 #define STS_HCE (1 << 12) 228 /* bits 13:31 reserved and should be preserved */ 229 230 /* 231 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 232 * Generate a device notification event when the HC sees a transaction with a 233 * notification type that matches a bit set in this bit field. 234 */ 235 #define DEV_NOTE_MASK (0xffff) 236 #define ENABLE_DEV_NOTE(x) (1 << (x)) 237 /* Most of the device notification types should only be used for debug. 238 * SW does need to pay attention to function wake notifications. 239 */ 240 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 241 242 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 243 /* bit 0 is the command ring cycle state */ 244 /* stop ring operation after completion of the currently executing command */ 245 #define CMD_RING_PAUSE (1 << 1) 246 /* stop ring immediately - abort the currently executing command */ 247 #define CMD_RING_ABORT (1 << 2) 248 /* true: command ring is running */ 249 #define CMD_RING_RUNNING (1 << 3) 250 /* bits 4:5 reserved and should be preserved */ 251 /* Command Ring pointer - bit mask for the lower 32 bits. */ 252 #define CMD_RING_RSVD_BITS (0x3f) 253 254 /* CONFIG - Configure Register - config_reg bitmasks */ 255 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 256 #define MAX_DEVS(p) ((p) & 0xff) 257 /* bits 8:31 - reserved and should be preserved */ 258 259 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 260 /* true: device connected */ 261 #define PORT_CONNECT (1 << 0) 262 /* true: port enabled */ 263 #define PORT_PE (1 << 1) 264 /* bit 2 reserved and zeroed */ 265 /* true: port has an over-current condition */ 266 #define PORT_OC (1 << 3) 267 /* true: port reset signaling asserted */ 268 #define PORT_RESET (1 << 4) 269 /* Port Link State - bits 5:8 270 * A read gives the current link PM state of the port, 271 * a write with Link State Write Strobe set sets the link state. 272 */ 273 #define PORT_PLS_MASK (0xf << 5) 274 #define XDEV_U0 (0x0 << 5) 275 #define XDEV_U3 (0x3 << 5) 276 #define XDEV_RESUME (0xf << 5) 277 /* true: port has power (see HCC_PPC) */ 278 #define PORT_POWER (1 << 9) 279 /* bits 10:13 indicate device speed: 280 * 0 - undefined speed - port hasn't be initialized by a reset yet 281 * 1 - full speed 282 * 2 - low speed 283 * 3 - high speed 284 * 4 - super speed 285 * 5-15 reserved 286 */ 287 #define DEV_SPEED_MASK (0xf << 10) 288 #define XDEV_FS (0x1 << 10) 289 #define XDEV_LS (0x2 << 10) 290 #define XDEV_HS (0x3 << 10) 291 #define XDEV_SS (0x4 << 10) 292 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 293 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 294 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 295 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 296 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 297 /* Bits 20:23 in the Slot Context are the speed for the device */ 298 #define SLOT_SPEED_FS (XDEV_FS << 10) 299 #define SLOT_SPEED_LS (XDEV_LS << 10) 300 #define SLOT_SPEED_HS (XDEV_HS << 10) 301 #define SLOT_SPEED_SS (XDEV_SS << 10) 302 /* Port Indicator Control */ 303 #define PORT_LED_OFF (0 << 14) 304 #define PORT_LED_AMBER (1 << 14) 305 #define PORT_LED_GREEN (2 << 14) 306 #define PORT_LED_MASK (3 << 14) 307 /* Port Link State Write Strobe - set this when changing link state */ 308 #define PORT_LINK_STROBE (1 << 16) 309 /* true: connect status change */ 310 #define PORT_CSC (1 << 17) 311 /* true: port enable change */ 312 #define PORT_PEC (1 << 18) 313 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 314 * into an enabled state, and the device into the default state. A "warm" reset 315 * also resets the link, forcing the device through the link training sequence. 316 * SW can also look at the Port Reset register to see when warm reset is done. 317 */ 318 #define PORT_WRC (1 << 19) 319 /* true: over-current change */ 320 #define PORT_OCC (1 << 20) 321 /* true: reset change - 1 to 0 transition of PORT_RESET */ 322 #define PORT_RC (1 << 21) 323 /* port link status change - set on some port link state transitions: 324 * Transition Reason 325 * ------------------------------------------------------------------------------ 326 * - U3 to Resume Wakeup signaling from a device 327 * - Resume to Recovery to U0 USB 3.0 device resume 328 * - Resume to U0 USB 2.0 device resume 329 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 330 * - U3 to U0 Software resume of USB 2.0 device complete 331 * - U2 to U0 L1 resume of USB 2.1 device complete 332 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 333 * - U0 to disabled L1 entry error with USB 2.1 device 334 * - Any state to inactive Error on USB 3.0 port 335 */ 336 #define PORT_PLC (1 << 22) 337 /* port configure error change - port failed to configure its link partner */ 338 #define PORT_CEC (1 << 23) 339 /* bit 24 reserved */ 340 /* wake on connect (enable) */ 341 #define PORT_WKCONN_E (1 << 25) 342 /* wake on disconnect (enable) */ 343 #define PORT_WKDISC_E (1 << 26) 344 /* wake on over-current (enable) */ 345 #define PORT_WKOC_E (1 << 27) 346 /* bits 28:29 reserved */ 347 /* true: device is removable - for USB 3.0 roothub emulation */ 348 #define PORT_DEV_REMOVE (1 << 30) 349 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 350 #define PORT_WR (1 << 31) 351 352 /* We mark duplicate entries with -1 */ 353 #define DUPLICATE_ENTRY ((u8)(-1)) 354 355 /* Port Power Management Status and Control - port_power_base bitmasks */ 356 /* Inactivity timer value for transitions into U1, in microseconds. 357 * Timeout can be up to 127us. 0xFF means an infinite timeout. 358 */ 359 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 360 /* Inactivity timer value for transitions into U2 */ 361 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 362 /* Bits 24:31 for port testing */ 363 364 /* USB2 Protocol PORTSPMSC */ 365 #define PORT_RWE (1 << 0x3) 366 367 /** 368 * struct xhci_intr_reg - Interrupt Register Set 369 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 370 * interrupts and check for pending interrupts. 371 * @irq_control: IMOD - Interrupt Moderation Register. 372 * Used to throttle interrupts. 373 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 374 * @erst_base: ERST base address. 375 * @erst_dequeue: Event ring dequeue pointer. 376 * 377 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 378 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 379 * multiple segments of the same size. The HC places events on the ring and 380 * "updates the Cycle bit in the TRBs to indicate to software the current 381 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 382 * updates the dequeue pointer. 383 */ 384 struct xhci_intr_reg { 385 __le32 irq_pending; 386 __le32 irq_control; 387 __le32 erst_size; 388 __le32 rsvd; 389 __le64 erst_base; 390 __le64 erst_dequeue; 391 }; 392 393 /* irq_pending bitmasks */ 394 #define ER_IRQ_PENDING(p) ((p) & 0x1) 395 /* bits 2:31 need to be preserved */ 396 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 397 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 398 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 399 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 400 401 /* irq_control bitmasks */ 402 /* Minimum interval between interrupts (in 250ns intervals). The interval 403 * between interrupts will be longer if there are no events on the event ring. 404 * Default is 4000 (1 ms). 405 */ 406 #define ER_IRQ_INTERVAL_MASK (0xffff) 407 /* Counter used to count down the time to the next interrupt - HW use only */ 408 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 409 410 /* erst_size bitmasks */ 411 /* Preserve bits 16:31 of erst_size */ 412 #define ERST_SIZE_MASK (0xffff << 16) 413 414 /* erst_dequeue bitmasks */ 415 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 416 * where the current dequeue pointer lies. This is an optional HW hint. 417 */ 418 #define ERST_DESI_MASK (0x7) 419 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 420 * a work queue (or delayed service routine)? 421 */ 422 #define ERST_EHB (1 << 3) 423 #define ERST_PTR_MASK (0xf) 424 425 /** 426 * struct xhci_run_regs 427 * @microframe_index: 428 * MFINDEX - current microframe number 429 * 430 * Section 5.5 Host Controller Runtime Registers: 431 * "Software should read and write these registers using only Dword (32 bit) 432 * or larger accesses" 433 */ 434 struct xhci_run_regs { 435 __le32 microframe_index; 436 __le32 rsvd[7]; 437 struct xhci_intr_reg ir_set[128]; 438 }; 439 440 /** 441 * struct doorbell_array 442 * 443 * Bits 0 - 7: Endpoint target 444 * Bits 8 - 15: RsvdZ 445 * Bits 16 - 31: Stream ID 446 * 447 * Section 5.6 448 */ 449 struct xhci_doorbell_array { 450 __le32 doorbell[256]; 451 }; 452 453 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 454 #define DB_VALUE_HOST 0x00000000 455 456 /** 457 * struct xhci_protocol_caps 458 * @revision: major revision, minor revision, capability ID, 459 * and next capability pointer. 460 * @name_string: Four ASCII characters to say which spec this xHC 461 * follows, typically "USB ". 462 * @port_info: Port offset, count, and protocol-defined information. 463 */ 464 struct xhci_protocol_caps { 465 u32 revision; 466 u32 name_string; 467 u32 port_info; 468 }; 469 470 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 471 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 472 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 473 474 /** 475 * struct xhci_container_ctx 476 * @type: Type of context. Used to calculated offsets to contained contexts. 477 * @size: Size of the context data 478 * @bytes: The raw context data given to HW 479 * @dma: dma address of the bytes 480 * 481 * Represents either a Device or Input context. Holds a pointer to the raw 482 * memory used for the context (bytes) and dma address of it (dma). 483 */ 484 struct xhci_container_ctx { 485 unsigned type; 486 #define XHCI_CTX_TYPE_DEVICE 0x1 487 #define XHCI_CTX_TYPE_INPUT 0x2 488 489 int size; 490 491 u8 *bytes; 492 dma_addr_t dma; 493 }; 494 495 /** 496 * struct xhci_slot_ctx 497 * @dev_info: Route string, device speed, hub info, and last valid endpoint 498 * @dev_info2: Max exit latency for device number, root hub port number 499 * @tt_info: tt_info is used to construct split transaction tokens 500 * @dev_state: slot state and device address 501 * 502 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 503 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 504 * reserved at the end of the slot context for HC internal use. 505 */ 506 struct xhci_slot_ctx { 507 __le32 dev_info; 508 __le32 dev_info2; 509 __le32 tt_info; 510 __le32 dev_state; 511 /* offset 0x10 to 0x1f reserved for HC internal use */ 512 __le32 reserved[4]; 513 }; 514 515 /* dev_info bitmasks */ 516 /* Route String - 0:19 */ 517 #define ROUTE_STRING_MASK (0xfffff) 518 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 519 #define DEV_SPEED (0xf << 20) 520 /* bit 24 reserved */ 521 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 522 #define DEV_MTT (0x1 << 25) 523 /* Set if the device is a hub - bit 26 */ 524 #define DEV_HUB (0x1 << 26) 525 /* Index of the last valid endpoint context in this device context - 27:31 */ 526 #define LAST_CTX_MASK (0x1f << 27) 527 #define LAST_CTX(p) ((p) << 27) 528 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 529 #define SLOT_FLAG (1 << 0) 530 #define EP0_FLAG (1 << 1) 531 532 /* dev_info2 bitmasks */ 533 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 534 #define MAX_EXIT (0xffff) 535 /* Root hub port number that is needed to access the USB device */ 536 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 537 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 538 /* Maximum number of ports under a hub device */ 539 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 540 541 /* tt_info bitmasks */ 542 /* 543 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 544 * The Slot ID of the hub that isolates the high speed signaling from 545 * this low or full-speed device. '0' if attached to root hub port. 546 */ 547 #define TT_SLOT (0xff) 548 /* 549 * The number of the downstream facing port of the high-speed hub 550 * '0' if the device is not low or full speed. 551 */ 552 #define TT_PORT (0xff << 8) 553 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 554 555 /* dev_state bitmasks */ 556 /* USB device address - assigned by the HC */ 557 #define DEV_ADDR_MASK (0xff) 558 /* bits 8:26 reserved */ 559 /* Slot state */ 560 #define SLOT_STATE (0x1f << 27) 561 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 562 563 #define SLOT_STATE_DISABLED 0 564 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 565 #define SLOT_STATE_DEFAULT 1 566 #define SLOT_STATE_ADDRESSED 2 567 #define SLOT_STATE_CONFIGURED 3 568 569 /** 570 * struct xhci_ep_ctx 571 * @ep_info: endpoint state, streams, mult, and interval information. 572 * @ep_info2: information on endpoint type, max packet size, max burst size, 573 * error count, and whether the HC will force an event for all 574 * transactions. 575 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 576 * defines one stream, this points to the endpoint transfer ring. 577 * Otherwise, it points to a stream context array, which has a 578 * ring pointer for each flow. 579 * @tx_info: 580 * Average TRB lengths for the endpoint ring and 581 * max payload within an Endpoint Service Interval Time (ESIT). 582 * 583 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 584 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 585 * reserved at the end of the endpoint context for HC internal use. 586 */ 587 struct xhci_ep_ctx { 588 __le32 ep_info; 589 __le32 ep_info2; 590 __le64 deq; 591 __le32 tx_info; 592 /* offset 0x14 - 0x1f reserved for HC internal use */ 593 __le32 reserved[3]; 594 }; 595 596 /* ep_info bitmasks */ 597 /* 598 * Endpoint State - bits 0:2 599 * 0 - disabled 600 * 1 - running 601 * 2 - halted due to halt condition - ok to manipulate endpoint ring 602 * 3 - stopped 603 * 4 - TRB error 604 * 5-7 - reserved 605 */ 606 #define EP_STATE_MASK (0xf) 607 #define EP_STATE_DISABLED 0 608 #define EP_STATE_RUNNING 1 609 #define EP_STATE_HALTED 2 610 #define EP_STATE_STOPPED 3 611 #define EP_STATE_ERROR 4 612 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 613 #define EP_MULT(p) (((p) & 0x3) << 8) 614 /* bits 10:14 are Max Primary Streams */ 615 /* bit 15 is Linear Stream Array */ 616 /* Interval - period between requests to an endpoint - 125u increments. */ 617 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 618 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 619 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 620 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 621 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 622 #define EP_HAS_LSA (1 << 15) 623 624 /* ep_info2 bitmasks */ 625 /* 626 * Force Event - generate transfer events for all TRBs for this endpoint 627 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 628 */ 629 #define FORCE_EVENT (0x1) 630 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 631 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 632 #define EP_TYPE(p) ((p) << 3) 633 #define ISOC_OUT_EP 1 634 #define BULK_OUT_EP 2 635 #define INT_OUT_EP 3 636 #define CTRL_EP 4 637 #define ISOC_IN_EP 5 638 #define BULK_IN_EP 6 639 #define INT_IN_EP 7 640 /* bit 6 reserved */ 641 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 642 #define MAX_BURST(p) (((p)&0xff) << 8) 643 #define MAX_PACKET(p) (((p)&0xffff) << 16) 644 #define MAX_PACKET_MASK (0xffff << 16) 645 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 646 647 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 648 * USB2.0 spec 9.6.6. 649 */ 650 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 651 652 /* tx_info bitmasks */ 653 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 654 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 655 656 /* deq bitmasks */ 657 #define EP_CTX_CYCLE_MASK (1 << 0) 658 659 660 /** 661 * struct xhci_input_control_context 662 * Input control context; see section 6.2.5. 663 * 664 * @drop_context: set the bit of the endpoint context you want to disable 665 * @add_context: set the bit of the endpoint context you want to enable 666 */ 667 struct xhci_input_control_ctx { 668 __le32 drop_flags; 669 __le32 add_flags; 670 __le32 rsvd2[6]; 671 }; 672 673 /* Represents everything that is needed to issue a command on the command ring. 674 * It's useful to pre-allocate these for commands that cannot fail due to 675 * out-of-memory errors, like freeing streams. 676 */ 677 struct xhci_command { 678 /* Input context for changing device state */ 679 struct xhci_container_ctx *in_ctx; 680 u32 status; 681 /* If completion is null, no one is waiting on this command 682 * and the structure can be freed after the command completes. 683 */ 684 struct completion *completion; 685 union xhci_trb *command_trb; 686 struct list_head cmd_list; 687 }; 688 689 /* drop context bitmasks */ 690 #define DROP_EP(x) (0x1 << x) 691 /* add context bitmasks */ 692 #define ADD_EP(x) (0x1 << x) 693 694 struct xhci_stream_ctx { 695 /* 64-bit stream ring address, cycle state, and stream type */ 696 __le64 stream_ring; 697 /* offset 0x14 - 0x1f reserved for HC internal use */ 698 __le32 reserved[2]; 699 }; 700 701 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 702 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7) 703 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 704 #define SCT_SEC_TR 0 705 /* Primary stream array type, dequeue pointer is to a transfer ring */ 706 #define SCT_PRI_TR 1 707 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 708 #define SCT_SSA_8 2 709 #define SCT_SSA_16 3 710 #define SCT_SSA_32 4 711 #define SCT_SSA_64 5 712 #define SCT_SSA_128 6 713 #define SCT_SSA_256 7 714 715 /* Assume no secondary streams for now */ 716 struct xhci_stream_info { 717 struct xhci_ring **stream_rings; 718 /* Number of streams, including stream 0 (which drivers can't use) */ 719 unsigned int num_streams; 720 /* The stream context array may be bigger than 721 * the number of streams the driver asked for 722 */ 723 struct xhci_stream_ctx *stream_ctx_array; 724 unsigned int num_stream_ctxs; 725 dma_addr_t ctx_array_dma; 726 /* For mapping physical TRB addresses to segments in stream rings */ 727 struct radix_tree_root trb_address_map; 728 struct xhci_command *free_streams_command; 729 }; 730 731 #define SMALL_STREAM_ARRAY_SIZE 256 732 #define MEDIUM_STREAM_ARRAY_SIZE 1024 733 734 struct xhci_virt_ep { 735 struct xhci_ring *ring; 736 /* Related to endpoints that are configured to use stream IDs only */ 737 struct xhci_stream_info *stream_info; 738 /* Temporary storage in case the configure endpoint command fails and we 739 * have to restore the device state to the previous state 740 */ 741 struct xhci_ring *new_ring; 742 unsigned int ep_state; 743 #define SET_DEQ_PENDING (1 << 0) 744 #define EP_HALTED (1 << 1) /* For stall handling */ 745 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 746 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 747 #define EP_GETTING_STREAMS (1 << 3) 748 #define EP_HAS_STREAMS (1 << 4) 749 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 750 #define EP_GETTING_NO_STREAMS (1 << 5) 751 /* ---- Related to URB cancellation ---- */ 752 struct list_head cancelled_td_list; 753 /* The TRB that was last reported in a stopped endpoint ring */ 754 union xhci_trb *stopped_trb; 755 struct xhci_td *stopped_td; 756 unsigned int stopped_stream; 757 /* Watchdog timer for stop endpoint command to cancel URBs */ 758 struct timer_list stop_cmd_timer; 759 int stop_cmds_pending; 760 struct xhci_hcd *xhci; 761 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 762 * command. We'll need to update the ring's dequeue segment and dequeue 763 * pointer after the command completes. 764 */ 765 struct xhci_segment *queued_deq_seg; 766 union xhci_trb *queued_deq_ptr; 767 /* 768 * Sometimes the xHC can not process isochronous endpoint ring quickly 769 * enough, and it will miss some isoc tds on the ring and generate 770 * a Missed Service Error Event. 771 * Set skip flag when receive a Missed Service Error Event and 772 * process the missed tds on the endpoint ring. 773 */ 774 bool skip; 775 }; 776 777 struct xhci_virt_device { 778 struct usb_device *udev; 779 /* 780 * Commands to the hardware are passed an "input context" that 781 * tells the hardware what to change in its data structures. 782 * The hardware will return changes in an "output context" that 783 * software must allocate for the hardware. We need to keep 784 * track of input and output contexts separately because 785 * these commands might fail and we don't trust the hardware. 786 */ 787 struct xhci_container_ctx *out_ctx; 788 /* Used for addressing devices and configuration changes */ 789 struct xhci_container_ctx *in_ctx; 790 /* Rings saved to ensure old alt settings can be re-instated */ 791 struct xhci_ring **ring_cache; 792 int num_rings_cached; 793 /* Store xHC assigned device address */ 794 int address; 795 #define XHCI_MAX_RINGS_CACHED 31 796 struct xhci_virt_ep eps[31]; 797 struct completion cmd_completion; 798 /* Status of the last command issued for this device */ 799 u32 cmd_status; 800 struct list_head cmd_list; 801 u8 port; 802 }; 803 804 805 /** 806 * struct xhci_device_context_array 807 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 808 */ 809 struct xhci_device_context_array { 810 /* 64-bit device addresses; we only write 32-bit addresses */ 811 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 812 /* private xHCD pointers */ 813 dma_addr_t dma; 814 }; 815 /* TODO: write function to set the 64-bit device DMA address */ 816 /* 817 * TODO: change this to be dynamically sized at HC mem init time since the HC 818 * might not be able to handle the maximum number of devices possible. 819 */ 820 821 822 struct xhci_transfer_event { 823 /* 64-bit buffer address, or immediate data */ 824 __le64 buffer; 825 __le32 transfer_len; 826 /* This field is interpreted differently based on the type of TRB */ 827 __le32 flags; 828 }; 829 830 /** Transfer Event bit fields **/ 831 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 832 833 /* Completion Code - only applicable for some types of TRBs */ 834 #define COMP_CODE_MASK (0xff << 24) 835 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 836 #define COMP_SUCCESS 1 837 /* Data Buffer Error */ 838 #define COMP_DB_ERR 2 839 /* Babble Detected Error */ 840 #define COMP_BABBLE 3 841 /* USB Transaction Error */ 842 #define COMP_TX_ERR 4 843 /* TRB Error - some TRB field is invalid */ 844 #define COMP_TRB_ERR 5 845 /* Stall Error - USB device is stalled */ 846 #define COMP_STALL 6 847 /* Resource Error - HC doesn't have memory for that device configuration */ 848 #define COMP_ENOMEM 7 849 /* Bandwidth Error - not enough room in schedule for this dev config */ 850 #define COMP_BW_ERR 8 851 /* No Slots Available Error - HC ran out of device slots */ 852 #define COMP_ENOSLOTS 9 853 /* Invalid Stream Type Error */ 854 #define COMP_STREAM_ERR 10 855 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 856 #define COMP_EBADSLT 11 857 /* Endpoint Not Enabled Error */ 858 #define COMP_EBADEP 12 859 /* Short Packet */ 860 #define COMP_SHORT_TX 13 861 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 862 #define COMP_UNDERRUN 14 863 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 864 #define COMP_OVERRUN 15 865 /* Virtual Function Event Ring Full Error */ 866 #define COMP_VF_FULL 16 867 /* Parameter Error - Context parameter is invalid */ 868 #define COMP_EINVAL 17 869 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 870 #define COMP_BW_OVER 18 871 /* Context State Error - illegal context state transition requested */ 872 #define COMP_CTX_STATE 19 873 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 874 #define COMP_PING_ERR 20 875 /* Event Ring is full */ 876 #define COMP_ER_FULL 21 877 /* Incompatible Device Error */ 878 #define COMP_DEV_ERR 22 879 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 880 #define COMP_MISSED_INT 23 881 /* Successfully stopped command ring */ 882 #define COMP_CMD_STOP 24 883 /* Successfully aborted current command and stopped command ring */ 884 #define COMP_CMD_ABORT 25 885 /* Stopped - transfer was terminated by a stop endpoint command */ 886 #define COMP_STOP 26 887 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 888 #define COMP_STOP_INVAL 27 889 /* Control Abort Error - Debug Capability - control pipe aborted */ 890 #define COMP_DBG_ABORT 28 891 /* Max Exit Latency Too Large Error */ 892 #define COMP_MEL_ERR 29 893 /* TRB type 30 reserved */ 894 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 895 #define COMP_BUFF_OVER 31 896 /* Event Lost Error - xHC has an "internal event overrun condition" */ 897 #define COMP_ISSUES 32 898 /* Undefined Error - reported when other error codes don't apply */ 899 #define COMP_UNKNOWN 33 900 /* Invalid Stream ID Error */ 901 #define COMP_STRID_ERR 34 902 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 903 /* FIXME - check for this */ 904 #define COMP_2ND_BW_ERR 35 905 /* Split Transaction Error */ 906 #define COMP_SPLIT_ERR 36 907 908 struct xhci_link_trb { 909 /* 64-bit segment pointer*/ 910 __le64 segment_ptr; 911 __le32 intr_target; 912 __le32 control; 913 }; 914 915 /* control bitfields */ 916 #define LINK_TOGGLE (0x1<<1) 917 918 /* Command completion event TRB */ 919 struct xhci_event_cmd { 920 /* Pointer to command TRB, or the value passed by the event data trb */ 921 __le64 cmd_trb; 922 __le32 status; 923 __le32 flags; 924 }; 925 926 /* flags bitmasks */ 927 /* bits 16:23 are the virtual function ID */ 928 /* bits 24:31 are the slot ID */ 929 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 930 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 931 932 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 933 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 934 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 935 936 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 937 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 938 #define LAST_EP_INDEX 30 939 940 /* Set TR Dequeue Pointer command TRB fields */ 941 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 942 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 943 944 945 /* Port Status Change Event TRB fields */ 946 /* Port ID - bits 31:24 */ 947 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 948 949 /* Normal TRB fields */ 950 /* transfer_len bitmasks - bits 0:16 */ 951 #define TRB_LEN(p) ((p) & 0x1ffff) 952 /* Interrupter Target - which MSI-X vector to target the completion event at */ 953 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 954 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 955 #define TRB_TBC(p) (((p) & 0x3) << 7) 956 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 957 958 /* Cycle bit - indicates TRB ownership by HC or HCD */ 959 #define TRB_CYCLE (1<<0) 960 /* 961 * Force next event data TRB to be evaluated before task switch. 962 * Used to pass OS data back after a TD completes. 963 */ 964 #define TRB_ENT (1<<1) 965 /* Interrupt on short packet */ 966 #define TRB_ISP (1<<2) 967 /* Set PCIe no snoop attribute */ 968 #define TRB_NO_SNOOP (1<<3) 969 /* Chain multiple TRBs into a TD */ 970 #define TRB_CHAIN (1<<4) 971 /* Interrupt on completion */ 972 #define TRB_IOC (1<<5) 973 /* The buffer pointer contains immediate data */ 974 #define TRB_IDT (1<<6) 975 976 /* Block Event Interrupt */ 977 #define TRB_BEI (1<<9) 978 979 /* Control transfer TRB specific fields */ 980 #define TRB_DIR_IN (1<<16) 981 #define TRB_TX_TYPE(p) ((p) << 16) 982 #define TRB_DATA_OUT 2 983 #define TRB_DATA_IN 3 984 985 /* Isochronous TRB specific fields */ 986 #define TRB_SIA (1<<31) 987 988 struct xhci_generic_trb { 989 __le32 field[4]; 990 }; 991 992 union xhci_trb { 993 struct xhci_link_trb link; 994 struct xhci_transfer_event trans_event; 995 struct xhci_event_cmd event_cmd; 996 struct xhci_generic_trb generic; 997 }; 998 999 /* TRB bit mask */ 1000 #define TRB_TYPE_BITMASK (0xfc00) 1001 #define TRB_TYPE(p) ((p) << 10) 1002 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1003 /* TRB type IDs */ 1004 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1005 #define TRB_NORMAL 1 1006 /* setup stage for control transfers */ 1007 #define TRB_SETUP 2 1008 /* data stage for control transfers */ 1009 #define TRB_DATA 3 1010 /* status stage for control transfers */ 1011 #define TRB_STATUS 4 1012 /* isoc transfers */ 1013 #define TRB_ISOC 5 1014 /* TRB for linking ring segments */ 1015 #define TRB_LINK 6 1016 #define TRB_EVENT_DATA 7 1017 /* Transfer Ring No-op (not for the command ring) */ 1018 #define TRB_TR_NOOP 8 1019 /* Command TRBs */ 1020 /* Enable Slot Command */ 1021 #define TRB_ENABLE_SLOT 9 1022 /* Disable Slot Command */ 1023 #define TRB_DISABLE_SLOT 10 1024 /* Address Device Command */ 1025 #define TRB_ADDR_DEV 11 1026 /* Configure Endpoint Command */ 1027 #define TRB_CONFIG_EP 12 1028 /* Evaluate Context Command */ 1029 #define TRB_EVAL_CONTEXT 13 1030 /* Reset Endpoint Command */ 1031 #define TRB_RESET_EP 14 1032 /* Stop Transfer Ring Command */ 1033 #define TRB_STOP_RING 15 1034 /* Set Transfer Ring Dequeue Pointer Command */ 1035 #define TRB_SET_DEQ 16 1036 /* Reset Device Command */ 1037 #define TRB_RESET_DEV 17 1038 /* Force Event Command (opt) */ 1039 #define TRB_FORCE_EVENT 18 1040 /* Negotiate Bandwidth Command (opt) */ 1041 #define TRB_NEG_BANDWIDTH 19 1042 /* Set Latency Tolerance Value Command (opt) */ 1043 #define TRB_SET_LT 20 1044 /* Get port bandwidth Command */ 1045 #define TRB_GET_BW 21 1046 /* Force Header Command - generate a transaction or link management packet */ 1047 #define TRB_FORCE_HEADER 22 1048 /* No-op Command - not for transfer rings */ 1049 #define TRB_CMD_NOOP 23 1050 /* TRB IDs 24-31 reserved */ 1051 /* Event TRBS */ 1052 /* Transfer Event */ 1053 #define TRB_TRANSFER 32 1054 /* Command Completion Event */ 1055 #define TRB_COMPLETION 33 1056 /* Port Status Change Event */ 1057 #define TRB_PORT_STATUS 34 1058 /* Bandwidth Request Event (opt) */ 1059 #define TRB_BANDWIDTH_EVENT 35 1060 /* Doorbell Event (opt) */ 1061 #define TRB_DOORBELL 36 1062 /* Host Controller Event */ 1063 #define TRB_HC_EVENT 37 1064 /* Device Notification Event - device sent function wake notification */ 1065 #define TRB_DEV_NOTE 38 1066 /* MFINDEX Wrap Event - microframe counter wrapped */ 1067 #define TRB_MFINDEX_WRAP 39 1068 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1069 1070 /* Nec vendor-specific command completion event. */ 1071 #define TRB_NEC_CMD_COMP 48 1072 /* Get NEC firmware revision. */ 1073 #define TRB_NEC_GET_FW 49 1074 1075 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1076 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1077 1078 /* 1079 * TRBS_PER_SEGMENT must be a multiple of 4, 1080 * since the command ring is 64-byte aligned. 1081 * It must also be greater than 16. 1082 */ 1083 #define TRBS_PER_SEGMENT 64 1084 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1085 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1086 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1087 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 1088 * Change this if you change TRBS_PER_SEGMENT! 1089 */ 1090 #define SEGMENT_SHIFT 10 1091 /* TRB buffer pointers can't cross 64KB boundaries */ 1092 #define TRB_MAX_BUFF_SHIFT 16 1093 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1094 1095 struct xhci_segment { 1096 union xhci_trb *trbs; 1097 /* private to HCD */ 1098 struct xhci_segment *next; 1099 dma_addr_t dma; 1100 }; 1101 1102 struct xhci_td { 1103 struct list_head td_list; 1104 struct list_head cancelled_td_list; 1105 struct urb *urb; 1106 struct xhci_segment *start_seg; 1107 union xhci_trb *first_trb; 1108 union xhci_trb *last_trb; 1109 }; 1110 1111 struct xhci_dequeue_state { 1112 struct xhci_segment *new_deq_seg; 1113 union xhci_trb *new_deq_ptr; 1114 int new_cycle_state; 1115 }; 1116 1117 struct xhci_ring { 1118 struct xhci_segment *first_seg; 1119 union xhci_trb *enqueue; 1120 struct xhci_segment *enq_seg; 1121 unsigned int enq_updates; 1122 union xhci_trb *dequeue; 1123 struct xhci_segment *deq_seg; 1124 unsigned int deq_updates; 1125 struct list_head td_list; 1126 /* 1127 * Write the cycle state into the TRB cycle field to give ownership of 1128 * the TRB to the host controller (if we are the producer), or to check 1129 * if we own the TRB (if we are the consumer). See section 4.9.1. 1130 */ 1131 u32 cycle_state; 1132 unsigned int stream_id; 1133 bool last_td_was_short; 1134 }; 1135 1136 struct xhci_erst_entry { 1137 /* 64-bit event ring segment address */ 1138 __le64 seg_addr; 1139 __le32 seg_size; 1140 /* Set to zero */ 1141 __le32 rsvd; 1142 }; 1143 1144 struct xhci_erst { 1145 struct xhci_erst_entry *entries; 1146 unsigned int num_entries; 1147 /* xhci->event_ring keeps track of segment dma addresses */ 1148 dma_addr_t erst_dma_addr; 1149 /* Num entries the ERST can contain */ 1150 unsigned int erst_size; 1151 }; 1152 1153 struct xhci_scratchpad { 1154 u64 *sp_array; 1155 dma_addr_t sp_dma; 1156 void **sp_buffers; 1157 dma_addr_t *sp_dma_buffers; 1158 }; 1159 1160 struct urb_priv { 1161 int length; 1162 int td_cnt; 1163 struct xhci_td *td[0]; 1164 }; 1165 1166 /* 1167 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1168 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1169 * meaning 64 ring segments. 1170 * Initial allocated size of the ERST, in number of entries */ 1171 #define ERST_NUM_SEGS 1 1172 /* Initial allocated size of the ERST, in number of entries */ 1173 #define ERST_SIZE 64 1174 /* Initial number of event segment rings allocated */ 1175 #define ERST_ENTRIES 1 1176 /* Poll every 60 seconds */ 1177 #define POLL_TIMEOUT 60 1178 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1179 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1180 /* XXX: Make these module parameters */ 1181 1182 struct s3_save { 1183 u32 command; 1184 u32 dev_nt; 1185 u64 dcbaa_ptr; 1186 u32 config_reg; 1187 u32 irq_pending; 1188 u32 irq_control; 1189 u32 erst_size; 1190 u64 erst_base; 1191 u64 erst_dequeue; 1192 }; 1193 1194 struct xhci_bus_state { 1195 unsigned long bus_suspended; 1196 unsigned long next_statechange; 1197 1198 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1199 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1200 u32 port_c_suspend; 1201 u32 suspended_ports; 1202 unsigned long resume_done[USB_MAXCHILDREN]; 1203 }; 1204 1205 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1206 { 1207 if (hcd->speed == HCD_USB3) 1208 return 0; 1209 else 1210 return 1; 1211 } 1212 1213 /* There is one ehci_hci structure per controller */ 1214 struct xhci_hcd { 1215 struct usb_hcd *main_hcd; 1216 struct usb_hcd *shared_hcd; 1217 /* glue to PCI and HCD framework */ 1218 struct xhci_cap_regs __iomem *cap_regs; 1219 struct xhci_op_regs __iomem *op_regs; 1220 struct xhci_run_regs __iomem *run_regs; 1221 struct xhci_doorbell_array __iomem *dba; 1222 /* Our HCD's current interrupter register set */ 1223 struct xhci_intr_reg __iomem *ir_set; 1224 1225 /* Cached register copies of read-only HC data */ 1226 __u32 hcs_params1; 1227 __u32 hcs_params2; 1228 __u32 hcs_params3; 1229 __u32 hcc_params; 1230 1231 spinlock_t lock; 1232 1233 /* packed release number */ 1234 u8 sbrn; 1235 u16 hci_version; 1236 u8 max_slots; 1237 u8 max_interrupters; 1238 u8 max_ports; 1239 u8 isoc_threshold; 1240 int event_ring_max; 1241 int addr_64; 1242 /* 4KB min, 128MB max */ 1243 int page_size; 1244 /* Valid values are 12 to 20, inclusive */ 1245 int page_shift; 1246 /* msi-x vectors */ 1247 int msix_count; 1248 struct msix_entry *msix_entries; 1249 /* data structures */ 1250 struct xhci_device_context_array *dcbaa; 1251 struct xhci_ring *cmd_ring; 1252 unsigned int cmd_ring_reserved_trbs; 1253 struct xhci_ring *event_ring; 1254 struct xhci_erst erst; 1255 /* Scratchpad */ 1256 struct xhci_scratchpad *scratchpad; 1257 1258 /* slot enabling and address device helpers */ 1259 struct completion addr_dev; 1260 int slot_id; 1261 /* Internal mirror of the HW's dcbaa */ 1262 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1263 1264 /* DMA pools */ 1265 struct dma_pool *device_pool; 1266 struct dma_pool *segment_pool; 1267 struct dma_pool *small_streams_pool; 1268 struct dma_pool *medium_streams_pool; 1269 1270 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1271 /* Poll the rings - for debugging */ 1272 struct timer_list event_ring_timer; 1273 int zombie; 1274 #endif 1275 /* Host controller watchdog timer structures */ 1276 unsigned int xhc_state; 1277 1278 u32 command; 1279 struct s3_save s3; 1280 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1281 * 1282 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1283 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1284 * that sees this status (other than the timer that set it) should stop touching 1285 * hardware immediately. Interrupt handlers should return immediately when 1286 * they see this status (any time they drop and re-acquire xhci->lock). 1287 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1288 * putting the TD on the canceled list, etc. 1289 * 1290 * There are no reports of xHCI host controllers that display this issue. 1291 */ 1292 #define XHCI_STATE_DYING (1 << 0) 1293 #define XHCI_STATE_HALTED (1 << 1) 1294 /* Statistics */ 1295 int error_bitmask; 1296 unsigned int quirks; 1297 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1298 #define XHCI_RESET_EP_QUIRK (1 << 1) 1299 #define XHCI_NEC_HOST (1 << 2) 1300 #define XHCI_AMD_PLL_FIX (1 << 3) 1301 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1302 /* 1303 * Certain Intel host controllers have a limit to the number of endpoint 1304 * contexts they can handle. Ideally, they would signal that they can't handle 1305 * anymore endpoint contexts by returning a Resource Error for the Configure 1306 * Endpoint command, but they don't. Instead they expect software to keep track 1307 * of the number of active endpoints for them, across configure endpoint 1308 * commands, reset device commands, disable slot commands, and address device 1309 * commands. 1310 */ 1311 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1312 #define XHCI_BROKEN_MSI (1 << 6) 1313 #define XHCI_RESET_ON_RESUME (1 << 7) 1314 unsigned int num_active_eps; 1315 unsigned int limit_active_eps; 1316 /* There are two roothubs to keep track of bus suspend info for */ 1317 struct xhci_bus_state bus_state[2]; 1318 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1319 u8 *port_array; 1320 /* Array of pointers to USB 3.0 PORTSC registers */ 1321 __le32 __iomem **usb3_ports; 1322 unsigned int num_usb3_ports; 1323 /* Array of pointers to USB 2.0 PORTSC registers */ 1324 __le32 __iomem **usb2_ports; 1325 unsigned int num_usb2_ports; 1326 }; 1327 1328 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1329 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1330 { 1331 return *((struct xhci_hcd **) (hcd->hcd_priv)); 1332 } 1333 1334 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1335 { 1336 return xhci->main_hcd; 1337 } 1338 1339 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1340 #define XHCI_DEBUG 1 1341 #else 1342 #define XHCI_DEBUG 0 1343 #endif 1344 1345 #define xhci_dbg(xhci, fmt, args...) \ 1346 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1347 #define xhci_info(xhci, fmt, args...) \ 1348 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) 1349 #define xhci_err(xhci, fmt, args...) \ 1350 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1351 #define xhci_warn(xhci, fmt, args...) \ 1352 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1353 1354 /* TODO: copied from ehci.h - can be refactored? */ 1355 /* xHCI spec says all registers are little endian */ 1356 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, 1357 __le32 __iomem *regs) 1358 { 1359 return readl(regs); 1360 } 1361 static inline void xhci_writel(struct xhci_hcd *xhci, 1362 const unsigned int val, __le32 __iomem *regs) 1363 { 1364 writel(val, regs); 1365 } 1366 1367 /* 1368 * Registers should always be accessed with double word or quad word accesses. 1369 * 1370 * Some xHCI implementations may support 64-bit address pointers. Registers 1371 * with 64-bit address pointers should be written to with dword accesses by 1372 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1373 * xHCI implementations that do not support 64-bit address pointers will ignore 1374 * the high dword, and write order is irrelevant. 1375 */ 1376 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1377 __le64 __iomem *regs) 1378 { 1379 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1380 u64 val_lo = readl(ptr); 1381 u64 val_hi = readl(ptr + 1); 1382 return val_lo + (val_hi << 32); 1383 } 1384 static inline void xhci_write_64(struct xhci_hcd *xhci, 1385 const u64 val, __le64 __iomem *regs) 1386 { 1387 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1388 u32 val_lo = lower_32_bits(val); 1389 u32 val_hi = upper_32_bits(val); 1390 1391 writel(val_lo, ptr); 1392 writel(val_hi, ptr + 1); 1393 } 1394 1395 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1396 { 1397 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); 1398 return ((HC_VERSION(temp) == 0x95) && 1399 (xhci->quirks & XHCI_LINK_TRB_QUIRK)); 1400 } 1401 1402 /* xHCI debugging */ 1403 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1404 void xhci_print_registers(struct xhci_hcd *xhci); 1405 void xhci_dbg_regs(struct xhci_hcd *xhci); 1406 void xhci_print_run_regs(struct xhci_hcd *xhci); 1407 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1408 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1409 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1410 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1411 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1412 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1413 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1414 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1415 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1416 struct xhci_container_ctx *ctx); 1417 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1418 unsigned int slot_id, unsigned int ep_index, 1419 struct xhci_virt_ep *ep); 1420 1421 /* xHCI memory management */ 1422 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1423 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1424 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1425 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1426 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1427 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1428 struct usb_device *udev); 1429 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1430 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1431 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1432 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1433 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1434 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1435 struct xhci_container_ctx *in_ctx, 1436 struct xhci_container_ctx *out_ctx, 1437 unsigned int ep_index); 1438 void xhci_slot_copy(struct xhci_hcd *xhci, 1439 struct xhci_container_ctx *in_ctx, 1440 struct xhci_container_ctx *out_ctx); 1441 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1442 struct usb_device *udev, struct usb_host_endpoint *ep, 1443 gfp_t mem_flags); 1444 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1445 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1446 struct xhci_virt_device *virt_dev, 1447 unsigned int ep_index); 1448 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1449 unsigned int num_stream_ctxs, 1450 unsigned int num_streams, gfp_t flags); 1451 void xhci_free_stream_info(struct xhci_hcd *xhci, 1452 struct xhci_stream_info *stream_info); 1453 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1454 struct xhci_ep_ctx *ep_ctx, 1455 struct xhci_stream_info *stream_info); 1456 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1457 struct xhci_ep_ctx *ep_ctx, 1458 struct xhci_virt_ep *ep); 1459 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1460 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1461 struct xhci_ring *xhci_dma_to_transfer_ring( 1462 struct xhci_virt_ep *ep, 1463 u64 address); 1464 struct xhci_ring *xhci_stream_id_to_ring( 1465 struct xhci_virt_device *dev, 1466 unsigned int ep_index, 1467 unsigned int stream_id); 1468 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1469 bool allocate_in_ctx, bool allocate_completion, 1470 gfp_t mem_flags); 1471 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); 1472 void xhci_free_command(struct xhci_hcd *xhci, 1473 struct xhci_command *command); 1474 1475 #ifdef CONFIG_PCI 1476 /* xHCI PCI glue */ 1477 int xhci_register_pci(void); 1478 void xhci_unregister_pci(void); 1479 #endif 1480 1481 /* xHCI host controller glue */ 1482 void xhci_quiesce(struct xhci_hcd *xhci); 1483 int xhci_halt(struct xhci_hcd *xhci); 1484 int xhci_reset(struct xhci_hcd *xhci); 1485 int xhci_init(struct usb_hcd *hcd); 1486 int xhci_run(struct usb_hcd *hcd); 1487 void xhci_stop(struct usb_hcd *hcd); 1488 void xhci_shutdown(struct usb_hcd *hcd); 1489 1490 #ifdef CONFIG_PM 1491 int xhci_suspend(struct xhci_hcd *xhci); 1492 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1493 #else 1494 #define xhci_suspend NULL 1495 #define xhci_resume NULL 1496 #endif 1497 1498 int xhci_get_frame(struct usb_hcd *hcd); 1499 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1500 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd); 1501 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1502 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1503 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1504 struct usb_host_endpoint **eps, unsigned int num_eps, 1505 unsigned int num_streams, gfp_t mem_flags); 1506 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1507 struct usb_host_endpoint **eps, unsigned int num_eps, 1508 gfp_t mem_flags); 1509 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1510 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1511 struct usb_tt *tt, gfp_t mem_flags); 1512 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1513 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1514 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1515 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1516 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1517 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1518 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1519 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1520 1521 /* xHCI ring, segment, TRB, and TD functions */ 1522 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1523 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1524 union xhci_trb *start_trb, union xhci_trb *end_trb, 1525 dma_addr_t suspect_dma); 1526 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1527 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1528 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1529 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1530 u32 slot_id); 1531 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 1532 u32 field1, u32 field2, u32 field3, u32 field4); 1533 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1534 unsigned int ep_index, int suspend); 1535 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1536 int slot_id, unsigned int ep_index); 1537 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1538 int slot_id, unsigned int ep_index); 1539 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1540 int slot_id, unsigned int ep_index); 1541 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1542 struct urb *urb, int slot_id, unsigned int ep_index); 1543 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1544 u32 slot_id, bool command_must_succeed); 1545 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1546 u32 slot_id); 1547 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1548 unsigned int ep_index); 1549 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); 1550 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1551 unsigned int slot_id, unsigned int ep_index, 1552 unsigned int stream_id, struct xhci_td *cur_td, 1553 struct xhci_dequeue_state *state); 1554 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1555 unsigned int slot_id, unsigned int ep_index, 1556 unsigned int stream_id, 1557 struct xhci_dequeue_state *deq_state); 1558 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1559 struct usb_device *udev, unsigned int ep_index); 1560 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1561 unsigned int slot_id, unsigned int ep_index, 1562 struct xhci_dequeue_state *deq_state); 1563 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1564 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1565 unsigned int ep_index, unsigned int stream_id); 1566 1567 /* xHCI roothub code */ 1568 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1569 char *buf, u16 wLength); 1570 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1571 1572 #ifdef CONFIG_PM 1573 int xhci_bus_suspend(struct usb_hcd *hcd); 1574 int xhci_bus_resume(struct usb_hcd *hcd); 1575 #else 1576 #define xhci_bus_suspend NULL 1577 #define xhci_bus_resume NULL 1578 #endif /* CONFIG_PM */ 1579 1580 u32 xhci_port_state_to_neutral(u32 state); 1581 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1582 u16 port); 1583 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1584 1585 /* xHCI contexts */ 1586 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1587 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1588 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1589 1590 #endif /* __LINUX_XHCI_HCD_H */ 1591