1 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __LINUX_XHCI_HCD_H 25 #define __LINUX_XHCI_HCD_H 26 27 #include <linux/usb.h> 28 #include <linux/timer.h> 29 #include <linux/kernel.h> 30 #include <linux/usb/hcd.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 33 /* Code sharing between pci-quirks and xhci hcd */ 34 #include "xhci-ext-caps.h" 35 #include "pci-quirks.h" 36 37 /* xHCI PCI Configuration Registers */ 38 #define XHCI_SBRN_OFFSET (0x60) 39 40 /* Max number of USB devices for any host controller - limit in section 6.1 */ 41 #define MAX_HC_SLOTS 256 42 /* Section 5.3.3 - MaxPorts */ 43 #define MAX_HC_PORTS 127 44 45 /* 46 * xHCI register interface. 47 * This corresponds to the eXtensible Host Controller Interface (xHCI) 48 * Revision 0.95 specification 49 */ 50 51 /** 52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 53 * @hc_capbase: length of the capabilities register and HC version number 54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 57 * @hcc_params: HCCPARAMS - Capability Parameters 58 * @db_off: DBOFF - Doorbell array offset 59 * @run_regs_off: RTSOFF - Runtime register space offset 60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 61 */ 62 struct xhci_cap_regs { 63 __le32 hc_capbase; 64 __le32 hcs_params1; 65 __le32 hcs_params2; 66 __le32 hcs_params3; 67 __le32 hcc_params; 68 __le32 db_off; 69 __le32 run_regs_off; 70 __le32 hcc_params2; /* xhci 1.1 */ 71 /* Reserved up to (CAPLENGTH - 0x1C) */ 72 }; 73 74 /* hc_capbase bitmasks */ 75 /* bits 7:0 - how long is the Capabilities register */ 76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 77 /* bits 31:16 */ 78 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 79 80 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 81 /* bits 0:7, Max Device Slots */ 82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 83 #define HCS_SLOTS_MASK 0xff 84 /* bits 8:18, Max Interrupters */ 85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 88 89 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 90 /* bits 0:3, frames or uframes that SW needs to queue transactions 91 * ahead of the HW to meet periodic deadlines */ 92 #define HCS_IST(p) (((p) >> 0) & 0xf) 93 /* bits 4:7, max number of Event Ring segments */ 94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 99 100 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 105 106 /* HCCPARAMS - hcc_params - bitmasks */ 107 /* true: HC can use 64-bit address pointers */ 108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 109 /* true: HC can do bandwidth negotiation */ 110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 111 /* true: HC uses 64-byte Device Context structures 112 * FIXME 64-byte context structures aren't supported yet. 113 */ 114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 115 /* true: HC has port power switches */ 116 #define HCC_PPC(p) ((p) & (1 << 3)) 117 /* true: HC has port indicators */ 118 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 119 /* true: HC has Light HC Reset Capability */ 120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 121 /* true: HC supports latency tolerance messaging */ 122 #define HCC_LTC(p) ((p) & (1 << 6)) 123 /* true: no secondary Stream ID Support */ 124 #define HCC_NSS(p) ((p) & (1 << 7)) 125 /* true: HC supports Stopped - Short Packet */ 126 #define HCC_SPC(p) ((p) & (1 << 9)) 127 /* true: HC has Contiguous Frame ID Capability */ 128 #define HCC_CFC(p) ((p) & (1 << 11)) 129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 133 134 /* db_off bitmask - bits 0:1 reserved */ 135 #define DBOFF_MASK (~0x3) 136 137 /* run_regs_off bitmask - bits 0:4 reserved */ 138 #define RTSOFF_MASK (~0x1f) 139 140 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 141 /* true: HC supports U3 entry Capability */ 142 #define HCC2_U3C(p) ((p) & (1 << 0)) 143 /* true: HC supports Configure endpoint command Max exit latency too large */ 144 #define HCC2_CMC(p) ((p) & (1 << 1)) 145 /* true: HC supports Force Save context Capability */ 146 #define HCC2_FSC(p) ((p) & (1 << 2)) 147 /* true: HC supports Compliance Transition Capability */ 148 #define HCC2_CTC(p) ((p) & (1 << 3)) 149 /* true: HC support Large ESIT payload Capability > 48k */ 150 #define HCC2_LEC(p) ((p) & (1 << 4)) 151 /* true: HC support Configuration Information Capability */ 152 #define HCC2_CIC(p) ((p) & (1 << 5)) 153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 154 #define HCC2_ETC(p) ((p) & (1 << 6)) 155 156 /* Number of registers per port */ 157 #define NUM_PORT_REGS 4 158 159 #define PORTSC 0 160 #define PORTPMSC 1 161 #define PORTLI 2 162 #define PORTHLPMC 3 163 164 /** 165 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 166 * @command: USBCMD - xHC command register 167 * @status: USBSTS - xHC status register 168 * @page_size: This indicates the page size that the host controller 169 * supports. If bit n is set, the HC supports a page size 170 * of 2^(n+12), up to a 128MB page size. 171 * 4K is the minimum page size. 172 * @cmd_ring: CRP - 64-bit Command Ring Pointer 173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 174 * @config_reg: CONFIG - Configure Register 175 * @port_status_base: PORTSCn - base address for Port Status and Control 176 * Each port has a Port Status and Control register, 177 * followed by a Port Power Management Status and Control 178 * register, a Port Link Info register, and a reserved 179 * register. 180 * @port_power_base: PORTPMSCn - base address for 181 * Port Power Management Status and Control 182 * @port_link_base: PORTLIn - base address for Port Link Info (current 183 * Link PM state and control) for USB 2.1 and USB 3.0 184 * devices. 185 */ 186 struct xhci_op_regs { 187 __le32 command; 188 __le32 status; 189 __le32 page_size; 190 __le32 reserved1; 191 __le32 reserved2; 192 __le32 dev_notification; 193 __le64 cmd_ring; 194 /* rsvd: offset 0x20-2F */ 195 __le32 reserved3[4]; 196 __le64 dcbaa_ptr; 197 __le32 config_reg; 198 /* rsvd: offset 0x3C-3FF */ 199 __le32 reserved4[241]; 200 /* port 1 registers, which serve as a base address for other ports */ 201 __le32 port_status_base; 202 __le32 port_power_base; 203 __le32 port_link_base; 204 __le32 reserved5; 205 /* registers for ports 2-255 */ 206 __le32 reserved6[NUM_PORT_REGS*254]; 207 }; 208 209 /* USBCMD - USB command - command bitmasks */ 210 /* start/stop HC execution - do not write unless HC is halted*/ 211 #define CMD_RUN XHCI_CMD_RUN 212 /* Reset HC - resets internal HC state machine and all registers (except 213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 214 * The xHCI driver must reinitialize the xHC after setting this bit. 215 */ 216 #define CMD_RESET (1 << 1) 217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 218 #define CMD_EIE XHCI_CMD_EIE 219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 220 #define CMD_HSEIE XHCI_CMD_HSEIE 221 /* bits 4:6 are reserved (and should be preserved on writes). */ 222 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 223 #define CMD_LRESET (1 << 7) 224 /* host controller save/restore state. */ 225 #define CMD_CSS (1 << 8) 226 #define CMD_CRS (1 << 9) 227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 228 #define CMD_EWE XHCI_CMD_EWE 229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 231 * '0' means the xHC can power it off if all ports are in the disconnect, 232 * disabled, or powered-off state. 233 */ 234 #define CMD_PM_INDEX (1 << 11) 235 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 236 #define CMD_ETE (1 << 14) 237 /* bits 15:31 are reserved (and should be preserved on writes). */ 238 239 /* IMAN - Interrupt Management Register */ 240 #define IMAN_IE (1 << 1) 241 #define IMAN_IP (1 << 0) 242 243 /* USBSTS - USB status - status bitmasks */ 244 /* HC not running - set to 1 when run/stop bit is cleared. */ 245 #define STS_HALT XHCI_STS_HALT 246 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 247 #define STS_FATAL (1 << 2) 248 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 249 #define STS_EINT (1 << 3) 250 /* port change detect */ 251 #define STS_PORT (1 << 4) 252 /* bits 5:7 reserved and zeroed */ 253 /* save state status - '1' means xHC is saving state */ 254 #define STS_SAVE (1 << 8) 255 /* restore state status - '1' means xHC is restoring state */ 256 #define STS_RESTORE (1 << 9) 257 /* true: save or restore error */ 258 #define STS_SRE (1 << 10) 259 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 260 #define STS_CNR XHCI_STS_CNR 261 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 262 #define STS_HCE (1 << 12) 263 /* bits 13:31 reserved and should be preserved */ 264 265 /* 266 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 267 * Generate a device notification event when the HC sees a transaction with a 268 * notification type that matches a bit set in this bit field. 269 */ 270 #define DEV_NOTE_MASK (0xffff) 271 #define ENABLE_DEV_NOTE(x) (1 << (x)) 272 /* Most of the device notification types should only be used for debug. 273 * SW does need to pay attention to function wake notifications. 274 */ 275 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 276 277 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 278 /* bit 0 is the command ring cycle state */ 279 /* stop ring operation after completion of the currently executing command */ 280 #define CMD_RING_PAUSE (1 << 1) 281 /* stop ring immediately - abort the currently executing command */ 282 #define CMD_RING_ABORT (1 << 2) 283 /* true: command ring is running */ 284 #define CMD_RING_RUNNING (1 << 3) 285 /* bits 4:5 reserved and should be preserved */ 286 /* Command Ring pointer - bit mask for the lower 32 bits. */ 287 #define CMD_RING_RSVD_BITS (0x3f) 288 289 /* CONFIG - Configure Register - config_reg bitmasks */ 290 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 291 #define MAX_DEVS(p) ((p) & 0xff) 292 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 293 #define CONFIG_U3E (1 << 8) 294 /* bit 9: Configuration Information Enable, xhci 1.1 */ 295 #define CONFIG_CIE (1 << 9) 296 /* bits 10:31 - reserved and should be preserved */ 297 298 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 299 /* true: device connected */ 300 #define PORT_CONNECT (1 << 0) 301 /* true: port enabled */ 302 #define PORT_PE (1 << 1) 303 /* bit 2 reserved and zeroed */ 304 /* true: port has an over-current condition */ 305 #define PORT_OC (1 << 3) 306 /* true: port reset signaling asserted */ 307 #define PORT_RESET (1 << 4) 308 /* Port Link State - bits 5:8 309 * A read gives the current link PM state of the port, 310 * a write with Link State Write Strobe set sets the link state. 311 */ 312 #define PORT_PLS_MASK (0xf << 5) 313 #define XDEV_U0 (0x0 << 5) 314 #define XDEV_U2 (0x2 << 5) 315 #define XDEV_U3 (0x3 << 5) 316 #define XDEV_INACTIVE (0x6 << 5) 317 #define XDEV_POLLING (0x7 << 5) 318 #define XDEV_COMP_MODE (0xa << 5) 319 #define XDEV_RESUME (0xf << 5) 320 /* true: port has power (see HCC_PPC) */ 321 #define PORT_POWER (1 << 9) 322 /* bits 10:13 indicate device speed: 323 * 0 - undefined speed - port hasn't be initialized by a reset yet 324 * 1 - full speed 325 * 2 - low speed 326 * 3 - high speed 327 * 4 - super speed 328 * 5-15 reserved 329 */ 330 #define DEV_SPEED_MASK (0xf << 10) 331 #define XDEV_FS (0x1 << 10) 332 #define XDEV_LS (0x2 << 10) 333 #define XDEV_HS (0x3 << 10) 334 #define XDEV_SS (0x4 << 10) 335 #define XDEV_SSP (0x5 << 10) 336 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 337 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 338 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 339 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 340 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 341 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 342 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 343 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 344 345 /* Bits 20:23 in the Slot Context are the speed for the device */ 346 #define SLOT_SPEED_FS (XDEV_FS << 10) 347 #define SLOT_SPEED_LS (XDEV_LS << 10) 348 #define SLOT_SPEED_HS (XDEV_HS << 10) 349 #define SLOT_SPEED_SS (XDEV_SS << 10) 350 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 351 /* Port Indicator Control */ 352 #define PORT_LED_OFF (0 << 14) 353 #define PORT_LED_AMBER (1 << 14) 354 #define PORT_LED_GREEN (2 << 14) 355 #define PORT_LED_MASK (3 << 14) 356 /* Port Link State Write Strobe - set this when changing link state */ 357 #define PORT_LINK_STROBE (1 << 16) 358 /* true: connect status change */ 359 #define PORT_CSC (1 << 17) 360 /* true: port enable change */ 361 #define PORT_PEC (1 << 18) 362 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 363 * into an enabled state, and the device into the default state. A "warm" reset 364 * also resets the link, forcing the device through the link training sequence. 365 * SW can also look at the Port Reset register to see when warm reset is done. 366 */ 367 #define PORT_WRC (1 << 19) 368 /* true: over-current change */ 369 #define PORT_OCC (1 << 20) 370 /* true: reset change - 1 to 0 transition of PORT_RESET */ 371 #define PORT_RC (1 << 21) 372 /* port link status change - set on some port link state transitions: 373 * Transition Reason 374 * ------------------------------------------------------------------------------ 375 * - U3 to Resume Wakeup signaling from a device 376 * - Resume to Recovery to U0 USB 3.0 device resume 377 * - Resume to U0 USB 2.0 device resume 378 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 379 * - U3 to U0 Software resume of USB 2.0 device complete 380 * - U2 to U0 L1 resume of USB 2.1 device complete 381 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 382 * - U0 to disabled L1 entry error with USB 2.1 device 383 * - Any state to inactive Error on USB 3.0 port 384 */ 385 #define PORT_PLC (1 << 22) 386 /* port configure error change - port failed to configure its link partner */ 387 #define PORT_CEC (1 << 23) 388 /* Cold Attach Status - xHC can set this bit to report device attached during 389 * Sx state. Warm port reset should be perfomed to clear this bit and move port 390 * to connected state. 391 */ 392 #define PORT_CAS (1 << 24) 393 /* wake on connect (enable) */ 394 #define PORT_WKCONN_E (1 << 25) 395 /* wake on disconnect (enable) */ 396 #define PORT_WKDISC_E (1 << 26) 397 /* wake on over-current (enable) */ 398 #define PORT_WKOC_E (1 << 27) 399 /* bits 28:29 reserved */ 400 /* true: device is non-removable - for USB 3.0 roothub emulation */ 401 #define PORT_DEV_REMOVE (1 << 30) 402 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 403 #define PORT_WR (1 << 31) 404 405 /* We mark duplicate entries with -1 */ 406 #define DUPLICATE_ENTRY ((u8)(-1)) 407 408 /* Port Power Management Status and Control - port_power_base bitmasks */ 409 /* Inactivity timer value for transitions into U1, in microseconds. 410 * Timeout can be up to 127us. 0xFF means an infinite timeout. 411 */ 412 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 413 #define PORT_U1_TIMEOUT_MASK 0xff 414 /* Inactivity timer value for transitions into U2 */ 415 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 416 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 417 /* Bits 24:31 for port testing */ 418 419 /* USB2 Protocol PORTSPMSC */ 420 #define PORT_L1S_MASK 7 421 #define PORT_L1S_SUCCESS 1 422 #define PORT_RWE (1 << 3) 423 #define PORT_HIRD(p) (((p) & 0xf) << 4) 424 #define PORT_HIRD_MASK (0xf << 4) 425 #define PORT_L1DS_MASK (0xff << 8) 426 #define PORT_L1DS(p) (((p) & 0xff) << 8) 427 #define PORT_HLE (1 << 16) 428 #define PORT_TEST_MODE_SHIFT 28 429 430 /* USB3 Protocol PORTLI Port Link Information */ 431 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 432 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 433 434 /* USB2 Protocol PORTHLPMC */ 435 #define PORT_HIRDM(p)((p) & 3) 436 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 437 #define PORT_BESLD(p)(((p) & 0xf) << 10) 438 439 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 440 #define XHCI_L1_TIMEOUT 512 441 442 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 443 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 444 * by other operating systems. 445 * 446 * XHCI 1.0 errata 8/14/12 Table 13 notes: 447 * "Software should choose xHC BESL/BESLD field values that do not violate a 448 * device's resume latency requirements, 449 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 450 * or not program values < '4' if BLC = '0' and a BESL device is attached. 451 */ 452 #define XHCI_DEFAULT_BESL 4 453 454 /** 455 * struct xhci_intr_reg - Interrupt Register Set 456 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 457 * interrupts and check for pending interrupts. 458 * @irq_control: IMOD - Interrupt Moderation Register. 459 * Used to throttle interrupts. 460 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 461 * @erst_base: ERST base address. 462 * @erst_dequeue: Event ring dequeue pointer. 463 * 464 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 465 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 466 * multiple segments of the same size. The HC places events on the ring and 467 * "updates the Cycle bit in the TRBs to indicate to software the current 468 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 469 * updates the dequeue pointer. 470 */ 471 struct xhci_intr_reg { 472 __le32 irq_pending; 473 __le32 irq_control; 474 __le32 erst_size; 475 __le32 rsvd; 476 __le64 erst_base; 477 __le64 erst_dequeue; 478 }; 479 480 /* irq_pending bitmasks */ 481 #define ER_IRQ_PENDING(p) ((p) & 0x1) 482 /* bits 2:31 need to be preserved */ 483 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 484 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 485 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 486 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 487 488 /* irq_control bitmasks */ 489 /* Minimum interval between interrupts (in 250ns intervals). The interval 490 * between interrupts will be longer if there are no events on the event ring. 491 * Default is 4000 (1 ms). 492 */ 493 #define ER_IRQ_INTERVAL_MASK (0xffff) 494 /* Counter used to count down the time to the next interrupt - HW use only */ 495 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 496 497 /* erst_size bitmasks */ 498 /* Preserve bits 16:31 of erst_size */ 499 #define ERST_SIZE_MASK (0xffff << 16) 500 501 /* erst_dequeue bitmasks */ 502 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 503 * where the current dequeue pointer lies. This is an optional HW hint. 504 */ 505 #define ERST_DESI_MASK (0x7) 506 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 507 * a work queue (or delayed service routine)? 508 */ 509 #define ERST_EHB (1 << 3) 510 #define ERST_PTR_MASK (0xf) 511 512 /** 513 * struct xhci_run_regs 514 * @microframe_index: 515 * MFINDEX - current microframe number 516 * 517 * Section 5.5 Host Controller Runtime Registers: 518 * "Software should read and write these registers using only Dword (32 bit) 519 * or larger accesses" 520 */ 521 struct xhci_run_regs { 522 __le32 microframe_index; 523 __le32 rsvd[7]; 524 struct xhci_intr_reg ir_set[128]; 525 }; 526 527 /** 528 * struct doorbell_array 529 * 530 * Bits 0 - 7: Endpoint target 531 * Bits 8 - 15: RsvdZ 532 * Bits 16 - 31: Stream ID 533 * 534 * Section 5.6 535 */ 536 struct xhci_doorbell_array { 537 __le32 doorbell[256]; 538 }; 539 540 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 541 #define DB_VALUE_HOST 0x00000000 542 543 /** 544 * struct xhci_protocol_caps 545 * @revision: major revision, minor revision, capability ID, 546 * and next capability pointer. 547 * @name_string: Four ASCII characters to say which spec this xHC 548 * follows, typically "USB ". 549 * @port_info: Port offset, count, and protocol-defined information. 550 */ 551 struct xhci_protocol_caps { 552 u32 revision; 553 u32 name_string; 554 u32 port_info; 555 }; 556 557 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 558 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 559 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 560 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 561 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 562 563 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 564 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 565 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 566 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 567 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 568 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 569 570 #define PLT_MASK (0x03 << 6) 571 #define PLT_SYM (0x00 << 6) 572 #define PLT_ASYM_RX (0x02 << 6) 573 #define PLT_ASYM_TX (0x03 << 6) 574 575 /** 576 * struct xhci_container_ctx 577 * @type: Type of context. Used to calculated offsets to contained contexts. 578 * @size: Size of the context data 579 * @bytes: The raw context data given to HW 580 * @dma: dma address of the bytes 581 * 582 * Represents either a Device or Input context. Holds a pointer to the raw 583 * memory used for the context (bytes) and dma address of it (dma). 584 */ 585 struct xhci_container_ctx { 586 unsigned type; 587 #define XHCI_CTX_TYPE_DEVICE 0x1 588 #define XHCI_CTX_TYPE_INPUT 0x2 589 590 int size; 591 592 u8 *bytes; 593 dma_addr_t dma; 594 }; 595 596 /** 597 * struct xhci_slot_ctx 598 * @dev_info: Route string, device speed, hub info, and last valid endpoint 599 * @dev_info2: Max exit latency for device number, root hub port number 600 * @tt_info: tt_info is used to construct split transaction tokens 601 * @dev_state: slot state and device address 602 * 603 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 604 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 605 * reserved at the end of the slot context for HC internal use. 606 */ 607 struct xhci_slot_ctx { 608 __le32 dev_info; 609 __le32 dev_info2; 610 __le32 tt_info; 611 __le32 dev_state; 612 /* offset 0x10 to 0x1f reserved for HC internal use */ 613 __le32 reserved[4]; 614 }; 615 616 /* dev_info bitmasks */ 617 /* Route String - 0:19 */ 618 #define ROUTE_STRING_MASK (0xfffff) 619 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 620 #define DEV_SPEED (0xf << 20) 621 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 622 /* bit 24 reserved */ 623 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 624 #define DEV_MTT (0x1 << 25) 625 /* Set if the device is a hub - bit 26 */ 626 #define DEV_HUB (0x1 << 26) 627 /* Index of the last valid endpoint context in this device context - 27:31 */ 628 #define LAST_CTX_MASK (0x1f << 27) 629 #define LAST_CTX(p) ((p) << 27) 630 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 631 #define SLOT_FLAG (1 << 0) 632 #define EP0_FLAG (1 << 1) 633 634 /* dev_info2 bitmasks */ 635 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 636 #define MAX_EXIT (0xffff) 637 /* Root hub port number that is needed to access the USB device */ 638 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 639 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 640 /* Maximum number of ports under a hub device */ 641 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 642 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 643 644 /* tt_info bitmasks */ 645 /* 646 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 647 * The Slot ID of the hub that isolates the high speed signaling from 648 * this low or full-speed device. '0' if attached to root hub port. 649 */ 650 #define TT_SLOT (0xff) 651 /* 652 * The number of the downstream facing port of the high-speed hub 653 * '0' if the device is not low or full speed. 654 */ 655 #define TT_PORT (0xff << 8) 656 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 657 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 658 659 /* dev_state bitmasks */ 660 /* USB device address - assigned by the HC */ 661 #define DEV_ADDR_MASK (0xff) 662 /* bits 8:26 reserved */ 663 /* Slot state */ 664 #define SLOT_STATE (0x1f << 27) 665 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 666 667 #define SLOT_STATE_DISABLED 0 668 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 669 #define SLOT_STATE_DEFAULT 1 670 #define SLOT_STATE_ADDRESSED 2 671 #define SLOT_STATE_CONFIGURED 3 672 673 /** 674 * struct xhci_ep_ctx 675 * @ep_info: endpoint state, streams, mult, and interval information. 676 * @ep_info2: information on endpoint type, max packet size, max burst size, 677 * error count, and whether the HC will force an event for all 678 * transactions. 679 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 680 * defines one stream, this points to the endpoint transfer ring. 681 * Otherwise, it points to a stream context array, which has a 682 * ring pointer for each flow. 683 * @tx_info: 684 * Average TRB lengths for the endpoint ring and 685 * max payload within an Endpoint Service Interval Time (ESIT). 686 * 687 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 688 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 689 * reserved at the end of the endpoint context for HC internal use. 690 */ 691 struct xhci_ep_ctx { 692 __le32 ep_info; 693 __le32 ep_info2; 694 __le64 deq; 695 __le32 tx_info; 696 /* offset 0x14 - 0x1f reserved for HC internal use */ 697 __le32 reserved[3]; 698 }; 699 700 /* ep_info bitmasks */ 701 /* 702 * Endpoint State - bits 0:2 703 * 0 - disabled 704 * 1 - running 705 * 2 - halted due to halt condition - ok to manipulate endpoint ring 706 * 3 - stopped 707 * 4 - TRB error 708 * 5-7 - reserved 709 */ 710 #define EP_STATE_MASK (0xf) 711 #define EP_STATE_DISABLED 0 712 #define EP_STATE_RUNNING 1 713 #define EP_STATE_HALTED 2 714 #define EP_STATE_STOPPED 3 715 #define EP_STATE_ERROR 4 716 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 717 718 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 719 #define EP_MULT(p) (((p) & 0x3) << 8) 720 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 721 /* bits 10:14 are Max Primary Streams */ 722 /* bit 15 is Linear Stream Array */ 723 /* Interval - period between requests to an endpoint - 125u increments. */ 724 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 725 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 726 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 727 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 728 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 729 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 730 #define EP_HAS_LSA (1 << 15) 731 732 /* ep_info2 bitmasks */ 733 /* 734 * Force Event - generate transfer events for all TRBs for this endpoint 735 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 736 */ 737 #define FORCE_EVENT (0x1) 738 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 739 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 740 #define EP_TYPE(p) ((p) << 3) 741 #define ISOC_OUT_EP 1 742 #define BULK_OUT_EP 2 743 #define INT_OUT_EP 3 744 #define CTRL_EP 4 745 #define ISOC_IN_EP 5 746 #define BULK_IN_EP 6 747 #define INT_IN_EP 7 748 /* bit 6 reserved */ 749 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 750 #define MAX_BURST(p) (((p)&0xff) << 8) 751 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 752 #define MAX_PACKET(p) (((p)&0xffff) << 16) 753 #define MAX_PACKET_MASK (0xffff << 16) 754 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 755 756 /* tx_info bitmasks */ 757 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 758 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 759 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 760 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 761 762 /* deq bitmasks */ 763 #define EP_CTX_CYCLE_MASK (1 << 0) 764 #define SCTX_DEQ_MASK (~0xfL) 765 766 767 /** 768 * struct xhci_input_control_context 769 * Input control context; see section 6.2.5. 770 * 771 * @drop_context: set the bit of the endpoint context you want to disable 772 * @add_context: set the bit of the endpoint context you want to enable 773 */ 774 struct xhci_input_control_ctx { 775 __le32 drop_flags; 776 __le32 add_flags; 777 __le32 rsvd2[6]; 778 }; 779 780 #define EP_IS_ADDED(ctrl_ctx, i) \ 781 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 782 #define EP_IS_DROPPED(ctrl_ctx, i) \ 783 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 784 785 /* Represents everything that is needed to issue a command on the command ring. 786 * It's useful to pre-allocate these for commands that cannot fail due to 787 * out-of-memory errors, like freeing streams. 788 */ 789 struct xhci_command { 790 /* Input context for changing device state */ 791 struct xhci_container_ctx *in_ctx; 792 u32 status; 793 int slot_id; 794 /* If completion is null, no one is waiting on this command 795 * and the structure can be freed after the command completes. 796 */ 797 struct completion *completion; 798 union xhci_trb *command_trb; 799 struct list_head cmd_list; 800 }; 801 802 /* drop context bitmasks */ 803 #define DROP_EP(x) (0x1 << x) 804 /* add context bitmasks */ 805 #define ADD_EP(x) (0x1 << x) 806 807 struct xhci_stream_ctx { 808 /* 64-bit stream ring address, cycle state, and stream type */ 809 __le64 stream_ring; 810 /* offset 0x14 - 0x1f reserved for HC internal use */ 811 __le32 reserved[2]; 812 }; 813 814 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 815 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 816 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 817 #define SCT_SEC_TR 0 818 /* Primary stream array type, dequeue pointer is to a transfer ring */ 819 #define SCT_PRI_TR 1 820 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 821 #define SCT_SSA_8 2 822 #define SCT_SSA_16 3 823 #define SCT_SSA_32 4 824 #define SCT_SSA_64 5 825 #define SCT_SSA_128 6 826 #define SCT_SSA_256 7 827 828 /* Assume no secondary streams for now */ 829 struct xhci_stream_info { 830 struct xhci_ring **stream_rings; 831 /* Number of streams, including stream 0 (which drivers can't use) */ 832 unsigned int num_streams; 833 /* The stream context array may be bigger than 834 * the number of streams the driver asked for 835 */ 836 struct xhci_stream_ctx *stream_ctx_array; 837 unsigned int num_stream_ctxs; 838 dma_addr_t ctx_array_dma; 839 /* For mapping physical TRB addresses to segments in stream rings */ 840 struct radix_tree_root trb_address_map; 841 struct xhci_command *free_streams_command; 842 }; 843 844 #define SMALL_STREAM_ARRAY_SIZE 256 845 #define MEDIUM_STREAM_ARRAY_SIZE 1024 846 847 /* Some Intel xHCI host controllers need software to keep track of the bus 848 * bandwidth. Keep track of endpoint info here. Each root port is allocated 849 * the full bus bandwidth. We must also treat TTs (including each port under a 850 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 851 * (DMI) also limits the total bandwidth (across all domains) that can be used. 852 */ 853 struct xhci_bw_info { 854 /* ep_interval is zero-based */ 855 unsigned int ep_interval; 856 /* mult and num_packets are one-based */ 857 unsigned int mult; 858 unsigned int num_packets; 859 unsigned int max_packet_size; 860 unsigned int max_esit_payload; 861 unsigned int type; 862 }; 863 864 /* "Block" sizes in bytes the hardware uses for different device speeds. 865 * The logic in this part of the hardware limits the number of bits the hardware 866 * can use, so must represent bandwidth in a less precise manner to mimic what 867 * the scheduler hardware computes. 868 */ 869 #define FS_BLOCK 1 870 #define HS_BLOCK 4 871 #define SS_BLOCK 16 872 #define DMI_BLOCK 32 873 874 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 875 * with each byte transferred. SuperSpeed devices have an initial overhead to 876 * set up bursts. These are in blocks, see above. LS overhead has already been 877 * translated into FS blocks. 878 */ 879 #define DMI_OVERHEAD 8 880 #define DMI_OVERHEAD_BURST 4 881 #define SS_OVERHEAD 8 882 #define SS_OVERHEAD_BURST 32 883 #define HS_OVERHEAD 26 884 #define FS_OVERHEAD 20 885 #define LS_OVERHEAD 128 886 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 887 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 888 * of overhead associated with split transfers crossing microframe boundaries. 889 * 31 blocks is pure protocol overhead. 890 */ 891 #define TT_HS_OVERHEAD (31 + 94) 892 #define TT_DMI_OVERHEAD (25 + 12) 893 894 /* Bandwidth limits in blocks */ 895 #define FS_BW_LIMIT 1285 896 #define TT_BW_LIMIT 1320 897 #define HS_BW_LIMIT 1607 898 #define SS_BW_LIMIT_IN 3906 899 #define DMI_BW_LIMIT_IN 3906 900 #define SS_BW_LIMIT_OUT 3906 901 #define DMI_BW_LIMIT_OUT 3906 902 903 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 904 #define FS_BW_RESERVED 10 905 #define HS_BW_RESERVED 20 906 #define SS_BW_RESERVED 10 907 908 struct xhci_virt_ep { 909 struct xhci_ring *ring; 910 /* Related to endpoints that are configured to use stream IDs only */ 911 struct xhci_stream_info *stream_info; 912 /* Temporary storage in case the configure endpoint command fails and we 913 * have to restore the device state to the previous state 914 */ 915 struct xhci_ring *new_ring; 916 unsigned int ep_state; 917 #define SET_DEQ_PENDING (1 << 0) 918 #define EP_HALTED (1 << 1) /* For stall handling */ 919 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 920 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 921 #define EP_GETTING_STREAMS (1 << 3) 922 #define EP_HAS_STREAMS (1 << 4) 923 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 924 #define EP_GETTING_NO_STREAMS (1 << 5) 925 /* ---- Related to URB cancellation ---- */ 926 struct list_head cancelled_td_list; 927 /* Watchdog timer for stop endpoint command to cancel URBs */ 928 struct timer_list stop_cmd_timer; 929 struct xhci_hcd *xhci; 930 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 931 * command. We'll need to update the ring's dequeue segment and dequeue 932 * pointer after the command completes. 933 */ 934 struct xhci_segment *queued_deq_seg; 935 union xhci_trb *queued_deq_ptr; 936 /* 937 * Sometimes the xHC can not process isochronous endpoint ring quickly 938 * enough, and it will miss some isoc tds on the ring and generate 939 * a Missed Service Error Event. 940 * Set skip flag when receive a Missed Service Error Event and 941 * process the missed tds on the endpoint ring. 942 */ 943 bool skip; 944 /* Bandwidth checking storage */ 945 struct xhci_bw_info bw_info; 946 struct list_head bw_endpoint_list; 947 /* Isoch Frame ID checking storage */ 948 int next_frame_id; 949 /* Use new Isoch TRB layout needed for extended TBC support */ 950 bool use_extended_tbc; 951 }; 952 953 enum xhci_overhead_type { 954 LS_OVERHEAD_TYPE = 0, 955 FS_OVERHEAD_TYPE, 956 HS_OVERHEAD_TYPE, 957 }; 958 959 struct xhci_interval_bw { 960 unsigned int num_packets; 961 /* Sorted by max packet size. 962 * Head of the list is the greatest max packet size. 963 */ 964 struct list_head endpoints; 965 /* How many endpoints of each speed are present. */ 966 unsigned int overhead[3]; 967 }; 968 969 #define XHCI_MAX_INTERVAL 16 970 971 struct xhci_interval_bw_table { 972 unsigned int interval0_esit_payload; 973 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 974 /* Includes reserved bandwidth for async endpoints */ 975 unsigned int bw_used; 976 unsigned int ss_bw_in; 977 unsigned int ss_bw_out; 978 }; 979 980 981 struct xhci_virt_device { 982 struct usb_device *udev; 983 /* 984 * Commands to the hardware are passed an "input context" that 985 * tells the hardware what to change in its data structures. 986 * The hardware will return changes in an "output context" that 987 * software must allocate for the hardware. We need to keep 988 * track of input and output contexts separately because 989 * these commands might fail and we don't trust the hardware. 990 */ 991 struct xhci_container_ctx *out_ctx; 992 /* Used for addressing devices and configuration changes */ 993 struct xhci_container_ctx *in_ctx; 994 struct xhci_virt_ep eps[31]; 995 u8 fake_port; 996 u8 real_port; 997 struct xhci_interval_bw_table *bw_table; 998 struct xhci_tt_bw_info *tt_info; 999 /* The current max exit latency for the enabled USB3 link states. */ 1000 u16 current_mel; 1001 }; 1002 1003 /* 1004 * For each roothub, keep track of the bandwidth information for each periodic 1005 * interval. 1006 * 1007 * If a high speed hub is attached to the roothub, each TT associated with that 1008 * hub is a separate bandwidth domain. The interval information for the 1009 * endpoints on the devices under that TT will appear in the TT structure. 1010 */ 1011 struct xhci_root_port_bw_info { 1012 struct list_head tts; 1013 unsigned int num_active_tts; 1014 struct xhci_interval_bw_table bw_table; 1015 }; 1016 1017 struct xhci_tt_bw_info { 1018 struct list_head tt_list; 1019 int slot_id; 1020 int ttport; 1021 struct xhci_interval_bw_table bw_table; 1022 int active_eps; 1023 }; 1024 1025 1026 /** 1027 * struct xhci_device_context_array 1028 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1029 */ 1030 struct xhci_device_context_array { 1031 /* 64-bit device addresses; we only write 32-bit addresses */ 1032 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1033 /* private xHCD pointers */ 1034 dma_addr_t dma; 1035 }; 1036 /* TODO: write function to set the 64-bit device DMA address */ 1037 /* 1038 * TODO: change this to be dynamically sized at HC mem init time since the HC 1039 * might not be able to handle the maximum number of devices possible. 1040 */ 1041 1042 1043 struct xhci_transfer_event { 1044 /* 64-bit buffer address, or immediate data */ 1045 __le64 buffer; 1046 __le32 transfer_len; 1047 /* This field is interpreted differently based on the type of TRB */ 1048 __le32 flags; 1049 }; 1050 1051 /* Transfer event TRB length bit mask */ 1052 /* bits 0:23 */ 1053 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1054 1055 /** Transfer Event bit fields **/ 1056 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1057 1058 /* Completion Code - only applicable for some types of TRBs */ 1059 #define COMP_CODE_MASK (0xff << 24) 1060 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1061 #define COMP_INVALID 0 1062 #define COMP_SUCCESS 1 1063 #define COMP_DATA_BUFFER_ERROR 2 1064 #define COMP_BABBLE_DETECTED_ERROR 3 1065 #define COMP_USB_TRANSACTION_ERROR 4 1066 #define COMP_TRB_ERROR 5 1067 #define COMP_STALL_ERROR 6 1068 #define COMP_RESOURCE_ERROR 7 1069 #define COMP_BANDWIDTH_ERROR 8 1070 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1071 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1072 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1073 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1074 #define COMP_SHORT_PACKET 13 1075 #define COMP_RING_UNDERRUN 14 1076 #define COMP_RING_OVERRUN 15 1077 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1078 #define COMP_PARAMETER_ERROR 17 1079 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1080 #define COMP_CONTEXT_STATE_ERROR 19 1081 #define COMP_NO_PING_RESPONSE_ERROR 20 1082 #define COMP_EVENT_RING_FULL_ERROR 21 1083 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1084 #define COMP_MISSED_SERVICE_ERROR 23 1085 #define COMP_COMMAND_RING_STOPPED 24 1086 #define COMP_COMMAND_ABORTED 25 1087 #define COMP_STOPPED 26 1088 #define COMP_STOPPED_LENGTH_INVALID 27 1089 #define COMP_STOPPED_SHORT_PACKET 28 1090 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1091 #define COMP_ISOCH_BUFFER_OVERRUN 31 1092 #define COMP_EVENT_LOST_ERROR 32 1093 #define COMP_UNDEFINED_ERROR 33 1094 #define COMP_INVALID_STREAM_ID_ERROR 34 1095 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1096 #define COMP_SPLIT_TRANSACTION_ERROR 36 1097 1098 static inline const char *xhci_trb_comp_code_string(u8 status) 1099 { 1100 switch (status) { 1101 case COMP_INVALID: 1102 return "Invalid"; 1103 case COMP_SUCCESS: 1104 return "Success"; 1105 case COMP_DATA_BUFFER_ERROR: 1106 return "Data Buffer Error"; 1107 case COMP_BABBLE_DETECTED_ERROR: 1108 return "Babble Detected"; 1109 case COMP_USB_TRANSACTION_ERROR: 1110 return "USB Transaction Error"; 1111 case COMP_TRB_ERROR: 1112 return "TRB Error"; 1113 case COMP_STALL_ERROR: 1114 return "Stall Error"; 1115 case COMP_RESOURCE_ERROR: 1116 return "Resource Error"; 1117 case COMP_BANDWIDTH_ERROR: 1118 return "Bandwidth Error"; 1119 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1120 return "No Slots Available Error"; 1121 case COMP_INVALID_STREAM_TYPE_ERROR: 1122 return "Invalid Stream Type Error"; 1123 case COMP_SLOT_NOT_ENABLED_ERROR: 1124 return "Slot Not Enabled Error"; 1125 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1126 return "Endpoint Not Enabled Error"; 1127 case COMP_SHORT_PACKET: 1128 return "Short Packet"; 1129 case COMP_RING_UNDERRUN: 1130 return "Ring Underrun"; 1131 case COMP_RING_OVERRUN: 1132 return "Ring Overrun"; 1133 case COMP_VF_EVENT_RING_FULL_ERROR: 1134 return "VF Event Ring Full Error"; 1135 case COMP_PARAMETER_ERROR: 1136 return "Parameter Error"; 1137 case COMP_BANDWIDTH_OVERRUN_ERROR: 1138 return "Bandwidth Overrun Error"; 1139 case COMP_CONTEXT_STATE_ERROR: 1140 return "Context State Error"; 1141 case COMP_NO_PING_RESPONSE_ERROR: 1142 return "No Ping Response Error"; 1143 case COMP_EVENT_RING_FULL_ERROR: 1144 return "Event Ring Full Error"; 1145 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1146 return "Incompatible Device Error"; 1147 case COMP_MISSED_SERVICE_ERROR: 1148 return "Missed Service Error"; 1149 case COMP_COMMAND_RING_STOPPED: 1150 return "Command Ring Stopped"; 1151 case COMP_COMMAND_ABORTED: 1152 return "Command Aborted"; 1153 case COMP_STOPPED: 1154 return "Stopped"; 1155 case COMP_STOPPED_LENGTH_INVALID: 1156 return "Stopped - Length Invalid"; 1157 case COMP_STOPPED_SHORT_PACKET: 1158 return "Stopped - Short Packet"; 1159 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1160 return "Max Exit Latency Too Large Error"; 1161 case COMP_ISOCH_BUFFER_OVERRUN: 1162 return "Isoch Buffer Overrun"; 1163 case COMP_EVENT_LOST_ERROR: 1164 return "Event Lost Error"; 1165 case COMP_UNDEFINED_ERROR: 1166 return "Undefined Error"; 1167 case COMP_INVALID_STREAM_ID_ERROR: 1168 return "Invalid Stream ID Error"; 1169 case COMP_SECONDARY_BANDWIDTH_ERROR: 1170 return "Secondary Bandwidth Error"; 1171 case COMP_SPLIT_TRANSACTION_ERROR: 1172 return "Split Transaction Error"; 1173 default: 1174 return "Unknown!!"; 1175 } 1176 } 1177 1178 struct xhci_link_trb { 1179 /* 64-bit segment pointer*/ 1180 __le64 segment_ptr; 1181 __le32 intr_target; 1182 __le32 control; 1183 }; 1184 1185 /* control bitfields */ 1186 #define LINK_TOGGLE (0x1<<1) 1187 1188 /* Command completion event TRB */ 1189 struct xhci_event_cmd { 1190 /* Pointer to command TRB, or the value passed by the event data trb */ 1191 __le64 cmd_trb; 1192 __le32 status; 1193 __le32 flags; 1194 }; 1195 1196 /* flags bitmasks */ 1197 1198 /* Address device - disable SetAddress */ 1199 #define TRB_BSR (1<<9) 1200 1201 /* Configure Endpoint - Deconfigure */ 1202 #define TRB_DC (1<<9) 1203 1204 /* Stop Ring - Transfer State Preserve */ 1205 #define TRB_TSP (1<<9) 1206 1207 enum xhci_ep_reset_type { 1208 EP_HARD_RESET, 1209 EP_SOFT_RESET, 1210 }; 1211 1212 /* Force Event */ 1213 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1214 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1215 1216 /* Set Latency Tolerance Value */ 1217 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1218 1219 /* Get Port Bandwidth */ 1220 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1221 1222 /* Force Header */ 1223 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1224 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1225 1226 enum xhci_setup_dev { 1227 SETUP_CONTEXT_ONLY, 1228 SETUP_CONTEXT_ADDRESS, 1229 }; 1230 1231 /* bits 16:23 are the virtual function ID */ 1232 /* bits 24:31 are the slot ID */ 1233 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1234 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1235 1236 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1237 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1238 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1239 1240 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1241 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1242 #define LAST_EP_INDEX 30 1243 1244 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1245 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1246 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1247 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1248 1249 /* Link TRB specific fields */ 1250 #define TRB_TC (1<<1) 1251 1252 /* Port Status Change Event TRB fields */ 1253 /* Port ID - bits 31:24 */ 1254 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1255 1256 #define EVENT_DATA (1 << 2) 1257 1258 /* Normal TRB fields */ 1259 /* transfer_len bitmasks - bits 0:16 */ 1260 #define TRB_LEN(p) ((p) & 0x1ffff) 1261 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1262 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1263 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1264 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1265 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1266 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1267 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1268 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1269 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1270 #define TRB_TBC(p) (((p) & 0x3) << 7) 1271 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1272 1273 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1274 #define TRB_CYCLE (1<<0) 1275 /* 1276 * Force next event data TRB to be evaluated before task switch. 1277 * Used to pass OS data back after a TD completes. 1278 */ 1279 #define TRB_ENT (1<<1) 1280 /* Interrupt on short packet */ 1281 #define TRB_ISP (1<<2) 1282 /* Set PCIe no snoop attribute */ 1283 #define TRB_NO_SNOOP (1<<3) 1284 /* Chain multiple TRBs into a TD */ 1285 #define TRB_CHAIN (1<<4) 1286 /* Interrupt on completion */ 1287 #define TRB_IOC (1<<5) 1288 /* The buffer pointer contains immediate data */ 1289 #define TRB_IDT (1<<6) 1290 1291 /* Block Event Interrupt */ 1292 #define TRB_BEI (1<<9) 1293 1294 /* Control transfer TRB specific fields */ 1295 #define TRB_DIR_IN (1<<16) 1296 #define TRB_TX_TYPE(p) ((p) << 16) 1297 #define TRB_DATA_OUT 2 1298 #define TRB_DATA_IN 3 1299 1300 /* Isochronous TRB specific fields */ 1301 #define TRB_SIA (1<<31) 1302 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1303 1304 struct xhci_generic_trb { 1305 __le32 field[4]; 1306 }; 1307 1308 union xhci_trb { 1309 struct xhci_link_trb link; 1310 struct xhci_transfer_event trans_event; 1311 struct xhci_event_cmd event_cmd; 1312 struct xhci_generic_trb generic; 1313 }; 1314 1315 /* TRB bit mask */ 1316 #define TRB_TYPE_BITMASK (0xfc00) 1317 #define TRB_TYPE(p) ((p) << 10) 1318 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1319 /* TRB type IDs */ 1320 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1321 #define TRB_NORMAL 1 1322 /* setup stage for control transfers */ 1323 #define TRB_SETUP 2 1324 /* data stage for control transfers */ 1325 #define TRB_DATA 3 1326 /* status stage for control transfers */ 1327 #define TRB_STATUS 4 1328 /* isoc transfers */ 1329 #define TRB_ISOC 5 1330 /* TRB for linking ring segments */ 1331 #define TRB_LINK 6 1332 #define TRB_EVENT_DATA 7 1333 /* Transfer Ring No-op (not for the command ring) */ 1334 #define TRB_TR_NOOP 8 1335 /* Command TRBs */ 1336 /* Enable Slot Command */ 1337 #define TRB_ENABLE_SLOT 9 1338 /* Disable Slot Command */ 1339 #define TRB_DISABLE_SLOT 10 1340 /* Address Device Command */ 1341 #define TRB_ADDR_DEV 11 1342 /* Configure Endpoint Command */ 1343 #define TRB_CONFIG_EP 12 1344 /* Evaluate Context Command */ 1345 #define TRB_EVAL_CONTEXT 13 1346 /* Reset Endpoint Command */ 1347 #define TRB_RESET_EP 14 1348 /* Stop Transfer Ring Command */ 1349 #define TRB_STOP_RING 15 1350 /* Set Transfer Ring Dequeue Pointer Command */ 1351 #define TRB_SET_DEQ 16 1352 /* Reset Device Command */ 1353 #define TRB_RESET_DEV 17 1354 /* Force Event Command (opt) */ 1355 #define TRB_FORCE_EVENT 18 1356 /* Negotiate Bandwidth Command (opt) */ 1357 #define TRB_NEG_BANDWIDTH 19 1358 /* Set Latency Tolerance Value Command (opt) */ 1359 #define TRB_SET_LT 20 1360 /* Get port bandwidth Command */ 1361 #define TRB_GET_BW 21 1362 /* Force Header Command - generate a transaction or link management packet */ 1363 #define TRB_FORCE_HEADER 22 1364 /* No-op Command - not for transfer rings */ 1365 #define TRB_CMD_NOOP 23 1366 /* TRB IDs 24-31 reserved */ 1367 /* Event TRBS */ 1368 /* Transfer Event */ 1369 #define TRB_TRANSFER 32 1370 /* Command Completion Event */ 1371 #define TRB_COMPLETION 33 1372 /* Port Status Change Event */ 1373 #define TRB_PORT_STATUS 34 1374 /* Bandwidth Request Event (opt) */ 1375 #define TRB_BANDWIDTH_EVENT 35 1376 /* Doorbell Event (opt) */ 1377 #define TRB_DOORBELL 36 1378 /* Host Controller Event */ 1379 #define TRB_HC_EVENT 37 1380 /* Device Notification Event - device sent function wake notification */ 1381 #define TRB_DEV_NOTE 38 1382 /* MFINDEX Wrap Event - microframe counter wrapped */ 1383 #define TRB_MFINDEX_WRAP 39 1384 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1385 1386 /* Nec vendor-specific command completion event. */ 1387 #define TRB_NEC_CMD_COMP 48 1388 /* Get NEC firmware revision. */ 1389 #define TRB_NEC_GET_FW 49 1390 1391 static inline const char *xhci_trb_type_string(u8 type) 1392 { 1393 switch (type) { 1394 case TRB_NORMAL: 1395 return "Normal"; 1396 case TRB_SETUP: 1397 return "Setup Stage"; 1398 case TRB_DATA: 1399 return "Data Stage"; 1400 case TRB_STATUS: 1401 return "Status Stage"; 1402 case TRB_ISOC: 1403 return "Isoch"; 1404 case TRB_LINK: 1405 return "Link"; 1406 case TRB_EVENT_DATA: 1407 return "Event Data"; 1408 case TRB_TR_NOOP: 1409 return "No-Op"; 1410 case TRB_ENABLE_SLOT: 1411 return "Enable Slot Command"; 1412 case TRB_DISABLE_SLOT: 1413 return "Disable Slot Command"; 1414 case TRB_ADDR_DEV: 1415 return "Address Device Command"; 1416 case TRB_CONFIG_EP: 1417 return "Configure Endpoint Command"; 1418 case TRB_EVAL_CONTEXT: 1419 return "Evaluate Context Command"; 1420 case TRB_RESET_EP: 1421 return "Reset Endpoint Command"; 1422 case TRB_STOP_RING: 1423 return "Stop Ring Command"; 1424 case TRB_SET_DEQ: 1425 return "Set TR Dequeue Pointer Command"; 1426 case TRB_RESET_DEV: 1427 return "Reset Device Command"; 1428 case TRB_FORCE_EVENT: 1429 return "Force Event Command"; 1430 case TRB_NEG_BANDWIDTH: 1431 return "Negotiate Bandwidth Command"; 1432 case TRB_SET_LT: 1433 return "Set Latency Tolerance Value Command"; 1434 case TRB_GET_BW: 1435 return "Get Port Bandwidth Command"; 1436 case TRB_FORCE_HEADER: 1437 return "Force Header Command"; 1438 case TRB_CMD_NOOP: 1439 return "No-Op Command"; 1440 case TRB_TRANSFER: 1441 return "Transfer Event"; 1442 case TRB_COMPLETION: 1443 return "Command Completion Event"; 1444 case TRB_PORT_STATUS: 1445 return "Port Status Change Event"; 1446 case TRB_BANDWIDTH_EVENT: 1447 return "Bandwidth Request Event"; 1448 case TRB_DOORBELL: 1449 return "Doorbell Event"; 1450 case TRB_HC_EVENT: 1451 return "Host Controller Event"; 1452 case TRB_DEV_NOTE: 1453 return "Device Notification Event"; 1454 case TRB_MFINDEX_WRAP: 1455 return "MFINDEX Wrap Event"; 1456 case TRB_NEC_CMD_COMP: 1457 return "NEC Command Completion Event"; 1458 case TRB_NEC_GET_FW: 1459 return "NET Get Firmware Revision Command"; 1460 default: 1461 return "UNKNOWN"; 1462 } 1463 } 1464 1465 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1466 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1467 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1468 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1469 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1470 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1471 1472 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1473 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1474 1475 /* 1476 * TRBS_PER_SEGMENT must be a multiple of 4, 1477 * since the command ring is 64-byte aligned. 1478 * It must also be greater than 16. 1479 */ 1480 #define TRBS_PER_SEGMENT 256 1481 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1482 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1483 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1484 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1485 /* TRB buffer pointers can't cross 64KB boundaries */ 1486 #define TRB_MAX_BUFF_SHIFT 16 1487 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1488 /* How much data is left before the 64KB boundary? */ 1489 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1490 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1491 1492 struct xhci_segment { 1493 union xhci_trb *trbs; 1494 /* private to HCD */ 1495 struct xhci_segment *next; 1496 dma_addr_t dma; 1497 /* Max packet sized bounce buffer for td-fragmant alignment */ 1498 dma_addr_t bounce_dma; 1499 void *bounce_buf; 1500 unsigned int bounce_offs; 1501 unsigned int bounce_len; 1502 }; 1503 1504 struct xhci_td { 1505 struct list_head td_list; 1506 struct list_head cancelled_td_list; 1507 struct urb *urb; 1508 struct xhci_segment *start_seg; 1509 union xhci_trb *first_trb; 1510 union xhci_trb *last_trb; 1511 struct xhci_segment *bounce_seg; 1512 /* actual_length of the URB has already been set */ 1513 bool urb_length_set; 1514 }; 1515 1516 /* xHCI command default timeout value */ 1517 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1518 1519 /* command descriptor */ 1520 struct xhci_cd { 1521 struct xhci_command *command; 1522 union xhci_trb *cmd_trb; 1523 }; 1524 1525 struct xhci_dequeue_state { 1526 struct xhci_segment *new_deq_seg; 1527 union xhci_trb *new_deq_ptr; 1528 int new_cycle_state; 1529 unsigned int stream_id; 1530 }; 1531 1532 enum xhci_ring_type { 1533 TYPE_CTRL = 0, 1534 TYPE_ISOC, 1535 TYPE_BULK, 1536 TYPE_INTR, 1537 TYPE_STREAM, 1538 TYPE_COMMAND, 1539 TYPE_EVENT, 1540 }; 1541 1542 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1543 { 1544 switch (type) { 1545 case TYPE_CTRL: 1546 return "CTRL"; 1547 case TYPE_ISOC: 1548 return "ISOC"; 1549 case TYPE_BULK: 1550 return "BULK"; 1551 case TYPE_INTR: 1552 return "INTR"; 1553 case TYPE_STREAM: 1554 return "STREAM"; 1555 case TYPE_COMMAND: 1556 return "CMD"; 1557 case TYPE_EVENT: 1558 return "EVENT"; 1559 } 1560 1561 return "UNKNOWN"; 1562 } 1563 1564 struct xhci_ring { 1565 struct xhci_segment *first_seg; 1566 struct xhci_segment *last_seg; 1567 union xhci_trb *enqueue; 1568 struct xhci_segment *enq_seg; 1569 union xhci_trb *dequeue; 1570 struct xhci_segment *deq_seg; 1571 struct list_head td_list; 1572 /* 1573 * Write the cycle state into the TRB cycle field to give ownership of 1574 * the TRB to the host controller (if we are the producer), or to check 1575 * if we own the TRB (if we are the consumer). See section 4.9.1. 1576 */ 1577 u32 cycle_state; 1578 unsigned int stream_id; 1579 unsigned int num_segs; 1580 unsigned int num_trbs_free; 1581 unsigned int num_trbs_free_temp; 1582 unsigned int bounce_buf_len; 1583 enum xhci_ring_type type; 1584 bool last_td_was_short; 1585 struct radix_tree_root *trb_address_map; 1586 }; 1587 1588 struct xhci_erst_entry { 1589 /* 64-bit event ring segment address */ 1590 __le64 seg_addr; 1591 __le32 seg_size; 1592 /* Set to zero */ 1593 __le32 rsvd; 1594 }; 1595 1596 struct xhci_erst { 1597 struct xhci_erst_entry *entries; 1598 unsigned int num_entries; 1599 /* xhci->event_ring keeps track of segment dma addresses */ 1600 dma_addr_t erst_dma_addr; 1601 /* Num entries the ERST can contain */ 1602 unsigned int erst_size; 1603 }; 1604 1605 struct xhci_scratchpad { 1606 u64 *sp_array; 1607 dma_addr_t sp_dma; 1608 void **sp_buffers; 1609 }; 1610 1611 struct urb_priv { 1612 int num_tds; 1613 int num_tds_done; 1614 struct xhci_td td[0]; 1615 }; 1616 1617 /* 1618 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1619 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1620 * meaning 64 ring segments. 1621 * Initial allocated size of the ERST, in number of entries */ 1622 #define ERST_NUM_SEGS 1 1623 /* Initial allocated size of the ERST, in number of entries */ 1624 #define ERST_SIZE 64 1625 /* Initial number of event segment rings allocated */ 1626 #define ERST_ENTRIES 1 1627 /* Poll every 60 seconds */ 1628 #define POLL_TIMEOUT 60 1629 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1630 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1631 /* XXX: Make these module parameters */ 1632 1633 struct s3_save { 1634 u32 command; 1635 u32 dev_nt; 1636 u64 dcbaa_ptr; 1637 u32 config_reg; 1638 u32 irq_pending; 1639 u32 irq_control; 1640 u32 erst_size; 1641 u64 erst_base; 1642 u64 erst_dequeue; 1643 }; 1644 1645 /* Use for lpm */ 1646 struct dev_info { 1647 u32 dev_id; 1648 struct list_head list; 1649 }; 1650 1651 struct xhci_bus_state { 1652 unsigned long bus_suspended; 1653 unsigned long next_statechange; 1654 1655 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1656 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1657 u32 port_c_suspend; 1658 u32 suspended_ports; 1659 u32 port_remote_wakeup; 1660 unsigned long resume_done[USB_MAXCHILDREN]; 1661 /* which ports have started to resume */ 1662 unsigned long resuming_ports; 1663 /* Which ports are waiting on RExit to U0 transition. */ 1664 unsigned long rexit_ports; 1665 struct completion rexit_done[USB_MAXCHILDREN]; 1666 }; 1667 1668 1669 /* 1670 * It can take up to 20 ms to transition from RExit to U0 on the 1671 * Intel Lynx Point LP xHCI host. 1672 */ 1673 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1674 1675 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1676 { 1677 if (hcd->speed == HCD_USB3) 1678 return 0; 1679 else 1680 return 1; 1681 } 1682 1683 struct xhci_hub { 1684 u8 maj_rev; 1685 u8 min_rev; 1686 u32 *psi; /* array of protocol speed ID entries */ 1687 u8 psi_count; 1688 u8 psi_uid_count; 1689 }; 1690 1691 /* There is one xhci_hcd structure per controller */ 1692 struct xhci_hcd { 1693 struct usb_hcd *main_hcd; 1694 struct usb_hcd *shared_hcd; 1695 /* glue to PCI and HCD framework */ 1696 struct xhci_cap_regs __iomem *cap_regs; 1697 struct xhci_op_regs __iomem *op_regs; 1698 struct xhci_run_regs __iomem *run_regs; 1699 struct xhci_doorbell_array __iomem *dba; 1700 /* Our HCD's current interrupter register set */ 1701 struct xhci_intr_reg __iomem *ir_set; 1702 1703 /* Cached register copies of read-only HC data */ 1704 __u32 hcs_params1; 1705 __u32 hcs_params2; 1706 __u32 hcs_params3; 1707 __u32 hcc_params; 1708 __u32 hcc_params2; 1709 1710 spinlock_t lock; 1711 1712 /* packed release number */ 1713 u8 sbrn; 1714 u16 hci_version; 1715 u8 max_slots; 1716 u8 max_interrupters; 1717 u8 max_ports; 1718 u8 isoc_threshold; 1719 int event_ring_max; 1720 /* 4KB min, 128MB max */ 1721 int page_size; 1722 /* Valid values are 12 to 20, inclusive */ 1723 int page_shift; 1724 /* msi-x vectors */ 1725 int msix_count; 1726 /* optional clock */ 1727 struct clk *clk; 1728 /* data structures */ 1729 struct xhci_device_context_array *dcbaa; 1730 struct xhci_ring *cmd_ring; 1731 unsigned int cmd_ring_state; 1732 #define CMD_RING_STATE_RUNNING (1 << 0) 1733 #define CMD_RING_STATE_ABORTED (1 << 1) 1734 #define CMD_RING_STATE_STOPPED (1 << 2) 1735 struct list_head cmd_list; 1736 unsigned int cmd_ring_reserved_trbs; 1737 struct delayed_work cmd_timer; 1738 struct completion cmd_ring_stop_completion; 1739 struct xhci_command *current_cmd; 1740 struct xhci_ring *event_ring; 1741 struct xhci_erst erst; 1742 /* Scratchpad */ 1743 struct xhci_scratchpad *scratchpad; 1744 /* Store LPM test failed devices' information */ 1745 struct list_head lpm_failed_devs; 1746 1747 /* slot enabling and address device helpers */ 1748 /* these are not thread safe so use mutex */ 1749 struct mutex mutex; 1750 /* For USB 3.0 LPM enable/disable. */ 1751 struct xhci_command *lpm_command; 1752 /* Internal mirror of the HW's dcbaa */ 1753 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1754 /* For keeping track of bandwidth domains per roothub. */ 1755 struct xhci_root_port_bw_info *rh_bw; 1756 1757 /* DMA pools */ 1758 struct dma_pool *device_pool; 1759 struct dma_pool *segment_pool; 1760 struct dma_pool *small_streams_pool; 1761 struct dma_pool *medium_streams_pool; 1762 1763 /* Host controller watchdog timer structures */ 1764 unsigned int xhc_state; 1765 1766 u32 command; 1767 struct s3_save s3; 1768 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1769 * 1770 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1771 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1772 * that sees this status (other than the timer that set it) should stop touching 1773 * hardware immediately. Interrupt handlers should return immediately when 1774 * they see this status (any time they drop and re-acquire xhci->lock). 1775 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1776 * putting the TD on the canceled list, etc. 1777 * 1778 * There are no reports of xHCI host controllers that display this issue. 1779 */ 1780 #define XHCI_STATE_DYING (1 << 0) 1781 #define XHCI_STATE_HALTED (1 << 1) 1782 #define XHCI_STATE_REMOVING (1 << 2) 1783 unsigned int quirks; 1784 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1785 #define XHCI_RESET_EP_QUIRK (1 << 1) 1786 #define XHCI_NEC_HOST (1 << 2) 1787 #define XHCI_AMD_PLL_FIX (1 << 3) 1788 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1789 /* 1790 * Certain Intel host controllers have a limit to the number of endpoint 1791 * contexts they can handle. Ideally, they would signal that they can't handle 1792 * anymore endpoint contexts by returning a Resource Error for the Configure 1793 * Endpoint command, but they don't. Instead they expect software to keep track 1794 * of the number of active endpoints for them, across configure endpoint 1795 * commands, reset device commands, disable slot commands, and address device 1796 * commands. 1797 */ 1798 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1799 #define XHCI_BROKEN_MSI (1 << 6) 1800 #define XHCI_RESET_ON_RESUME (1 << 7) 1801 #define XHCI_SW_BW_CHECKING (1 << 8) 1802 #define XHCI_AMD_0x96_HOST (1 << 9) 1803 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1804 #define XHCI_LPM_SUPPORT (1 << 11) 1805 #define XHCI_INTEL_HOST (1 << 12) 1806 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1807 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1808 #define XHCI_AVOID_BEI (1 << 15) 1809 #define XHCI_PLAT (1 << 16) 1810 #define XHCI_SLOW_SUSPEND (1 << 17) 1811 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1812 /* For controllers with a broken beyond repair streams implementation */ 1813 #define XHCI_BROKEN_STREAMS (1 << 19) 1814 #define XHCI_PME_STUCK_QUIRK (1 << 20) 1815 #define XHCI_MTK_HOST (1 << 21) 1816 #define XHCI_SSIC_PORT_UNUSED (1 << 22) 1817 #define XHCI_NO_64BIT_SUPPORT (1 << 23) 1818 #define XHCI_MISSING_CAS (1 << 24) 1819 /* For controller with a broken Port Disable implementation */ 1820 #define XHCI_BROKEN_PORT_PED (1 << 25) 1821 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) 1822 #define XHCI_U2_DISABLE_WAKE (1 << 27) 1823 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) 1824 1825 unsigned int num_active_eps; 1826 unsigned int limit_active_eps; 1827 /* There are two roothubs to keep track of bus suspend info for */ 1828 struct xhci_bus_state bus_state[2]; 1829 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1830 u8 *port_array; 1831 /* Array of pointers to USB 3.0 PORTSC registers */ 1832 __le32 __iomem **usb3_ports; 1833 unsigned int num_usb3_ports; 1834 /* Array of pointers to USB 2.0 PORTSC registers */ 1835 __le32 __iomem **usb2_ports; 1836 struct xhci_hub usb2_rhub; 1837 struct xhci_hub usb3_rhub; 1838 unsigned int num_usb2_ports; 1839 /* support xHCI 0.96 spec USB2 software LPM */ 1840 unsigned sw_lpm_support:1; 1841 /* support xHCI 1.0 spec USB2 hardware LPM */ 1842 unsigned hw_lpm_support:1; 1843 /* cached usb2 extened protocol capabilites */ 1844 u32 *ext_caps; 1845 unsigned int num_ext_caps; 1846 /* Compliance Mode Recovery Data */ 1847 struct timer_list comp_mode_recovery_timer; 1848 u32 port_status_u0; 1849 u16 test_mode; 1850 /* Compliance Mode Timer Triggered every 2 seconds */ 1851 #define COMP_MODE_RCVRY_MSECS 2000 1852 1853 /* platform-specific data -- must come last */ 1854 unsigned long priv[0] __aligned(sizeof(s64)); 1855 }; 1856 1857 /* Platform specific overrides to generic XHCI hc_driver ops */ 1858 struct xhci_driver_overrides { 1859 size_t extra_priv_size; 1860 int (*reset)(struct usb_hcd *hcd); 1861 int (*start)(struct usb_hcd *hcd); 1862 }; 1863 1864 #define XHCI_CFC_DELAY 10 1865 1866 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1867 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1868 { 1869 struct usb_hcd *primary_hcd; 1870 1871 if (usb_hcd_is_primary_hcd(hcd)) 1872 primary_hcd = hcd; 1873 else 1874 primary_hcd = hcd->primary_hcd; 1875 1876 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1877 } 1878 1879 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1880 { 1881 return xhci->main_hcd; 1882 } 1883 1884 #define xhci_dbg(xhci, fmt, args...) \ 1885 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1886 #define xhci_err(xhci, fmt, args...) \ 1887 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1888 #define xhci_warn(xhci, fmt, args...) \ 1889 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1890 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1891 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1892 #define xhci_info(xhci, fmt, args...) \ 1893 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1894 1895 /* 1896 * Registers should always be accessed with double word or quad word accesses. 1897 * 1898 * Some xHCI implementations may support 64-bit address pointers. Registers 1899 * with 64-bit address pointers should be written to with dword accesses by 1900 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1901 * xHCI implementations that do not support 64-bit address pointers will ignore 1902 * the high dword, and write order is irrelevant. 1903 */ 1904 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1905 __le64 __iomem *regs) 1906 { 1907 return lo_hi_readq(regs); 1908 } 1909 static inline void xhci_write_64(struct xhci_hcd *xhci, 1910 const u64 val, __le64 __iomem *regs) 1911 { 1912 lo_hi_writeq(val, regs); 1913 } 1914 1915 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1916 { 1917 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1918 } 1919 1920 /* xHCI debugging */ 1921 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1922 void xhci_print_registers(struct xhci_hcd *xhci); 1923 void xhci_dbg_regs(struct xhci_hcd *xhci); 1924 void xhci_print_run_regs(struct xhci_hcd *xhci); 1925 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1926 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1927 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1928 struct xhci_container_ctx *ctx); 1929 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1930 const char *fmt, ...); 1931 1932 /* xHCI memory management */ 1933 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1934 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1935 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1936 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1937 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1938 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1939 struct usb_device *udev); 1940 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1941 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1942 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1943 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1944 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1945 struct xhci_virt_device *virt_dev, 1946 int old_active_eps); 1947 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1948 void xhci_update_bw_info(struct xhci_hcd *xhci, 1949 struct xhci_container_ctx *in_ctx, 1950 struct xhci_input_control_ctx *ctrl_ctx, 1951 struct xhci_virt_device *virt_dev); 1952 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1953 struct xhci_container_ctx *in_ctx, 1954 struct xhci_container_ctx *out_ctx, 1955 unsigned int ep_index); 1956 void xhci_slot_copy(struct xhci_hcd *xhci, 1957 struct xhci_container_ctx *in_ctx, 1958 struct xhci_container_ctx *out_ctx); 1959 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1960 struct usb_device *udev, struct usb_host_endpoint *ep, 1961 gfp_t mem_flags); 1962 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1963 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1964 unsigned int num_trbs, gfp_t flags); 1965 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1966 struct xhci_virt_device *virt_dev, 1967 unsigned int ep_index); 1968 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1969 unsigned int num_stream_ctxs, 1970 unsigned int num_streams, 1971 unsigned int max_packet, gfp_t flags); 1972 void xhci_free_stream_info(struct xhci_hcd *xhci, 1973 struct xhci_stream_info *stream_info); 1974 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1975 struct xhci_ep_ctx *ep_ctx, 1976 struct xhci_stream_info *stream_info); 1977 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1978 struct xhci_virt_ep *ep); 1979 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1980 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1981 struct xhci_ring *xhci_dma_to_transfer_ring( 1982 struct xhci_virt_ep *ep, 1983 u64 address); 1984 struct xhci_ring *xhci_stream_id_to_ring( 1985 struct xhci_virt_device *dev, 1986 unsigned int ep_index, 1987 unsigned int stream_id); 1988 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1989 bool allocate_in_ctx, bool allocate_completion, 1990 gfp_t mem_flags); 1991 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1992 void xhci_free_command(struct xhci_hcd *xhci, 1993 struct xhci_command *command); 1994 1995 /* xHCI host controller glue */ 1996 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1997 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 1998 void xhci_quiesce(struct xhci_hcd *xhci); 1999 int xhci_halt(struct xhci_hcd *xhci); 2000 int xhci_start(struct xhci_hcd *xhci); 2001 int xhci_reset(struct xhci_hcd *xhci); 2002 int xhci_run(struct usb_hcd *hcd); 2003 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2004 void xhci_init_driver(struct hc_driver *drv, 2005 const struct xhci_driver_overrides *over); 2006 int xhci_disable_slot(struct xhci_hcd *xhci, 2007 struct xhci_command *command, u32 slot_id); 2008 2009 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2010 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 2011 2012 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2013 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2014 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2015 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2016 struct xhci_virt_device *virt_dev, 2017 struct usb_device *hdev, 2018 struct usb_tt *tt, gfp_t mem_flags); 2019 2020 /* xHCI ring, segment, TRB, and TD functions */ 2021 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2022 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2023 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2024 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2025 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2026 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2027 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2028 u32 trb_type, u32 slot_id); 2029 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2030 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2031 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2032 u32 field1, u32 field2, u32 field3, u32 field4); 2033 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2034 int slot_id, unsigned int ep_index, int suspend); 2035 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2036 int slot_id, unsigned int ep_index); 2037 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2038 int slot_id, unsigned int ep_index); 2039 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2040 int slot_id, unsigned int ep_index); 2041 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2042 struct urb *urb, int slot_id, unsigned int ep_index); 2043 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2044 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2045 bool command_must_succeed); 2046 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2047 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2048 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2049 int slot_id, unsigned int ep_index, 2050 enum xhci_ep_reset_type reset_type); 2051 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2052 u32 slot_id); 2053 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 2054 unsigned int slot_id, unsigned int ep_index, 2055 unsigned int stream_id, struct xhci_td *cur_td, 2056 struct xhci_dequeue_state *state); 2057 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 2058 unsigned int slot_id, unsigned int ep_index, 2059 struct xhci_dequeue_state *deq_state); 2060 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index, 2061 unsigned int stream_id, struct xhci_td *td); 2062 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 2063 void xhci_handle_command_timeout(struct work_struct *work); 2064 2065 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2066 unsigned int ep_index, unsigned int stream_id); 2067 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2068 2069 /* xHCI roothub code */ 2070 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2071 int port_id, u32 link_state); 2072 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2073 int port_id, u32 port_bit); 2074 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2075 char *buf, u16 wLength); 2076 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2077 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2078 void xhci_hc_died(struct xhci_hcd *xhci); 2079 2080 #ifdef CONFIG_PM 2081 int xhci_bus_suspend(struct usb_hcd *hcd); 2082 int xhci_bus_resume(struct usb_hcd *hcd); 2083 #else 2084 #define xhci_bus_suspend NULL 2085 #define xhci_bus_resume NULL 2086 #endif /* CONFIG_PM */ 2087 2088 u32 xhci_port_state_to_neutral(u32 state); 2089 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2090 u16 port); 2091 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2092 2093 /* xHCI contexts */ 2094 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2095 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2096 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2097 2098 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2099 unsigned int slot_id, unsigned int ep_index, 2100 unsigned int stream_id); 2101 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2102 struct urb *urb) 2103 { 2104 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2105 xhci_get_endpoint_index(&urb->ep->desc), 2106 urb->stream_id); 2107 } 2108 2109 static inline char *xhci_slot_state_string(u32 state) 2110 { 2111 switch (state) { 2112 case SLOT_STATE_ENABLED: 2113 return "enabled/disabled"; 2114 case SLOT_STATE_DEFAULT: 2115 return "default"; 2116 case SLOT_STATE_ADDRESSED: 2117 return "addressed"; 2118 case SLOT_STATE_CONFIGURED: 2119 return "configured"; 2120 default: 2121 return "reserved"; 2122 } 2123 } 2124 2125 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, 2126 u32 field3) 2127 { 2128 static char str[256]; 2129 int type = TRB_FIELD_TO_TYPE(field3); 2130 2131 switch (type) { 2132 case TRB_LINK: 2133 sprintf(str, 2134 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2135 field1, field0, GET_INTR_TARGET(field2), 2136 xhci_trb_type_string(type), 2137 field3 & TRB_IOC ? 'I' : 'i', 2138 field3 & TRB_CHAIN ? 'C' : 'c', 2139 field3 & TRB_TC ? 'T' : 't', 2140 field3 & TRB_CYCLE ? 'C' : 'c'); 2141 break; 2142 case TRB_TRANSFER: 2143 case TRB_COMPLETION: 2144 case TRB_PORT_STATUS: 2145 case TRB_BANDWIDTH_EVENT: 2146 case TRB_DOORBELL: 2147 case TRB_HC_EVENT: 2148 case TRB_DEV_NOTE: 2149 case TRB_MFINDEX_WRAP: 2150 sprintf(str, 2151 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2152 field1, field0, 2153 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2154 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2155 /* Macro decrements 1, maybe it shouldn't?!? */ 2156 TRB_TO_EP_INDEX(field3) + 1, 2157 xhci_trb_type_string(type), 2158 field3 & EVENT_DATA ? 'E' : 'e', 2159 field3 & TRB_CYCLE ? 'C' : 'c'); 2160 2161 break; 2162 case TRB_SETUP: 2163 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2164 field0 & 0xff, 2165 (field0 & 0xff00) >> 8, 2166 (field0 & 0xff000000) >> 24, 2167 (field0 & 0xff0000) >> 16, 2168 (field1 & 0xff00) >> 8, 2169 field1 & 0xff, 2170 (field1 & 0xff000000) >> 16 | 2171 (field1 & 0xff0000) >> 16, 2172 TRB_LEN(field2), GET_TD_SIZE(field2), 2173 GET_INTR_TARGET(field2), 2174 xhci_trb_type_string(type), 2175 field3 & TRB_IDT ? 'I' : 'i', 2176 field3 & TRB_IOC ? 'I' : 'i', 2177 field3 & TRB_CYCLE ? 'C' : 'c'); 2178 break; 2179 case TRB_DATA: 2180 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2181 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2182 GET_INTR_TARGET(field2), 2183 xhci_trb_type_string(type), 2184 field3 & TRB_IDT ? 'I' : 'i', 2185 field3 & TRB_IOC ? 'I' : 'i', 2186 field3 & TRB_CHAIN ? 'C' : 'c', 2187 field3 & TRB_NO_SNOOP ? 'S' : 's', 2188 field3 & TRB_ISP ? 'I' : 'i', 2189 field3 & TRB_ENT ? 'E' : 'e', 2190 field3 & TRB_CYCLE ? 'C' : 'c'); 2191 break; 2192 case TRB_STATUS: 2193 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2194 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2195 GET_INTR_TARGET(field2), 2196 xhci_trb_type_string(type), 2197 field3 & TRB_IOC ? 'I' : 'i', 2198 field3 & TRB_CHAIN ? 'C' : 'c', 2199 field3 & TRB_ENT ? 'E' : 'e', 2200 field3 & TRB_CYCLE ? 'C' : 'c'); 2201 break; 2202 case TRB_NORMAL: 2203 case TRB_ISOC: 2204 case TRB_EVENT_DATA: 2205 case TRB_TR_NOOP: 2206 sprintf(str, 2207 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2208 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2209 GET_INTR_TARGET(field2), 2210 xhci_trb_type_string(type), 2211 field3 & TRB_BEI ? 'B' : 'b', 2212 field3 & TRB_IDT ? 'I' : 'i', 2213 field3 & TRB_IOC ? 'I' : 'i', 2214 field3 & TRB_CHAIN ? 'C' : 'c', 2215 field3 & TRB_NO_SNOOP ? 'S' : 's', 2216 field3 & TRB_ISP ? 'I' : 'i', 2217 field3 & TRB_ENT ? 'E' : 'e', 2218 field3 & TRB_CYCLE ? 'C' : 'c'); 2219 break; 2220 2221 case TRB_CMD_NOOP: 2222 case TRB_ENABLE_SLOT: 2223 sprintf(str, 2224 "%s: flags %c", 2225 xhci_trb_type_string(type), 2226 field3 & TRB_CYCLE ? 'C' : 'c'); 2227 break; 2228 case TRB_DISABLE_SLOT: 2229 case TRB_NEG_BANDWIDTH: 2230 sprintf(str, 2231 "%s: slot %d flags %c", 2232 xhci_trb_type_string(type), 2233 TRB_TO_SLOT_ID(field3), 2234 field3 & TRB_CYCLE ? 'C' : 'c'); 2235 break; 2236 case TRB_ADDR_DEV: 2237 sprintf(str, 2238 "%s: ctx %08x%08x slot %d flags %c:%c", 2239 xhci_trb_type_string(type), 2240 field1, field0, 2241 TRB_TO_SLOT_ID(field3), 2242 field3 & TRB_BSR ? 'B' : 'b', 2243 field3 & TRB_CYCLE ? 'C' : 'c'); 2244 break; 2245 case TRB_CONFIG_EP: 2246 sprintf(str, 2247 "%s: ctx %08x%08x slot %d flags %c:%c", 2248 xhci_trb_type_string(type), 2249 field1, field0, 2250 TRB_TO_SLOT_ID(field3), 2251 field3 & TRB_DC ? 'D' : 'd', 2252 field3 & TRB_CYCLE ? 'C' : 'c'); 2253 break; 2254 case TRB_EVAL_CONTEXT: 2255 sprintf(str, 2256 "%s: ctx %08x%08x slot %d flags %c", 2257 xhci_trb_type_string(type), 2258 field1, field0, 2259 TRB_TO_SLOT_ID(field3), 2260 field3 & TRB_CYCLE ? 'C' : 'c'); 2261 break; 2262 case TRB_RESET_EP: 2263 sprintf(str, 2264 "%s: ctx %08x%08x slot %d ep %d flags %c", 2265 xhci_trb_type_string(type), 2266 field1, field0, 2267 TRB_TO_SLOT_ID(field3), 2268 /* Macro decrements 1, maybe it shouldn't?!? */ 2269 TRB_TO_EP_INDEX(field3) + 1, 2270 field3 & TRB_CYCLE ? 'C' : 'c'); 2271 break; 2272 case TRB_STOP_RING: 2273 sprintf(str, 2274 "%s: slot %d sp %d ep %d flags %c", 2275 xhci_trb_type_string(type), 2276 TRB_TO_SLOT_ID(field3), 2277 TRB_TO_SUSPEND_PORT(field3), 2278 /* Macro decrements 1, maybe it shouldn't?!? */ 2279 TRB_TO_EP_INDEX(field3) + 1, 2280 field3 & TRB_CYCLE ? 'C' : 'c'); 2281 break; 2282 case TRB_SET_DEQ: 2283 sprintf(str, 2284 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2285 xhci_trb_type_string(type), 2286 field1, field0, 2287 TRB_TO_STREAM_ID(field2), 2288 TRB_TO_SLOT_ID(field3), 2289 /* Macro decrements 1, maybe it shouldn't?!? */ 2290 TRB_TO_EP_INDEX(field3) + 1, 2291 field3 & TRB_CYCLE ? 'C' : 'c'); 2292 break; 2293 case TRB_RESET_DEV: 2294 sprintf(str, 2295 "%s: slot %d flags %c", 2296 xhci_trb_type_string(type), 2297 TRB_TO_SLOT_ID(field3), 2298 field3 & TRB_CYCLE ? 'C' : 'c'); 2299 break; 2300 case TRB_FORCE_EVENT: 2301 sprintf(str, 2302 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2303 xhci_trb_type_string(type), 2304 field1, field0, 2305 TRB_TO_VF_INTR_TARGET(field2), 2306 TRB_TO_VF_ID(field3), 2307 field3 & TRB_CYCLE ? 'C' : 'c'); 2308 break; 2309 case TRB_SET_LT: 2310 sprintf(str, 2311 "%s: belt %d flags %c", 2312 xhci_trb_type_string(type), 2313 TRB_TO_BELT(field3), 2314 field3 & TRB_CYCLE ? 'C' : 'c'); 2315 break; 2316 case TRB_GET_BW: 2317 sprintf(str, 2318 "%s: ctx %08x%08x slot %d speed %d flags %c", 2319 xhci_trb_type_string(type), 2320 field1, field0, 2321 TRB_TO_SLOT_ID(field3), 2322 TRB_TO_DEV_SPEED(field3), 2323 field3 & TRB_CYCLE ? 'C' : 'c'); 2324 break; 2325 case TRB_FORCE_HEADER: 2326 sprintf(str, 2327 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2328 xhci_trb_type_string(type), 2329 field2, field1, field0 & 0xffffffe0, 2330 TRB_TO_PACKET_TYPE(field0), 2331 TRB_TO_ROOTHUB_PORT(field3), 2332 field3 & TRB_CYCLE ? 'C' : 'c'); 2333 break; 2334 default: 2335 sprintf(str, 2336 "type '%s' -> raw %08x %08x %08x %08x", 2337 xhci_trb_type_string(type), 2338 field0, field1, field2, field3); 2339 } 2340 2341 return str; 2342 } 2343 2344 static inline const char *xhci_decode_slot_context(u32 info, u32 info2, 2345 u32 tt_info, u32 state) 2346 { 2347 static char str[1024]; 2348 u32 speed; 2349 u32 hub; 2350 u32 mtt; 2351 int ret = 0; 2352 2353 speed = info & DEV_SPEED; 2354 hub = info & DEV_HUB; 2355 mtt = info & DEV_MTT; 2356 2357 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2358 info & ROUTE_STRING_MASK, 2359 ({ char *s; 2360 switch (speed) { 2361 case SLOT_SPEED_FS: 2362 s = "full-speed"; 2363 break; 2364 case SLOT_SPEED_LS: 2365 s = "low-speed"; 2366 break; 2367 case SLOT_SPEED_HS: 2368 s = "high-speed"; 2369 break; 2370 case SLOT_SPEED_SS: 2371 s = "super-speed"; 2372 break; 2373 case SLOT_SPEED_SSP: 2374 s = "super-speed plus"; 2375 break; 2376 default: 2377 s = "UNKNOWN speed"; 2378 } s; }), 2379 mtt ? " multi-TT" : "", 2380 hub ? " Hub" : "", 2381 (info & LAST_CTX_MASK) >> 27, 2382 info2 & MAX_EXIT, 2383 DEVINFO_TO_ROOT_HUB_PORT(info2), 2384 DEVINFO_TO_MAX_PORTS(info2)); 2385 2386 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2387 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2388 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2389 state & DEV_ADDR_MASK, 2390 xhci_slot_state_string(GET_SLOT_STATE(state))); 2391 2392 return str; 2393 } 2394 2395 static inline const char *xhci_ep_state_string(u8 state) 2396 { 2397 switch (state) { 2398 case EP_STATE_DISABLED: 2399 return "disabled"; 2400 case EP_STATE_RUNNING: 2401 return "running"; 2402 case EP_STATE_HALTED: 2403 return "halted"; 2404 case EP_STATE_STOPPED: 2405 return "stopped"; 2406 case EP_STATE_ERROR: 2407 return "error"; 2408 default: 2409 return "INVALID"; 2410 } 2411 } 2412 2413 static inline const char *xhci_ep_type_string(u8 type) 2414 { 2415 switch (type) { 2416 case ISOC_OUT_EP: 2417 return "Isoc OUT"; 2418 case BULK_OUT_EP: 2419 return "Bulk OUT"; 2420 case INT_OUT_EP: 2421 return "Int OUT"; 2422 case CTRL_EP: 2423 return "Ctrl"; 2424 case ISOC_IN_EP: 2425 return "Isoc IN"; 2426 case BULK_IN_EP: 2427 return "Bulk IN"; 2428 case INT_IN_EP: 2429 return "Int IN"; 2430 default: 2431 return "INVALID"; 2432 } 2433 } 2434 2435 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq, 2436 u32 tx_info) 2437 { 2438 static char str[1024]; 2439 int ret; 2440 2441 u32 esit; 2442 u16 maxp; 2443 u16 avg; 2444 2445 u8 max_pstr; 2446 u8 ep_state; 2447 u8 interval; 2448 u8 ep_type; 2449 u8 burst; 2450 u8 cerr; 2451 u8 mult; 2452 u8 lsa; 2453 u8 hid; 2454 2455 esit = EP_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2456 EP_MAX_ESIT_PAYLOAD_LO(tx_info); 2457 2458 ep_state = info & EP_STATE_MASK; 2459 max_pstr = info & EP_MAXPSTREAMS_MASK; 2460 interval = CTX_TO_EP_INTERVAL(info); 2461 mult = CTX_TO_EP_MULT(info) + 1; 2462 lsa = info & EP_HAS_LSA; 2463 2464 cerr = (info2 & (3 << 1)) >> 1; 2465 ep_type = CTX_TO_EP_TYPE(info2); 2466 hid = info2 & (1 << 7); 2467 burst = CTX_TO_MAX_BURST(info2); 2468 maxp = MAX_PACKET_DECODED(info2); 2469 2470 avg = EP_AVG_TRB_LENGTH(tx_info); 2471 2472 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2473 xhci_ep_state_string(ep_state), mult, 2474 max_pstr, lsa ? "LSA " : ""); 2475 2476 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2477 (1 << interval) * 125, esit, cerr); 2478 2479 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2480 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2481 burst, maxp, deq); 2482 2483 ret += sprintf(str + ret, "avg trb len %d", avg); 2484 2485 return str; 2486 } 2487 2488 #endif /* __LINUX_XHCI_HCD_H */ 2489