1 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __LINUX_XHCI_HCD_H 25 #define __LINUX_XHCI_HCD_H 26 27 #include <linux/usb.h> 28 #include <linux/timer.h> 29 #include <linux/kernel.h> 30 #include <linux/usb/hcd.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 33 /* Code sharing between pci-quirks and xhci hcd */ 34 #include "xhci-ext-caps.h" 35 #include "pci-quirks.h" 36 37 /* xHCI PCI Configuration Registers */ 38 #define XHCI_SBRN_OFFSET (0x60) 39 40 /* Max number of USB devices for any host controller - limit in section 6.1 */ 41 #define MAX_HC_SLOTS 256 42 /* Section 5.3.3 - MaxPorts */ 43 #define MAX_HC_PORTS 127 44 45 /* 46 * xHCI register interface. 47 * This corresponds to the eXtensible Host Controller Interface (xHCI) 48 * Revision 0.95 specification 49 */ 50 51 /** 52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 53 * @hc_capbase: length of the capabilities register and HC version number 54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 57 * @hcc_params: HCCPARAMS - Capability Parameters 58 * @db_off: DBOFF - Doorbell array offset 59 * @run_regs_off: RTSOFF - Runtime register space offset 60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 61 */ 62 struct xhci_cap_regs { 63 __le32 hc_capbase; 64 __le32 hcs_params1; 65 __le32 hcs_params2; 66 __le32 hcs_params3; 67 __le32 hcc_params; 68 __le32 db_off; 69 __le32 run_regs_off; 70 __le32 hcc_params2; /* xhci 1.1 */ 71 /* Reserved up to (CAPLENGTH - 0x1C) */ 72 }; 73 74 /* hc_capbase bitmasks */ 75 /* bits 7:0 - how long is the Capabilities register */ 76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 77 /* bits 31:16 */ 78 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 79 80 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 81 /* bits 0:7, Max Device Slots */ 82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 83 #define HCS_SLOTS_MASK 0xff 84 /* bits 8:18, Max Interrupters */ 85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 88 89 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 90 /* bits 0:3, frames or uframes that SW needs to queue transactions 91 * ahead of the HW to meet periodic deadlines */ 92 #define HCS_IST(p) (((p) >> 0) & 0xf) 93 /* bits 4:7, max number of Event Ring segments */ 94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 99 100 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 105 106 /* HCCPARAMS - hcc_params - bitmasks */ 107 /* true: HC can use 64-bit address pointers */ 108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 109 /* true: HC can do bandwidth negotiation */ 110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 111 /* true: HC uses 64-byte Device Context structures 112 * FIXME 64-byte context structures aren't supported yet. 113 */ 114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 115 /* true: HC has port power switches */ 116 #define HCC_PPC(p) ((p) & (1 << 3)) 117 /* true: HC has port indicators */ 118 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 119 /* true: HC has Light HC Reset Capability */ 120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 121 /* true: HC supports latency tolerance messaging */ 122 #define HCC_LTC(p) ((p) & (1 << 6)) 123 /* true: no secondary Stream ID Support */ 124 #define HCC_NSS(p) ((p) & (1 << 7)) 125 /* true: HC supports Stopped - Short Packet */ 126 #define HCC_SPC(p) ((p) & (1 << 9)) 127 /* true: HC has Contiguous Frame ID Capability */ 128 #define HCC_CFC(p) ((p) & (1 << 11)) 129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 133 134 /* db_off bitmask - bits 0:1 reserved */ 135 #define DBOFF_MASK (~0x3) 136 137 /* run_regs_off bitmask - bits 0:4 reserved */ 138 #define RTSOFF_MASK (~0x1f) 139 140 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 141 /* true: HC supports U3 entry Capability */ 142 #define HCC2_U3C(p) ((p) & (1 << 0)) 143 /* true: HC supports Configure endpoint command Max exit latency too large */ 144 #define HCC2_CMC(p) ((p) & (1 << 1)) 145 /* true: HC supports Force Save context Capability */ 146 #define HCC2_FSC(p) ((p) & (1 << 2)) 147 /* true: HC supports Compliance Transition Capability */ 148 #define HCC2_CTC(p) ((p) & (1 << 3)) 149 /* true: HC support Large ESIT payload Capability > 48k */ 150 #define HCC2_LEC(p) ((p) & (1 << 4)) 151 /* true: HC support Configuration Information Capability */ 152 #define HCC2_CIC(p) ((p) & (1 << 5)) 153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 154 #define HCC2_ETC(p) ((p) & (1 << 6)) 155 156 /* Number of registers per port */ 157 #define NUM_PORT_REGS 4 158 159 #define PORTSC 0 160 #define PORTPMSC 1 161 #define PORTLI 2 162 #define PORTHLPMC 3 163 164 /** 165 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 166 * @command: USBCMD - xHC command register 167 * @status: USBSTS - xHC status register 168 * @page_size: This indicates the page size that the host controller 169 * supports. If bit n is set, the HC supports a page size 170 * of 2^(n+12), up to a 128MB page size. 171 * 4K is the minimum page size. 172 * @cmd_ring: CRP - 64-bit Command Ring Pointer 173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 174 * @config_reg: CONFIG - Configure Register 175 * @port_status_base: PORTSCn - base address for Port Status and Control 176 * Each port has a Port Status and Control register, 177 * followed by a Port Power Management Status and Control 178 * register, a Port Link Info register, and a reserved 179 * register. 180 * @port_power_base: PORTPMSCn - base address for 181 * Port Power Management Status and Control 182 * @port_link_base: PORTLIn - base address for Port Link Info (current 183 * Link PM state and control) for USB 2.1 and USB 3.0 184 * devices. 185 */ 186 struct xhci_op_regs { 187 __le32 command; 188 __le32 status; 189 __le32 page_size; 190 __le32 reserved1; 191 __le32 reserved2; 192 __le32 dev_notification; 193 __le64 cmd_ring; 194 /* rsvd: offset 0x20-2F */ 195 __le32 reserved3[4]; 196 __le64 dcbaa_ptr; 197 __le32 config_reg; 198 /* rsvd: offset 0x3C-3FF */ 199 __le32 reserved4[241]; 200 /* port 1 registers, which serve as a base address for other ports */ 201 __le32 port_status_base; 202 __le32 port_power_base; 203 __le32 port_link_base; 204 __le32 reserved5; 205 /* registers for ports 2-255 */ 206 __le32 reserved6[NUM_PORT_REGS*254]; 207 }; 208 209 /* USBCMD - USB command - command bitmasks */ 210 /* start/stop HC execution - do not write unless HC is halted*/ 211 #define CMD_RUN XHCI_CMD_RUN 212 /* Reset HC - resets internal HC state machine and all registers (except 213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 214 * The xHCI driver must reinitialize the xHC after setting this bit. 215 */ 216 #define CMD_RESET (1 << 1) 217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 218 #define CMD_EIE XHCI_CMD_EIE 219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 220 #define CMD_HSEIE XHCI_CMD_HSEIE 221 /* bits 4:6 are reserved (and should be preserved on writes). */ 222 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 223 #define CMD_LRESET (1 << 7) 224 /* host controller save/restore state. */ 225 #define CMD_CSS (1 << 8) 226 #define CMD_CRS (1 << 9) 227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 228 #define CMD_EWE XHCI_CMD_EWE 229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 231 * '0' means the xHC can power it off if all ports are in the disconnect, 232 * disabled, or powered-off state. 233 */ 234 #define CMD_PM_INDEX (1 << 11) 235 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 236 #define CMD_ETE (1 << 14) 237 /* bits 15:31 are reserved (and should be preserved on writes). */ 238 239 /* IMAN - Interrupt Management Register */ 240 #define IMAN_IE (1 << 1) 241 #define IMAN_IP (1 << 0) 242 243 /* USBSTS - USB status - status bitmasks */ 244 /* HC not running - set to 1 when run/stop bit is cleared. */ 245 #define STS_HALT XHCI_STS_HALT 246 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 247 #define STS_FATAL (1 << 2) 248 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 249 #define STS_EINT (1 << 3) 250 /* port change detect */ 251 #define STS_PORT (1 << 4) 252 /* bits 5:7 reserved and zeroed */ 253 /* save state status - '1' means xHC is saving state */ 254 #define STS_SAVE (1 << 8) 255 /* restore state status - '1' means xHC is restoring state */ 256 #define STS_RESTORE (1 << 9) 257 /* true: save or restore error */ 258 #define STS_SRE (1 << 10) 259 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 260 #define STS_CNR XHCI_STS_CNR 261 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 262 #define STS_HCE (1 << 12) 263 /* bits 13:31 reserved and should be preserved */ 264 265 /* 266 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 267 * Generate a device notification event when the HC sees a transaction with a 268 * notification type that matches a bit set in this bit field. 269 */ 270 #define DEV_NOTE_MASK (0xffff) 271 #define ENABLE_DEV_NOTE(x) (1 << (x)) 272 /* Most of the device notification types should only be used for debug. 273 * SW does need to pay attention to function wake notifications. 274 */ 275 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 276 277 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 278 /* bit 0 is the command ring cycle state */ 279 /* stop ring operation after completion of the currently executing command */ 280 #define CMD_RING_PAUSE (1 << 1) 281 /* stop ring immediately - abort the currently executing command */ 282 #define CMD_RING_ABORT (1 << 2) 283 /* true: command ring is running */ 284 #define CMD_RING_RUNNING (1 << 3) 285 /* bits 4:5 reserved and should be preserved */ 286 /* Command Ring pointer - bit mask for the lower 32 bits. */ 287 #define CMD_RING_RSVD_BITS (0x3f) 288 289 /* CONFIG - Configure Register - config_reg bitmasks */ 290 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 291 #define MAX_DEVS(p) ((p) & 0xff) 292 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 293 #define CONFIG_U3E (1 << 8) 294 /* bit 9: Configuration Information Enable, xhci 1.1 */ 295 #define CONFIG_CIE (1 << 9) 296 /* bits 10:31 - reserved and should be preserved */ 297 298 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 299 /* true: device connected */ 300 #define PORT_CONNECT (1 << 0) 301 /* true: port enabled */ 302 #define PORT_PE (1 << 1) 303 /* bit 2 reserved and zeroed */ 304 /* true: port has an over-current condition */ 305 #define PORT_OC (1 << 3) 306 /* true: port reset signaling asserted */ 307 #define PORT_RESET (1 << 4) 308 /* Port Link State - bits 5:8 309 * A read gives the current link PM state of the port, 310 * a write with Link State Write Strobe set sets the link state. 311 */ 312 #define PORT_PLS_MASK (0xf << 5) 313 #define XDEV_U0 (0x0 << 5) 314 #define XDEV_U1 (0x1 << 5) 315 #define XDEV_U2 (0x2 << 5) 316 #define XDEV_U3 (0x3 << 5) 317 #define XDEV_DISABLED (0x4 << 5) 318 #define XDEV_RXDETECT (0x5 << 5) 319 #define XDEV_INACTIVE (0x6 << 5) 320 #define XDEV_POLLING (0x7 << 5) 321 #define XDEV_RECOVERY (0x8 << 5) 322 #define XDEV_HOT_RESET (0x9 << 5) 323 #define XDEV_COMP_MODE (0xa << 5) 324 #define XDEV_TEST_MODE (0xb << 5) 325 #define XDEV_RESUME (0xf << 5) 326 327 /* true: port has power (see HCC_PPC) */ 328 #define PORT_POWER (1 << 9) 329 /* bits 10:13 indicate device speed: 330 * 0 - undefined speed - port hasn't be initialized by a reset yet 331 * 1 - full speed 332 * 2 - low speed 333 * 3 - high speed 334 * 4 - super speed 335 * 5-15 reserved 336 */ 337 #define DEV_SPEED_MASK (0xf << 10) 338 #define XDEV_FS (0x1 << 10) 339 #define XDEV_LS (0x2 << 10) 340 #define XDEV_HS (0x3 << 10) 341 #define XDEV_SS (0x4 << 10) 342 #define XDEV_SSP (0x5 << 10) 343 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 344 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 345 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 346 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 347 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 348 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 349 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 350 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 351 352 /* Bits 20:23 in the Slot Context are the speed for the device */ 353 #define SLOT_SPEED_FS (XDEV_FS << 10) 354 #define SLOT_SPEED_LS (XDEV_LS << 10) 355 #define SLOT_SPEED_HS (XDEV_HS << 10) 356 #define SLOT_SPEED_SS (XDEV_SS << 10) 357 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 358 /* Port Indicator Control */ 359 #define PORT_LED_OFF (0 << 14) 360 #define PORT_LED_AMBER (1 << 14) 361 #define PORT_LED_GREEN (2 << 14) 362 #define PORT_LED_MASK (3 << 14) 363 /* Port Link State Write Strobe - set this when changing link state */ 364 #define PORT_LINK_STROBE (1 << 16) 365 /* true: connect status change */ 366 #define PORT_CSC (1 << 17) 367 /* true: port enable change */ 368 #define PORT_PEC (1 << 18) 369 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 370 * into an enabled state, and the device into the default state. A "warm" reset 371 * also resets the link, forcing the device through the link training sequence. 372 * SW can also look at the Port Reset register to see when warm reset is done. 373 */ 374 #define PORT_WRC (1 << 19) 375 /* true: over-current change */ 376 #define PORT_OCC (1 << 20) 377 /* true: reset change - 1 to 0 transition of PORT_RESET */ 378 #define PORT_RC (1 << 21) 379 /* port link status change - set on some port link state transitions: 380 * Transition Reason 381 * ------------------------------------------------------------------------------ 382 * - U3 to Resume Wakeup signaling from a device 383 * - Resume to Recovery to U0 USB 3.0 device resume 384 * - Resume to U0 USB 2.0 device resume 385 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 386 * - U3 to U0 Software resume of USB 2.0 device complete 387 * - U2 to U0 L1 resume of USB 2.1 device complete 388 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 389 * - U0 to disabled L1 entry error with USB 2.1 device 390 * - Any state to inactive Error on USB 3.0 port 391 */ 392 #define PORT_PLC (1 << 22) 393 /* port configure error change - port failed to configure its link partner */ 394 #define PORT_CEC (1 << 23) 395 /* Cold Attach Status - xHC can set this bit to report device attached during 396 * Sx state. Warm port reset should be perfomed to clear this bit and move port 397 * to connected state. 398 */ 399 #define PORT_CAS (1 << 24) 400 /* wake on connect (enable) */ 401 #define PORT_WKCONN_E (1 << 25) 402 /* wake on disconnect (enable) */ 403 #define PORT_WKDISC_E (1 << 26) 404 /* wake on over-current (enable) */ 405 #define PORT_WKOC_E (1 << 27) 406 /* bits 28:29 reserved */ 407 /* true: device is non-removable - for USB 3.0 roothub emulation */ 408 #define PORT_DEV_REMOVE (1 << 30) 409 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 410 #define PORT_WR (1 << 31) 411 412 /* We mark duplicate entries with -1 */ 413 #define DUPLICATE_ENTRY ((u8)(-1)) 414 415 /* Port Power Management Status and Control - port_power_base bitmasks */ 416 /* Inactivity timer value for transitions into U1, in microseconds. 417 * Timeout can be up to 127us. 0xFF means an infinite timeout. 418 */ 419 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 420 #define PORT_U1_TIMEOUT_MASK 0xff 421 /* Inactivity timer value for transitions into U2 */ 422 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 423 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 424 /* Bits 24:31 for port testing */ 425 426 /* USB2 Protocol PORTSPMSC */ 427 #define PORT_L1S_MASK 7 428 #define PORT_L1S_SUCCESS 1 429 #define PORT_RWE (1 << 3) 430 #define PORT_HIRD(p) (((p) & 0xf) << 4) 431 #define PORT_HIRD_MASK (0xf << 4) 432 #define PORT_L1DS_MASK (0xff << 8) 433 #define PORT_L1DS(p) (((p) & 0xff) << 8) 434 #define PORT_HLE (1 << 16) 435 #define PORT_TEST_MODE_SHIFT 28 436 437 /* USB3 Protocol PORTLI Port Link Information */ 438 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 439 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 440 441 /* USB2 Protocol PORTHLPMC */ 442 #define PORT_HIRDM(p)((p) & 3) 443 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 444 #define PORT_BESLD(p)(((p) & 0xf) << 10) 445 446 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 447 #define XHCI_L1_TIMEOUT 512 448 449 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 451 * by other operating systems. 452 * 453 * XHCI 1.0 errata 8/14/12 Table 13 notes: 454 * "Software should choose xHC BESL/BESLD field values that do not violate a 455 * device's resume latency requirements, 456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 457 * or not program values < '4' if BLC = '0' and a BESL device is attached. 458 */ 459 #define XHCI_DEFAULT_BESL 4 460 461 /** 462 * struct xhci_intr_reg - Interrupt Register Set 463 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 464 * interrupts and check for pending interrupts. 465 * @irq_control: IMOD - Interrupt Moderation Register. 466 * Used to throttle interrupts. 467 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 468 * @erst_base: ERST base address. 469 * @erst_dequeue: Event ring dequeue pointer. 470 * 471 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 472 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 473 * multiple segments of the same size. The HC places events on the ring and 474 * "updates the Cycle bit in the TRBs to indicate to software the current 475 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 476 * updates the dequeue pointer. 477 */ 478 struct xhci_intr_reg { 479 __le32 irq_pending; 480 __le32 irq_control; 481 __le32 erst_size; 482 __le32 rsvd; 483 __le64 erst_base; 484 __le64 erst_dequeue; 485 }; 486 487 /* irq_pending bitmasks */ 488 #define ER_IRQ_PENDING(p) ((p) & 0x1) 489 /* bits 2:31 need to be preserved */ 490 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 491 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 492 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 493 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 494 495 /* irq_control bitmasks */ 496 /* Minimum interval between interrupts (in 250ns intervals). The interval 497 * between interrupts will be longer if there are no events on the event ring. 498 * Default is 4000 (1 ms). 499 */ 500 #define ER_IRQ_INTERVAL_MASK (0xffff) 501 /* Counter used to count down the time to the next interrupt - HW use only */ 502 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 503 504 /* erst_size bitmasks */ 505 /* Preserve bits 16:31 of erst_size */ 506 #define ERST_SIZE_MASK (0xffff << 16) 507 508 /* erst_dequeue bitmasks */ 509 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 510 * where the current dequeue pointer lies. This is an optional HW hint. 511 */ 512 #define ERST_DESI_MASK (0x7) 513 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 514 * a work queue (or delayed service routine)? 515 */ 516 #define ERST_EHB (1 << 3) 517 #define ERST_PTR_MASK (0xf) 518 519 /** 520 * struct xhci_run_regs 521 * @microframe_index: 522 * MFINDEX - current microframe number 523 * 524 * Section 5.5 Host Controller Runtime Registers: 525 * "Software should read and write these registers using only Dword (32 bit) 526 * or larger accesses" 527 */ 528 struct xhci_run_regs { 529 __le32 microframe_index; 530 __le32 rsvd[7]; 531 struct xhci_intr_reg ir_set[128]; 532 }; 533 534 /** 535 * struct doorbell_array 536 * 537 * Bits 0 - 7: Endpoint target 538 * Bits 8 - 15: RsvdZ 539 * Bits 16 - 31: Stream ID 540 * 541 * Section 5.6 542 */ 543 struct xhci_doorbell_array { 544 __le32 doorbell[256]; 545 }; 546 547 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 548 #define DB_VALUE_HOST 0x00000000 549 550 /** 551 * struct xhci_protocol_caps 552 * @revision: major revision, minor revision, capability ID, 553 * and next capability pointer. 554 * @name_string: Four ASCII characters to say which spec this xHC 555 * follows, typically "USB ". 556 * @port_info: Port offset, count, and protocol-defined information. 557 */ 558 struct xhci_protocol_caps { 559 u32 revision; 560 u32 name_string; 561 u32 port_info; 562 }; 563 564 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 565 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 566 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 567 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 568 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 569 570 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 571 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 572 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 573 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 574 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 575 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 576 577 #define PLT_MASK (0x03 << 6) 578 #define PLT_SYM (0x00 << 6) 579 #define PLT_ASYM_RX (0x02 << 6) 580 #define PLT_ASYM_TX (0x03 << 6) 581 582 /** 583 * struct xhci_container_ctx 584 * @type: Type of context. Used to calculated offsets to contained contexts. 585 * @size: Size of the context data 586 * @bytes: The raw context data given to HW 587 * @dma: dma address of the bytes 588 * 589 * Represents either a Device or Input context. Holds a pointer to the raw 590 * memory used for the context (bytes) and dma address of it (dma). 591 */ 592 struct xhci_container_ctx { 593 unsigned type; 594 #define XHCI_CTX_TYPE_DEVICE 0x1 595 #define XHCI_CTX_TYPE_INPUT 0x2 596 597 int size; 598 599 u8 *bytes; 600 dma_addr_t dma; 601 }; 602 603 /** 604 * struct xhci_slot_ctx 605 * @dev_info: Route string, device speed, hub info, and last valid endpoint 606 * @dev_info2: Max exit latency for device number, root hub port number 607 * @tt_info: tt_info is used to construct split transaction tokens 608 * @dev_state: slot state and device address 609 * 610 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 611 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 612 * reserved at the end of the slot context for HC internal use. 613 */ 614 struct xhci_slot_ctx { 615 __le32 dev_info; 616 __le32 dev_info2; 617 __le32 tt_info; 618 __le32 dev_state; 619 /* offset 0x10 to 0x1f reserved for HC internal use */ 620 __le32 reserved[4]; 621 }; 622 623 /* dev_info bitmasks */ 624 /* Route String - 0:19 */ 625 #define ROUTE_STRING_MASK (0xfffff) 626 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 627 #define DEV_SPEED (0xf << 20) 628 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 629 /* bit 24 reserved */ 630 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 631 #define DEV_MTT (0x1 << 25) 632 /* Set if the device is a hub - bit 26 */ 633 #define DEV_HUB (0x1 << 26) 634 /* Index of the last valid endpoint context in this device context - 27:31 */ 635 #define LAST_CTX_MASK (0x1f << 27) 636 #define LAST_CTX(p) ((p) << 27) 637 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 638 #define SLOT_FLAG (1 << 0) 639 #define EP0_FLAG (1 << 1) 640 641 /* dev_info2 bitmasks */ 642 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 643 #define MAX_EXIT (0xffff) 644 /* Root hub port number that is needed to access the USB device */ 645 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 646 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 647 /* Maximum number of ports under a hub device */ 648 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 649 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 650 651 /* tt_info bitmasks */ 652 /* 653 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 654 * The Slot ID of the hub that isolates the high speed signaling from 655 * this low or full-speed device. '0' if attached to root hub port. 656 */ 657 #define TT_SLOT (0xff) 658 /* 659 * The number of the downstream facing port of the high-speed hub 660 * '0' if the device is not low or full speed. 661 */ 662 #define TT_PORT (0xff << 8) 663 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 664 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 665 666 /* dev_state bitmasks */ 667 /* USB device address - assigned by the HC */ 668 #define DEV_ADDR_MASK (0xff) 669 /* bits 8:26 reserved */ 670 /* Slot state */ 671 #define SLOT_STATE (0x1f << 27) 672 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 673 674 #define SLOT_STATE_DISABLED 0 675 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 676 #define SLOT_STATE_DEFAULT 1 677 #define SLOT_STATE_ADDRESSED 2 678 #define SLOT_STATE_CONFIGURED 3 679 680 /** 681 * struct xhci_ep_ctx 682 * @ep_info: endpoint state, streams, mult, and interval information. 683 * @ep_info2: information on endpoint type, max packet size, max burst size, 684 * error count, and whether the HC will force an event for all 685 * transactions. 686 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 687 * defines one stream, this points to the endpoint transfer ring. 688 * Otherwise, it points to a stream context array, which has a 689 * ring pointer for each flow. 690 * @tx_info: 691 * Average TRB lengths for the endpoint ring and 692 * max payload within an Endpoint Service Interval Time (ESIT). 693 * 694 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 695 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 696 * reserved at the end of the endpoint context for HC internal use. 697 */ 698 struct xhci_ep_ctx { 699 __le32 ep_info; 700 __le32 ep_info2; 701 __le64 deq; 702 __le32 tx_info; 703 /* offset 0x14 - 0x1f reserved for HC internal use */ 704 __le32 reserved[3]; 705 }; 706 707 /* ep_info bitmasks */ 708 /* 709 * Endpoint State - bits 0:2 710 * 0 - disabled 711 * 1 - running 712 * 2 - halted due to halt condition - ok to manipulate endpoint ring 713 * 3 - stopped 714 * 4 - TRB error 715 * 5-7 - reserved 716 */ 717 #define EP_STATE_MASK (0xf) 718 #define EP_STATE_DISABLED 0 719 #define EP_STATE_RUNNING 1 720 #define EP_STATE_HALTED 2 721 #define EP_STATE_STOPPED 3 722 #define EP_STATE_ERROR 4 723 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 724 725 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 726 #define EP_MULT(p) (((p) & 0x3) << 8) 727 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 728 /* bits 10:14 are Max Primary Streams */ 729 /* bit 15 is Linear Stream Array */ 730 /* Interval - period between requests to an endpoint - 125u increments. */ 731 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 732 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 733 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 734 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 735 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 736 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 737 #define EP_HAS_LSA (1 << 15) 738 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 739 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 740 741 /* ep_info2 bitmasks */ 742 /* 743 * Force Event - generate transfer events for all TRBs for this endpoint 744 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 745 */ 746 #define FORCE_EVENT (0x1) 747 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 748 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 749 #define EP_TYPE(p) ((p) << 3) 750 #define ISOC_OUT_EP 1 751 #define BULK_OUT_EP 2 752 #define INT_OUT_EP 3 753 #define CTRL_EP 4 754 #define ISOC_IN_EP 5 755 #define BULK_IN_EP 6 756 #define INT_IN_EP 7 757 /* bit 6 reserved */ 758 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 759 #define MAX_BURST(p) (((p)&0xff) << 8) 760 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 761 #define MAX_PACKET(p) (((p)&0xffff) << 16) 762 #define MAX_PACKET_MASK (0xffff << 16) 763 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 764 765 /* tx_info bitmasks */ 766 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 767 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 768 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 769 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 770 771 /* deq bitmasks */ 772 #define EP_CTX_CYCLE_MASK (1 << 0) 773 #define SCTX_DEQ_MASK (~0xfL) 774 775 776 /** 777 * struct xhci_input_control_context 778 * Input control context; see section 6.2.5. 779 * 780 * @drop_context: set the bit of the endpoint context you want to disable 781 * @add_context: set the bit of the endpoint context you want to enable 782 */ 783 struct xhci_input_control_ctx { 784 __le32 drop_flags; 785 __le32 add_flags; 786 __le32 rsvd2[6]; 787 }; 788 789 #define EP_IS_ADDED(ctrl_ctx, i) \ 790 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 791 #define EP_IS_DROPPED(ctrl_ctx, i) \ 792 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 793 794 /* Represents everything that is needed to issue a command on the command ring. 795 * It's useful to pre-allocate these for commands that cannot fail due to 796 * out-of-memory errors, like freeing streams. 797 */ 798 struct xhci_command { 799 /* Input context for changing device state */ 800 struct xhci_container_ctx *in_ctx; 801 u32 status; 802 int slot_id; 803 /* If completion is null, no one is waiting on this command 804 * and the structure can be freed after the command completes. 805 */ 806 struct completion *completion; 807 union xhci_trb *command_trb; 808 struct list_head cmd_list; 809 }; 810 811 /* drop context bitmasks */ 812 #define DROP_EP(x) (0x1 << x) 813 /* add context bitmasks */ 814 #define ADD_EP(x) (0x1 << x) 815 816 struct xhci_stream_ctx { 817 /* 64-bit stream ring address, cycle state, and stream type */ 818 __le64 stream_ring; 819 /* offset 0x14 - 0x1f reserved for HC internal use */ 820 __le32 reserved[2]; 821 }; 822 823 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 824 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 825 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 826 #define SCT_SEC_TR 0 827 /* Primary stream array type, dequeue pointer is to a transfer ring */ 828 #define SCT_PRI_TR 1 829 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 830 #define SCT_SSA_8 2 831 #define SCT_SSA_16 3 832 #define SCT_SSA_32 4 833 #define SCT_SSA_64 5 834 #define SCT_SSA_128 6 835 #define SCT_SSA_256 7 836 837 /* Assume no secondary streams for now */ 838 struct xhci_stream_info { 839 struct xhci_ring **stream_rings; 840 /* Number of streams, including stream 0 (which drivers can't use) */ 841 unsigned int num_streams; 842 /* The stream context array may be bigger than 843 * the number of streams the driver asked for 844 */ 845 struct xhci_stream_ctx *stream_ctx_array; 846 unsigned int num_stream_ctxs; 847 dma_addr_t ctx_array_dma; 848 /* For mapping physical TRB addresses to segments in stream rings */ 849 struct radix_tree_root trb_address_map; 850 struct xhci_command *free_streams_command; 851 }; 852 853 #define SMALL_STREAM_ARRAY_SIZE 256 854 #define MEDIUM_STREAM_ARRAY_SIZE 1024 855 856 /* Some Intel xHCI host controllers need software to keep track of the bus 857 * bandwidth. Keep track of endpoint info here. Each root port is allocated 858 * the full bus bandwidth. We must also treat TTs (including each port under a 859 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 860 * (DMI) also limits the total bandwidth (across all domains) that can be used. 861 */ 862 struct xhci_bw_info { 863 /* ep_interval is zero-based */ 864 unsigned int ep_interval; 865 /* mult and num_packets are one-based */ 866 unsigned int mult; 867 unsigned int num_packets; 868 unsigned int max_packet_size; 869 unsigned int max_esit_payload; 870 unsigned int type; 871 }; 872 873 /* "Block" sizes in bytes the hardware uses for different device speeds. 874 * The logic in this part of the hardware limits the number of bits the hardware 875 * can use, so must represent bandwidth in a less precise manner to mimic what 876 * the scheduler hardware computes. 877 */ 878 #define FS_BLOCK 1 879 #define HS_BLOCK 4 880 #define SS_BLOCK 16 881 #define DMI_BLOCK 32 882 883 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 884 * with each byte transferred. SuperSpeed devices have an initial overhead to 885 * set up bursts. These are in blocks, see above. LS overhead has already been 886 * translated into FS blocks. 887 */ 888 #define DMI_OVERHEAD 8 889 #define DMI_OVERHEAD_BURST 4 890 #define SS_OVERHEAD 8 891 #define SS_OVERHEAD_BURST 32 892 #define HS_OVERHEAD 26 893 #define FS_OVERHEAD 20 894 #define LS_OVERHEAD 128 895 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 896 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 897 * of overhead associated with split transfers crossing microframe boundaries. 898 * 31 blocks is pure protocol overhead. 899 */ 900 #define TT_HS_OVERHEAD (31 + 94) 901 #define TT_DMI_OVERHEAD (25 + 12) 902 903 /* Bandwidth limits in blocks */ 904 #define FS_BW_LIMIT 1285 905 #define TT_BW_LIMIT 1320 906 #define HS_BW_LIMIT 1607 907 #define SS_BW_LIMIT_IN 3906 908 #define DMI_BW_LIMIT_IN 3906 909 #define SS_BW_LIMIT_OUT 3906 910 #define DMI_BW_LIMIT_OUT 3906 911 912 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 913 #define FS_BW_RESERVED 10 914 #define HS_BW_RESERVED 20 915 #define SS_BW_RESERVED 10 916 917 struct xhci_virt_ep { 918 struct xhci_ring *ring; 919 /* Related to endpoints that are configured to use stream IDs only */ 920 struct xhci_stream_info *stream_info; 921 /* Temporary storage in case the configure endpoint command fails and we 922 * have to restore the device state to the previous state 923 */ 924 struct xhci_ring *new_ring; 925 unsigned int ep_state; 926 #define SET_DEQ_PENDING (1 << 0) 927 #define EP_HALTED (1 << 1) /* For stall handling */ 928 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 929 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 930 #define EP_GETTING_STREAMS (1 << 3) 931 #define EP_HAS_STREAMS (1 << 4) 932 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 933 #define EP_GETTING_NO_STREAMS (1 << 5) 934 /* ---- Related to URB cancellation ---- */ 935 struct list_head cancelled_td_list; 936 /* Watchdog timer for stop endpoint command to cancel URBs */ 937 struct timer_list stop_cmd_timer; 938 struct xhci_hcd *xhci; 939 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 940 * command. We'll need to update the ring's dequeue segment and dequeue 941 * pointer after the command completes. 942 */ 943 struct xhci_segment *queued_deq_seg; 944 union xhci_trb *queued_deq_ptr; 945 /* 946 * Sometimes the xHC can not process isochronous endpoint ring quickly 947 * enough, and it will miss some isoc tds on the ring and generate 948 * a Missed Service Error Event. 949 * Set skip flag when receive a Missed Service Error Event and 950 * process the missed tds on the endpoint ring. 951 */ 952 bool skip; 953 /* Bandwidth checking storage */ 954 struct xhci_bw_info bw_info; 955 struct list_head bw_endpoint_list; 956 /* Isoch Frame ID checking storage */ 957 int next_frame_id; 958 /* Use new Isoch TRB layout needed for extended TBC support */ 959 bool use_extended_tbc; 960 }; 961 962 enum xhci_overhead_type { 963 LS_OVERHEAD_TYPE = 0, 964 FS_OVERHEAD_TYPE, 965 HS_OVERHEAD_TYPE, 966 }; 967 968 struct xhci_interval_bw { 969 unsigned int num_packets; 970 /* Sorted by max packet size. 971 * Head of the list is the greatest max packet size. 972 */ 973 struct list_head endpoints; 974 /* How many endpoints of each speed are present. */ 975 unsigned int overhead[3]; 976 }; 977 978 #define XHCI_MAX_INTERVAL 16 979 980 struct xhci_interval_bw_table { 981 unsigned int interval0_esit_payload; 982 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 983 /* Includes reserved bandwidth for async endpoints */ 984 unsigned int bw_used; 985 unsigned int ss_bw_in; 986 unsigned int ss_bw_out; 987 }; 988 989 990 struct xhci_virt_device { 991 struct usb_device *udev; 992 /* 993 * Commands to the hardware are passed an "input context" that 994 * tells the hardware what to change in its data structures. 995 * The hardware will return changes in an "output context" that 996 * software must allocate for the hardware. We need to keep 997 * track of input and output contexts separately because 998 * these commands might fail and we don't trust the hardware. 999 */ 1000 struct xhci_container_ctx *out_ctx; 1001 /* Used for addressing devices and configuration changes */ 1002 struct xhci_container_ctx *in_ctx; 1003 struct xhci_virt_ep eps[31]; 1004 u8 fake_port; 1005 u8 real_port; 1006 struct xhci_interval_bw_table *bw_table; 1007 struct xhci_tt_bw_info *tt_info; 1008 /* The current max exit latency for the enabled USB3 link states. */ 1009 u16 current_mel; 1010 }; 1011 1012 /* 1013 * For each roothub, keep track of the bandwidth information for each periodic 1014 * interval. 1015 * 1016 * If a high speed hub is attached to the roothub, each TT associated with that 1017 * hub is a separate bandwidth domain. The interval information for the 1018 * endpoints on the devices under that TT will appear in the TT structure. 1019 */ 1020 struct xhci_root_port_bw_info { 1021 struct list_head tts; 1022 unsigned int num_active_tts; 1023 struct xhci_interval_bw_table bw_table; 1024 }; 1025 1026 struct xhci_tt_bw_info { 1027 struct list_head tt_list; 1028 int slot_id; 1029 int ttport; 1030 struct xhci_interval_bw_table bw_table; 1031 int active_eps; 1032 }; 1033 1034 1035 /** 1036 * struct xhci_device_context_array 1037 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1038 */ 1039 struct xhci_device_context_array { 1040 /* 64-bit device addresses; we only write 32-bit addresses */ 1041 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1042 /* private xHCD pointers */ 1043 dma_addr_t dma; 1044 }; 1045 /* TODO: write function to set the 64-bit device DMA address */ 1046 /* 1047 * TODO: change this to be dynamically sized at HC mem init time since the HC 1048 * might not be able to handle the maximum number of devices possible. 1049 */ 1050 1051 1052 struct xhci_transfer_event { 1053 /* 64-bit buffer address, or immediate data */ 1054 __le64 buffer; 1055 __le32 transfer_len; 1056 /* This field is interpreted differently based on the type of TRB */ 1057 __le32 flags; 1058 }; 1059 1060 /* Transfer event TRB length bit mask */ 1061 /* bits 0:23 */ 1062 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1063 1064 /** Transfer Event bit fields **/ 1065 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1066 1067 /* Completion Code - only applicable for some types of TRBs */ 1068 #define COMP_CODE_MASK (0xff << 24) 1069 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1070 #define COMP_INVALID 0 1071 #define COMP_SUCCESS 1 1072 #define COMP_DATA_BUFFER_ERROR 2 1073 #define COMP_BABBLE_DETECTED_ERROR 3 1074 #define COMP_USB_TRANSACTION_ERROR 4 1075 #define COMP_TRB_ERROR 5 1076 #define COMP_STALL_ERROR 6 1077 #define COMP_RESOURCE_ERROR 7 1078 #define COMP_BANDWIDTH_ERROR 8 1079 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1080 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1081 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1082 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1083 #define COMP_SHORT_PACKET 13 1084 #define COMP_RING_UNDERRUN 14 1085 #define COMP_RING_OVERRUN 15 1086 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1087 #define COMP_PARAMETER_ERROR 17 1088 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1089 #define COMP_CONTEXT_STATE_ERROR 19 1090 #define COMP_NO_PING_RESPONSE_ERROR 20 1091 #define COMP_EVENT_RING_FULL_ERROR 21 1092 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1093 #define COMP_MISSED_SERVICE_ERROR 23 1094 #define COMP_COMMAND_RING_STOPPED 24 1095 #define COMP_COMMAND_ABORTED 25 1096 #define COMP_STOPPED 26 1097 #define COMP_STOPPED_LENGTH_INVALID 27 1098 #define COMP_STOPPED_SHORT_PACKET 28 1099 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1100 #define COMP_ISOCH_BUFFER_OVERRUN 31 1101 #define COMP_EVENT_LOST_ERROR 32 1102 #define COMP_UNDEFINED_ERROR 33 1103 #define COMP_INVALID_STREAM_ID_ERROR 34 1104 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1105 #define COMP_SPLIT_TRANSACTION_ERROR 36 1106 1107 static inline const char *xhci_trb_comp_code_string(u8 status) 1108 { 1109 switch (status) { 1110 case COMP_INVALID: 1111 return "Invalid"; 1112 case COMP_SUCCESS: 1113 return "Success"; 1114 case COMP_DATA_BUFFER_ERROR: 1115 return "Data Buffer Error"; 1116 case COMP_BABBLE_DETECTED_ERROR: 1117 return "Babble Detected"; 1118 case COMP_USB_TRANSACTION_ERROR: 1119 return "USB Transaction Error"; 1120 case COMP_TRB_ERROR: 1121 return "TRB Error"; 1122 case COMP_STALL_ERROR: 1123 return "Stall Error"; 1124 case COMP_RESOURCE_ERROR: 1125 return "Resource Error"; 1126 case COMP_BANDWIDTH_ERROR: 1127 return "Bandwidth Error"; 1128 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1129 return "No Slots Available Error"; 1130 case COMP_INVALID_STREAM_TYPE_ERROR: 1131 return "Invalid Stream Type Error"; 1132 case COMP_SLOT_NOT_ENABLED_ERROR: 1133 return "Slot Not Enabled Error"; 1134 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1135 return "Endpoint Not Enabled Error"; 1136 case COMP_SHORT_PACKET: 1137 return "Short Packet"; 1138 case COMP_RING_UNDERRUN: 1139 return "Ring Underrun"; 1140 case COMP_RING_OVERRUN: 1141 return "Ring Overrun"; 1142 case COMP_VF_EVENT_RING_FULL_ERROR: 1143 return "VF Event Ring Full Error"; 1144 case COMP_PARAMETER_ERROR: 1145 return "Parameter Error"; 1146 case COMP_BANDWIDTH_OVERRUN_ERROR: 1147 return "Bandwidth Overrun Error"; 1148 case COMP_CONTEXT_STATE_ERROR: 1149 return "Context State Error"; 1150 case COMP_NO_PING_RESPONSE_ERROR: 1151 return "No Ping Response Error"; 1152 case COMP_EVENT_RING_FULL_ERROR: 1153 return "Event Ring Full Error"; 1154 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1155 return "Incompatible Device Error"; 1156 case COMP_MISSED_SERVICE_ERROR: 1157 return "Missed Service Error"; 1158 case COMP_COMMAND_RING_STOPPED: 1159 return "Command Ring Stopped"; 1160 case COMP_COMMAND_ABORTED: 1161 return "Command Aborted"; 1162 case COMP_STOPPED: 1163 return "Stopped"; 1164 case COMP_STOPPED_LENGTH_INVALID: 1165 return "Stopped - Length Invalid"; 1166 case COMP_STOPPED_SHORT_PACKET: 1167 return "Stopped - Short Packet"; 1168 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1169 return "Max Exit Latency Too Large Error"; 1170 case COMP_ISOCH_BUFFER_OVERRUN: 1171 return "Isoch Buffer Overrun"; 1172 case COMP_EVENT_LOST_ERROR: 1173 return "Event Lost Error"; 1174 case COMP_UNDEFINED_ERROR: 1175 return "Undefined Error"; 1176 case COMP_INVALID_STREAM_ID_ERROR: 1177 return "Invalid Stream ID Error"; 1178 case COMP_SECONDARY_BANDWIDTH_ERROR: 1179 return "Secondary Bandwidth Error"; 1180 case COMP_SPLIT_TRANSACTION_ERROR: 1181 return "Split Transaction Error"; 1182 default: 1183 return "Unknown!!"; 1184 } 1185 } 1186 1187 struct xhci_link_trb { 1188 /* 64-bit segment pointer*/ 1189 __le64 segment_ptr; 1190 __le32 intr_target; 1191 __le32 control; 1192 }; 1193 1194 /* control bitfields */ 1195 #define LINK_TOGGLE (0x1<<1) 1196 1197 /* Command completion event TRB */ 1198 struct xhci_event_cmd { 1199 /* Pointer to command TRB, or the value passed by the event data trb */ 1200 __le64 cmd_trb; 1201 __le32 status; 1202 __le32 flags; 1203 }; 1204 1205 /* flags bitmasks */ 1206 1207 /* Address device - disable SetAddress */ 1208 #define TRB_BSR (1<<9) 1209 1210 /* Configure Endpoint - Deconfigure */ 1211 #define TRB_DC (1<<9) 1212 1213 /* Stop Ring - Transfer State Preserve */ 1214 #define TRB_TSP (1<<9) 1215 1216 enum xhci_ep_reset_type { 1217 EP_HARD_RESET, 1218 EP_SOFT_RESET, 1219 }; 1220 1221 /* Force Event */ 1222 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1223 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1224 1225 /* Set Latency Tolerance Value */ 1226 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1227 1228 /* Get Port Bandwidth */ 1229 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1230 1231 /* Force Header */ 1232 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1233 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1234 1235 enum xhci_setup_dev { 1236 SETUP_CONTEXT_ONLY, 1237 SETUP_CONTEXT_ADDRESS, 1238 }; 1239 1240 /* bits 16:23 are the virtual function ID */ 1241 /* bits 24:31 are the slot ID */ 1242 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1243 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1244 1245 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1246 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1247 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1248 1249 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1250 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1251 #define LAST_EP_INDEX 30 1252 1253 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1254 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1255 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1256 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1257 1258 /* Link TRB specific fields */ 1259 #define TRB_TC (1<<1) 1260 1261 /* Port Status Change Event TRB fields */ 1262 /* Port ID - bits 31:24 */ 1263 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1264 1265 #define EVENT_DATA (1 << 2) 1266 1267 /* Normal TRB fields */ 1268 /* transfer_len bitmasks - bits 0:16 */ 1269 #define TRB_LEN(p) ((p) & 0x1ffff) 1270 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1271 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1272 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1273 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1274 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1275 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1276 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1277 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1278 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1279 #define TRB_TBC(p) (((p) & 0x3) << 7) 1280 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1281 1282 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1283 #define TRB_CYCLE (1<<0) 1284 /* 1285 * Force next event data TRB to be evaluated before task switch. 1286 * Used to pass OS data back after a TD completes. 1287 */ 1288 #define TRB_ENT (1<<1) 1289 /* Interrupt on short packet */ 1290 #define TRB_ISP (1<<2) 1291 /* Set PCIe no snoop attribute */ 1292 #define TRB_NO_SNOOP (1<<3) 1293 /* Chain multiple TRBs into a TD */ 1294 #define TRB_CHAIN (1<<4) 1295 /* Interrupt on completion */ 1296 #define TRB_IOC (1<<5) 1297 /* The buffer pointer contains immediate data */ 1298 #define TRB_IDT (1<<6) 1299 1300 /* Block Event Interrupt */ 1301 #define TRB_BEI (1<<9) 1302 1303 /* Control transfer TRB specific fields */ 1304 #define TRB_DIR_IN (1<<16) 1305 #define TRB_TX_TYPE(p) ((p) << 16) 1306 #define TRB_DATA_OUT 2 1307 #define TRB_DATA_IN 3 1308 1309 /* Isochronous TRB specific fields */ 1310 #define TRB_SIA (1<<31) 1311 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1312 1313 struct xhci_generic_trb { 1314 __le32 field[4]; 1315 }; 1316 1317 union xhci_trb { 1318 struct xhci_link_trb link; 1319 struct xhci_transfer_event trans_event; 1320 struct xhci_event_cmd event_cmd; 1321 struct xhci_generic_trb generic; 1322 }; 1323 1324 /* TRB bit mask */ 1325 #define TRB_TYPE_BITMASK (0xfc00) 1326 #define TRB_TYPE(p) ((p) << 10) 1327 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1328 /* TRB type IDs */ 1329 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1330 #define TRB_NORMAL 1 1331 /* setup stage for control transfers */ 1332 #define TRB_SETUP 2 1333 /* data stage for control transfers */ 1334 #define TRB_DATA 3 1335 /* status stage for control transfers */ 1336 #define TRB_STATUS 4 1337 /* isoc transfers */ 1338 #define TRB_ISOC 5 1339 /* TRB for linking ring segments */ 1340 #define TRB_LINK 6 1341 #define TRB_EVENT_DATA 7 1342 /* Transfer Ring No-op (not for the command ring) */ 1343 #define TRB_TR_NOOP 8 1344 /* Command TRBs */ 1345 /* Enable Slot Command */ 1346 #define TRB_ENABLE_SLOT 9 1347 /* Disable Slot Command */ 1348 #define TRB_DISABLE_SLOT 10 1349 /* Address Device Command */ 1350 #define TRB_ADDR_DEV 11 1351 /* Configure Endpoint Command */ 1352 #define TRB_CONFIG_EP 12 1353 /* Evaluate Context Command */ 1354 #define TRB_EVAL_CONTEXT 13 1355 /* Reset Endpoint Command */ 1356 #define TRB_RESET_EP 14 1357 /* Stop Transfer Ring Command */ 1358 #define TRB_STOP_RING 15 1359 /* Set Transfer Ring Dequeue Pointer Command */ 1360 #define TRB_SET_DEQ 16 1361 /* Reset Device Command */ 1362 #define TRB_RESET_DEV 17 1363 /* Force Event Command (opt) */ 1364 #define TRB_FORCE_EVENT 18 1365 /* Negotiate Bandwidth Command (opt) */ 1366 #define TRB_NEG_BANDWIDTH 19 1367 /* Set Latency Tolerance Value Command (opt) */ 1368 #define TRB_SET_LT 20 1369 /* Get port bandwidth Command */ 1370 #define TRB_GET_BW 21 1371 /* Force Header Command - generate a transaction or link management packet */ 1372 #define TRB_FORCE_HEADER 22 1373 /* No-op Command - not for transfer rings */ 1374 #define TRB_CMD_NOOP 23 1375 /* TRB IDs 24-31 reserved */ 1376 /* Event TRBS */ 1377 /* Transfer Event */ 1378 #define TRB_TRANSFER 32 1379 /* Command Completion Event */ 1380 #define TRB_COMPLETION 33 1381 /* Port Status Change Event */ 1382 #define TRB_PORT_STATUS 34 1383 /* Bandwidth Request Event (opt) */ 1384 #define TRB_BANDWIDTH_EVENT 35 1385 /* Doorbell Event (opt) */ 1386 #define TRB_DOORBELL 36 1387 /* Host Controller Event */ 1388 #define TRB_HC_EVENT 37 1389 /* Device Notification Event - device sent function wake notification */ 1390 #define TRB_DEV_NOTE 38 1391 /* MFINDEX Wrap Event - microframe counter wrapped */ 1392 #define TRB_MFINDEX_WRAP 39 1393 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1394 1395 /* Nec vendor-specific command completion event. */ 1396 #define TRB_NEC_CMD_COMP 48 1397 /* Get NEC firmware revision. */ 1398 #define TRB_NEC_GET_FW 49 1399 1400 static inline const char *xhci_trb_type_string(u8 type) 1401 { 1402 switch (type) { 1403 case TRB_NORMAL: 1404 return "Normal"; 1405 case TRB_SETUP: 1406 return "Setup Stage"; 1407 case TRB_DATA: 1408 return "Data Stage"; 1409 case TRB_STATUS: 1410 return "Status Stage"; 1411 case TRB_ISOC: 1412 return "Isoch"; 1413 case TRB_LINK: 1414 return "Link"; 1415 case TRB_EVENT_DATA: 1416 return "Event Data"; 1417 case TRB_TR_NOOP: 1418 return "No-Op"; 1419 case TRB_ENABLE_SLOT: 1420 return "Enable Slot Command"; 1421 case TRB_DISABLE_SLOT: 1422 return "Disable Slot Command"; 1423 case TRB_ADDR_DEV: 1424 return "Address Device Command"; 1425 case TRB_CONFIG_EP: 1426 return "Configure Endpoint Command"; 1427 case TRB_EVAL_CONTEXT: 1428 return "Evaluate Context Command"; 1429 case TRB_RESET_EP: 1430 return "Reset Endpoint Command"; 1431 case TRB_STOP_RING: 1432 return "Stop Ring Command"; 1433 case TRB_SET_DEQ: 1434 return "Set TR Dequeue Pointer Command"; 1435 case TRB_RESET_DEV: 1436 return "Reset Device Command"; 1437 case TRB_FORCE_EVENT: 1438 return "Force Event Command"; 1439 case TRB_NEG_BANDWIDTH: 1440 return "Negotiate Bandwidth Command"; 1441 case TRB_SET_LT: 1442 return "Set Latency Tolerance Value Command"; 1443 case TRB_GET_BW: 1444 return "Get Port Bandwidth Command"; 1445 case TRB_FORCE_HEADER: 1446 return "Force Header Command"; 1447 case TRB_CMD_NOOP: 1448 return "No-Op Command"; 1449 case TRB_TRANSFER: 1450 return "Transfer Event"; 1451 case TRB_COMPLETION: 1452 return "Command Completion Event"; 1453 case TRB_PORT_STATUS: 1454 return "Port Status Change Event"; 1455 case TRB_BANDWIDTH_EVENT: 1456 return "Bandwidth Request Event"; 1457 case TRB_DOORBELL: 1458 return "Doorbell Event"; 1459 case TRB_HC_EVENT: 1460 return "Host Controller Event"; 1461 case TRB_DEV_NOTE: 1462 return "Device Notification Event"; 1463 case TRB_MFINDEX_WRAP: 1464 return "MFINDEX Wrap Event"; 1465 case TRB_NEC_CMD_COMP: 1466 return "NEC Command Completion Event"; 1467 case TRB_NEC_GET_FW: 1468 return "NET Get Firmware Revision Command"; 1469 default: 1470 return "UNKNOWN"; 1471 } 1472 } 1473 1474 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1475 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1476 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1477 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1478 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1479 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1480 1481 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1482 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1483 1484 /* 1485 * TRBS_PER_SEGMENT must be a multiple of 4, 1486 * since the command ring is 64-byte aligned. 1487 * It must also be greater than 16. 1488 */ 1489 #define TRBS_PER_SEGMENT 256 1490 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1491 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1492 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1493 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1494 /* TRB buffer pointers can't cross 64KB boundaries */ 1495 #define TRB_MAX_BUFF_SHIFT 16 1496 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1497 /* How much data is left before the 64KB boundary? */ 1498 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1499 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1500 1501 struct xhci_segment { 1502 union xhci_trb *trbs; 1503 /* private to HCD */ 1504 struct xhci_segment *next; 1505 dma_addr_t dma; 1506 /* Max packet sized bounce buffer for td-fragmant alignment */ 1507 dma_addr_t bounce_dma; 1508 void *bounce_buf; 1509 unsigned int bounce_offs; 1510 unsigned int bounce_len; 1511 }; 1512 1513 struct xhci_td { 1514 struct list_head td_list; 1515 struct list_head cancelled_td_list; 1516 struct urb *urb; 1517 struct xhci_segment *start_seg; 1518 union xhci_trb *first_trb; 1519 union xhci_trb *last_trb; 1520 struct xhci_segment *bounce_seg; 1521 /* actual_length of the URB has already been set */ 1522 bool urb_length_set; 1523 }; 1524 1525 /* xHCI command default timeout value */ 1526 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1527 1528 /* command descriptor */ 1529 struct xhci_cd { 1530 struct xhci_command *command; 1531 union xhci_trb *cmd_trb; 1532 }; 1533 1534 struct xhci_dequeue_state { 1535 struct xhci_segment *new_deq_seg; 1536 union xhci_trb *new_deq_ptr; 1537 int new_cycle_state; 1538 unsigned int stream_id; 1539 }; 1540 1541 enum xhci_ring_type { 1542 TYPE_CTRL = 0, 1543 TYPE_ISOC, 1544 TYPE_BULK, 1545 TYPE_INTR, 1546 TYPE_STREAM, 1547 TYPE_COMMAND, 1548 TYPE_EVENT, 1549 }; 1550 1551 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1552 { 1553 switch (type) { 1554 case TYPE_CTRL: 1555 return "CTRL"; 1556 case TYPE_ISOC: 1557 return "ISOC"; 1558 case TYPE_BULK: 1559 return "BULK"; 1560 case TYPE_INTR: 1561 return "INTR"; 1562 case TYPE_STREAM: 1563 return "STREAM"; 1564 case TYPE_COMMAND: 1565 return "CMD"; 1566 case TYPE_EVENT: 1567 return "EVENT"; 1568 } 1569 1570 return "UNKNOWN"; 1571 } 1572 1573 struct xhci_ring { 1574 struct xhci_segment *first_seg; 1575 struct xhci_segment *last_seg; 1576 union xhci_trb *enqueue; 1577 struct xhci_segment *enq_seg; 1578 union xhci_trb *dequeue; 1579 struct xhci_segment *deq_seg; 1580 struct list_head td_list; 1581 /* 1582 * Write the cycle state into the TRB cycle field to give ownership of 1583 * the TRB to the host controller (if we are the producer), or to check 1584 * if we own the TRB (if we are the consumer). See section 4.9.1. 1585 */ 1586 u32 cycle_state; 1587 unsigned int stream_id; 1588 unsigned int num_segs; 1589 unsigned int num_trbs_free; 1590 unsigned int num_trbs_free_temp; 1591 unsigned int bounce_buf_len; 1592 enum xhci_ring_type type; 1593 bool last_td_was_short; 1594 struct radix_tree_root *trb_address_map; 1595 }; 1596 1597 struct xhci_erst_entry { 1598 /* 64-bit event ring segment address */ 1599 __le64 seg_addr; 1600 __le32 seg_size; 1601 /* Set to zero */ 1602 __le32 rsvd; 1603 }; 1604 1605 struct xhci_erst { 1606 struct xhci_erst_entry *entries; 1607 unsigned int num_entries; 1608 /* xhci->event_ring keeps track of segment dma addresses */ 1609 dma_addr_t erst_dma_addr; 1610 /* Num entries the ERST can contain */ 1611 unsigned int erst_size; 1612 }; 1613 1614 struct xhci_scratchpad { 1615 u64 *sp_array; 1616 dma_addr_t sp_dma; 1617 void **sp_buffers; 1618 }; 1619 1620 struct urb_priv { 1621 int num_tds; 1622 int num_tds_done; 1623 struct xhci_td td[0]; 1624 }; 1625 1626 /* 1627 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1628 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1629 * meaning 64 ring segments. 1630 * Initial allocated size of the ERST, in number of entries */ 1631 #define ERST_NUM_SEGS 1 1632 /* Initial allocated size of the ERST, in number of entries */ 1633 #define ERST_SIZE 64 1634 /* Initial number of event segment rings allocated */ 1635 #define ERST_ENTRIES 1 1636 /* Poll every 60 seconds */ 1637 #define POLL_TIMEOUT 60 1638 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1639 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1640 /* XXX: Make these module parameters */ 1641 1642 struct s3_save { 1643 u32 command; 1644 u32 dev_nt; 1645 u64 dcbaa_ptr; 1646 u32 config_reg; 1647 u32 irq_pending; 1648 u32 irq_control; 1649 u32 erst_size; 1650 u64 erst_base; 1651 u64 erst_dequeue; 1652 }; 1653 1654 /* Use for lpm */ 1655 struct dev_info { 1656 u32 dev_id; 1657 struct list_head list; 1658 }; 1659 1660 struct xhci_bus_state { 1661 unsigned long bus_suspended; 1662 unsigned long next_statechange; 1663 1664 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1665 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1666 u32 port_c_suspend; 1667 u32 suspended_ports; 1668 u32 port_remote_wakeup; 1669 unsigned long resume_done[USB_MAXCHILDREN]; 1670 /* which ports have started to resume */ 1671 unsigned long resuming_ports; 1672 /* Which ports are waiting on RExit to U0 transition. */ 1673 unsigned long rexit_ports; 1674 struct completion rexit_done[USB_MAXCHILDREN]; 1675 }; 1676 1677 1678 /* 1679 * It can take up to 20 ms to transition from RExit to U0 on the 1680 * Intel Lynx Point LP xHCI host. 1681 */ 1682 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1683 1684 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1685 { 1686 if (hcd->speed >= HCD_USB3) 1687 return 0; 1688 else 1689 return 1; 1690 } 1691 1692 struct xhci_hub { 1693 u8 maj_rev; 1694 u8 min_rev; 1695 u32 *psi; /* array of protocol speed ID entries */ 1696 u8 psi_count; 1697 u8 psi_uid_count; 1698 }; 1699 1700 /* There is one xhci_hcd structure per controller */ 1701 struct xhci_hcd { 1702 struct usb_hcd *main_hcd; 1703 struct usb_hcd *shared_hcd; 1704 /* glue to PCI and HCD framework */ 1705 struct xhci_cap_regs __iomem *cap_regs; 1706 struct xhci_op_regs __iomem *op_regs; 1707 struct xhci_run_regs __iomem *run_regs; 1708 struct xhci_doorbell_array __iomem *dba; 1709 /* Our HCD's current interrupter register set */ 1710 struct xhci_intr_reg __iomem *ir_set; 1711 1712 /* Cached register copies of read-only HC data */ 1713 __u32 hcs_params1; 1714 __u32 hcs_params2; 1715 __u32 hcs_params3; 1716 __u32 hcc_params; 1717 __u32 hcc_params2; 1718 1719 spinlock_t lock; 1720 1721 /* packed release number */ 1722 u8 sbrn; 1723 u16 hci_version; 1724 u8 max_slots; 1725 u8 max_interrupters; 1726 u8 max_ports; 1727 u8 isoc_threshold; 1728 int event_ring_max; 1729 /* 4KB min, 128MB max */ 1730 int page_size; 1731 /* Valid values are 12 to 20, inclusive */ 1732 int page_shift; 1733 /* msi-x vectors */ 1734 int msix_count; 1735 /* optional clock */ 1736 struct clk *clk; 1737 /* data structures */ 1738 struct xhci_device_context_array *dcbaa; 1739 struct xhci_ring *cmd_ring; 1740 unsigned int cmd_ring_state; 1741 #define CMD_RING_STATE_RUNNING (1 << 0) 1742 #define CMD_RING_STATE_ABORTED (1 << 1) 1743 #define CMD_RING_STATE_STOPPED (1 << 2) 1744 struct list_head cmd_list; 1745 unsigned int cmd_ring_reserved_trbs; 1746 struct delayed_work cmd_timer; 1747 struct completion cmd_ring_stop_completion; 1748 struct xhci_command *current_cmd; 1749 struct xhci_ring *event_ring; 1750 struct xhci_erst erst; 1751 /* Scratchpad */ 1752 struct xhci_scratchpad *scratchpad; 1753 /* Store LPM test failed devices' information */ 1754 struct list_head lpm_failed_devs; 1755 1756 /* slot enabling and address device helpers */ 1757 /* these are not thread safe so use mutex */ 1758 struct mutex mutex; 1759 /* For USB 3.0 LPM enable/disable. */ 1760 struct xhci_command *lpm_command; 1761 /* Internal mirror of the HW's dcbaa */ 1762 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1763 /* For keeping track of bandwidth domains per roothub. */ 1764 struct xhci_root_port_bw_info *rh_bw; 1765 1766 /* DMA pools */ 1767 struct dma_pool *device_pool; 1768 struct dma_pool *segment_pool; 1769 struct dma_pool *small_streams_pool; 1770 struct dma_pool *medium_streams_pool; 1771 1772 /* Host controller watchdog timer structures */ 1773 unsigned int xhc_state; 1774 1775 u32 command; 1776 struct s3_save s3; 1777 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1778 * 1779 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1780 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1781 * that sees this status (other than the timer that set it) should stop touching 1782 * hardware immediately. Interrupt handlers should return immediately when 1783 * they see this status (any time they drop and re-acquire xhci->lock). 1784 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1785 * putting the TD on the canceled list, etc. 1786 * 1787 * There are no reports of xHCI host controllers that display this issue. 1788 */ 1789 #define XHCI_STATE_DYING (1 << 0) 1790 #define XHCI_STATE_HALTED (1 << 1) 1791 #define XHCI_STATE_REMOVING (1 << 2) 1792 unsigned int quirks; 1793 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1794 #define XHCI_RESET_EP_QUIRK (1 << 1) 1795 #define XHCI_NEC_HOST (1 << 2) 1796 #define XHCI_AMD_PLL_FIX (1 << 3) 1797 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1798 /* 1799 * Certain Intel host controllers have a limit to the number of endpoint 1800 * contexts they can handle. Ideally, they would signal that they can't handle 1801 * anymore endpoint contexts by returning a Resource Error for the Configure 1802 * Endpoint command, but they don't. Instead they expect software to keep track 1803 * of the number of active endpoints for them, across configure endpoint 1804 * commands, reset device commands, disable slot commands, and address device 1805 * commands. 1806 */ 1807 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1808 #define XHCI_BROKEN_MSI (1 << 6) 1809 #define XHCI_RESET_ON_RESUME (1 << 7) 1810 #define XHCI_SW_BW_CHECKING (1 << 8) 1811 #define XHCI_AMD_0x96_HOST (1 << 9) 1812 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1813 #define XHCI_LPM_SUPPORT (1 << 11) 1814 #define XHCI_INTEL_HOST (1 << 12) 1815 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1816 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1817 #define XHCI_AVOID_BEI (1 << 15) 1818 #define XHCI_PLAT (1 << 16) 1819 #define XHCI_SLOW_SUSPEND (1 << 17) 1820 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1821 /* For controllers with a broken beyond repair streams implementation */ 1822 #define XHCI_BROKEN_STREAMS (1 << 19) 1823 #define XHCI_PME_STUCK_QUIRK (1 << 20) 1824 #define XHCI_MTK_HOST (1 << 21) 1825 #define XHCI_SSIC_PORT_UNUSED (1 << 22) 1826 #define XHCI_NO_64BIT_SUPPORT (1 << 23) 1827 #define XHCI_MISSING_CAS (1 << 24) 1828 /* For controller with a broken Port Disable implementation */ 1829 #define XHCI_BROKEN_PORT_PED (1 << 25) 1830 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) 1831 /* Reserved. It was XHCI_U2_DISABLE_WAKE */ 1832 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) 1833 1834 unsigned int num_active_eps; 1835 unsigned int limit_active_eps; 1836 /* There are two roothubs to keep track of bus suspend info for */ 1837 struct xhci_bus_state bus_state[2]; 1838 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1839 u8 *port_array; 1840 /* Array of pointers to USB 3.0 PORTSC registers */ 1841 __le32 __iomem **usb3_ports; 1842 unsigned int num_usb3_ports; 1843 /* Array of pointers to USB 2.0 PORTSC registers */ 1844 __le32 __iomem **usb2_ports; 1845 struct xhci_hub usb2_rhub; 1846 struct xhci_hub usb3_rhub; 1847 unsigned int num_usb2_ports; 1848 /* support xHCI 0.96 spec USB2 software LPM */ 1849 unsigned sw_lpm_support:1; 1850 /* support xHCI 1.0 spec USB2 hardware LPM */ 1851 unsigned hw_lpm_support:1; 1852 /* cached usb2 extened protocol capabilites */ 1853 u32 *ext_caps; 1854 unsigned int num_ext_caps; 1855 /* Compliance Mode Recovery Data */ 1856 struct timer_list comp_mode_recovery_timer; 1857 u32 port_status_u0; 1858 u16 test_mode; 1859 /* Compliance Mode Timer Triggered every 2 seconds */ 1860 #define COMP_MODE_RCVRY_MSECS 2000 1861 1862 /* platform-specific data -- must come last */ 1863 unsigned long priv[0] __aligned(sizeof(s64)); 1864 }; 1865 1866 /* Platform specific overrides to generic XHCI hc_driver ops */ 1867 struct xhci_driver_overrides { 1868 size_t extra_priv_size; 1869 int (*reset)(struct usb_hcd *hcd); 1870 int (*start)(struct usb_hcd *hcd); 1871 }; 1872 1873 #define XHCI_CFC_DELAY 10 1874 1875 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1876 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1877 { 1878 struct usb_hcd *primary_hcd; 1879 1880 if (usb_hcd_is_primary_hcd(hcd)) 1881 primary_hcd = hcd; 1882 else 1883 primary_hcd = hcd->primary_hcd; 1884 1885 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1886 } 1887 1888 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1889 { 1890 return xhci->main_hcd; 1891 } 1892 1893 #define xhci_dbg(xhci, fmt, args...) \ 1894 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1895 #define xhci_err(xhci, fmt, args...) \ 1896 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1897 #define xhci_warn(xhci, fmt, args...) \ 1898 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1899 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1900 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1901 #define xhci_info(xhci, fmt, args...) \ 1902 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1903 1904 /* 1905 * Registers should always be accessed with double word or quad word accesses. 1906 * 1907 * Some xHCI implementations may support 64-bit address pointers. Registers 1908 * with 64-bit address pointers should be written to with dword accesses by 1909 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1910 * xHCI implementations that do not support 64-bit address pointers will ignore 1911 * the high dword, and write order is irrelevant. 1912 */ 1913 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1914 __le64 __iomem *regs) 1915 { 1916 return lo_hi_readq(regs); 1917 } 1918 static inline void xhci_write_64(struct xhci_hcd *xhci, 1919 const u64 val, __le64 __iomem *regs) 1920 { 1921 lo_hi_writeq(val, regs); 1922 } 1923 1924 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1925 { 1926 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1927 } 1928 1929 /* xHCI debugging */ 1930 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1931 void xhci_print_registers(struct xhci_hcd *xhci); 1932 void xhci_dbg_regs(struct xhci_hcd *xhci); 1933 void xhci_print_run_regs(struct xhci_hcd *xhci); 1934 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1935 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1936 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1937 struct xhci_container_ctx *ctx); 1938 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1939 const char *fmt, ...); 1940 1941 /* xHCI memory management */ 1942 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1943 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1944 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1945 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1946 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1947 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1948 struct usb_device *udev); 1949 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1950 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1951 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1952 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1953 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1954 struct xhci_virt_device *virt_dev, 1955 int old_active_eps); 1956 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1957 void xhci_update_bw_info(struct xhci_hcd *xhci, 1958 struct xhci_container_ctx *in_ctx, 1959 struct xhci_input_control_ctx *ctrl_ctx, 1960 struct xhci_virt_device *virt_dev); 1961 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1962 struct xhci_container_ctx *in_ctx, 1963 struct xhci_container_ctx *out_ctx, 1964 unsigned int ep_index); 1965 void xhci_slot_copy(struct xhci_hcd *xhci, 1966 struct xhci_container_ctx *in_ctx, 1967 struct xhci_container_ctx *out_ctx); 1968 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1969 struct usb_device *udev, struct usb_host_endpoint *ep, 1970 gfp_t mem_flags); 1971 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1972 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1973 unsigned int num_trbs, gfp_t flags); 1974 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1975 struct xhci_virt_device *virt_dev, 1976 unsigned int ep_index); 1977 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1978 unsigned int num_stream_ctxs, 1979 unsigned int num_streams, 1980 unsigned int max_packet, gfp_t flags); 1981 void xhci_free_stream_info(struct xhci_hcd *xhci, 1982 struct xhci_stream_info *stream_info); 1983 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1984 struct xhci_ep_ctx *ep_ctx, 1985 struct xhci_stream_info *stream_info); 1986 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1987 struct xhci_virt_ep *ep); 1988 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1989 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1990 struct xhci_ring *xhci_dma_to_transfer_ring( 1991 struct xhci_virt_ep *ep, 1992 u64 address); 1993 struct xhci_ring *xhci_stream_id_to_ring( 1994 struct xhci_virt_device *dev, 1995 unsigned int ep_index, 1996 unsigned int stream_id); 1997 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1998 bool allocate_in_ctx, bool allocate_completion, 1999 gfp_t mem_flags); 2000 void xhci_urb_free_priv(struct urb_priv *urb_priv); 2001 void xhci_free_command(struct xhci_hcd *xhci, 2002 struct xhci_command *command); 2003 2004 /* xHCI host controller glue */ 2005 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 2006 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 2007 void xhci_quiesce(struct xhci_hcd *xhci); 2008 int xhci_halt(struct xhci_hcd *xhci); 2009 int xhci_start(struct xhci_hcd *xhci); 2010 int xhci_reset(struct xhci_hcd *xhci); 2011 int xhci_run(struct usb_hcd *hcd); 2012 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2013 void xhci_init_driver(struct hc_driver *drv, 2014 const struct xhci_driver_overrides *over); 2015 int xhci_disable_slot(struct xhci_hcd *xhci, 2016 struct xhci_command *command, u32 slot_id); 2017 2018 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2019 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 2020 2021 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2022 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2023 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2024 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2025 struct xhci_virt_device *virt_dev, 2026 struct usb_device *hdev, 2027 struct usb_tt *tt, gfp_t mem_flags); 2028 2029 /* xHCI ring, segment, TRB, and TD functions */ 2030 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2031 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2032 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2033 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2034 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2035 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2036 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2037 u32 trb_type, u32 slot_id); 2038 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2039 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2040 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2041 u32 field1, u32 field2, u32 field3, u32 field4); 2042 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2043 int slot_id, unsigned int ep_index, int suspend); 2044 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2045 int slot_id, unsigned int ep_index); 2046 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2047 int slot_id, unsigned int ep_index); 2048 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2049 int slot_id, unsigned int ep_index); 2050 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2051 struct urb *urb, int slot_id, unsigned int ep_index); 2052 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2053 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2054 bool command_must_succeed); 2055 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2056 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2057 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2058 int slot_id, unsigned int ep_index, 2059 enum xhci_ep_reset_type reset_type); 2060 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2061 u32 slot_id); 2062 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 2063 unsigned int slot_id, unsigned int ep_index, 2064 unsigned int stream_id, struct xhci_td *cur_td, 2065 struct xhci_dequeue_state *state); 2066 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 2067 unsigned int slot_id, unsigned int ep_index, 2068 struct xhci_dequeue_state *deq_state); 2069 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index, 2070 unsigned int stream_id, struct xhci_td *td); 2071 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 2072 void xhci_handle_command_timeout(struct work_struct *work); 2073 2074 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2075 unsigned int ep_index, unsigned int stream_id); 2076 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2077 2078 /* xHCI roothub code */ 2079 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2080 int port_id, u32 link_state); 2081 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2082 int port_id, u32 port_bit); 2083 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2084 char *buf, u16 wLength); 2085 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2086 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2087 void xhci_hc_died(struct xhci_hcd *xhci); 2088 2089 #ifdef CONFIG_PM 2090 int xhci_bus_suspend(struct usb_hcd *hcd); 2091 int xhci_bus_resume(struct usb_hcd *hcd); 2092 #else 2093 #define xhci_bus_suspend NULL 2094 #define xhci_bus_resume NULL 2095 #endif /* CONFIG_PM */ 2096 2097 u32 xhci_port_state_to_neutral(u32 state); 2098 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2099 u16 port); 2100 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2101 2102 /* xHCI contexts */ 2103 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2104 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2105 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2106 2107 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2108 unsigned int slot_id, unsigned int ep_index, 2109 unsigned int stream_id); 2110 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2111 struct urb *urb) 2112 { 2113 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2114 xhci_get_endpoint_index(&urb->ep->desc), 2115 urb->stream_id); 2116 } 2117 2118 static inline char *xhci_slot_state_string(u32 state) 2119 { 2120 switch (state) { 2121 case SLOT_STATE_ENABLED: 2122 return "enabled/disabled"; 2123 case SLOT_STATE_DEFAULT: 2124 return "default"; 2125 case SLOT_STATE_ADDRESSED: 2126 return "addressed"; 2127 case SLOT_STATE_CONFIGURED: 2128 return "configured"; 2129 default: 2130 return "reserved"; 2131 } 2132 } 2133 2134 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, 2135 u32 field3) 2136 { 2137 static char str[256]; 2138 int type = TRB_FIELD_TO_TYPE(field3); 2139 2140 switch (type) { 2141 case TRB_LINK: 2142 sprintf(str, 2143 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2144 field1, field0, GET_INTR_TARGET(field2), 2145 xhci_trb_type_string(type), 2146 field3 & TRB_IOC ? 'I' : 'i', 2147 field3 & TRB_CHAIN ? 'C' : 'c', 2148 field3 & TRB_TC ? 'T' : 't', 2149 field3 & TRB_CYCLE ? 'C' : 'c'); 2150 break; 2151 case TRB_TRANSFER: 2152 case TRB_COMPLETION: 2153 case TRB_PORT_STATUS: 2154 case TRB_BANDWIDTH_EVENT: 2155 case TRB_DOORBELL: 2156 case TRB_HC_EVENT: 2157 case TRB_DEV_NOTE: 2158 case TRB_MFINDEX_WRAP: 2159 sprintf(str, 2160 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2161 field1, field0, 2162 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2163 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2164 /* Macro decrements 1, maybe it shouldn't?!? */ 2165 TRB_TO_EP_INDEX(field3) + 1, 2166 xhci_trb_type_string(type), 2167 field3 & EVENT_DATA ? 'E' : 'e', 2168 field3 & TRB_CYCLE ? 'C' : 'c'); 2169 2170 break; 2171 case TRB_SETUP: 2172 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2173 field0 & 0xff, 2174 (field0 & 0xff00) >> 8, 2175 (field0 & 0xff000000) >> 24, 2176 (field0 & 0xff0000) >> 16, 2177 (field1 & 0xff00) >> 8, 2178 field1 & 0xff, 2179 (field1 & 0xff000000) >> 16 | 2180 (field1 & 0xff0000) >> 16, 2181 TRB_LEN(field2), GET_TD_SIZE(field2), 2182 GET_INTR_TARGET(field2), 2183 xhci_trb_type_string(type), 2184 field3 & TRB_IDT ? 'I' : 'i', 2185 field3 & TRB_IOC ? 'I' : 'i', 2186 field3 & TRB_CYCLE ? 'C' : 'c'); 2187 break; 2188 case TRB_DATA: 2189 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2190 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2191 GET_INTR_TARGET(field2), 2192 xhci_trb_type_string(type), 2193 field3 & TRB_IDT ? 'I' : 'i', 2194 field3 & TRB_IOC ? 'I' : 'i', 2195 field3 & TRB_CHAIN ? 'C' : 'c', 2196 field3 & TRB_NO_SNOOP ? 'S' : 's', 2197 field3 & TRB_ISP ? 'I' : 'i', 2198 field3 & TRB_ENT ? 'E' : 'e', 2199 field3 & TRB_CYCLE ? 'C' : 'c'); 2200 break; 2201 case TRB_STATUS: 2202 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2203 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2204 GET_INTR_TARGET(field2), 2205 xhci_trb_type_string(type), 2206 field3 & TRB_IOC ? 'I' : 'i', 2207 field3 & TRB_CHAIN ? 'C' : 'c', 2208 field3 & TRB_ENT ? 'E' : 'e', 2209 field3 & TRB_CYCLE ? 'C' : 'c'); 2210 break; 2211 case TRB_NORMAL: 2212 case TRB_ISOC: 2213 case TRB_EVENT_DATA: 2214 case TRB_TR_NOOP: 2215 sprintf(str, 2216 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2217 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2218 GET_INTR_TARGET(field2), 2219 xhci_trb_type_string(type), 2220 field3 & TRB_BEI ? 'B' : 'b', 2221 field3 & TRB_IDT ? 'I' : 'i', 2222 field3 & TRB_IOC ? 'I' : 'i', 2223 field3 & TRB_CHAIN ? 'C' : 'c', 2224 field3 & TRB_NO_SNOOP ? 'S' : 's', 2225 field3 & TRB_ISP ? 'I' : 'i', 2226 field3 & TRB_ENT ? 'E' : 'e', 2227 field3 & TRB_CYCLE ? 'C' : 'c'); 2228 break; 2229 2230 case TRB_CMD_NOOP: 2231 case TRB_ENABLE_SLOT: 2232 sprintf(str, 2233 "%s: flags %c", 2234 xhci_trb_type_string(type), 2235 field3 & TRB_CYCLE ? 'C' : 'c'); 2236 break; 2237 case TRB_DISABLE_SLOT: 2238 case TRB_NEG_BANDWIDTH: 2239 sprintf(str, 2240 "%s: slot %d flags %c", 2241 xhci_trb_type_string(type), 2242 TRB_TO_SLOT_ID(field3), 2243 field3 & TRB_CYCLE ? 'C' : 'c'); 2244 break; 2245 case TRB_ADDR_DEV: 2246 sprintf(str, 2247 "%s: ctx %08x%08x slot %d flags %c:%c", 2248 xhci_trb_type_string(type), 2249 field1, field0, 2250 TRB_TO_SLOT_ID(field3), 2251 field3 & TRB_BSR ? 'B' : 'b', 2252 field3 & TRB_CYCLE ? 'C' : 'c'); 2253 break; 2254 case TRB_CONFIG_EP: 2255 sprintf(str, 2256 "%s: ctx %08x%08x slot %d flags %c:%c", 2257 xhci_trb_type_string(type), 2258 field1, field0, 2259 TRB_TO_SLOT_ID(field3), 2260 field3 & TRB_DC ? 'D' : 'd', 2261 field3 & TRB_CYCLE ? 'C' : 'c'); 2262 break; 2263 case TRB_EVAL_CONTEXT: 2264 sprintf(str, 2265 "%s: ctx %08x%08x slot %d flags %c", 2266 xhci_trb_type_string(type), 2267 field1, field0, 2268 TRB_TO_SLOT_ID(field3), 2269 field3 & TRB_CYCLE ? 'C' : 'c'); 2270 break; 2271 case TRB_RESET_EP: 2272 sprintf(str, 2273 "%s: ctx %08x%08x slot %d ep %d flags %c", 2274 xhci_trb_type_string(type), 2275 field1, field0, 2276 TRB_TO_SLOT_ID(field3), 2277 /* Macro decrements 1, maybe it shouldn't?!? */ 2278 TRB_TO_EP_INDEX(field3) + 1, 2279 field3 & TRB_CYCLE ? 'C' : 'c'); 2280 break; 2281 case TRB_STOP_RING: 2282 sprintf(str, 2283 "%s: slot %d sp %d ep %d flags %c", 2284 xhci_trb_type_string(type), 2285 TRB_TO_SLOT_ID(field3), 2286 TRB_TO_SUSPEND_PORT(field3), 2287 /* Macro decrements 1, maybe it shouldn't?!? */ 2288 TRB_TO_EP_INDEX(field3) + 1, 2289 field3 & TRB_CYCLE ? 'C' : 'c'); 2290 break; 2291 case TRB_SET_DEQ: 2292 sprintf(str, 2293 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2294 xhci_trb_type_string(type), 2295 field1, field0, 2296 TRB_TO_STREAM_ID(field2), 2297 TRB_TO_SLOT_ID(field3), 2298 /* Macro decrements 1, maybe it shouldn't?!? */ 2299 TRB_TO_EP_INDEX(field3) + 1, 2300 field3 & TRB_CYCLE ? 'C' : 'c'); 2301 break; 2302 case TRB_RESET_DEV: 2303 sprintf(str, 2304 "%s: slot %d flags %c", 2305 xhci_trb_type_string(type), 2306 TRB_TO_SLOT_ID(field3), 2307 field3 & TRB_CYCLE ? 'C' : 'c'); 2308 break; 2309 case TRB_FORCE_EVENT: 2310 sprintf(str, 2311 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2312 xhci_trb_type_string(type), 2313 field1, field0, 2314 TRB_TO_VF_INTR_TARGET(field2), 2315 TRB_TO_VF_ID(field3), 2316 field3 & TRB_CYCLE ? 'C' : 'c'); 2317 break; 2318 case TRB_SET_LT: 2319 sprintf(str, 2320 "%s: belt %d flags %c", 2321 xhci_trb_type_string(type), 2322 TRB_TO_BELT(field3), 2323 field3 & TRB_CYCLE ? 'C' : 'c'); 2324 break; 2325 case TRB_GET_BW: 2326 sprintf(str, 2327 "%s: ctx %08x%08x slot %d speed %d flags %c", 2328 xhci_trb_type_string(type), 2329 field1, field0, 2330 TRB_TO_SLOT_ID(field3), 2331 TRB_TO_DEV_SPEED(field3), 2332 field3 & TRB_CYCLE ? 'C' : 'c'); 2333 break; 2334 case TRB_FORCE_HEADER: 2335 sprintf(str, 2336 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2337 xhci_trb_type_string(type), 2338 field2, field1, field0 & 0xffffffe0, 2339 TRB_TO_PACKET_TYPE(field0), 2340 TRB_TO_ROOTHUB_PORT(field3), 2341 field3 & TRB_CYCLE ? 'C' : 'c'); 2342 break; 2343 default: 2344 sprintf(str, 2345 "type '%s' -> raw %08x %08x %08x %08x", 2346 xhci_trb_type_string(type), 2347 field0, field1, field2, field3); 2348 } 2349 2350 return str; 2351 } 2352 2353 static inline const char *xhci_decode_slot_context(u32 info, u32 info2, 2354 u32 tt_info, u32 state) 2355 { 2356 static char str[1024]; 2357 u32 speed; 2358 u32 hub; 2359 u32 mtt; 2360 int ret = 0; 2361 2362 speed = info & DEV_SPEED; 2363 hub = info & DEV_HUB; 2364 mtt = info & DEV_MTT; 2365 2366 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2367 info & ROUTE_STRING_MASK, 2368 ({ char *s; 2369 switch (speed) { 2370 case SLOT_SPEED_FS: 2371 s = "full-speed"; 2372 break; 2373 case SLOT_SPEED_LS: 2374 s = "low-speed"; 2375 break; 2376 case SLOT_SPEED_HS: 2377 s = "high-speed"; 2378 break; 2379 case SLOT_SPEED_SS: 2380 s = "super-speed"; 2381 break; 2382 case SLOT_SPEED_SSP: 2383 s = "super-speed plus"; 2384 break; 2385 default: 2386 s = "UNKNOWN speed"; 2387 } s; }), 2388 mtt ? " multi-TT" : "", 2389 hub ? " Hub" : "", 2390 (info & LAST_CTX_MASK) >> 27, 2391 info2 & MAX_EXIT, 2392 DEVINFO_TO_ROOT_HUB_PORT(info2), 2393 DEVINFO_TO_MAX_PORTS(info2)); 2394 2395 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2396 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2397 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2398 state & DEV_ADDR_MASK, 2399 xhci_slot_state_string(GET_SLOT_STATE(state))); 2400 2401 return str; 2402 } 2403 2404 2405 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2406 { 2407 switch (portsc & PORT_PLS_MASK) { 2408 case XDEV_U0: 2409 return "U0"; 2410 case XDEV_U1: 2411 return "U1"; 2412 case XDEV_U2: 2413 return "U2"; 2414 case XDEV_U3: 2415 return "U3"; 2416 case XDEV_DISABLED: 2417 return "Disabled"; 2418 case XDEV_RXDETECT: 2419 return "RxDetect"; 2420 case XDEV_INACTIVE: 2421 return "Inactive"; 2422 case XDEV_POLLING: 2423 return "Polling"; 2424 case XDEV_RECOVERY: 2425 return "Recovery"; 2426 case XDEV_HOT_RESET: 2427 return "Hot Reset"; 2428 case XDEV_COMP_MODE: 2429 return "Compliance mode"; 2430 case XDEV_TEST_MODE: 2431 return "Test mode"; 2432 case XDEV_RESUME: 2433 return "Resume"; 2434 default: 2435 break; 2436 } 2437 return "Unknown"; 2438 } 2439 2440 static inline const char *xhci_decode_portsc(u32 portsc) 2441 { 2442 static char str[256]; 2443 int ret; 2444 2445 ret = sprintf(str, "%s %s %s Link:%s ", 2446 portsc & PORT_POWER ? "Powered" : "Powered-off", 2447 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2448 portsc & PORT_PE ? "Enabled" : "Disabled", 2449 xhci_portsc_link_state_string(portsc)); 2450 2451 if (portsc & PORT_OC) 2452 ret += sprintf(str + ret, "OverCurrent "); 2453 if (portsc & PORT_RESET) 2454 ret += sprintf(str + ret, "In-Reset "); 2455 2456 ret += sprintf(str + ret, "Change: "); 2457 if (portsc & PORT_CSC) 2458 ret += sprintf(str + ret, "CSC "); 2459 if (portsc & PORT_PEC) 2460 ret += sprintf(str + ret, "PEC "); 2461 if (portsc & PORT_WRC) 2462 ret += sprintf(str + ret, "WRC "); 2463 if (portsc & PORT_OCC) 2464 ret += sprintf(str + ret, "OCC "); 2465 if (portsc & PORT_RC) 2466 ret += sprintf(str + ret, "PRC "); 2467 if (portsc & PORT_PLC) 2468 ret += sprintf(str + ret, "PLC "); 2469 if (portsc & PORT_CEC) 2470 ret += sprintf(str + ret, "CEC "); 2471 if (portsc & PORT_CAS) 2472 ret += sprintf(str + ret, "CAS "); 2473 2474 ret += sprintf(str + ret, "Wake: "); 2475 if (portsc & PORT_WKCONN_E) 2476 ret += sprintf(str + ret, "WCE "); 2477 if (portsc & PORT_WKDISC_E) 2478 ret += sprintf(str + ret, "WDE "); 2479 if (portsc & PORT_WKOC_E) 2480 ret += sprintf(str + ret, "WOE "); 2481 2482 return str; 2483 } 2484 2485 static inline const char *xhci_ep_state_string(u8 state) 2486 { 2487 switch (state) { 2488 case EP_STATE_DISABLED: 2489 return "disabled"; 2490 case EP_STATE_RUNNING: 2491 return "running"; 2492 case EP_STATE_HALTED: 2493 return "halted"; 2494 case EP_STATE_STOPPED: 2495 return "stopped"; 2496 case EP_STATE_ERROR: 2497 return "error"; 2498 default: 2499 return "INVALID"; 2500 } 2501 } 2502 2503 static inline const char *xhci_ep_type_string(u8 type) 2504 { 2505 switch (type) { 2506 case ISOC_OUT_EP: 2507 return "Isoc OUT"; 2508 case BULK_OUT_EP: 2509 return "Bulk OUT"; 2510 case INT_OUT_EP: 2511 return "Int OUT"; 2512 case CTRL_EP: 2513 return "Ctrl"; 2514 case ISOC_IN_EP: 2515 return "Isoc IN"; 2516 case BULK_IN_EP: 2517 return "Bulk IN"; 2518 case INT_IN_EP: 2519 return "Int IN"; 2520 default: 2521 return "INVALID"; 2522 } 2523 } 2524 2525 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq, 2526 u32 tx_info) 2527 { 2528 static char str[1024]; 2529 int ret; 2530 2531 u32 esit; 2532 u16 maxp; 2533 u16 avg; 2534 2535 u8 max_pstr; 2536 u8 ep_state; 2537 u8 interval; 2538 u8 ep_type; 2539 u8 burst; 2540 u8 cerr; 2541 u8 mult; 2542 u8 lsa; 2543 u8 hid; 2544 2545 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2546 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2547 2548 ep_state = info & EP_STATE_MASK; 2549 max_pstr = info & EP_MAXPSTREAMS_MASK; 2550 interval = CTX_TO_EP_INTERVAL(info); 2551 mult = CTX_TO_EP_MULT(info) + 1; 2552 lsa = info & EP_HAS_LSA; 2553 2554 cerr = (info2 & (3 << 1)) >> 1; 2555 ep_type = CTX_TO_EP_TYPE(info2); 2556 hid = info2 & (1 << 7); 2557 burst = CTX_TO_MAX_BURST(info2); 2558 maxp = MAX_PACKET_DECODED(info2); 2559 2560 avg = EP_AVG_TRB_LENGTH(tx_info); 2561 2562 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2563 xhci_ep_state_string(ep_state), mult, 2564 max_pstr, lsa ? "LSA " : ""); 2565 2566 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2567 (1 << interval) * 125, esit, cerr); 2568 2569 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2570 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2571 burst, maxp, deq); 2572 2573 ret += sprintf(str + ret, "avg trb len %d", avg); 2574 2575 return str; 2576 } 2577 2578 #endif /* __LINUX_XHCI_HCD_H */ 2579