1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 21 /* Code sharing between pci-quirks and xhci hcd */ 22 #include "xhci-ext-caps.h" 23 #include "pci-quirks.h" 24 25 /* xHCI PCI Configuration Registers */ 26 #define XHCI_SBRN_OFFSET (0x60) 27 28 /* Max number of USB devices for any host controller - limit in section 6.1 */ 29 #define MAX_HC_SLOTS 256 30 /* Section 5.3.3 - MaxPorts */ 31 #define MAX_HC_PORTS 127 32 33 /* 34 * xHCI register interface. 35 * This corresponds to the eXtensible Host Controller Interface (xHCI) 36 * Revision 0.95 specification 37 */ 38 39 /** 40 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 41 * @hc_capbase: length of the capabilities register and HC version number 42 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 43 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 44 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 45 * @hcc_params: HCCPARAMS - Capability Parameters 46 * @db_off: DBOFF - Doorbell array offset 47 * @run_regs_off: RTSOFF - Runtime register space offset 48 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 49 */ 50 struct xhci_cap_regs { 51 __le32 hc_capbase; 52 __le32 hcs_params1; 53 __le32 hcs_params2; 54 __le32 hcs_params3; 55 __le32 hcc_params; 56 __le32 db_off; 57 __le32 run_regs_off; 58 __le32 hcc_params2; /* xhci 1.1 */ 59 /* Reserved up to (CAPLENGTH - 0x1C) */ 60 }; 61 62 /* hc_capbase bitmasks */ 63 /* bits 7:0 - how long is the Capabilities register */ 64 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 65 /* bits 31:16 */ 66 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 67 68 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 69 /* bits 0:7, Max Device Slots */ 70 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 71 #define HCS_SLOTS_MASK 0xff 72 /* bits 8:18, Max Interrupters */ 73 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 74 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 75 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 76 77 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 78 /* bits 0:3, frames or uframes that SW needs to queue transactions 79 * ahead of the HW to meet periodic deadlines */ 80 #define HCS_IST(p) (((p) >> 0) & 0xf) 81 /* bits 4:7, max number of Event Ring segments */ 82 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 83 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 84 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 85 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 86 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 87 88 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 89 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 90 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 91 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 92 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 93 94 /* HCCPARAMS - hcc_params - bitmasks */ 95 /* true: HC can use 64-bit address pointers */ 96 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 97 /* true: HC can do bandwidth negotiation */ 98 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 99 /* true: HC uses 64-byte Device Context structures 100 * FIXME 64-byte context structures aren't supported yet. 101 */ 102 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 103 /* true: HC has port power switches */ 104 #define HCC_PPC(p) ((p) & (1 << 3)) 105 /* true: HC has port indicators */ 106 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 107 /* true: HC has Light HC Reset Capability */ 108 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 109 /* true: HC supports latency tolerance messaging */ 110 #define HCC_LTC(p) ((p) & (1 << 6)) 111 /* true: no secondary Stream ID Support */ 112 #define HCC_NSS(p) ((p) & (1 << 7)) 113 /* true: HC supports Stopped - Short Packet */ 114 #define HCC_SPC(p) ((p) & (1 << 9)) 115 /* true: HC has Contiguous Frame ID Capability */ 116 #define HCC_CFC(p) ((p) & (1 << 11)) 117 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 118 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 119 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 120 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 121 122 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 123 124 /* db_off bitmask - bits 0:1 reserved */ 125 #define DBOFF_MASK (~0x3) 126 127 /* run_regs_off bitmask - bits 0:4 reserved */ 128 #define RTSOFF_MASK (~0x1f) 129 130 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 131 /* true: HC supports U3 entry Capability */ 132 #define HCC2_U3C(p) ((p) & (1 << 0)) 133 /* true: HC supports Configure endpoint command Max exit latency too large */ 134 #define HCC2_CMC(p) ((p) & (1 << 1)) 135 /* true: HC supports Force Save context Capability */ 136 #define HCC2_FSC(p) ((p) & (1 << 2)) 137 /* true: HC supports Compliance Transition Capability */ 138 #define HCC2_CTC(p) ((p) & (1 << 3)) 139 /* true: HC support Large ESIT payload Capability > 48k */ 140 #define HCC2_LEC(p) ((p) & (1 << 4)) 141 /* true: HC support Configuration Information Capability */ 142 #define HCC2_CIC(p) ((p) & (1 << 5)) 143 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 144 #define HCC2_ETC(p) ((p) & (1 << 6)) 145 146 /* Number of registers per port */ 147 #define NUM_PORT_REGS 4 148 149 #define PORTSC 0 150 #define PORTPMSC 1 151 #define PORTLI 2 152 #define PORTHLPMC 3 153 154 /** 155 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 156 * @command: USBCMD - xHC command register 157 * @status: USBSTS - xHC status register 158 * @page_size: This indicates the page size that the host controller 159 * supports. If bit n is set, the HC supports a page size 160 * of 2^(n+12), up to a 128MB page size. 161 * 4K is the minimum page size. 162 * @cmd_ring: CRP - 64-bit Command Ring Pointer 163 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 164 * @config_reg: CONFIG - Configure Register 165 * @port_status_base: PORTSCn - base address for Port Status and Control 166 * Each port has a Port Status and Control register, 167 * followed by a Port Power Management Status and Control 168 * register, a Port Link Info register, and a reserved 169 * register. 170 * @port_power_base: PORTPMSCn - base address for 171 * Port Power Management Status and Control 172 * @port_link_base: PORTLIn - base address for Port Link Info (current 173 * Link PM state and control) for USB 2.1 and USB 3.0 174 * devices. 175 */ 176 struct xhci_op_regs { 177 __le32 command; 178 __le32 status; 179 __le32 page_size; 180 __le32 reserved1; 181 __le32 reserved2; 182 __le32 dev_notification; 183 __le64 cmd_ring; 184 /* rsvd: offset 0x20-2F */ 185 __le32 reserved3[4]; 186 __le64 dcbaa_ptr; 187 __le32 config_reg; 188 /* rsvd: offset 0x3C-3FF */ 189 __le32 reserved4[241]; 190 /* port 1 registers, which serve as a base address for other ports */ 191 __le32 port_status_base; 192 __le32 port_power_base; 193 __le32 port_link_base; 194 __le32 reserved5; 195 /* registers for ports 2-255 */ 196 __le32 reserved6[NUM_PORT_REGS*254]; 197 }; 198 199 /* USBCMD - USB command - command bitmasks */ 200 /* start/stop HC execution - do not write unless HC is halted*/ 201 #define CMD_RUN XHCI_CMD_RUN 202 /* Reset HC - resets internal HC state machine and all registers (except 203 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 204 * The xHCI driver must reinitialize the xHC after setting this bit. 205 */ 206 #define CMD_RESET (1 << 1) 207 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 208 #define CMD_EIE XHCI_CMD_EIE 209 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 210 #define CMD_HSEIE XHCI_CMD_HSEIE 211 /* bits 4:6 are reserved (and should be preserved on writes). */ 212 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 213 #define CMD_LRESET (1 << 7) 214 /* host controller save/restore state. */ 215 #define CMD_CSS (1 << 8) 216 #define CMD_CRS (1 << 9) 217 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 218 #define CMD_EWE XHCI_CMD_EWE 219 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 220 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 221 * '0' means the xHC can power it off if all ports are in the disconnect, 222 * disabled, or powered-off state. 223 */ 224 #define CMD_PM_INDEX (1 << 11) 225 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 226 #define CMD_ETE (1 << 14) 227 /* bits 15:31 are reserved (and should be preserved on writes). */ 228 229 /* IMAN - Interrupt Management Register */ 230 #define IMAN_IE (1 << 1) 231 #define IMAN_IP (1 << 0) 232 233 /* USBSTS - USB status - status bitmasks */ 234 /* HC not running - set to 1 when run/stop bit is cleared. */ 235 #define STS_HALT XHCI_STS_HALT 236 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 237 #define STS_FATAL (1 << 2) 238 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 239 #define STS_EINT (1 << 3) 240 /* port change detect */ 241 #define STS_PORT (1 << 4) 242 /* bits 5:7 reserved and zeroed */ 243 /* save state status - '1' means xHC is saving state */ 244 #define STS_SAVE (1 << 8) 245 /* restore state status - '1' means xHC is restoring state */ 246 #define STS_RESTORE (1 << 9) 247 /* true: save or restore error */ 248 #define STS_SRE (1 << 10) 249 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 250 #define STS_CNR XHCI_STS_CNR 251 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 252 #define STS_HCE (1 << 12) 253 /* bits 13:31 reserved and should be preserved */ 254 255 /* 256 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 257 * Generate a device notification event when the HC sees a transaction with a 258 * notification type that matches a bit set in this bit field. 259 */ 260 #define DEV_NOTE_MASK (0xffff) 261 #define ENABLE_DEV_NOTE(x) (1 << (x)) 262 /* Most of the device notification types should only be used for debug. 263 * SW does need to pay attention to function wake notifications. 264 */ 265 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 266 267 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 268 /* bit 0 is the command ring cycle state */ 269 /* stop ring operation after completion of the currently executing command */ 270 #define CMD_RING_PAUSE (1 << 1) 271 /* stop ring immediately - abort the currently executing command */ 272 #define CMD_RING_ABORT (1 << 2) 273 /* true: command ring is running */ 274 #define CMD_RING_RUNNING (1 << 3) 275 /* bits 4:5 reserved and should be preserved */ 276 /* Command Ring pointer - bit mask for the lower 32 bits. */ 277 #define CMD_RING_RSVD_BITS (0x3f) 278 279 /* CONFIG - Configure Register - config_reg bitmasks */ 280 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 281 #define MAX_DEVS(p) ((p) & 0xff) 282 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 283 #define CONFIG_U3E (1 << 8) 284 /* bit 9: Configuration Information Enable, xhci 1.1 */ 285 #define CONFIG_CIE (1 << 9) 286 /* bits 10:31 - reserved and should be preserved */ 287 288 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 289 /* true: device connected */ 290 #define PORT_CONNECT (1 << 0) 291 /* true: port enabled */ 292 #define PORT_PE (1 << 1) 293 /* bit 2 reserved and zeroed */ 294 /* true: port has an over-current condition */ 295 #define PORT_OC (1 << 3) 296 /* true: port reset signaling asserted */ 297 #define PORT_RESET (1 << 4) 298 /* Port Link State - bits 5:8 299 * A read gives the current link PM state of the port, 300 * a write with Link State Write Strobe set sets the link state. 301 */ 302 #define PORT_PLS_MASK (0xf << 5) 303 #define XDEV_U0 (0x0 << 5) 304 #define XDEV_U1 (0x1 << 5) 305 #define XDEV_U2 (0x2 << 5) 306 #define XDEV_U3 (0x3 << 5) 307 #define XDEV_DISABLED (0x4 << 5) 308 #define XDEV_RXDETECT (0x5 << 5) 309 #define XDEV_INACTIVE (0x6 << 5) 310 #define XDEV_POLLING (0x7 << 5) 311 #define XDEV_RECOVERY (0x8 << 5) 312 #define XDEV_HOT_RESET (0x9 << 5) 313 #define XDEV_COMP_MODE (0xa << 5) 314 #define XDEV_TEST_MODE (0xb << 5) 315 #define XDEV_RESUME (0xf << 5) 316 317 /* true: port has power (see HCC_PPC) */ 318 #define PORT_POWER (1 << 9) 319 /* bits 10:13 indicate device speed: 320 * 0 - undefined speed - port hasn't be initialized by a reset yet 321 * 1 - full speed 322 * 2 - low speed 323 * 3 - high speed 324 * 4 - super speed 325 * 5-15 reserved 326 */ 327 #define DEV_SPEED_MASK (0xf << 10) 328 #define XDEV_FS (0x1 << 10) 329 #define XDEV_LS (0x2 << 10) 330 #define XDEV_HS (0x3 << 10) 331 #define XDEV_SS (0x4 << 10) 332 #define XDEV_SSP (0x5 << 10) 333 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 334 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 335 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 336 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 337 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 338 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 339 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 340 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 341 342 /* Bits 20:23 in the Slot Context are the speed for the device */ 343 #define SLOT_SPEED_FS (XDEV_FS << 10) 344 #define SLOT_SPEED_LS (XDEV_LS << 10) 345 #define SLOT_SPEED_HS (XDEV_HS << 10) 346 #define SLOT_SPEED_SS (XDEV_SS << 10) 347 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 348 /* Port Indicator Control */ 349 #define PORT_LED_OFF (0 << 14) 350 #define PORT_LED_AMBER (1 << 14) 351 #define PORT_LED_GREEN (2 << 14) 352 #define PORT_LED_MASK (3 << 14) 353 /* Port Link State Write Strobe - set this when changing link state */ 354 #define PORT_LINK_STROBE (1 << 16) 355 /* true: connect status change */ 356 #define PORT_CSC (1 << 17) 357 /* true: port enable change */ 358 #define PORT_PEC (1 << 18) 359 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 360 * into an enabled state, and the device into the default state. A "warm" reset 361 * also resets the link, forcing the device through the link training sequence. 362 * SW can also look at the Port Reset register to see when warm reset is done. 363 */ 364 #define PORT_WRC (1 << 19) 365 /* true: over-current change */ 366 #define PORT_OCC (1 << 20) 367 /* true: reset change - 1 to 0 transition of PORT_RESET */ 368 #define PORT_RC (1 << 21) 369 /* port link status change - set on some port link state transitions: 370 * Transition Reason 371 * ------------------------------------------------------------------------------ 372 * - U3 to Resume Wakeup signaling from a device 373 * - Resume to Recovery to U0 USB 3.0 device resume 374 * - Resume to U0 USB 2.0 device resume 375 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 376 * - U3 to U0 Software resume of USB 2.0 device complete 377 * - U2 to U0 L1 resume of USB 2.1 device complete 378 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 379 * - U0 to disabled L1 entry error with USB 2.1 device 380 * - Any state to inactive Error on USB 3.0 port 381 */ 382 #define PORT_PLC (1 << 22) 383 /* port configure error change - port failed to configure its link partner */ 384 #define PORT_CEC (1 << 23) 385 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 386 PORT_RC | PORT_PLC | PORT_CEC) 387 388 389 /* Cold Attach Status - xHC can set this bit to report device attached during 390 * Sx state. Warm port reset should be perfomed to clear this bit and move port 391 * to connected state. 392 */ 393 #define PORT_CAS (1 << 24) 394 /* wake on connect (enable) */ 395 #define PORT_WKCONN_E (1 << 25) 396 /* wake on disconnect (enable) */ 397 #define PORT_WKDISC_E (1 << 26) 398 /* wake on over-current (enable) */ 399 #define PORT_WKOC_E (1 << 27) 400 /* bits 28:29 reserved */ 401 /* true: device is non-removable - for USB 3.0 roothub emulation */ 402 #define PORT_DEV_REMOVE (1 << 30) 403 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 404 #define PORT_WR (1 << 31) 405 406 /* We mark duplicate entries with -1 */ 407 #define DUPLICATE_ENTRY ((u8)(-1)) 408 409 /* Port Power Management Status and Control - port_power_base bitmasks */ 410 /* Inactivity timer value for transitions into U1, in microseconds. 411 * Timeout can be up to 127us. 0xFF means an infinite timeout. 412 */ 413 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 414 #define PORT_U1_TIMEOUT_MASK 0xff 415 /* Inactivity timer value for transitions into U2 */ 416 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 417 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 418 /* Bits 24:31 for port testing */ 419 420 /* USB2 Protocol PORTSPMSC */ 421 #define PORT_L1S_MASK 7 422 #define PORT_L1S_SUCCESS 1 423 #define PORT_RWE (1 << 3) 424 #define PORT_HIRD(p) (((p) & 0xf) << 4) 425 #define PORT_HIRD_MASK (0xf << 4) 426 #define PORT_L1DS_MASK (0xff << 8) 427 #define PORT_L1DS(p) (((p) & 0xff) << 8) 428 #define PORT_HLE (1 << 16) 429 #define PORT_TEST_MODE_SHIFT 28 430 431 /* USB3 Protocol PORTLI Port Link Information */ 432 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 433 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 434 435 /* USB2 Protocol PORTHLPMC */ 436 #define PORT_HIRDM(p)((p) & 3) 437 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 438 #define PORT_BESLD(p)(((p) & 0xf) << 10) 439 440 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 441 #define XHCI_L1_TIMEOUT 512 442 443 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 444 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 445 * by other operating systems. 446 * 447 * XHCI 1.0 errata 8/14/12 Table 13 notes: 448 * "Software should choose xHC BESL/BESLD field values that do not violate a 449 * device's resume latency requirements, 450 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 451 * or not program values < '4' if BLC = '0' and a BESL device is attached. 452 */ 453 #define XHCI_DEFAULT_BESL 4 454 455 /** 456 * struct xhci_intr_reg - Interrupt Register Set 457 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 458 * interrupts and check for pending interrupts. 459 * @irq_control: IMOD - Interrupt Moderation Register. 460 * Used to throttle interrupts. 461 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 462 * @erst_base: ERST base address. 463 * @erst_dequeue: Event ring dequeue pointer. 464 * 465 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 466 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 467 * multiple segments of the same size. The HC places events on the ring and 468 * "updates the Cycle bit in the TRBs to indicate to software the current 469 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 470 * updates the dequeue pointer. 471 */ 472 struct xhci_intr_reg { 473 __le32 irq_pending; 474 __le32 irq_control; 475 __le32 erst_size; 476 __le32 rsvd; 477 __le64 erst_base; 478 __le64 erst_dequeue; 479 }; 480 481 /* irq_pending bitmasks */ 482 #define ER_IRQ_PENDING(p) ((p) & 0x1) 483 /* bits 2:31 need to be preserved */ 484 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 485 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 486 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 487 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 488 489 /* irq_control bitmasks */ 490 /* Minimum interval between interrupts (in 250ns intervals). The interval 491 * between interrupts will be longer if there are no events on the event ring. 492 * Default is 4000 (1 ms). 493 */ 494 #define ER_IRQ_INTERVAL_MASK (0xffff) 495 /* Counter used to count down the time to the next interrupt - HW use only */ 496 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 497 498 /* erst_size bitmasks */ 499 /* Preserve bits 16:31 of erst_size */ 500 #define ERST_SIZE_MASK (0xffff << 16) 501 502 /* erst_dequeue bitmasks */ 503 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 504 * where the current dequeue pointer lies. This is an optional HW hint. 505 */ 506 #define ERST_DESI_MASK (0x7) 507 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 508 * a work queue (or delayed service routine)? 509 */ 510 #define ERST_EHB (1 << 3) 511 #define ERST_PTR_MASK (0xf) 512 513 /** 514 * struct xhci_run_regs 515 * @microframe_index: 516 * MFINDEX - current microframe number 517 * 518 * Section 5.5 Host Controller Runtime Registers: 519 * "Software should read and write these registers using only Dword (32 bit) 520 * or larger accesses" 521 */ 522 struct xhci_run_regs { 523 __le32 microframe_index; 524 __le32 rsvd[7]; 525 struct xhci_intr_reg ir_set[128]; 526 }; 527 528 /** 529 * struct doorbell_array 530 * 531 * Bits 0 - 7: Endpoint target 532 * Bits 8 - 15: RsvdZ 533 * Bits 16 - 31: Stream ID 534 * 535 * Section 5.6 536 */ 537 struct xhci_doorbell_array { 538 __le32 doorbell[256]; 539 }; 540 541 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 542 #define DB_VALUE_HOST 0x00000000 543 544 /** 545 * struct xhci_protocol_caps 546 * @revision: major revision, minor revision, capability ID, 547 * and next capability pointer. 548 * @name_string: Four ASCII characters to say which spec this xHC 549 * follows, typically "USB ". 550 * @port_info: Port offset, count, and protocol-defined information. 551 */ 552 struct xhci_protocol_caps { 553 u32 revision; 554 u32 name_string; 555 u32 port_info; 556 }; 557 558 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 559 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 560 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 561 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 562 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 563 564 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 565 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 566 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 567 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 568 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 569 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 570 571 #define PLT_MASK (0x03 << 6) 572 #define PLT_SYM (0x00 << 6) 573 #define PLT_ASYM_RX (0x02 << 6) 574 #define PLT_ASYM_TX (0x03 << 6) 575 576 /** 577 * struct xhci_container_ctx 578 * @type: Type of context. Used to calculated offsets to contained contexts. 579 * @size: Size of the context data 580 * @bytes: The raw context data given to HW 581 * @dma: dma address of the bytes 582 * 583 * Represents either a Device or Input context. Holds a pointer to the raw 584 * memory used for the context (bytes) and dma address of it (dma). 585 */ 586 struct xhci_container_ctx { 587 unsigned type; 588 #define XHCI_CTX_TYPE_DEVICE 0x1 589 #define XHCI_CTX_TYPE_INPUT 0x2 590 591 int size; 592 593 u8 *bytes; 594 dma_addr_t dma; 595 }; 596 597 /** 598 * struct xhci_slot_ctx 599 * @dev_info: Route string, device speed, hub info, and last valid endpoint 600 * @dev_info2: Max exit latency for device number, root hub port number 601 * @tt_info: tt_info is used to construct split transaction tokens 602 * @dev_state: slot state and device address 603 * 604 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 605 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 606 * reserved at the end of the slot context for HC internal use. 607 */ 608 struct xhci_slot_ctx { 609 __le32 dev_info; 610 __le32 dev_info2; 611 __le32 tt_info; 612 __le32 dev_state; 613 /* offset 0x10 to 0x1f reserved for HC internal use */ 614 __le32 reserved[4]; 615 }; 616 617 /* dev_info bitmasks */ 618 /* Route String - 0:19 */ 619 #define ROUTE_STRING_MASK (0xfffff) 620 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 621 #define DEV_SPEED (0xf << 20) 622 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 623 /* bit 24 reserved */ 624 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 625 #define DEV_MTT (0x1 << 25) 626 /* Set if the device is a hub - bit 26 */ 627 #define DEV_HUB (0x1 << 26) 628 /* Index of the last valid endpoint context in this device context - 27:31 */ 629 #define LAST_CTX_MASK (0x1f << 27) 630 #define LAST_CTX(p) ((p) << 27) 631 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 632 #define SLOT_FLAG (1 << 0) 633 #define EP0_FLAG (1 << 1) 634 635 /* dev_info2 bitmasks */ 636 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 637 #define MAX_EXIT (0xffff) 638 /* Root hub port number that is needed to access the USB device */ 639 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 640 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 641 /* Maximum number of ports under a hub device */ 642 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 643 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 644 645 /* tt_info bitmasks */ 646 /* 647 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 648 * The Slot ID of the hub that isolates the high speed signaling from 649 * this low or full-speed device. '0' if attached to root hub port. 650 */ 651 #define TT_SLOT (0xff) 652 /* 653 * The number of the downstream facing port of the high-speed hub 654 * '0' if the device is not low or full speed. 655 */ 656 #define TT_PORT (0xff << 8) 657 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 658 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 659 660 /* dev_state bitmasks */ 661 /* USB device address - assigned by the HC */ 662 #define DEV_ADDR_MASK (0xff) 663 /* bits 8:26 reserved */ 664 /* Slot state */ 665 #define SLOT_STATE (0x1f << 27) 666 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 667 668 #define SLOT_STATE_DISABLED 0 669 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 670 #define SLOT_STATE_DEFAULT 1 671 #define SLOT_STATE_ADDRESSED 2 672 #define SLOT_STATE_CONFIGURED 3 673 674 /** 675 * struct xhci_ep_ctx 676 * @ep_info: endpoint state, streams, mult, and interval information. 677 * @ep_info2: information on endpoint type, max packet size, max burst size, 678 * error count, and whether the HC will force an event for all 679 * transactions. 680 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 681 * defines one stream, this points to the endpoint transfer ring. 682 * Otherwise, it points to a stream context array, which has a 683 * ring pointer for each flow. 684 * @tx_info: 685 * Average TRB lengths for the endpoint ring and 686 * max payload within an Endpoint Service Interval Time (ESIT). 687 * 688 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 689 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 690 * reserved at the end of the endpoint context for HC internal use. 691 */ 692 struct xhci_ep_ctx { 693 __le32 ep_info; 694 __le32 ep_info2; 695 __le64 deq; 696 __le32 tx_info; 697 /* offset 0x14 - 0x1f reserved for HC internal use */ 698 __le32 reserved[3]; 699 }; 700 701 /* ep_info bitmasks */ 702 /* 703 * Endpoint State - bits 0:2 704 * 0 - disabled 705 * 1 - running 706 * 2 - halted due to halt condition - ok to manipulate endpoint ring 707 * 3 - stopped 708 * 4 - TRB error 709 * 5-7 - reserved 710 */ 711 #define EP_STATE_MASK (0xf) 712 #define EP_STATE_DISABLED 0 713 #define EP_STATE_RUNNING 1 714 #define EP_STATE_HALTED 2 715 #define EP_STATE_STOPPED 3 716 #define EP_STATE_ERROR 4 717 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 718 719 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 720 #define EP_MULT(p) (((p) & 0x3) << 8) 721 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 722 /* bits 10:14 are Max Primary Streams */ 723 /* bit 15 is Linear Stream Array */ 724 /* Interval - period between requests to an endpoint - 125u increments. */ 725 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 726 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 727 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 728 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 729 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 730 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 731 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 732 #define EP_HAS_LSA (1 << 15) 733 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 734 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 735 736 /* ep_info2 bitmasks */ 737 /* 738 * Force Event - generate transfer events for all TRBs for this endpoint 739 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 740 */ 741 #define FORCE_EVENT (0x1) 742 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 743 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 744 #define EP_TYPE(p) ((p) << 3) 745 #define ISOC_OUT_EP 1 746 #define BULK_OUT_EP 2 747 #define INT_OUT_EP 3 748 #define CTRL_EP 4 749 #define ISOC_IN_EP 5 750 #define BULK_IN_EP 6 751 #define INT_IN_EP 7 752 /* bit 6 reserved */ 753 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 754 #define MAX_BURST(p) (((p)&0xff) << 8) 755 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 756 #define MAX_PACKET(p) (((p)&0xffff) << 16) 757 #define MAX_PACKET_MASK (0xffff << 16) 758 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 759 760 /* tx_info bitmasks */ 761 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 762 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 763 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 764 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 765 766 /* deq bitmasks */ 767 #define EP_CTX_CYCLE_MASK (1 << 0) 768 #define SCTX_DEQ_MASK (~0xfL) 769 770 771 /** 772 * struct xhci_input_control_context 773 * Input control context; see section 6.2.5. 774 * 775 * @drop_context: set the bit of the endpoint context you want to disable 776 * @add_context: set the bit of the endpoint context you want to enable 777 */ 778 struct xhci_input_control_ctx { 779 __le32 drop_flags; 780 __le32 add_flags; 781 __le32 rsvd2[6]; 782 }; 783 784 #define EP_IS_ADDED(ctrl_ctx, i) \ 785 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 786 #define EP_IS_DROPPED(ctrl_ctx, i) \ 787 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 788 789 /* Represents everything that is needed to issue a command on the command ring. 790 * It's useful to pre-allocate these for commands that cannot fail due to 791 * out-of-memory errors, like freeing streams. 792 */ 793 struct xhci_command { 794 /* Input context for changing device state */ 795 struct xhci_container_ctx *in_ctx; 796 u32 status; 797 int slot_id; 798 /* If completion is null, no one is waiting on this command 799 * and the structure can be freed after the command completes. 800 */ 801 struct completion *completion; 802 union xhci_trb *command_trb; 803 struct list_head cmd_list; 804 }; 805 806 /* drop context bitmasks */ 807 #define DROP_EP(x) (0x1 << x) 808 /* add context bitmasks */ 809 #define ADD_EP(x) (0x1 << x) 810 811 struct xhci_stream_ctx { 812 /* 64-bit stream ring address, cycle state, and stream type */ 813 __le64 stream_ring; 814 /* offset 0x14 - 0x1f reserved for HC internal use */ 815 __le32 reserved[2]; 816 }; 817 818 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 819 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 820 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 821 #define SCT_SEC_TR 0 822 /* Primary stream array type, dequeue pointer is to a transfer ring */ 823 #define SCT_PRI_TR 1 824 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 825 #define SCT_SSA_8 2 826 #define SCT_SSA_16 3 827 #define SCT_SSA_32 4 828 #define SCT_SSA_64 5 829 #define SCT_SSA_128 6 830 #define SCT_SSA_256 7 831 832 /* Assume no secondary streams for now */ 833 struct xhci_stream_info { 834 struct xhci_ring **stream_rings; 835 /* Number of streams, including stream 0 (which drivers can't use) */ 836 unsigned int num_streams; 837 /* The stream context array may be bigger than 838 * the number of streams the driver asked for 839 */ 840 struct xhci_stream_ctx *stream_ctx_array; 841 unsigned int num_stream_ctxs; 842 dma_addr_t ctx_array_dma; 843 /* For mapping physical TRB addresses to segments in stream rings */ 844 struct radix_tree_root trb_address_map; 845 struct xhci_command *free_streams_command; 846 }; 847 848 #define SMALL_STREAM_ARRAY_SIZE 256 849 #define MEDIUM_STREAM_ARRAY_SIZE 1024 850 851 /* Some Intel xHCI host controllers need software to keep track of the bus 852 * bandwidth. Keep track of endpoint info here. Each root port is allocated 853 * the full bus bandwidth. We must also treat TTs (including each port under a 854 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 855 * (DMI) also limits the total bandwidth (across all domains) that can be used. 856 */ 857 struct xhci_bw_info { 858 /* ep_interval is zero-based */ 859 unsigned int ep_interval; 860 /* mult and num_packets are one-based */ 861 unsigned int mult; 862 unsigned int num_packets; 863 unsigned int max_packet_size; 864 unsigned int max_esit_payload; 865 unsigned int type; 866 }; 867 868 /* "Block" sizes in bytes the hardware uses for different device speeds. 869 * The logic in this part of the hardware limits the number of bits the hardware 870 * can use, so must represent bandwidth in a less precise manner to mimic what 871 * the scheduler hardware computes. 872 */ 873 #define FS_BLOCK 1 874 #define HS_BLOCK 4 875 #define SS_BLOCK 16 876 #define DMI_BLOCK 32 877 878 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 879 * with each byte transferred. SuperSpeed devices have an initial overhead to 880 * set up bursts. These are in blocks, see above. LS overhead has already been 881 * translated into FS blocks. 882 */ 883 #define DMI_OVERHEAD 8 884 #define DMI_OVERHEAD_BURST 4 885 #define SS_OVERHEAD 8 886 #define SS_OVERHEAD_BURST 32 887 #define HS_OVERHEAD 26 888 #define FS_OVERHEAD 20 889 #define LS_OVERHEAD 128 890 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 891 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 892 * of overhead associated with split transfers crossing microframe boundaries. 893 * 31 blocks is pure protocol overhead. 894 */ 895 #define TT_HS_OVERHEAD (31 + 94) 896 #define TT_DMI_OVERHEAD (25 + 12) 897 898 /* Bandwidth limits in blocks */ 899 #define FS_BW_LIMIT 1285 900 #define TT_BW_LIMIT 1320 901 #define HS_BW_LIMIT 1607 902 #define SS_BW_LIMIT_IN 3906 903 #define DMI_BW_LIMIT_IN 3906 904 #define SS_BW_LIMIT_OUT 3906 905 #define DMI_BW_LIMIT_OUT 3906 906 907 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 908 #define FS_BW_RESERVED 10 909 #define HS_BW_RESERVED 20 910 #define SS_BW_RESERVED 10 911 912 struct xhci_virt_ep { 913 struct xhci_ring *ring; 914 /* Related to endpoints that are configured to use stream IDs only */ 915 struct xhci_stream_info *stream_info; 916 /* Temporary storage in case the configure endpoint command fails and we 917 * have to restore the device state to the previous state 918 */ 919 struct xhci_ring *new_ring; 920 unsigned int ep_state; 921 #define SET_DEQ_PENDING (1 << 0) 922 #define EP_HALTED (1 << 1) /* For stall handling */ 923 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 924 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 925 #define EP_GETTING_STREAMS (1 << 3) 926 #define EP_HAS_STREAMS (1 << 4) 927 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 928 #define EP_GETTING_NO_STREAMS (1 << 5) 929 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 930 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 931 /* ---- Related to URB cancellation ---- */ 932 struct list_head cancelled_td_list; 933 /* Watchdog timer for stop endpoint command to cancel URBs */ 934 struct timer_list stop_cmd_timer; 935 struct xhci_hcd *xhci; 936 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 937 * command. We'll need to update the ring's dequeue segment and dequeue 938 * pointer after the command completes. 939 */ 940 struct xhci_segment *queued_deq_seg; 941 union xhci_trb *queued_deq_ptr; 942 /* 943 * Sometimes the xHC can not process isochronous endpoint ring quickly 944 * enough, and it will miss some isoc tds on the ring and generate 945 * a Missed Service Error Event. 946 * Set skip flag when receive a Missed Service Error Event and 947 * process the missed tds on the endpoint ring. 948 */ 949 bool skip; 950 /* Bandwidth checking storage */ 951 struct xhci_bw_info bw_info; 952 struct list_head bw_endpoint_list; 953 /* Isoch Frame ID checking storage */ 954 int next_frame_id; 955 /* Use new Isoch TRB layout needed for extended TBC support */ 956 bool use_extended_tbc; 957 }; 958 959 enum xhci_overhead_type { 960 LS_OVERHEAD_TYPE = 0, 961 FS_OVERHEAD_TYPE, 962 HS_OVERHEAD_TYPE, 963 }; 964 965 struct xhci_interval_bw { 966 unsigned int num_packets; 967 /* Sorted by max packet size. 968 * Head of the list is the greatest max packet size. 969 */ 970 struct list_head endpoints; 971 /* How many endpoints of each speed are present. */ 972 unsigned int overhead[3]; 973 }; 974 975 #define XHCI_MAX_INTERVAL 16 976 977 struct xhci_interval_bw_table { 978 unsigned int interval0_esit_payload; 979 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 980 /* Includes reserved bandwidth for async endpoints */ 981 unsigned int bw_used; 982 unsigned int ss_bw_in; 983 unsigned int ss_bw_out; 984 }; 985 986 987 struct xhci_virt_device { 988 struct usb_device *udev; 989 /* 990 * Commands to the hardware are passed an "input context" that 991 * tells the hardware what to change in its data structures. 992 * The hardware will return changes in an "output context" that 993 * software must allocate for the hardware. We need to keep 994 * track of input and output contexts separately because 995 * these commands might fail and we don't trust the hardware. 996 */ 997 struct xhci_container_ctx *out_ctx; 998 /* Used for addressing devices and configuration changes */ 999 struct xhci_container_ctx *in_ctx; 1000 struct xhci_virt_ep eps[31]; 1001 u8 fake_port; 1002 u8 real_port; 1003 struct xhci_interval_bw_table *bw_table; 1004 struct xhci_tt_bw_info *tt_info; 1005 /* The current max exit latency for the enabled USB3 link states. */ 1006 u16 current_mel; 1007 /* Used for the debugfs interfaces. */ 1008 void *debugfs_private; 1009 }; 1010 1011 /* 1012 * For each roothub, keep track of the bandwidth information for each periodic 1013 * interval. 1014 * 1015 * If a high speed hub is attached to the roothub, each TT associated with that 1016 * hub is a separate bandwidth domain. The interval information for the 1017 * endpoints on the devices under that TT will appear in the TT structure. 1018 */ 1019 struct xhci_root_port_bw_info { 1020 struct list_head tts; 1021 unsigned int num_active_tts; 1022 struct xhci_interval_bw_table bw_table; 1023 }; 1024 1025 struct xhci_tt_bw_info { 1026 struct list_head tt_list; 1027 int slot_id; 1028 int ttport; 1029 struct xhci_interval_bw_table bw_table; 1030 int active_eps; 1031 }; 1032 1033 1034 /** 1035 * struct xhci_device_context_array 1036 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1037 */ 1038 struct xhci_device_context_array { 1039 /* 64-bit device addresses; we only write 32-bit addresses */ 1040 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1041 /* private xHCD pointers */ 1042 dma_addr_t dma; 1043 }; 1044 /* TODO: write function to set the 64-bit device DMA address */ 1045 /* 1046 * TODO: change this to be dynamically sized at HC mem init time since the HC 1047 * might not be able to handle the maximum number of devices possible. 1048 */ 1049 1050 1051 struct xhci_transfer_event { 1052 /* 64-bit buffer address, or immediate data */ 1053 __le64 buffer; 1054 __le32 transfer_len; 1055 /* This field is interpreted differently based on the type of TRB */ 1056 __le32 flags; 1057 }; 1058 1059 /* Transfer event TRB length bit mask */ 1060 /* bits 0:23 */ 1061 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1062 1063 /** Transfer Event bit fields **/ 1064 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1065 1066 /* Completion Code - only applicable for some types of TRBs */ 1067 #define COMP_CODE_MASK (0xff << 24) 1068 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1069 #define COMP_INVALID 0 1070 #define COMP_SUCCESS 1 1071 #define COMP_DATA_BUFFER_ERROR 2 1072 #define COMP_BABBLE_DETECTED_ERROR 3 1073 #define COMP_USB_TRANSACTION_ERROR 4 1074 #define COMP_TRB_ERROR 5 1075 #define COMP_STALL_ERROR 6 1076 #define COMP_RESOURCE_ERROR 7 1077 #define COMP_BANDWIDTH_ERROR 8 1078 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1079 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1080 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1081 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1082 #define COMP_SHORT_PACKET 13 1083 #define COMP_RING_UNDERRUN 14 1084 #define COMP_RING_OVERRUN 15 1085 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1086 #define COMP_PARAMETER_ERROR 17 1087 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1088 #define COMP_CONTEXT_STATE_ERROR 19 1089 #define COMP_NO_PING_RESPONSE_ERROR 20 1090 #define COMP_EVENT_RING_FULL_ERROR 21 1091 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1092 #define COMP_MISSED_SERVICE_ERROR 23 1093 #define COMP_COMMAND_RING_STOPPED 24 1094 #define COMP_COMMAND_ABORTED 25 1095 #define COMP_STOPPED 26 1096 #define COMP_STOPPED_LENGTH_INVALID 27 1097 #define COMP_STOPPED_SHORT_PACKET 28 1098 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1099 #define COMP_ISOCH_BUFFER_OVERRUN 31 1100 #define COMP_EVENT_LOST_ERROR 32 1101 #define COMP_UNDEFINED_ERROR 33 1102 #define COMP_INVALID_STREAM_ID_ERROR 34 1103 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1104 #define COMP_SPLIT_TRANSACTION_ERROR 36 1105 1106 static inline const char *xhci_trb_comp_code_string(u8 status) 1107 { 1108 switch (status) { 1109 case COMP_INVALID: 1110 return "Invalid"; 1111 case COMP_SUCCESS: 1112 return "Success"; 1113 case COMP_DATA_BUFFER_ERROR: 1114 return "Data Buffer Error"; 1115 case COMP_BABBLE_DETECTED_ERROR: 1116 return "Babble Detected"; 1117 case COMP_USB_TRANSACTION_ERROR: 1118 return "USB Transaction Error"; 1119 case COMP_TRB_ERROR: 1120 return "TRB Error"; 1121 case COMP_STALL_ERROR: 1122 return "Stall Error"; 1123 case COMP_RESOURCE_ERROR: 1124 return "Resource Error"; 1125 case COMP_BANDWIDTH_ERROR: 1126 return "Bandwidth Error"; 1127 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1128 return "No Slots Available Error"; 1129 case COMP_INVALID_STREAM_TYPE_ERROR: 1130 return "Invalid Stream Type Error"; 1131 case COMP_SLOT_NOT_ENABLED_ERROR: 1132 return "Slot Not Enabled Error"; 1133 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1134 return "Endpoint Not Enabled Error"; 1135 case COMP_SHORT_PACKET: 1136 return "Short Packet"; 1137 case COMP_RING_UNDERRUN: 1138 return "Ring Underrun"; 1139 case COMP_RING_OVERRUN: 1140 return "Ring Overrun"; 1141 case COMP_VF_EVENT_RING_FULL_ERROR: 1142 return "VF Event Ring Full Error"; 1143 case COMP_PARAMETER_ERROR: 1144 return "Parameter Error"; 1145 case COMP_BANDWIDTH_OVERRUN_ERROR: 1146 return "Bandwidth Overrun Error"; 1147 case COMP_CONTEXT_STATE_ERROR: 1148 return "Context State Error"; 1149 case COMP_NO_PING_RESPONSE_ERROR: 1150 return "No Ping Response Error"; 1151 case COMP_EVENT_RING_FULL_ERROR: 1152 return "Event Ring Full Error"; 1153 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1154 return "Incompatible Device Error"; 1155 case COMP_MISSED_SERVICE_ERROR: 1156 return "Missed Service Error"; 1157 case COMP_COMMAND_RING_STOPPED: 1158 return "Command Ring Stopped"; 1159 case COMP_COMMAND_ABORTED: 1160 return "Command Aborted"; 1161 case COMP_STOPPED: 1162 return "Stopped"; 1163 case COMP_STOPPED_LENGTH_INVALID: 1164 return "Stopped - Length Invalid"; 1165 case COMP_STOPPED_SHORT_PACKET: 1166 return "Stopped - Short Packet"; 1167 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1168 return "Max Exit Latency Too Large Error"; 1169 case COMP_ISOCH_BUFFER_OVERRUN: 1170 return "Isoch Buffer Overrun"; 1171 case COMP_EVENT_LOST_ERROR: 1172 return "Event Lost Error"; 1173 case COMP_UNDEFINED_ERROR: 1174 return "Undefined Error"; 1175 case COMP_INVALID_STREAM_ID_ERROR: 1176 return "Invalid Stream ID Error"; 1177 case COMP_SECONDARY_BANDWIDTH_ERROR: 1178 return "Secondary Bandwidth Error"; 1179 case COMP_SPLIT_TRANSACTION_ERROR: 1180 return "Split Transaction Error"; 1181 default: 1182 return "Unknown!!"; 1183 } 1184 } 1185 1186 struct xhci_link_trb { 1187 /* 64-bit segment pointer*/ 1188 __le64 segment_ptr; 1189 __le32 intr_target; 1190 __le32 control; 1191 }; 1192 1193 /* control bitfields */ 1194 #define LINK_TOGGLE (0x1<<1) 1195 1196 /* Command completion event TRB */ 1197 struct xhci_event_cmd { 1198 /* Pointer to command TRB, or the value passed by the event data trb */ 1199 __le64 cmd_trb; 1200 __le32 status; 1201 __le32 flags; 1202 }; 1203 1204 /* flags bitmasks */ 1205 1206 /* Address device - disable SetAddress */ 1207 #define TRB_BSR (1<<9) 1208 1209 /* Configure Endpoint - Deconfigure */ 1210 #define TRB_DC (1<<9) 1211 1212 /* Stop Ring - Transfer State Preserve */ 1213 #define TRB_TSP (1<<9) 1214 1215 enum xhci_ep_reset_type { 1216 EP_HARD_RESET, 1217 EP_SOFT_RESET, 1218 }; 1219 1220 /* Force Event */ 1221 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1222 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1223 1224 /* Set Latency Tolerance Value */ 1225 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1226 1227 /* Get Port Bandwidth */ 1228 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1229 1230 /* Force Header */ 1231 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1232 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1233 1234 enum xhci_setup_dev { 1235 SETUP_CONTEXT_ONLY, 1236 SETUP_CONTEXT_ADDRESS, 1237 }; 1238 1239 /* bits 16:23 are the virtual function ID */ 1240 /* bits 24:31 are the slot ID */ 1241 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1242 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1243 1244 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1245 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1246 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1247 1248 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1249 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1250 #define LAST_EP_INDEX 30 1251 1252 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1253 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1254 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1255 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1256 1257 /* Link TRB specific fields */ 1258 #define TRB_TC (1<<1) 1259 1260 /* Port Status Change Event TRB fields */ 1261 /* Port ID - bits 31:24 */ 1262 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1263 1264 #define EVENT_DATA (1 << 2) 1265 1266 /* Normal TRB fields */ 1267 /* transfer_len bitmasks - bits 0:16 */ 1268 #define TRB_LEN(p) ((p) & 0x1ffff) 1269 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1270 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1271 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1272 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1273 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1274 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1275 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1276 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1277 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1278 #define TRB_TBC(p) (((p) & 0x3) << 7) 1279 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1280 1281 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1282 #define TRB_CYCLE (1<<0) 1283 /* 1284 * Force next event data TRB to be evaluated before task switch. 1285 * Used to pass OS data back after a TD completes. 1286 */ 1287 #define TRB_ENT (1<<1) 1288 /* Interrupt on short packet */ 1289 #define TRB_ISP (1<<2) 1290 /* Set PCIe no snoop attribute */ 1291 #define TRB_NO_SNOOP (1<<3) 1292 /* Chain multiple TRBs into a TD */ 1293 #define TRB_CHAIN (1<<4) 1294 /* Interrupt on completion */ 1295 #define TRB_IOC (1<<5) 1296 /* The buffer pointer contains immediate data */ 1297 #define TRB_IDT (1<<6) 1298 1299 /* Block Event Interrupt */ 1300 #define TRB_BEI (1<<9) 1301 1302 /* Control transfer TRB specific fields */ 1303 #define TRB_DIR_IN (1<<16) 1304 #define TRB_TX_TYPE(p) ((p) << 16) 1305 #define TRB_DATA_OUT 2 1306 #define TRB_DATA_IN 3 1307 1308 /* Isochronous TRB specific fields */ 1309 #define TRB_SIA (1<<31) 1310 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1311 1312 struct xhci_generic_trb { 1313 __le32 field[4]; 1314 }; 1315 1316 union xhci_trb { 1317 struct xhci_link_trb link; 1318 struct xhci_transfer_event trans_event; 1319 struct xhci_event_cmd event_cmd; 1320 struct xhci_generic_trb generic; 1321 }; 1322 1323 /* TRB bit mask */ 1324 #define TRB_TYPE_BITMASK (0xfc00) 1325 #define TRB_TYPE(p) ((p) << 10) 1326 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1327 /* TRB type IDs */ 1328 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1329 #define TRB_NORMAL 1 1330 /* setup stage for control transfers */ 1331 #define TRB_SETUP 2 1332 /* data stage for control transfers */ 1333 #define TRB_DATA 3 1334 /* status stage for control transfers */ 1335 #define TRB_STATUS 4 1336 /* isoc transfers */ 1337 #define TRB_ISOC 5 1338 /* TRB for linking ring segments */ 1339 #define TRB_LINK 6 1340 #define TRB_EVENT_DATA 7 1341 /* Transfer Ring No-op (not for the command ring) */ 1342 #define TRB_TR_NOOP 8 1343 /* Command TRBs */ 1344 /* Enable Slot Command */ 1345 #define TRB_ENABLE_SLOT 9 1346 /* Disable Slot Command */ 1347 #define TRB_DISABLE_SLOT 10 1348 /* Address Device Command */ 1349 #define TRB_ADDR_DEV 11 1350 /* Configure Endpoint Command */ 1351 #define TRB_CONFIG_EP 12 1352 /* Evaluate Context Command */ 1353 #define TRB_EVAL_CONTEXT 13 1354 /* Reset Endpoint Command */ 1355 #define TRB_RESET_EP 14 1356 /* Stop Transfer Ring Command */ 1357 #define TRB_STOP_RING 15 1358 /* Set Transfer Ring Dequeue Pointer Command */ 1359 #define TRB_SET_DEQ 16 1360 /* Reset Device Command */ 1361 #define TRB_RESET_DEV 17 1362 /* Force Event Command (opt) */ 1363 #define TRB_FORCE_EVENT 18 1364 /* Negotiate Bandwidth Command (opt) */ 1365 #define TRB_NEG_BANDWIDTH 19 1366 /* Set Latency Tolerance Value Command (opt) */ 1367 #define TRB_SET_LT 20 1368 /* Get port bandwidth Command */ 1369 #define TRB_GET_BW 21 1370 /* Force Header Command - generate a transaction or link management packet */ 1371 #define TRB_FORCE_HEADER 22 1372 /* No-op Command - not for transfer rings */ 1373 #define TRB_CMD_NOOP 23 1374 /* TRB IDs 24-31 reserved */ 1375 /* Event TRBS */ 1376 /* Transfer Event */ 1377 #define TRB_TRANSFER 32 1378 /* Command Completion Event */ 1379 #define TRB_COMPLETION 33 1380 /* Port Status Change Event */ 1381 #define TRB_PORT_STATUS 34 1382 /* Bandwidth Request Event (opt) */ 1383 #define TRB_BANDWIDTH_EVENT 35 1384 /* Doorbell Event (opt) */ 1385 #define TRB_DOORBELL 36 1386 /* Host Controller Event */ 1387 #define TRB_HC_EVENT 37 1388 /* Device Notification Event - device sent function wake notification */ 1389 #define TRB_DEV_NOTE 38 1390 /* MFINDEX Wrap Event - microframe counter wrapped */ 1391 #define TRB_MFINDEX_WRAP 39 1392 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1393 1394 /* Nec vendor-specific command completion event. */ 1395 #define TRB_NEC_CMD_COMP 48 1396 /* Get NEC firmware revision. */ 1397 #define TRB_NEC_GET_FW 49 1398 1399 static inline const char *xhci_trb_type_string(u8 type) 1400 { 1401 switch (type) { 1402 case TRB_NORMAL: 1403 return "Normal"; 1404 case TRB_SETUP: 1405 return "Setup Stage"; 1406 case TRB_DATA: 1407 return "Data Stage"; 1408 case TRB_STATUS: 1409 return "Status Stage"; 1410 case TRB_ISOC: 1411 return "Isoch"; 1412 case TRB_LINK: 1413 return "Link"; 1414 case TRB_EVENT_DATA: 1415 return "Event Data"; 1416 case TRB_TR_NOOP: 1417 return "No-Op"; 1418 case TRB_ENABLE_SLOT: 1419 return "Enable Slot Command"; 1420 case TRB_DISABLE_SLOT: 1421 return "Disable Slot Command"; 1422 case TRB_ADDR_DEV: 1423 return "Address Device Command"; 1424 case TRB_CONFIG_EP: 1425 return "Configure Endpoint Command"; 1426 case TRB_EVAL_CONTEXT: 1427 return "Evaluate Context Command"; 1428 case TRB_RESET_EP: 1429 return "Reset Endpoint Command"; 1430 case TRB_STOP_RING: 1431 return "Stop Ring Command"; 1432 case TRB_SET_DEQ: 1433 return "Set TR Dequeue Pointer Command"; 1434 case TRB_RESET_DEV: 1435 return "Reset Device Command"; 1436 case TRB_FORCE_EVENT: 1437 return "Force Event Command"; 1438 case TRB_NEG_BANDWIDTH: 1439 return "Negotiate Bandwidth Command"; 1440 case TRB_SET_LT: 1441 return "Set Latency Tolerance Value Command"; 1442 case TRB_GET_BW: 1443 return "Get Port Bandwidth Command"; 1444 case TRB_FORCE_HEADER: 1445 return "Force Header Command"; 1446 case TRB_CMD_NOOP: 1447 return "No-Op Command"; 1448 case TRB_TRANSFER: 1449 return "Transfer Event"; 1450 case TRB_COMPLETION: 1451 return "Command Completion Event"; 1452 case TRB_PORT_STATUS: 1453 return "Port Status Change Event"; 1454 case TRB_BANDWIDTH_EVENT: 1455 return "Bandwidth Request Event"; 1456 case TRB_DOORBELL: 1457 return "Doorbell Event"; 1458 case TRB_HC_EVENT: 1459 return "Host Controller Event"; 1460 case TRB_DEV_NOTE: 1461 return "Device Notification Event"; 1462 case TRB_MFINDEX_WRAP: 1463 return "MFINDEX Wrap Event"; 1464 case TRB_NEC_CMD_COMP: 1465 return "NEC Command Completion Event"; 1466 case TRB_NEC_GET_FW: 1467 return "NET Get Firmware Revision Command"; 1468 default: 1469 return "UNKNOWN"; 1470 } 1471 } 1472 1473 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1474 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1475 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1476 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1477 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1478 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1479 1480 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1481 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1482 1483 /* 1484 * TRBS_PER_SEGMENT must be a multiple of 4, 1485 * since the command ring is 64-byte aligned. 1486 * It must also be greater than 16. 1487 */ 1488 #define TRBS_PER_SEGMENT 256 1489 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1490 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1491 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1492 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1493 /* TRB buffer pointers can't cross 64KB boundaries */ 1494 #define TRB_MAX_BUFF_SHIFT 16 1495 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1496 /* How much data is left before the 64KB boundary? */ 1497 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1498 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1499 #define MAX_SOFT_RETRY 3 1500 1501 struct xhci_segment { 1502 union xhci_trb *trbs; 1503 /* private to HCD */ 1504 struct xhci_segment *next; 1505 dma_addr_t dma; 1506 /* Max packet sized bounce buffer for td-fragmant alignment */ 1507 dma_addr_t bounce_dma; 1508 void *bounce_buf; 1509 unsigned int bounce_offs; 1510 unsigned int bounce_len; 1511 }; 1512 1513 struct xhci_td { 1514 struct list_head td_list; 1515 struct list_head cancelled_td_list; 1516 struct urb *urb; 1517 struct xhci_segment *start_seg; 1518 union xhci_trb *first_trb; 1519 union xhci_trb *last_trb; 1520 struct xhci_segment *bounce_seg; 1521 /* actual_length of the URB has already been set */ 1522 bool urb_length_set; 1523 }; 1524 1525 /* xHCI command default timeout value */ 1526 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1527 1528 /* command descriptor */ 1529 struct xhci_cd { 1530 struct xhci_command *command; 1531 union xhci_trb *cmd_trb; 1532 }; 1533 1534 struct xhci_dequeue_state { 1535 struct xhci_segment *new_deq_seg; 1536 union xhci_trb *new_deq_ptr; 1537 int new_cycle_state; 1538 unsigned int stream_id; 1539 }; 1540 1541 enum xhci_ring_type { 1542 TYPE_CTRL = 0, 1543 TYPE_ISOC, 1544 TYPE_BULK, 1545 TYPE_INTR, 1546 TYPE_STREAM, 1547 TYPE_COMMAND, 1548 TYPE_EVENT, 1549 }; 1550 1551 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1552 { 1553 switch (type) { 1554 case TYPE_CTRL: 1555 return "CTRL"; 1556 case TYPE_ISOC: 1557 return "ISOC"; 1558 case TYPE_BULK: 1559 return "BULK"; 1560 case TYPE_INTR: 1561 return "INTR"; 1562 case TYPE_STREAM: 1563 return "STREAM"; 1564 case TYPE_COMMAND: 1565 return "CMD"; 1566 case TYPE_EVENT: 1567 return "EVENT"; 1568 } 1569 1570 return "UNKNOWN"; 1571 } 1572 1573 struct xhci_ring { 1574 struct xhci_segment *first_seg; 1575 struct xhci_segment *last_seg; 1576 union xhci_trb *enqueue; 1577 struct xhci_segment *enq_seg; 1578 union xhci_trb *dequeue; 1579 struct xhci_segment *deq_seg; 1580 struct list_head td_list; 1581 /* 1582 * Write the cycle state into the TRB cycle field to give ownership of 1583 * the TRB to the host controller (if we are the producer), or to check 1584 * if we own the TRB (if we are the consumer). See section 4.9.1. 1585 */ 1586 u32 cycle_state; 1587 unsigned int err_count; 1588 unsigned int stream_id; 1589 unsigned int num_segs; 1590 unsigned int num_trbs_free; 1591 unsigned int num_trbs_free_temp; 1592 unsigned int bounce_buf_len; 1593 enum xhci_ring_type type; 1594 bool last_td_was_short; 1595 struct radix_tree_root *trb_address_map; 1596 }; 1597 1598 struct xhci_erst_entry { 1599 /* 64-bit event ring segment address */ 1600 __le64 seg_addr; 1601 __le32 seg_size; 1602 /* Set to zero */ 1603 __le32 rsvd; 1604 }; 1605 1606 struct xhci_erst { 1607 struct xhci_erst_entry *entries; 1608 unsigned int num_entries; 1609 /* xhci->event_ring keeps track of segment dma addresses */ 1610 dma_addr_t erst_dma_addr; 1611 /* Num entries the ERST can contain */ 1612 unsigned int erst_size; 1613 }; 1614 1615 struct xhci_scratchpad { 1616 u64 *sp_array; 1617 dma_addr_t sp_dma; 1618 void **sp_buffers; 1619 }; 1620 1621 struct urb_priv { 1622 int num_tds; 1623 int num_tds_done; 1624 struct xhci_td td[0]; 1625 }; 1626 1627 /* 1628 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1629 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1630 * meaning 64 ring segments. 1631 * Initial allocated size of the ERST, in number of entries */ 1632 #define ERST_NUM_SEGS 1 1633 /* Initial allocated size of the ERST, in number of entries */ 1634 #define ERST_SIZE 64 1635 /* Initial number of event segment rings allocated */ 1636 #define ERST_ENTRIES 1 1637 /* Poll every 60 seconds */ 1638 #define POLL_TIMEOUT 60 1639 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1640 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1641 /* XXX: Make these module parameters */ 1642 1643 struct s3_save { 1644 u32 command; 1645 u32 dev_nt; 1646 u64 dcbaa_ptr; 1647 u32 config_reg; 1648 u32 irq_pending; 1649 u32 irq_control; 1650 u32 erst_size; 1651 u64 erst_base; 1652 u64 erst_dequeue; 1653 }; 1654 1655 /* Use for lpm */ 1656 struct dev_info { 1657 u32 dev_id; 1658 struct list_head list; 1659 }; 1660 1661 struct xhci_bus_state { 1662 unsigned long bus_suspended; 1663 unsigned long next_statechange; 1664 1665 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1666 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1667 u32 port_c_suspend; 1668 u32 suspended_ports; 1669 u32 port_remote_wakeup; 1670 unsigned long resume_done[USB_MAXCHILDREN]; 1671 /* which ports have started to resume */ 1672 unsigned long resuming_ports; 1673 /* Which ports are waiting on RExit to U0 transition. */ 1674 unsigned long rexit_ports; 1675 struct completion rexit_done[USB_MAXCHILDREN]; 1676 }; 1677 1678 1679 /* 1680 * It can take up to 20 ms to transition from RExit to U0 on the 1681 * Intel Lynx Point LP xHCI host. 1682 */ 1683 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1684 1685 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1686 { 1687 if (hcd->speed >= HCD_USB3) 1688 return 0; 1689 else 1690 return 1; 1691 } 1692 struct xhci_port { 1693 __le32 __iomem *addr; 1694 int hw_portnum; 1695 int hcd_portnum; 1696 struct xhci_hub *rhub; 1697 }; 1698 1699 struct xhci_hub { 1700 struct xhci_port **ports; 1701 unsigned int num_ports; 1702 struct usb_hcd *hcd; 1703 /* supported prococol extended capabiliy values */ 1704 u8 maj_rev; 1705 u8 min_rev; 1706 u32 *psi; /* array of protocol speed ID entries */ 1707 u8 psi_count; 1708 u8 psi_uid_count; 1709 }; 1710 1711 /* There is one xhci_hcd structure per controller */ 1712 struct xhci_hcd { 1713 struct usb_hcd *main_hcd; 1714 struct usb_hcd *shared_hcd; 1715 /* glue to PCI and HCD framework */ 1716 struct xhci_cap_regs __iomem *cap_regs; 1717 struct xhci_op_regs __iomem *op_regs; 1718 struct xhci_run_regs __iomem *run_regs; 1719 struct xhci_doorbell_array __iomem *dba; 1720 /* Our HCD's current interrupter register set */ 1721 struct xhci_intr_reg __iomem *ir_set; 1722 1723 /* Cached register copies of read-only HC data */ 1724 __u32 hcs_params1; 1725 __u32 hcs_params2; 1726 __u32 hcs_params3; 1727 __u32 hcc_params; 1728 __u32 hcc_params2; 1729 1730 spinlock_t lock; 1731 1732 /* packed release number */ 1733 u8 sbrn; 1734 u16 hci_version; 1735 u8 max_slots; 1736 u8 max_interrupters; 1737 u8 max_ports; 1738 u8 isoc_threshold; 1739 /* imod_interval in ns (I * 250ns) */ 1740 u32 imod_interval; 1741 int event_ring_max; 1742 /* 4KB min, 128MB max */ 1743 int page_size; 1744 /* Valid values are 12 to 20, inclusive */ 1745 int page_shift; 1746 /* msi-x vectors */ 1747 int msix_count; 1748 /* optional clocks */ 1749 struct clk *clk; 1750 struct clk *reg_clk; 1751 /* data structures */ 1752 struct xhci_device_context_array *dcbaa; 1753 struct xhci_ring *cmd_ring; 1754 unsigned int cmd_ring_state; 1755 #define CMD_RING_STATE_RUNNING (1 << 0) 1756 #define CMD_RING_STATE_ABORTED (1 << 1) 1757 #define CMD_RING_STATE_STOPPED (1 << 2) 1758 struct list_head cmd_list; 1759 unsigned int cmd_ring_reserved_trbs; 1760 struct delayed_work cmd_timer; 1761 struct completion cmd_ring_stop_completion; 1762 struct xhci_command *current_cmd; 1763 struct xhci_ring *event_ring; 1764 struct xhci_erst erst; 1765 /* Scratchpad */ 1766 struct xhci_scratchpad *scratchpad; 1767 /* Store LPM test failed devices' information */ 1768 struct list_head lpm_failed_devs; 1769 1770 /* slot enabling and address device helpers */ 1771 /* these are not thread safe so use mutex */ 1772 struct mutex mutex; 1773 /* For USB 3.0 LPM enable/disable. */ 1774 struct xhci_command *lpm_command; 1775 /* Internal mirror of the HW's dcbaa */ 1776 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1777 /* For keeping track of bandwidth domains per roothub. */ 1778 struct xhci_root_port_bw_info *rh_bw; 1779 1780 /* DMA pools */ 1781 struct dma_pool *device_pool; 1782 struct dma_pool *segment_pool; 1783 struct dma_pool *small_streams_pool; 1784 struct dma_pool *medium_streams_pool; 1785 1786 /* Host controller watchdog timer structures */ 1787 unsigned int xhc_state; 1788 1789 u32 command; 1790 struct s3_save s3; 1791 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1792 * 1793 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1794 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1795 * that sees this status (other than the timer that set it) should stop touching 1796 * hardware immediately. Interrupt handlers should return immediately when 1797 * they see this status (any time they drop and re-acquire xhci->lock). 1798 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1799 * putting the TD on the canceled list, etc. 1800 * 1801 * There are no reports of xHCI host controllers that display this issue. 1802 */ 1803 #define XHCI_STATE_DYING (1 << 0) 1804 #define XHCI_STATE_HALTED (1 << 1) 1805 #define XHCI_STATE_REMOVING (1 << 2) 1806 unsigned long long quirks; 1807 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1808 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) 1809 #define XHCI_NEC_HOST BIT_ULL(2) 1810 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1811 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1812 /* 1813 * Certain Intel host controllers have a limit to the number of endpoint 1814 * contexts they can handle. Ideally, they would signal that they can't handle 1815 * anymore endpoint contexts by returning a Resource Error for the Configure 1816 * Endpoint command, but they don't. Instead they expect software to keep track 1817 * of the number of active endpoints for them, across configure endpoint 1818 * commands, reset device commands, disable slot commands, and address device 1819 * commands. 1820 */ 1821 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1822 #define XHCI_BROKEN_MSI BIT_ULL(6) 1823 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1824 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1825 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1826 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) 1827 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1828 #define XHCI_INTEL_HOST BIT_ULL(12) 1829 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1830 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1831 #define XHCI_AVOID_BEI BIT_ULL(15) 1832 #define XHCI_PLAT BIT_ULL(16) 1833 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1834 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1835 /* For controllers with a broken beyond repair streams implementation */ 1836 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1837 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1838 #define XHCI_MTK_HOST BIT_ULL(21) 1839 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1840 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1841 #define XHCI_MISSING_CAS BIT_ULL(24) 1842 /* For controller with a broken Port Disable implementation */ 1843 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1844 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1845 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1846 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1847 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1848 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1849 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1850 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1851 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1852 1853 unsigned int num_active_eps; 1854 unsigned int limit_active_eps; 1855 /* There are two roothubs to keep track of bus suspend info for */ 1856 struct xhci_bus_state bus_state[2]; 1857 struct xhci_port *hw_ports; 1858 struct xhci_hub usb2_rhub; 1859 struct xhci_hub usb3_rhub; 1860 /* support xHCI 0.96 spec USB2 software LPM */ 1861 unsigned sw_lpm_support:1; 1862 /* support xHCI 1.0 spec USB2 hardware LPM */ 1863 unsigned hw_lpm_support:1; 1864 /* cached usb2 extened protocol capabilites */ 1865 u32 *ext_caps; 1866 unsigned int num_ext_caps; 1867 /* Compliance Mode Recovery Data */ 1868 struct timer_list comp_mode_recovery_timer; 1869 u32 port_status_u0; 1870 u16 test_mode; 1871 /* Compliance Mode Timer Triggered every 2 seconds */ 1872 #define COMP_MODE_RCVRY_MSECS 2000 1873 1874 struct dentry *debugfs_root; 1875 struct dentry *debugfs_slots; 1876 struct list_head regset_list; 1877 1878 void *dbc; 1879 /* platform-specific data -- must come last */ 1880 unsigned long priv[0] __aligned(sizeof(s64)); 1881 }; 1882 1883 /* Platform specific overrides to generic XHCI hc_driver ops */ 1884 struct xhci_driver_overrides { 1885 size_t extra_priv_size; 1886 int (*reset)(struct usb_hcd *hcd); 1887 int (*start)(struct usb_hcd *hcd); 1888 }; 1889 1890 #define XHCI_CFC_DELAY 10 1891 1892 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1893 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1894 { 1895 struct usb_hcd *primary_hcd; 1896 1897 if (usb_hcd_is_primary_hcd(hcd)) 1898 primary_hcd = hcd; 1899 else 1900 primary_hcd = hcd->primary_hcd; 1901 1902 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1903 } 1904 1905 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1906 { 1907 return xhci->main_hcd; 1908 } 1909 1910 #define xhci_dbg(xhci, fmt, args...) \ 1911 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1912 #define xhci_err(xhci, fmt, args...) \ 1913 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1914 #define xhci_warn(xhci, fmt, args...) \ 1915 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1916 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1917 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1918 #define xhci_info(xhci, fmt, args...) \ 1919 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1920 1921 /* 1922 * Registers should always be accessed with double word or quad word accesses. 1923 * 1924 * Some xHCI implementations may support 64-bit address pointers. Registers 1925 * with 64-bit address pointers should be written to with dword accesses by 1926 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1927 * xHCI implementations that do not support 64-bit address pointers will ignore 1928 * the high dword, and write order is irrelevant. 1929 */ 1930 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1931 __le64 __iomem *regs) 1932 { 1933 return lo_hi_readq(regs); 1934 } 1935 static inline void xhci_write_64(struct xhci_hcd *xhci, 1936 const u64 val, __le64 __iomem *regs) 1937 { 1938 lo_hi_writeq(val, regs); 1939 } 1940 1941 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1942 { 1943 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1944 } 1945 1946 /* xHCI debugging */ 1947 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1948 struct xhci_container_ctx *ctx); 1949 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1950 const char *fmt, ...); 1951 1952 /* xHCI memory management */ 1953 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1954 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1955 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1956 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1957 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1958 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1959 struct usb_device *udev); 1960 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1961 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1962 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1963 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1964 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1965 struct xhci_virt_device *virt_dev, 1966 int old_active_eps); 1967 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1968 void xhci_update_bw_info(struct xhci_hcd *xhci, 1969 struct xhci_container_ctx *in_ctx, 1970 struct xhci_input_control_ctx *ctrl_ctx, 1971 struct xhci_virt_device *virt_dev); 1972 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1973 struct xhci_container_ctx *in_ctx, 1974 struct xhci_container_ctx *out_ctx, 1975 unsigned int ep_index); 1976 void xhci_slot_copy(struct xhci_hcd *xhci, 1977 struct xhci_container_ctx *in_ctx, 1978 struct xhci_container_ctx *out_ctx); 1979 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1980 struct usb_device *udev, struct usb_host_endpoint *ep, 1981 gfp_t mem_flags); 1982 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, 1983 unsigned int num_segs, unsigned int cycle_state, 1984 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1985 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1986 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1987 unsigned int num_trbs, gfp_t flags); 1988 int xhci_alloc_erst(struct xhci_hcd *xhci, 1989 struct xhci_ring *evt_ring, 1990 struct xhci_erst *erst, 1991 gfp_t flags); 1992 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1993 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1994 struct xhci_virt_device *virt_dev, 1995 unsigned int ep_index); 1996 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1997 unsigned int num_stream_ctxs, 1998 unsigned int num_streams, 1999 unsigned int max_packet, gfp_t flags); 2000 void xhci_free_stream_info(struct xhci_hcd *xhci, 2001 struct xhci_stream_info *stream_info); 2002 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 2003 struct xhci_ep_ctx *ep_ctx, 2004 struct xhci_stream_info *stream_info); 2005 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 2006 struct xhci_virt_ep *ep); 2007 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 2008 struct xhci_virt_device *virt_dev, bool drop_control_ep); 2009 struct xhci_ring *xhci_dma_to_transfer_ring( 2010 struct xhci_virt_ep *ep, 2011 u64 address); 2012 struct xhci_ring *xhci_stream_id_to_ring( 2013 struct xhci_virt_device *dev, 2014 unsigned int ep_index, 2015 unsigned int stream_id); 2016 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 2017 bool allocate_completion, gfp_t mem_flags); 2018 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 2019 bool allocate_completion, gfp_t mem_flags); 2020 void xhci_urb_free_priv(struct urb_priv *urb_priv); 2021 void xhci_free_command(struct xhci_hcd *xhci, 2022 struct xhci_command *command); 2023 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 2024 int type, gfp_t flags); 2025 void xhci_free_container_ctx(struct xhci_hcd *xhci, 2026 struct xhci_container_ctx *ctx); 2027 2028 /* xHCI host controller glue */ 2029 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 2030 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 2031 void xhci_quiesce(struct xhci_hcd *xhci); 2032 int xhci_halt(struct xhci_hcd *xhci); 2033 int xhci_start(struct xhci_hcd *xhci); 2034 int xhci_reset(struct xhci_hcd *xhci); 2035 int xhci_run(struct usb_hcd *hcd); 2036 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2037 void xhci_init_driver(struct hc_driver *drv, 2038 const struct xhci_driver_overrides *over); 2039 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 2040 int xhci_ext_cap_init(struct xhci_hcd *xhci); 2041 2042 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2043 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 2044 2045 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2046 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2047 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2048 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2049 struct xhci_virt_device *virt_dev, 2050 struct usb_device *hdev, 2051 struct usb_tt *tt, gfp_t mem_flags); 2052 2053 /* xHCI ring, segment, TRB, and TD functions */ 2054 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2055 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2056 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2057 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2058 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2059 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2060 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2061 u32 trb_type, u32 slot_id); 2062 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2063 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2064 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2065 u32 field1, u32 field2, u32 field3, u32 field4); 2066 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2067 int slot_id, unsigned int ep_index, int suspend); 2068 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2069 int slot_id, unsigned int ep_index); 2070 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2071 int slot_id, unsigned int ep_index); 2072 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2073 int slot_id, unsigned int ep_index); 2074 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2075 struct urb *urb, int slot_id, unsigned int ep_index); 2076 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2077 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2078 bool command_must_succeed); 2079 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2080 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2081 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2082 int slot_id, unsigned int ep_index, 2083 enum xhci_ep_reset_type reset_type); 2084 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2085 u32 slot_id); 2086 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 2087 unsigned int slot_id, unsigned int ep_index, 2088 unsigned int stream_id, struct xhci_td *cur_td, 2089 struct xhci_dequeue_state *state); 2090 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 2091 unsigned int slot_id, unsigned int ep_index, 2092 struct xhci_dequeue_state *deq_state); 2093 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index, 2094 unsigned int stream_id, struct xhci_td *td); 2095 void xhci_stop_endpoint_command_watchdog(struct timer_list *t); 2096 void xhci_handle_command_timeout(struct work_struct *work); 2097 2098 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2099 unsigned int ep_index, unsigned int stream_id); 2100 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2101 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 2102 unsigned int count_trbs(u64 addr, u64 len); 2103 2104 /* xHCI roothub code */ 2105 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 2106 u32 link_state); 2107 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 2108 u32 port_bit); 2109 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2110 char *buf, u16 wLength); 2111 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2112 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2113 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 2114 2115 void xhci_hc_died(struct xhci_hcd *xhci); 2116 2117 #ifdef CONFIG_PM 2118 int xhci_bus_suspend(struct usb_hcd *hcd); 2119 int xhci_bus_resume(struct usb_hcd *hcd); 2120 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 2121 #else 2122 #define xhci_bus_suspend NULL 2123 #define xhci_bus_resume NULL 2124 #define xhci_get_resuming_ports NULL 2125 #endif /* CONFIG_PM */ 2126 2127 u32 xhci_port_state_to_neutral(u32 state); 2128 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2129 u16 port); 2130 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2131 2132 /* xHCI contexts */ 2133 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2134 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2135 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2136 2137 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2138 unsigned int slot_id, unsigned int ep_index, 2139 unsigned int stream_id); 2140 2141 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2142 struct urb *urb) 2143 { 2144 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2145 xhci_get_endpoint_index(&urb->ep->desc), 2146 urb->stream_id); 2147 } 2148 2149 static inline char *xhci_slot_state_string(u32 state) 2150 { 2151 switch (state) { 2152 case SLOT_STATE_ENABLED: 2153 return "enabled/disabled"; 2154 case SLOT_STATE_DEFAULT: 2155 return "default"; 2156 case SLOT_STATE_ADDRESSED: 2157 return "addressed"; 2158 case SLOT_STATE_CONFIGURED: 2159 return "configured"; 2160 default: 2161 return "reserved"; 2162 } 2163 } 2164 2165 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, 2166 u32 field3) 2167 { 2168 static char str[256]; 2169 int type = TRB_FIELD_TO_TYPE(field3); 2170 2171 switch (type) { 2172 case TRB_LINK: 2173 sprintf(str, 2174 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2175 field1, field0, GET_INTR_TARGET(field2), 2176 xhci_trb_type_string(type), 2177 field3 & TRB_IOC ? 'I' : 'i', 2178 field3 & TRB_CHAIN ? 'C' : 'c', 2179 field3 & TRB_TC ? 'T' : 't', 2180 field3 & TRB_CYCLE ? 'C' : 'c'); 2181 break; 2182 case TRB_TRANSFER: 2183 case TRB_COMPLETION: 2184 case TRB_PORT_STATUS: 2185 case TRB_BANDWIDTH_EVENT: 2186 case TRB_DOORBELL: 2187 case TRB_HC_EVENT: 2188 case TRB_DEV_NOTE: 2189 case TRB_MFINDEX_WRAP: 2190 sprintf(str, 2191 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2192 field1, field0, 2193 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2194 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2195 /* Macro decrements 1, maybe it shouldn't?!? */ 2196 TRB_TO_EP_INDEX(field3) + 1, 2197 xhci_trb_type_string(type), 2198 field3 & EVENT_DATA ? 'E' : 'e', 2199 field3 & TRB_CYCLE ? 'C' : 'c'); 2200 2201 break; 2202 case TRB_SETUP: 2203 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2204 field0 & 0xff, 2205 (field0 & 0xff00) >> 8, 2206 (field0 & 0xff000000) >> 24, 2207 (field0 & 0xff0000) >> 16, 2208 (field1 & 0xff00) >> 8, 2209 field1 & 0xff, 2210 (field1 & 0xff000000) >> 16 | 2211 (field1 & 0xff0000) >> 16, 2212 TRB_LEN(field2), GET_TD_SIZE(field2), 2213 GET_INTR_TARGET(field2), 2214 xhci_trb_type_string(type), 2215 field3 & TRB_IDT ? 'I' : 'i', 2216 field3 & TRB_IOC ? 'I' : 'i', 2217 field3 & TRB_CYCLE ? 'C' : 'c'); 2218 break; 2219 case TRB_DATA: 2220 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2221 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2222 GET_INTR_TARGET(field2), 2223 xhci_trb_type_string(type), 2224 field3 & TRB_IDT ? 'I' : 'i', 2225 field3 & TRB_IOC ? 'I' : 'i', 2226 field3 & TRB_CHAIN ? 'C' : 'c', 2227 field3 & TRB_NO_SNOOP ? 'S' : 's', 2228 field3 & TRB_ISP ? 'I' : 'i', 2229 field3 & TRB_ENT ? 'E' : 'e', 2230 field3 & TRB_CYCLE ? 'C' : 'c'); 2231 break; 2232 case TRB_STATUS: 2233 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2234 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2235 GET_INTR_TARGET(field2), 2236 xhci_trb_type_string(type), 2237 field3 & TRB_IOC ? 'I' : 'i', 2238 field3 & TRB_CHAIN ? 'C' : 'c', 2239 field3 & TRB_ENT ? 'E' : 'e', 2240 field3 & TRB_CYCLE ? 'C' : 'c'); 2241 break; 2242 case TRB_NORMAL: 2243 case TRB_ISOC: 2244 case TRB_EVENT_DATA: 2245 case TRB_TR_NOOP: 2246 sprintf(str, 2247 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2248 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2249 GET_INTR_TARGET(field2), 2250 xhci_trb_type_string(type), 2251 field3 & TRB_BEI ? 'B' : 'b', 2252 field3 & TRB_IDT ? 'I' : 'i', 2253 field3 & TRB_IOC ? 'I' : 'i', 2254 field3 & TRB_CHAIN ? 'C' : 'c', 2255 field3 & TRB_NO_SNOOP ? 'S' : 's', 2256 field3 & TRB_ISP ? 'I' : 'i', 2257 field3 & TRB_ENT ? 'E' : 'e', 2258 field3 & TRB_CYCLE ? 'C' : 'c'); 2259 break; 2260 2261 case TRB_CMD_NOOP: 2262 case TRB_ENABLE_SLOT: 2263 sprintf(str, 2264 "%s: flags %c", 2265 xhci_trb_type_string(type), 2266 field3 & TRB_CYCLE ? 'C' : 'c'); 2267 break; 2268 case TRB_DISABLE_SLOT: 2269 case TRB_NEG_BANDWIDTH: 2270 sprintf(str, 2271 "%s: slot %d flags %c", 2272 xhci_trb_type_string(type), 2273 TRB_TO_SLOT_ID(field3), 2274 field3 & TRB_CYCLE ? 'C' : 'c'); 2275 break; 2276 case TRB_ADDR_DEV: 2277 sprintf(str, 2278 "%s: ctx %08x%08x slot %d flags %c:%c", 2279 xhci_trb_type_string(type), 2280 field1, field0, 2281 TRB_TO_SLOT_ID(field3), 2282 field3 & TRB_BSR ? 'B' : 'b', 2283 field3 & TRB_CYCLE ? 'C' : 'c'); 2284 break; 2285 case TRB_CONFIG_EP: 2286 sprintf(str, 2287 "%s: ctx %08x%08x slot %d flags %c:%c", 2288 xhci_trb_type_string(type), 2289 field1, field0, 2290 TRB_TO_SLOT_ID(field3), 2291 field3 & TRB_DC ? 'D' : 'd', 2292 field3 & TRB_CYCLE ? 'C' : 'c'); 2293 break; 2294 case TRB_EVAL_CONTEXT: 2295 sprintf(str, 2296 "%s: ctx %08x%08x slot %d flags %c", 2297 xhci_trb_type_string(type), 2298 field1, field0, 2299 TRB_TO_SLOT_ID(field3), 2300 field3 & TRB_CYCLE ? 'C' : 'c'); 2301 break; 2302 case TRB_RESET_EP: 2303 sprintf(str, 2304 "%s: ctx %08x%08x slot %d ep %d flags %c", 2305 xhci_trb_type_string(type), 2306 field1, field0, 2307 TRB_TO_SLOT_ID(field3), 2308 /* Macro decrements 1, maybe it shouldn't?!? */ 2309 TRB_TO_EP_INDEX(field3) + 1, 2310 field3 & TRB_CYCLE ? 'C' : 'c'); 2311 break; 2312 case TRB_STOP_RING: 2313 sprintf(str, 2314 "%s: slot %d sp %d ep %d flags %c", 2315 xhci_trb_type_string(type), 2316 TRB_TO_SLOT_ID(field3), 2317 TRB_TO_SUSPEND_PORT(field3), 2318 /* Macro decrements 1, maybe it shouldn't?!? */ 2319 TRB_TO_EP_INDEX(field3) + 1, 2320 field3 & TRB_CYCLE ? 'C' : 'c'); 2321 break; 2322 case TRB_SET_DEQ: 2323 sprintf(str, 2324 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2325 xhci_trb_type_string(type), 2326 field1, field0, 2327 TRB_TO_STREAM_ID(field2), 2328 TRB_TO_SLOT_ID(field3), 2329 /* Macro decrements 1, maybe it shouldn't?!? */ 2330 TRB_TO_EP_INDEX(field3) + 1, 2331 field3 & TRB_CYCLE ? 'C' : 'c'); 2332 break; 2333 case TRB_RESET_DEV: 2334 sprintf(str, 2335 "%s: slot %d flags %c", 2336 xhci_trb_type_string(type), 2337 TRB_TO_SLOT_ID(field3), 2338 field3 & TRB_CYCLE ? 'C' : 'c'); 2339 break; 2340 case TRB_FORCE_EVENT: 2341 sprintf(str, 2342 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2343 xhci_trb_type_string(type), 2344 field1, field0, 2345 TRB_TO_VF_INTR_TARGET(field2), 2346 TRB_TO_VF_ID(field3), 2347 field3 & TRB_CYCLE ? 'C' : 'c'); 2348 break; 2349 case TRB_SET_LT: 2350 sprintf(str, 2351 "%s: belt %d flags %c", 2352 xhci_trb_type_string(type), 2353 TRB_TO_BELT(field3), 2354 field3 & TRB_CYCLE ? 'C' : 'c'); 2355 break; 2356 case TRB_GET_BW: 2357 sprintf(str, 2358 "%s: ctx %08x%08x slot %d speed %d flags %c", 2359 xhci_trb_type_string(type), 2360 field1, field0, 2361 TRB_TO_SLOT_ID(field3), 2362 TRB_TO_DEV_SPEED(field3), 2363 field3 & TRB_CYCLE ? 'C' : 'c'); 2364 break; 2365 case TRB_FORCE_HEADER: 2366 sprintf(str, 2367 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2368 xhci_trb_type_string(type), 2369 field2, field1, field0 & 0xffffffe0, 2370 TRB_TO_PACKET_TYPE(field0), 2371 TRB_TO_ROOTHUB_PORT(field3), 2372 field3 & TRB_CYCLE ? 'C' : 'c'); 2373 break; 2374 default: 2375 sprintf(str, 2376 "type '%s' -> raw %08x %08x %08x %08x", 2377 xhci_trb_type_string(type), 2378 field0, field1, field2, field3); 2379 } 2380 2381 return str; 2382 } 2383 2384 static inline const char *xhci_decode_slot_context(u32 info, u32 info2, 2385 u32 tt_info, u32 state) 2386 { 2387 static char str[1024]; 2388 u32 speed; 2389 u32 hub; 2390 u32 mtt; 2391 int ret = 0; 2392 2393 speed = info & DEV_SPEED; 2394 hub = info & DEV_HUB; 2395 mtt = info & DEV_MTT; 2396 2397 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2398 info & ROUTE_STRING_MASK, 2399 ({ char *s; 2400 switch (speed) { 2401 case SLOT_SPEED_FS: 2402 s = "full-speed"; 2403 break; 2404 case SLOT_SPEED_LS: 2405 s = "low-speed"; 2406 break; 2407 case SLOT_SPEED_HS: 2408 s = "high-speed"; 2409 break; 2410 case SLOT_SPEED_SS: 2411 s = "super-speed"; 2412 break; 2413 case SLOT_SPEED_SSP: 2414 s = "super-speed plus"; 2415 break; 2416 default: 2417 s = "UNKNOWN speed"; 2418 } s; }), 2419 mtt ? " multi-TT" : "", 2420 hub ? " Hub" : "", 2421 (info & LAST_CTX_MASK) >> 27, 2422 info2 & MAX_EXIT, 2423 DEVINFO_TO_ROOT_HUB_PORT(info2), 2424 DEVINFO_TO_MAX_PORTS(info2)); 2425 2426 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2427 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2428 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2429 state & DEV_ADDR_MASK, 2430 xhci_slot_state_string(GET_SLOT_STATE(state))); 2431 2432 return str; 2433 } 2434 2435 2436 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2437 { 2438 switch (portsc & PORT_PLS_MASK) { 2439 case XDEV_U0: 2440 return "U0"; 2441 case XDEV_U1: 2442 return "U1"; 2443 case XDEV_U2: 2444 return "U2"; 2445 case XDEV_U3: 2446 return "U3"; 2447 case XDEV_DISABLED: 2448 return "Disabled"; 2449 case XDEV_RXDETECT: 2450 return "RxDetect"; 2451 case XDEV_INACTIVE: 2452 return "Inactive"; 2453 case XDEV_POLLING: 2454 return "Polling"; 2455 case XDEV_RECOVERY: 2456 return "Recovery"; 2457 case XDEV_HOT_RESET: 2458 return "Hot Reset"; 2459 case XDEV_COMP_MODE: 2460 return "Compliance mode"; 2461 case XDEV_TEST_MODE: 2462 return "Test mode"; 2463 case XDEV_RESUME: 2464 return "Resume"; 2465 default: 2466 break; 2467 } 2468 return "Unknown"; 2469 } 2470 2471 static inline const char *xhci_decode_portsc(u32 portsc) 2472 { 2473 static char str[256]; 2474 int ret; 2475 2476 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ", 2477 portsc & PORT_POWER ? "Powered" : "Powered-off", 2478 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2479 portsc & PORT_PE ? "Enabled" : "Disabled", 2480 xhci_portsc_link_state_string(portsc), 2481 DEV_PORT_SPEED(portsc)); 2482 2483 if (portsc & PORT_OC) 2484 ret += sprintf(str + ret, "OverCurrent "); 2485 if (portsc & PORT_RESET) 2486 ret += sprintf(str + ret, "In-Reset "); 2487 2488 ret += sprintf(str + ret, "Change: "); 2489 if (portsc & PORT_CSC) 2490 ret += sprintf(str + ret, "CSC "); 2491 if (portsc & PORT_PEC) 2492 ret += sprintf(str + ret, "PEC "); 2493 if (portsc & PORT_WRC) 2494 ret += sprintf(str + ret, "WRC "); 2495 if (portsc & PORT_OCC) 2496 ret += sprintf(str + ret, "OCC "); 2497 if (portsc & PORT_RC) 2498 ret += sprintf(str + ret, "PRC "); 2499 if (portsc & PORT_PLC) 2500 ret += sprintf(str + ret, "PLC "); 2501 if (portsc & PORT_CEC) 2502 ret += sprintf(str + ret, "CEC "); 2503 if (portsc & PORT_CAS) 2504 ret += sprintf(str + ret, "CAS "); 2505 2506 ret += sprintf(str + ret, "Wake: "); 2507 if (portsc & PORT_WKCONN_E) 2508 ret += sprintf(str + ret, "WCE "); 2509 if (portsc & PORT_WKDISC_E) 2510 ret += sprintf(str + ret, "WDE "); 2511 if (portsc & PORT_WKOC_E) 2512 ret += sprintf(str + ret, "WOE "); 2513 2514 return str; 2515 } 2516 2517 static inline const char *xhci_ep_state_string(u8 state) 2518 { 2519 switch (state) { 2520 case EP_STATE_DISABLED: 2521 return "disabled"; 2522 case EP_STATE_RUNNING: 2523 return "running"; 2524 case EP_STATE_HALTED: 2525 return "halted"; 2526 case EP_STATE_STOPPED: 2527 return "stopped"; 2528 case EP_STATE_ERROR: 2529 return "error"; 2530 default: 2531 return "INVALID"; 2532 } 2533 } 2534 2535 static inline const char *xhci_ep_type_string(u8 type) 2536 { 2537 switch (type) { 2538 case ISOC_OUT_EP: 2539 return "Isoc OUT"; 2540 case BULK_OUT_EP: 2541 return "Bulk OUT"; 2542 case INT_OUT_EP: 2543 return "Int OUT"; 2544 case CTRL_EP: 2545 return "Ctrl"; 2546 case ISOC_IN_EP: 2547 return "Isoc IN"; 2548 case BULK_IN_EP: 2549 return "Bulk IN"; 2550 case INT_IN_EP: 2551 return "Int IN"; 2552 default: 2553 return "INVALID"; 2554 } 2555 } 2556 2557 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq, 2558 u32 tx_info) 2559 { 2560 static char str[1024]; 2561 int ret; 2562 2563 u32 esit; 2564 u16 maxp; 2565 u16 avg; 2566 2567 u8 max_pstr; 2568 u8 ep_state; 2569 u8 interval; 2570 u8 ep_type; 2571 u8 burst; 2572 u8 cerr; 2573 u8 mult; 2574 2575 bool lsa; 2576 bool hid; 2577 2578 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2579 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2580 2581 ep_state = info & EP_STATE_MASK; 2582 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2583 interval = CTX_TO_EP_INTERVAL(info); 2584 mult = CTX_TO_EP_MULT(info) + 1; 2585 lsa = !!(info & EP_HAS_LSA); 2586 2587 cerr = (info2 & (3 << 1)) >> 1; 2588 ep_type = CTX_TO_EP_TYPE(info2); 2589 hid = !!(info2 & (1 << 7)); 2590 burst = CTX_TO_MAX_BURST(info2); 2591 maxp = MAX_PACKET_DECODED(info2); 2592 2593 avg = EP_AVG_TRB_LENGTH(tx_info); 2594 2595 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2596 xhci_ep_state_string(ep_state), mult, 2597 max_pstr, lsa ? "LSA " : ""); 2598 2599 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2600 (1 << interval) * 125, esit, cerr); 2601 2602 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2603 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2604 burst, maxp, deq); 2605 2606 ret += sprintf(str + ret, "avg trb len %d", avg); 2607 2608 return str; 2609 } 2610 2611 #endif /* __LINUX_XHCI_HCD_H */ 2612