1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #ifndef __LINUX_XHCI_HCD_H 24 #define __LINUX_XHCI_HCD_H 25 26 #include <linux/usb.h> 27 #include <linux/timer.h> 28 #include <linux/kernel.h> 29 #include <linux/usb/hcd.h> 30 31 /* 32 * Registers should always be accessed with double word or quad word accesses. 33 * 34 * Some xHCI implementations may support 64-bit address pointers. Registers 35 * with 64-bit address pointers should be written to with dword accesses by 36 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 37 * xHCI implementations that do not support 64-bit address pointers will ignore 38 * the high dword, and write order is irrelevant. 39 */ 40 #include <asm-generic/io-64-nonatomic-lo-hi.h> 41 42 /* Code sharing between pci-quirks and xhci hcd */ 43 #include "xhci-ext-caps.h" 44 #include "pci-quirks.h" 45 46 /* xHCI PCI Configuration Registers */ 47 #define XHCI_SBRN_OFFSET (0x60) 48 49 /* Max number of USB devices for any host controller - limit in section 6.1 */ 50 #define MAX_HC_SLOTS 256 51 /* Section 5.3.3 - MaxPorts */ 52 #define MAX_HC_PORTS 127 53 54 /* 55 * xHCI register interface. 56 * This corresponds to the eXtensible Host Controller Interface (xHCI) 57 * Revision 0.95 specification 58 */ 59 60 /** 61 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 62 * @hc_capbase: length of the capabilities register and HC version number 63 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 64 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 65 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 66 * @hcc_params: HCCPARAMS - Capability Parameters 67 * @db_off: DBOFF - Doorbell array offset 68 * @run_regs_off: RTSOFF - Runtime register space offset 69 */ 70 struct xhci_cap_regs { 71 __le32 hc_capbase; 72 __le32 hcs_params1; 73 __le32 hcs_params2; 74 __le32 hcs_params3; 75 __le32 hcc_params; 76 __le32 db_off; 77 __le32 run_regs_off; 78 /* Reserved up to (CAPLENGTH - 0x1C) */ 79 }; 80 81 /* hc_capbase bitmasks */ 82 /* bits 7:0 - how long is the Capabilities register */ 83 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 84 /* bits 31:16 */ 85 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 86 87 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 88 /* bits 0:7, Max Device Slots */ 89 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 90 #define HCS_SLOTS_MASK 0xff 91 /* bits 8:18, Max Interrupters */ 92 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 93 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 94 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 95 96 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 97 /* bits 0:3, frames or uframes that SW needs to queue transactions 98 * ahead of the HW to meet periodic deadlines */ 99 #define HCS_IST(p) (((p) >> 0) & 0xf) 100 /* bits 4:7, max number of Event Ring segments */ 101 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 102 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 103 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 104 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 105 106 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 107 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 108 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 109 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 110 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 111 112 /* HCCPARAMS - hcc_params - bitmasks */ 113 /* true: HC can use 64-bit address pointers */ 114 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 115 /* true: HC can do bandwidth negotiation */ 116 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 117 /* true: HC uses 64-byte Device Context structures 118 * FIXME 64-byte context structures aren't supported yet. 119 */ 120 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 121 /* true: HC has port power switches */ 122 #define HCC_PPC(p) ((p) & (1 << 3)) 123 /* true: HC has port indicators */ 124 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 125 /* true: HC has Light HC Reset Capability */ 126 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 127 /* true: HC supports latency tolerance messaging */ 128 #define HCC_LTC(p) ((p) & (1 << 6)) 129 /* true: no secondary Stream ID Support */ 130 #define HCC_NSS(p) ((p) & (1 << 7)) 131 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 132 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 133 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 134 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 135 136 /* db_off bitmask - bits 0:1 reserved */ 137 #define DBOFF_MASK (~0x3) 138 139 /* run_regs_off bitmask - bits 0:4 reserved */ 140 #define RTSOFF_MASK (~0x1f) 141 142 143 /* Number of registers per port */ 144 #define NUM_PORT_REGS 4 145 146 #define PORTSC 0 147 #define PORTPMSC 1 148 #define PORTLI 2 149 #define PORTHLPMC 3 150 151 /** 152 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 153 * @command: USBCMD - xHC command register 154 * @status: USBSTS - xHC status register 155 * @page_size: This indicates the page size that the host controller 156 * supports. If bit n is set, the HC supports a page size 157 * of 2^(n+12), up to a 128MB page size. 158 * 4K is the minimum page size. 159 * @cmd_ring: CRP - 64-bit Command Ring Pointer 160 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 161 * @config_reg: CONFIG - Configure Register 162 * @port_status_base: PORTSCn - base address for Port Status and Control 163 * Each port has a Port Status and Control register, 164 * followed by a Port Power Management Status and Control 165 * register, a Port Link Info register, and a reserved 166 * register. 167 * @port_power_base: PORTPMSCn - base address for 168 * Port Power Management Status and Control 169 * @port_link_base: PORTLIn - base address for Port Link Info (current 170 * Link PM state and control) for USB 2.1 and USB 3.0 171 * devices. 172 */ 173 struct xhci_op_regs { 174 __le32 command; 175 __le32 status; 176 __le32 page_size; 177 __le32 reserved1; 178 __le32 reserved2; 179 __le32 dev_notification; 180 __le64 cmd_ring; 181 /* rsvd: offset 0x20-2F */ 182 __le32 reserved3[4]; 183 __le64 dcbaa_ptr; 184 __le32 config_reg; 185 /* rsvd: offset 0x3C-3FF */ 186 __le32 reserved4[241]; 187 /* port 1 registers, which serve as a base address for other ports */ 188 __le32 port_status_base; 189 __le32 port_power_base; 190 __le32 port_link_base; 191 __le32 reserved5; 192 /* registers for ports 2-255 */ 193 __le32 reserved6[NUM_PORT_REGS*254]; 194 }; 195 196 /* USBCMD - USB command - command bitmasks */ 197 /* start/stop HC execution - do not write unless HC is halted*/ 198 #define CMD_RUN XHCI_CMD_RUN 199 /* Reset HC - resets internal HC state machine and all registers (except 200 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 201 * The xHCI driver must reinitialize the xHC after setting this bit. 202 */ 203 #define CMD_RESET (1 << 1) 204 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 205 #define CMD_EIE XHCI_CMD_EIE 206 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 207 #define CMD_HSEIE XHCI_CMD_HSEIE 208 /* bits 4:6 are reserved (and should be preserved on writes). */ 209 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 210 #define CMD_LRESET (1 << 7) 211 /* host controller save/restore state. */ 212 #define CMD_CSS (1 << 8) 213 #define CMD_CRS (1 << 9) 214 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 215 #define CMD_EWE XHCI_CMD_EWE 216 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 217 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 218 * '0' means the xHC can power it off if all ports are in the disconnect, 219 * disabled, or powered-off state. 220 */ 221 #define CMD_PM_INDEX (1 << 11) 222 /* bits 12:31 are reserved (and should be preserved on writes). */ 223 224 /* IMAN - Interrupt Management Register */ 225 #define IMAN_IE (1 << 1) 226 #define IMAN_IP (1 << 0) 227 228 /* USBSTS - USB status - status bitmasks */ 229 /* HC not running - set to 1 when run/stop bit is cleared. */ 230 #define STS_HALT XHCI_STS_HALT 231 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 232 #define STS_FATAL (1 << 2) 233 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 234 #define STS_EINT (1 << 3) 235 /* port change detect */ 236 #define STS_PORT (1 << 4) 237 /* bits 5:7 reserved and zeroed */ 238 /* save state status - '1' means xHC is saving state */ 239 #define STS_SAVE (1 << 8) 240 /* restore state status - '1' means xHC is restoring state */ 241 #define STS_RESTORE (1 << 9) 242 /* true: save or restore error */ 243 #define STS_SRE (1 << 10) 244 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 245 #define STS_CNR XHCI_STS_CNR 246 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 247 #define STS_HCE (1 << 12) 248 /* bits 13:31 reserved and should be preserved */ 249 250 /* 251 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 252 * Generate a device notification event when the HC sees a transaction with a 253 * notification type that matches a bit set in this bit field. 254 */ 255 #define DEV_NOTE_MASK (0xffff) 256 #define ENABLE_DEV_NOTE(x) (1 << (x)) 257 /* Most of the device notification types should only be used for debug. 258 * SW does need to pay attention to function wake notifications. 259 */ 260 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 261 262 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 263 /* bit 0 is the command ring cycle state */ 264 /* stop ring operation after completion of the currently executing command */ 265 #define CMD_RING_PAUSE (1 << 1) 266 /* stop ring immediately - abort the currently executing command */ 267 #define CMD_RING_ABORT (1 << 2) 268 /* true: command ring is running */ 269 #define CMD_RING_RUNNING (1 << 3) 270 /* bits 4:5 reserved and should be preserved */ 271 /* Command Ring pointer - bit mask for the lower 32 bits. */ 272 #define CMD_RING_RSVD_BITS (0x3f) 273 274 /* CONFIG - Configure Register - config_reg bitmasks */ 275 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 276 #define MAX_DEVS(p) ((p) & 0xff) 277 /* bits 8:31 - reserved and should be preserved */ 278 279 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 280 /* true: device connected */ 281 #define PORT_CONNECT (1 << 0) 282 /* true: port enabled */ 283 #define PORT_PE (1 << 1) 284 /* bit 2 reserved and zeroed */ 285 /* true: port has an over-current condition */ 286 #define PORT_OC (1 << 3) 287 /* true: port reset signaling asserted */ 288 #define PORT_RESET (1 << 4) 289 /* Port Link State - bits 5:8 290 * A read gives the current link PM state of the port, 291 * a write with Link State Write Strobe set sets the link state. 292 */ 293 #define PORT_PLS_MASK (0xf << 5) 294 #define XDEV_U0 (0x0 << 5) 295 #define XDEV_U2 (0x2 << 5) 296 #define XDEV_U3 (0x3 << 5) 297 #define XDEV_RESUME (0xf << 5) 298 /* true: port has power (see HCC_PPC) */ 299 #define PORT_POWER (1 << 9) 300 /* bits 10:13 indicate device speed: 301 * 0 - undefined speed - port hasn't be initialized by a reset yet 302 * 1 - full speed 303 * 2 - low speed 304 * 3 - high speed 305 * 4 - super speed 306 * 5-15 reserved 307 */ 308 #define DEV_SPEED_MASK (0xf << 10) 309 #define XDEV_FS (0x1 << 10) 310 #define XDEV_LS (0x2 << 10) 311 #define XDEV_HS (0x3 << 10) 312 #define XDEV_SS (0x4 << 10) 313 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 314 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 315 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 316 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 317 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 318 /* Bits 20:23 in the Slot Context are the speed for the device */ 319 #define SLOT_SPEED_FS (XDEV_FS << 10) 320 #define SLOT_SPEED_LS (XDEV_LS << 10) 321 #define SLOT_SPEED_HS (XDEV_HS << 10) 322 #define SLOT_SPEED_SS (XDEV_SS << 10) 323 /* Port Indicator Control */ 324 #define PORT_LED_OFF (0 << 14) 325 #define PORT_LED_AMBER (1 << 14) 326 #define PORT_LED_GREEN (2 << 14) 327 #define PORT_LED_MASK (3 << 14) 328 /* Port Link State Write Strobe - set this when changing link state */ 329 #define PORT_LINK_STROBE (1 << 16) 330 /* true: connect status change */ 331 #define PORT_CSC (1 << 17) 332 /* true: port enable change */ 333 #define PORT_PEC (1 << 18) 334 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 335 * into an enabled state, and the device into the default state. A "warm" reset 336 * also resets the link, forcing the device through the link training sequence. 337 * SW can also look at the Port Reset register to see when warm reset is done. 338 */ 339 #define PORT_WRC (1 << 19) 340 /* true: over-current change */ 341 #define PORT_OCC (1 << 20) 342 /* true: reset change - 1 to 0 transition of PORT_RESET */ 343 #define PORT_RC (1 << 21) 344 /* port link status change - set on some port link state transitions: 345 * Transition Reason 346 * ------------------------------------------------------------------------------ 347 * - U3 to Resume Wakeup signaling from a device 348 * - Resume to Recovery to U0 USB 3.0 device resume 349 * - Resume to U0 USB 2.0 device resume 350 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 351 * - U3 to U0 Software resume of USB 2.0 device complete 352 * - U2 to U0 L1 resume of USB 2.1 device complete 353 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 354 * - U0 to disabled L1 entry error with USB 2.1 device 355 * - Any state to inactive Error on USB 3.0 port 356 */ 357 #define PORT_PLC (1 << 22) 358 /* port configure error change - port failed to configure its link partner */ 359 #define PORT_CEC (1 << 23) 360 /* Cold Attach Status - xHC can set this bit to report device attached during 361 * Sx state. Warm port reset should be perfomed to clear this bit and move port 362 * to connected state. 363 */ 364 #define PORT_CAS (1 << 24) 365 /* wake on connect (enable) */ 366 #define PORT_WKCONN_E (1 << 25) 367 /* wake on disconnect (enable) */ 368 #define PORT_WKDISC_E (1 << 26) 369 /* wake on over-current (enable) */ 370 #define PORT_WKOC_E (1 << 27) 371 /* bits 28:29 reserved */ 372 /* true: device is removable - for USB 3.0 roothub emulation */ 373 #define PORT_DEV_REMOVE (1 << 30) 374 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 375 #define PORT_WR (1 << 31) 376 377 /* We mark duplicate entries with -1 */ 378 #define DUPLICATE_ENTRY ((u8)(-1)) 379 380 /* Port Power Management Status and Control - port_power_base bitmasks */ 381 /* Inactivity timer value for transitions into U1, in microseconds. 382 * Timeout can be up to 127us. 0xFF means an infinite timeout. 383 */ 384 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 385 #define PORT_U1_TIMEOUT_MASK 0xff 386 /* Inactivity timer value for transitions into U2 */ 387 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 388 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 389 /* Bits 24:31 for port testing */ 390 391 /* USB2 Protocol PORTSPMSC */ 392 #define PORT_L1S_MASK 7 393 #define PORT_L1S_SUCCESS 1 394 #define PORT_RWE (1 << 3) 395 #define PORT_HIRD(p) (((p) & 0xf) << 4) 396 #define PORT_HIRD_MASK (0xf << 4) 397 #define PORT_L1DS_MASK (0xff << 8) 398 #define PORT_L1DS(p) (((p) & 0xff) << 8) 399 #define PORT_HLE (1 << 16) 400 401 402 /* USB2 Protocol PORTHLPMC */ 403 #define PORT_HIRDM(p)((p) & 3) 404 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 405 #define PORT_BESLD(p)(((p) & 0xf) << 10) 406 407 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 408 #define XHCI_L1_TIMEOUT 512 409 410 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 411 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 412 * by other operating systems. 413 * 414 * XHCI 1.0 errata 8/14/12 Table 13 notes: 415 * "Software should choose xHC BESL/BESLD field values that do not violate a 416 * device's resume latency requirements, 417 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 418 * or not program values < '4' if BLC = '0' and a BESL device is attached. 419 */ 420 #define XHCI_DEFAULT_BESL 4 421 422 /** 423 * struct xhci_intr_reg - Interrupt Register Set 424 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 425 * interrupts and check for pending interrupts. 426 * @irq_control: IMOD - Interrupt Moderation Register. 427 * Used to throttle interrupts. 428 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 429 * @erst_base: ERST base address. 430 * @erst_dequeue: Event ring dequeue pointer. 431 * 432 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 433 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 434 * multiple segments of the same size. The HC places events on the ring and 435 * "updates the Cycle bit in the TRBs to indicate to software the current 436 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 437 * updates the dequeue pointer. 438 */ 439 struct xhci_intr_reg { 440 __le32 irq_pending; 441 __le32 irq_control; 442 __le32 erst_size; 443 __le32 rsvd; 444 __le64 erst_base; 445 __le64 erst_dequeue; 446 }; 447 448 /* irq_pending bitmasks */ 449 #define ER_IRQ_PENDING(p) ((p) & 0x1) 450 /* bits 2:31 need to be preserved */ 451 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 452 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 453 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 454 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 455 456 /* irq_control bitmasks */ 457 /* Minimum interval between interrupts (in 250ns intervals). The interval 458 * between interrupts will be longer if there are no events on the event ring. 459 * Default is 4000 (1 ms). 460 */ 461 #define ER_IRQ_INTERVAL_MASK (0xffff) 462 /* Counter used to count down the time to the next interrupt - HW use only */ 463 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 464 465 /* erst_size bitmasks */ 466 /* Preserve bits 16:31 of erst_size */ 467 #define ERST_SIZE_MASK (0xffff << 16) 468 469 /* erst_dequeue bitmasks */ 470 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 471 * where the current dequeue pointer lies. This is an optional HW hint. 472 */ 473 #define ERST_DESI_MASK (0x7) 474 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 475 * a work queue (or delayed service routine)? 476 */ 477 #define ERST_EHB (1 << 3) 478 #define ERST_PTR_MASK (0xf) 479 480 /** 481 * struct xhci_run_regs 482 * @microframe_index: 483 * MFINDEX - current microframe number 484 * 485 * Section 5.5 Host Controller Runtime Registers: 486 * "Software should read and write these registers using only Dword (32 bit) 487 * or larger accesses" 488 */ 489 struct xhci_run_regs { 490 __le32 microframe_index; 491 __le32 rsvd[7]; 492 struct xhci_intr_reg ir_set[128]; 493 }; 494 495 /** 496 * struct doorbell_array 497 * 498 * Bits 0 - 7: Endpoint target 499 * Bits 8 - 15: RsvdZ 500 * Bits 16 - 31: Stream ID 501 * 502 * Section 5.6 503 */ 504 struct xhci_doorbell_array { 505 __le32 doorbell[256]; 506 }; 507 508 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 509 #define DB_VALUE_HOST 0x00000000 510 511 /** 512 * struct xhci_protocol_caps 513 * @revision: major revision, minor revision, capability ID, 514 * and next capability pointer. 515 * @name_string: Four ASCII characters to say which spec this xHC 516 * follows, typically "USB ". 517 * @port_info: Port offset, count, and protocol-defined information. 518 */ 519 struct xhci_protocol_caps { 520 u32 revision; 521 u32 name_string; 522 u32 port_info; 523 }; 524 525 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 526 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 527 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 528 529 /** 530 * struct xhci_container_ctx 531 * @type: Type of context. Used to calculated offsets to contained contexts. 532 * @size: Size of the context data 533 * @bytes: The raw context data given to HW 534 * @dma: dma address of the bytes 535 * 536 * Represents either a Device or Input context. Holds a pointer to the raw 537 * memory used for the context (bytes) and dma address of it (dma). 538 */ 539 struct xhci_container_ctx { 540 unsigned type; 541 #define XHCI_CTX_TYPE_DEVICE 0x1 542 #define XHCI_CTX_TYPE_INPUT 0x2 543 544 int size; 545 546 u8 *bytes; 547 dma_addr_t dma; 548 }; 549 550 /** 551 * struct xhci_slot_ctx 552 * @dev_info: Route string, device speed, hub info, and last valid endpoint 553 * @dev_info2: Max exit latency for device number, root hub port number 554 * @tt_info: tt_info is used to construct split transaction tokens 555 * @dev_state: slot state and device address 556 * 557 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 558 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 559 * reserved at the end of the slot context for HC internal use. 560 */ 561 struct xhci_slot_ctx { 562 __le32 dev_info; 563 __le32 dev_info2; 564 __le32 tt_info; 565 __le32 dev_state; 566 /* offset 0x10 to 0x1f reserved for HC internal use */ 567 __le32 reserved[4]; 568 }; 569 570 /* dev_info bitmasks */ 571 /* Route String - 0:19 */ 572 #define ROUTE_STRING_MASK (0xfffff) 573 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 574 #define DEV_SPEED (0xf << 20) 575 /* bit 24 reserved */ 576 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 577 #define DEV_MTT (0x1 << 25) 578 /* Set if the device is a hub - bit 26 */ 579 #define DEV_HUB (0x1 << 26) 580 /* Index of the last valid endpoint context in this device context - 27:31 */ 581 #define LAST_CTX_MASK (0x1f << 27) 582 #define LAST_CTX(p) ((p) << 27) 583 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 584 #define SLOT_FLAG (1 << 0) 585 #define EP0_FLAG (1 << 1) 586 587 /* dev_info2 bitmasks */ 588 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 589 #define MAX_EXIT (0xffff) 590 /* Root hub port number that is needed to access the USB device */ 591 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 592 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 593 /* Maximum number of ports under a hub device */ 594 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 595 596 /* tt_info bitmasks */ 597 /* 598 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 599 * The Slot ID of the hub that isolates the high speed signaling from 600 * this low or full-speed device. '0' if attached to root hub port. 601 */ 602 #define TT_SLOT (0xff) 603 /* 604 * The number of the downstream facing port of the high-speed hub 605 * '0' if the device is not low or full speed. 606 */ 607 #define TT_PORT (0xff << 8) 608 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 609 610 /* dev_state bitmasks */ 611 /* USB device address - assigned by the HC */ 612 #define DEV_ADDR_MASK (0xff) 613 /* bits 8:26 reserved */ 614 /* Slot state */ 615 #define SLOT_STATE (0x1f << 27) 616 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 617 618 #define SLOT_STATE_DISABLED 0 619 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 620 #define SLOT_STATE_DEFAULT 1 621 #define SLOT_STATE_ADDRESSED 2 622 #define SLOT_STATE_CONFIGURED 3 623 624 /** 625 * struct xhci_ep_ctx 626 * @ep_info: endpoint state, streams, mult, and interval information. 627 * @ep_info2: information on endpoint type, max packet size, max burst size, 628 * error count, and whether the HC will force an event for all 629 * transactions. 630 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 631 * defines one stream, this points to the endpoint transfer ring. 632 * Otherwise, it points to a stream context array, which has a 633 * ring pointer for each flow. 634 * @tx_info: 635 * Average TRB lengths for the endpoint ring and 636 * max payload within an Endpoint Service Interval Time (ESIT). 637 * 638 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 639 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 640 * reserved at the end of the endpoint context for HC internal use. 641 */ 642 struct xhci_ep_ctx { 643 __le32 ep_info; 644 __le32 ep_info2; 645 __le64 deq; 646 __le32 tx_info; 647 /* offset 0x14 - 0x1f reserved for HC internal use */ 648 __le32 reserved[3]; 649 }; 650 651 /* ep_info bitmasks */ 652 /* 653 * Endpoint State - bits 0:2 654 * 0 - disabled 655 * 1 - running 656 * 2 - halted due to halt condition - ok to manipulate endpoint ring 657 * 3 - stopped 658 * 4 - TRB error 659 * 5-7 - reserved 660 */ 661 #define EP_STATE_MASK (0xf) 662 #define EP_STATE_DISABLED 0 663 #define EP_STATE_RUNNING 1 664 #define EP_STATE_HALTED 2 665 #define EP_STATE_STOPPED 3 666 #define EP_STATE_ERROR 4 667 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 668 #define EP_MULT(p) (((p) & 0x3) << 8) 669 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 670 /* bits 10:14 are Max Primary Streams */ 671 /* bit 15 is Linear Stream Array */ 672 /* Interval - period between requests to an endpoint - 125u increments. */ 673 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 674 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 675 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 676 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 677 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 678 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 679 #define EP_HAS_LSA (1 << 15) 680 681 /* ep_info2 bitmasks */ 682 /* 683 * Force Event - generate transfer events for all TRBs for this endpoint 684 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 685 */ 686 #define FORCE_EVENT (0x1) 687 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 688 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 689 #define EP_TYPE(p) ((p) << 3) 690 #define ISOC_OUT_EP 1 691 #define BULK_OUT_EP 2 692 #define INT_OUT_EP 3 693 #define CTRL_EP 4 694 #define ISOC_IN_EP 5 695 #define BULK_IN_EP 6 696 #define INT_IN_EP 7 697 /* bit 6 reserved */ 698 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 699 #define MAX_BURST(p) (((p)&0xff) << 8) 700 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 701 #define MAX_PACKET(p) (((p)&0xffff) << 16) 702 #define MAX_PACKET_MASK (0xffff << 16) 703 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 704 705 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 706 * USB2.0 spec 9.6.6. 707 */ 708 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 709 710 /* tx_info bitmasks */ 711 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 712 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 713 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 714 715 /* deq bitmasks */ 716 #define EP_CTX_CYCLE_MASK (1 << 0) 717 718 719 /** 720 * struct xhci_input_control_context 721 * Input control context; see section 6.2.5. 722 * 723 * @drop_context: set the bit of the endpoint context you want to disable 724 * @add_context: set the bit of the endpoint context you want to enable 725 */ 726 struct xhci_input_control_ctx { 727 __le32 drop_flags; 728 __le32 add_flags; 729 __le32 rsvd2[6]; 730 }; 731 732 #define EP_IS_ADDED(ctrl_ctx, i) \ 733 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 734 #define EP_IS_DROPPED(ctrl_ctx, i) \ 735 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 736 737 /* Represents everything that is needed to issue a command on the command ring. 738 * It's useful to pre-allocate these for commands that cannot fail due to 739 * out-of-memory errors, like freeing streams. 740 */ 741 struct xhci_command { 742 /* Input context for changing device state */ 743 struct xhci_container_ctx *in_ctx; 744 u32 status; 745 /* If completion is null, no one is waiting on this command 746 * and the structure can be freed after the command completes. 747 */ 748 struct completion *completion; 749 union xhci_trb *command_trb; 750 struct list_head cmd_list; 751 }; 752 753 /* drop context bitmasks */ 754 #define DROP_EP(x) (0x1 << x) 755 /* add context bitmasks */ 756 #define ADD_EP(x) (0x1 << x) 757 758 struct xhci_stream_ctx { 759 /* 64-bit stream ring address, cycle state, and stream type */ 760 __le64 stream_ring; 761 /* offset 0x14 - 0x1f reserved for HC internal use */ 762 __le32 reserved[2]; 763 }; 764 765 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 766 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 767 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 768 #define SCT_SEC_TR 0 769 /* Primary stream array type, dequeue pointer is to a transfer ring */ 770 #define SCT_PRI_TR 1 771 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 772 #define SCT_SSA_8 2 773 #define SCT_SSA_16 3 774 #define SCT_SSA_32 4 775 #define SCT_SSA_64 5 776 #define SCT_SSA_128 6 777 #define SCT_SSA_256 7 778 779 /* Assume no secondary streams for now */ 780 struct xhci_stream_info { 781 struct xhci_ring **stream_rings; 782 /* Number of streams, including stream 0 (which drivers can't use) */ 783 unsigned int num_streams; 784 /* The stream context array may be bigger than 785 * the number of streams the driver asked for 786 */ 787 struct xhci_stream_ctx *stream_ctx_array; 788 unsigned int num_stream_ctxs; 789 dma_addr_t ctx_array_dma; 790 /* For mapping physical TRB addresses to segments in stream rings */ 791 struct radix_tree_root trb_address_map; 792 struct xhci_command *free_streams_command; 793 }; 794 795 #define SMALL_STREAM_ARRAY_SIZE 256 796 #define MEDIUM_STREAM_ARRAY_SIZE 1024 797 798 /* Some Intel xHCI host controllers need software to keep track of the bus 799 * bandwidth. Keep track of endpoint info here. Each root port is allocated 800 * the full bus bandwidth. We must also treat TTs (including each port under a 801 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 802 * (DMI) also limits the total bandwidth (across all domains) that can be used. 803 */ 804 struct xhci_bw_info { 805 /* ep_interval is zero-based */ 806 unsigned int ep_interval; 807 /* mult and num_packets are one-based */ 808 unsigned int mult; 809 unsigned int num_packets; 810 unsigned int max_packet_size; 811 unsigned int max_esit_payload; 812 unsigned int type; 813 }; 814 815 /* "Block" sizes in bytes the hardware uses for different device speeds. 816 * The logic in this part of the hardware limits the number of bits the hardware 817 * can use, so must represent bandwidth in a less precise manner to mimic what 818 * the scheduler hardware computes. 819 */ 820 #define FS_BLOCK 1 821 #define HS_BLOCK 4 822 #define SS_BLOCK 16 823 #define DMI_BLOCK 32 824 825 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 826 * with each byte transferred. SuperSpeed devices have an initial overhead to 827 * set up bursts. These are in blocks, see above. LS overhead has already been 828 * translated into FS blocks. 829 */ 830 #define DMI_OVERHEAD 8 831 #define DMI_OVERHEAD_BURST 4 832 #define SS_OVERHEAD 8 833 #define SS_OVERHEAD_BURST 32 834 #define HS_OVERHEAD 26 835 #define FS_OVERHEAD 20 836 #define LS_OVERHEAD 128 837 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 838 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 839 * of overhead associated with split transfers crossing microframe boundaries. 840 * 31 blocks is pure protocol overhead. 841 */ 842 #define TT_HS_OVERHEAD (31 + 94) 843 #define TT_DMI_OVERHEAD (25 + 12) 844 845 /* Bandwidth limits in blocks */ 846 #define FS_BW_LIMIT 1285 847 #define TT_BW_LIMIT 1320 848 #define HS_BW_LIMIT 1607 849 #define SS_BW_LIMIT_IN 3906 850 #define DMI_BW_LIMIT_IN 3906 851 #define SS_BW_LIMIT_OUT 3906 852 #define DMI_BW_LIMIT_OUT 3906 853 854 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 855 #define FS_BW_RESERVED 10 856 #define HS_BW_RESERVED 20 857 #define SS_BW_RESERVED 10 858 859 struct xhci_virt_ep { 860 struct xhci_ring *ring; 861 /* Related to endpoints that are configured to use stream IDs only */ 862 struct xhci_stream_info *stream_info; 863 /* Temporary storage in case the configure endpoint command fails and we 864 * have to restore the device state to the previous state 865 */ 866 struct xhci_ring *new_ring; 867 unsigned int ep_state; 868 #define SET_DEQ_PENDING (1 << 0) 869 #define EP_HALTED (1 << 1) /* For stall handling */ 870 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 871 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 872 #define EP_GETTING_STREAMS (1 << 3) 873 #define EP_HAS_STREAMS (1 << 4) 874 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 875 #define EP_GETTING_NO_STREAMS (1 << 5) 876 /* ---- Related to URB cancellation ---- */ 877 struct list_head cancelled_td_list; 878 /* The TRB that was last reported in a stopped endpoint ring */ 879 union xhci_trb *stopped_trb; 880 struct xhci_td *stopped_td; 881 unsigned int stopped_stream; 882 /* Watchdog timer for stop endpoint command to cancel URBs */ 883 struct timer_list stop_cmd_timer; 884 int stop_cmds_pending; 885 struct xhci_hcd *xhci; 886 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 887 * command. We'll need to update the ring's dequeue segment and dequeue 888 * pointer after the command completes. 889 */ 890 struct xhci_segment *queued_deq_seg; 891 union xhci_trb *queued_deq_ptr; 892 /* 893 * Sometimes the xHC can not process isochronous endpoint ring quickly 894 * enough, and it will miss some isoc tds on the ring and generate 895 * a Missed Service Error Event. 896 * Set skip flag when receive a Missed Service Error Event and 897 * process the missed tds on the endpoint ring. 898 */ 899 bool skip; 900 /* Bandwidth checking storage */ 901 struct xhci_bw_info bw_info; 902 struct list_head bw_endpoint_list; 903 }; 904 905 enum xhci_overhead_type { 906 LS_OVERHEAD_TYPE = 0, 907 FS_OVERHEAD_TYPE, 908 HS_OVERHEAD_TYPE, 909 }; 910 911 struct xhci_interval_bw { 912 unsigned int num_packets; 913 /* Sorted by max packet size. 914 * Head of the list is the greatest max packet size. 915 */ 916 struct list_head endpoints; 917 /* How many endpoints of each speed are present. */ 918 unsigned int overhead[3]; 919 }; 920 921 #define XHCI_MAX_INTERVAL 16 922 923 struct xhci_interval_bw_table { 924 unsigned int interval0_esit_payload; 925 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 926 /* Includes reserved bandwidth for async endpoints */ 927 unsigned int bw_used; 928 unsigned int ss_bw_in; 929 unsigned int ss_bw_out; 930 }; 931 932 933 struct xhci_virt_device { 934 struct usb_device *udev; 935 /* 936 * Commands to the hardware are passed an "input context" that 937 * tells the hardware what to change in its data structures. 938 * The hardware will return changes in an "output context" that 939 * software must allocate for the hardware. We need to keep 940 * track of input and output contexts separately because 941 * these commands might fail and we don't trust the hardware. 942 */ 943 struct xhci_container_ctx *out_ctx; 944 /* Used for addressing devices and configuration changes */ 945 struct xhci_container_ctx *in_ctx; 946 /* Rings saved to ensure old alt settings can be re-instated */ 947 struct xhci_ring **ring_cache; 948 int num_rings_cached; 949 #define XHCI_MAX_RINGS_CACHED 31 950 struct xhci_virt_ep eps[31]; 951 struct completion cmd_completion; 952 /* Status of the last command issued for this device */ 953 u32 cmd_status; 954 struct list_head cmd_list; 955 u8 fake_port; 956 u8 real_port; 957 struct xhci_interval_bw_table *bw_table; 958 struct xhci_tt_bw_info *tt_info; 959 /* The current max exit latency for the enabled USB3 link states. */ 960 u16 current_mel; 961 }; 962 963 /* 964 * For each roothub, keep track of the bandwidth information for each periodic 965 * interval. 966 * 967 * If a high speed hub is attached to the roothub, each TT associated with that 968 * hub is a separate bandwidth domain. The interval information for the 969 * endpoints on the devices under that TT will appear in the TT structure. 970 */ 971 struct xhci_root_port_bw_info { 972 struct list_head tts; 973 unsigned int num_active_tts; 974 struct xhci_interval_bw_table bw_table; 975 }; 976 977 struct xhci_tt_bw_info { 978 struct list_head tt_list; 979 int slot_id; 980 int ttport; 981 struct xhci_interval_bw_table bw_table; 982 int active_eps; 983 }; 984 985 986 /** 987 * struct xhci_device_context_array 988 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 989 */ 990 struct xhci_device_context_array { 991 /* 64-bit device addresses; we only write 32-bit addresses */ 992 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 993 /* private xHCD pointers */ 994 dma_addr_t dma; 995 }; 996 /* TODO: write function to set the 64-bit device DMA address */ 997 /* 998 * TODO: change this to be dynamically sized at HC mem init time since the HC 999 * might not be able to handle the maximum number of devices possible. 1000 */ 1001 1002 1003 struct xhci_transfer_event { 1004 /* 64-bit buffer address, or immediate data */ 1005 __le64 buffer; 1006 __le32 transfer_len; 1007 /* This field is interpreted differently based on the type of TRB */ 1008 __le32 flags; 1009 }; 1010 1011 /* Transfer event TRB length bit mask */ 1012 /* bits 0:23 */ 1013 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1014 1015 /** Transfer Event bit fields **/ 1016 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1017 1018 /* Completion Code - only applicable for some types of TRBs */ 1019 #define COMP_CODE_MASK (0xff << 24) 1020 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1021 #define COMP_SUCCESS 1 1022 /* Data Buffer Error */ 1023 #define COMP_DB_ERR 2 1024 /* Babble Detected Error */ 1025 #define COMP_BABBLE 3 1026 /* USB Transaction Error */ 1027 #define COMP_TX_ERR 4 1028 /* TRB Error - some TRB field is invalid */ 1029 #define COMP_TRB_ERR 5 1030 /* Stall Error - USB device is stalled */ 1031 #define COMP_STALL 6 1032 /* Resource Error - HC doesn't have memory for that device configuration */ 1033 #define COMP_ENOMEM 7 1034 /* Bandwidth Error - not enough room in schedule for this dev config */ 1035 #define COMP_BW_ERR 8 1036 /* No Slots Available Error - HC ran out of device slots */ 1037 #define COMP_ENOSLOTS 9 1038 /* Invalid Stream Type Error */ 1039 #define COMP_STREAM_ERR 10 1040 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 1041 #define COMP_EBADSLT 11 1042 /* Endpoint Not Enabled Error */ 1043 #define COMP_EBADEP 12 1044 /* Short Packet */ 1045 #define COMP_SHORT_TX 13 1046 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 1047 #define COMP_UNDERRUN 14 1048 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 1049 #define COMP_OVERRUN 15 1050 /* Virtual Function Event Ring Full Error */ 1051 #define COMP_VF_FULL 16 1052 /* Parameter Error - Context parameter is invalid */ 1053 #define COMP_EINVAL 17 1054 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 1055 #define COMP_BW_OVER 18 1056 /* Context State Error - illegal context state transition requested */ 1057 #define COMP_CTX_STATE 19 1058 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 1059 #define COMP_PING_ERR 20 1060 /* Event Ring is full */ 1061 #define COMP_ER_FULL 21 1062 /* Incompatible Device Error */ 1063 #define COMP_DEV_ERR 22 1064 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 1065 #define COMP_MISSED_INT 23 1066 /* Successfully stopped command ring */ 1067 #define COMP_CMD_STOP 24 1068 /* Successfully aborted current command and stopped command ring */ 1069 #define COMP_CMD_ABORT 25 1070 /* Stopped - transfer was terminated by a stop endpoint command */ 1071 #define COMP_STOP 26 1072 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 1073 #define COMP_STOP_INVAL 27 1074 /* Control Abort Error - Debug Capability - control pipe aborted */ 1075 #define COMP_DBG_ABORT 28 1076 /* Max Exit Latency Too Large Error */ 1077 #define COMP_MEL_ERR 29 1078 /* TRB type 30 reserved */ 1079 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 1080 #define COMP_BUFF_OVER 31 1081 /* Event Lost Error - xHC has an "internal event overrun condition" */ 1082 #define COMP_ISSUES 32 1083 /* Undefined Error - reported when other error codes don't apply */ 1084 #define COMP_UNKNOWN 33 1085 /* Invalid Stream ID Error */ 1086 #define COMP_STRID_ERR 34 1087 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 1088 #define COMP_2ND_BW_ERR 35 1089 /* Split Transaction Error */ 1090 #define COMP_SPLIT_ERR 36 1091 1092 struct xhci_link_trb { 1093 /* 64-bit segment pointer*/ 1094 __le64 segment_ptr; 1095 __le32 intr_target; 1096 __le32 control; 1097 }; 1098 1099 /* control bitfields */ 1100 #define LINK_TOGGLE (0x1<<1) 1101 1102 /* Command completion event TRB */ 1103 struct xhci_event_cmd { 1104 /* Pointer to command TRB, or the value passed by the event data trb */ 1105 __le64 cmd_trb; 1106 __le32 status; 1107 __le32 flags; 1108 }; 1109 1110 /* flags bitmasks */ 1111 1112 /* Address device - disable SetAddress */ 1113 #define TRB_BSR (1<<9) 1114 enum xhci_setup_dev { 1115 SETUP_CONTEXT_ONLY, 1116 SETUP_CONTEXT_ADDRESS, 1117 }; 1118 1119 /* bits 16:23 are the virtual function ID */ 1120 /* bits 24:31 are the slot ID */ 1121 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1122 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1123 1124 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1125 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1126 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1127 1128 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1129 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1130 #define LAST_EP_INDEX 30 1131 1132 /* Set TR Dequeue Pointer command TRB fields */ 1133 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1134 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1135 1136 1137 /* Port Status Change Event TRB fields */ 1138 /* Port ID - bits 31:24 */ 1139 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1140 1141 /* Normal TRB fields */ 1142 /* transfer_len bitmasks - bits 0:16 */ 1143 #define TRB_LEN(p) ((p) & 0x1ffff) 1144 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1145 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1146 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1147 #define TRB_TBC(p) (((p) & 0x3) << 7) 1148 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1149 1150 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1151 #define TRB_CYCLE (1<<0) 1152 /* 1153 * Force next event data TRB to be evaluated before task switch. 1154 * Used to pass OS data back after a TD completes. 1155 */ 1156 #define TRB_ENT (1<<1) 1157 /* Interrupt on short packet */ 1158 #define TRB_ISP (1<<2) 1159 /* Set PCIe no snoop attribute */ 1160 #define TRB_NO_SNOOP (1<<3) 1161 /* Chain multiple TRBs into a TD */ 1162 #define TRB_CHAIN (1<<4) 1163 /* Interrupt on completion */ 1164 #define TRB_IOC (1<<5) 1165 /* The buffer pointer contains immediate data */ 1166 #define TRB_IDT (1<<6) 1167 1168 /* Block Event Interrupt */ 1169 #define TRB_BEI (1<<9) 1170 1171 /* Control transfer TRB specific fields */ 1172 #define TRB_DIR_IN (1<<16) 1173 #define TRB_TX_TYPE(p) ((p) << 16) 1174 #define TRB_DATA_OUT 2 1175 #define TRB_DATA_IN 3 1176 1177 /* Isochronous TRB specific fields */ 1178 #define TRB_SIA (1<<31) 1179 1180 struct xhci_generic_trb { 1181 __le32 field[4]; 1182 }; 1183 1184 union xhci_trb { 1185 struct xhci_link_trb link; 1186 struct xhci_transfer_event trans_event; 1187 struct xhci_event_cmd event_cmd; 1188 struct xhci_generic_trb generic; 1189 }; 1190 1191 /* TRB bit mask */ 1192 #define TRB_TYPE_BITMASK (0xfc00) 1193 #define TRB_TYPE(p) ((p) << 10) 1194 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1195 /* TRB type IDs */ 1196 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1197 #define TRB_NORMAL 1 1198 /* setup stage for control transfers */ 1199 #define TRB_SETUP 2 1200 /* data stage for control transfers */ 1201 #define TRB_DATA 3 1202 /* status stage for control transfers */ 1203 #define TRB_STATUS 4 1204 /* isoc transfers */ 1205 #define TRB_ISOC 5 1206 /* TRB for linking ring segments */ 1207 #define TRB_LINK 6 1208 #define TRB_EVENT_DATA 7 1209 /* Transfer Ring No-op (not for the command ring) */ 1210 #define TRB_TR_NOOP 8 1211 /* Command TRBs */ 1212 /* Enable Slot Command */ 1213 #define TRB_ENABLE_SLOT 9 1214 /* Disable Slot Command */ 1215 #define TRB_DISABLE_SLOT 10 1216 /* Address Device Command */ 1217 #define TRB_ADDR_DEV 11 1218 /* Configure Endpoint Command */ 1219 #define TRB_CONFIG_EP 12 1220 /* Evaluate Context Command */ 1221 #define TRB_EVAL_CONTEXT 13 1222 /* Reset Endpoint Command */ 1223 #define TRB_RESET_EP 14 1224 /* Stop Transfer Ring Command */ 1225 #define TRB_STOP_RING 15 1226 /* Set Transfer Ring Dequeue Pointer Command */ 1227 #define TRB_SET_DEQ 16 1228 /* Reset Device Command */ 1229 #define TRB_RESET_DEV 17 1230 /* Force Event Command (opt) */ 1231 #define TRB_FORCE_EVENT 18 1232 /* Negotiate Bandwidth Command (opt) */ 1233 #define TRB_NEG_BANDWIDTH 19 1234 /* Set Latency Tolerance Value Command (opt) */ 1235 #define TRB_SET_LT 20 1236 /* Get port bandwidth Command */ 1237 #define TRB_GET_BW 21 1238 /* Force Header Command - generate a transaction or link management packet */ 1239 #define TRB_FORCE_HEADER 22 1240 /* No-op Command - not for transfer rings */ 1241 #define TRB_CMD_NOOP 23 1242 /* TRB IDs 24-31 reserved */ 1243 /* Event TRBS */ 1244 /* Transfer Event */ 1245 #define TRB_TRANSFER 32 1246 /* Command Completion Event */ 1247 #define TRB_COMPLETION 33 1248 /* Port Status Change Event */ 1249 #define TRB_PORT_STATUS 34 1250 /* Bandwidth Request Event (opt) */ 1251 #define TRB_BANDWIDTH_EVENT 35 1252 /* Doorbell Event (opt) */ 1253 #define TRB_DOORBELL 36 1254 /* Host Controller Event */ 1255 #define TRB_HC_EVENT 37 1256 /* Device Notification Event - device sent function wake notification */ 1257 #define TRB_DEV_NOTE 38 1258 /* MFINDEX Wrap Event - microframe counter wrapped */ 1259 #define TRB_MFINDEX_WRAP 39 1260 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1261 1262 /* Nec vendor-specific command completion event. */ 1263 #define TRB_NEC_CMD_COMP 48 1264 /* Get NEC firmware revision. */ 1265 #define TRB_NEC_GET_FW 49 1266 1267 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1268 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1269 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1270 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1271 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1272 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1273 1274 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1275 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1276 1277 /* 1278 * TRBS_PER_SEGMENT must be a multiple of 4, 1279 * since the command ring is 64-byte aligned. 1280 * It must also be greater than 16. 1281 */ 1282 #define TRBS_PER_SEGMENT 256 1283 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1284 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1285 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1286 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1287 /* TRB buffer pointers can't cross 64KB boundaries */ 1288 #define TRB_MAX_BUFF_SHIFT 16 1289 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1290 1291 struct xhci_segment { 1292 union xhci_trb *trbs; 1293 /* private to HCD */ 1294 struct xhci_segment *next; 1295 dma_addr_t dma; 1296 }; 1297 1298 struct xhci_td { 1299 struct list_head td_list; 1300 struct list_head cancelled_td_list; 1301 struct urb *urb; 1302 struct xhci_segment *start_seg; 1303 union xhci_trb *first_trb; 1304 union xhci_trb *last_trb; 1305 }; 1306 1307 /* xHCI command default timeout value */ 1308 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1309 1310 /* command descriptor */ 1311 struct xhci_cd { 1312 struct list_head cancel_cmd_list; 1313 struct xhci_command *command; 1314 union xhci_trb *cmd_trb; 1315 }; 1316 1317 struct xhci_dequeue_state { 1318 struct xhci_segment *new_deq_seg; 1319 union xhci_trb *new_deq_ptr; 1320 int new_cycle_state; 1321 }; 1322 1323 enum xhci_ring_type { 1324 TYPE_CTRL = 0, 1325 TYPE_ISOC, 1326 TYPE_BULK, 1327 TYPE_INTR, 1328 TYPE_STREAM, 1329 TYPE_COMMAND, 1330 TYPE_EVENT, 1331 }; 1332 1333 struct xhci_ring { 1334 struct xhci_segment *first_seg; 1335 struct xhci_segment *last_seg; 1336 union xhci_trb *enqueue; 1337 struct xhci_segment *enq_seg; 1338 unsigned int enq_updates; 1339 union xhci_trb *dequeue; 1340 struct xhci_segment *deq_seg; 1341 unsigned int deq_updates; 1342 struct list_head td_list; 1343 /* 1344 * Write the cycle state into the TRB cycle field to give ownership of 1345 * the TRB to the host controller (if we are the producer), or to check 1346 * if we own the TRB (if we are the consumer). See section 4.9.1. 1347 */ 1348 u32 cycle_state; 1349 unsigned int stream_id; 1350 unsigned int num_segs; 1351 unsigned int num_trbs_free; 1352 unsigned int num_trbs_free_temp; 1353 enum xhci_ring_type type; 1354 bool last_td_was_short; 1355 }; 1356 1357 struct xhci_erst_entry { 1358 /* 64-bit event ring segment address */ 1359 __le64 seg_addr; 1360 __le32 seg_size; 1361 /* Set to zero */ 1362 __le32 rsvd; 1363 }; 1364 1365 struct xhci_erst { 1366 struct xhci_erst_entry *entries; 1367 unsigned int num_entries; 1368 /* xhci->event_ring keeps track of segment dma addresses */ 1369 dma_addr_t erst_dma_addr; 1370 /* Num entries the ERST can contain */ 1371 unsigned int erst_size; 1372 }; 1373 1374 struct xhci_scratchpad { 1375 u64 *sp_array; 1376 dma_addr_t sp_dma; 1377 void **sp_buffers; 1378 dma_addr_t *sp_dma_buffers; 1379 }; 1380 1381 struct urb_priv { 1382 int length; 1383 int td_cnt; 1384 struct xhci_td *td[0]; 1385 }; 1386 1387 /* 1388 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1389 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1390 * meaning 64 ring segments. 1391 * Initial allocated size of the ERST, in number of entries */ 1392 #define ERST_NUM_SEGS 1 1393 /* Initial allocated size of the ERST, in number of entries */ 1394 #define ERST_SIZE 64 1395 /* Initial number of event segment rings allocated */ 1396 #define ERST_ENTRIES 1 1397 /* Poll every 60 seconds */ 1398 #define POLL_TIMEOUT 60 1399 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1400 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1401 /* XXX: Make these module parameters */ 1402 1403 struct s3_save { 1404 u32 command; 1405 u32 dev_nt; 1406 u64 dcbaa_ptr; 1407 u32 config_reg; 1408 u32 irq_pending; 1409 u32 irq_control; 1410 u32 erst_size; 1411 u64 erst_base; 1412 u64 erst_dequeue; 1413 }; 1414 1415 /* Use for lpm */ 1416 struct dev_info { 1417 u32 dev_id; 1418 struct list_head list; 1419 }; 1420 1421 struct xhci_bus_state { 1422 unsigned long bus_suspended; 1423 unsigned long next_statechange; 1424 1425 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1426 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1427 u32 port_c_suspend; 1428 u32 suspended_ports; 1429 u32 port_remote_wakeup; 1430 unsigned long resume_done[USB_MAXCHILDREN]; 1431 /* which ports have started to resume */ 1432 unsigned long resuming_ports; 1433 /* Which ports are waiting on RExit to U0 transition. */ 1434 unsigned long rexit_ports; 1435 struct completion rexit_done[USB_MAXCHILDREN]; 1436 }; 1437 1438 1439 /* 1440 * It can take up to 20 ms to transition from RExit to U0 on the 1441 * Intel Lynx Point LP xHCI host. 1442 */ 1443 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1444 1445 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1446 { 1447 if (hcd->speed == HCD_USB3) 1448 return 0; 1449 else 1450 return 1; 1451 } 1452 1453 /* There is one xhci_hcd structure per controller */ 1454 struct xhci_hcd { 1455 struct usb_hcd *main_hcd; 1456 struct usb_hcd *shared_hcd; 1457 /* glue to PCI and HCD framework */ 1458 struct xhci_cap_regs __iomem *cap_regs; 1459 struct xhci_op_regs __iomem *op_regs; 1460 struct xhci_run_regs __iomem *run_regs; 1461 struct xhci_doorbell_array __iomem *dba; 1462 /* Our HCD's current interrupter register set */ 1463 struct xhci_intr_reg __iomem *ir_set; 1464 1465 /* Cached register copies of read-only HC data */ 1466 __u32 hcs_params1; 1467 __u32 hcs_params2; 1468 __u32 hcs_params3; 1469 __u32 hcc_params; 1470 1471 spinlock_t lock; 1472 1473 /* packed release number */ 1474 u8 sbrn; 1475 u16 hci_version; 1476 u8 max_slots; 1477 u8 max_interrupters; 1478 u8 max_ports; 1479 u8 isoc_threshold; 1480 int event_ring_max; 1481 int addr_64; 1482 /* 4KB min, 128MB max */ 1483 int page_size; 1484 /* Valid values are 12 to 20, inclusive */ 1485 int page_shift; 1486 /* msi-x vectors */ 1487 int msix_count; 1488 struct msix_entry *msix_entries; 1489 /* data structures */ 1490 struct xhci_device_context_array *dcbaa; 1491 struct xhci_ring *cmd_ring; 1492 unsigned int cmd_ring_state; 1493 #define CMD_RING_STATE_RUNNING (1 << 0) 1494 #define CMD_RING_STATE_ABORTED (1 << 1) 1495 #define CMD_RING_STATE_STOPPED (1 << 2) 1496 struct list_head cancel_cmd_list; 1497 unsigned int cmd_ring_reserved_trbs; 1498 struct xhci_ring *event_ring; 1499 struct xhci_erst erst; 1500 /* Scratchpad */ 1501 struct xhci_scratchpad *scratchpad; 1502 /* Store LPM test failed devices' information */ 1503 struct list_head lpm_failed_devs; 1504 1505 /* slot enabling and address device helpers */ 1506 struct completion addr_dev; 1507 int slot_id; 1508 /* For USB 3.0 LPM enable/disable. */ 1509 struct xhci_command *lpm_command; 1510 /* Internal mirror of the HW's dcbaa */ 1511 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1512 /* For keeping track of bandwidth domains per roothub. */ 1513 struct xhci_root_port_bw_info *rh_bw; 1514 1515 /* DMA pools */ 1516 struct dma_pool *device_pool; 1517 struct dma_pool *segment_pool; 1518 struct dma_pool *small_streams_pool; 1519 struct dma_pool *medium_streams_pool; 1520 1521 /* Host controller watchdog timer structures */ 1522 unsigned int xhc_state; 1523 1524 u32 command; 1525 struct s3_save s3; 1526 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1527 * 1528 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1529 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1530 * that sees this status (other than the timer that set it) should stop touching 1531 * hardware immediately. Interrupt handlers should return immediately when 1532 * they see this status (any time they drop and re-acquire xhci->lock). 1533 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1534 * putting the TD on the canceled list, etc. 1535 * 1536 * There are no reports of xHCI host controllers that display this issue. 1537 */ 1538 #define XHCI_STATE_DYING (1 << 0) 1539 #define XHCI_STATE_HALTED (1 << 1) 1540 /* Statistics */ 1541 int error_bitmask; 1542 unsigned int quirks; 1543 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1544 #define XHCI_RESET_EP_QUIRK (1 << 1) 1545 #define XHCI_NEC_HOST (1 << 2) 1546 #define XHCI_AMD_PLL_FIX (1 << 3) 1547 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1548 /* 1549 * Certain Intel host controllers have a limit to the number of endpoint 1550 * contexts they can handle. Ideally, they would signal that they can't handle 1551 * anymore endpoint contexts by returning a Resource Error for the Configure 1552 * Endpoint command, but they don't. Instead they expect software to keep track 1553 * of the number of active endpoints for them, across configure endpoint 1554 * commands, reset device commands, disable slot commands, and address device 1555 * commands. 1556 */ 1557 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1558 #define XHCI_BROKEN_MSI (1 << 6) 1559 #define XHCI_RESET_ON_RESUME (1 << 7) 1560 #define XHCI_SW_BW_CHECKING (1 << 8) 1561 #define XHCI_AMD_0x96_HOST (1 << 9) 1562 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1563 #define XHCI_LPM_SUPPORT (1 << 11) 1564 #define XHCI_INTEL_HOST (1 << 12) 1565 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1566 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1567 #define XHCI_AVOID_BEI (1 << 15) 1568 #define XHCI_PLAT (1 << 16) 1569 #define XHCI_SLOW_SUSPEND (1 << 17) 1570 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1571 unsigned int num_active_eps; 1572 unsigned int limit_active_eps; 1573 /* There are two roothubs to keep track of bus suspend info for */ 1574 struct xhci_bus_state bus_state[2]; 1575 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1576 u8 *port_array; 1577 /* Array of pointers to USB 3.0 PORTSC registers */ 1578 __le32 __iomem **usb3_ports; 1579 unsigned int num_usb3_ports; 1580 /* Array of pointers to USB 2.0 PORTSC registers */ 1581 __le32 __iomem **usb2_ports; 1582 unsigned int num_usb2_ports; 1583 /* support xHCI 0.96 spec USB2 software LPM */ 1584 unsigned sw_lpm_support:1; 1585 /* support xHCI 1.0 spec USB2 hardware LPM */ 1586 unsigned hw_lpm_support:1; 1587 /* cached usb2 extened protocol capabilites */ 1588 u32 *ext_caps; 1589 unsigned int num_ext_caps; 1590 /* Compliance Mode Recovery Data */ 1591 struct timer_list comp_mode_recovery_timer; 1592 u32 port_status_u0; 1593 /* Compliance Mode Timer Triggered every 2 seconds */ 1594 #define COMP_MODE_RCVRY_MSECS 2000 1595 }; 1596 1597 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1598 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1599 { 1600 return *((struct xhci_hcd **) (hcd->hcd_priv)); 1601 } 1602 1603 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1604 { 1605 return xhci->main_hcd; 1606 } 1607 1608 #define xhci_dbg(xhci, fmt, args...) \ 1609 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1610 #define xhci_err(xhci, fmt, args...) \ 1611 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1612 #define xhci_warn(xhci, fmt, args...) \ 1613 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1614 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1615 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1616 1617 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1618 { 1619 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1620 } 1621 1622 /* xHCI debugging */ 1623 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1624 void xhci_print_registers(struct xhci_hcd *xhci); 1625 void xhci_dbg_regs(struct xhci_hcd *xhci); 1626 void xhci_print_run_regs(struct xhci_hcd *xhci); 1627 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1628 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1629 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1630 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1631 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1632 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1633 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1634 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1635 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1636 struct xhci_container_ctx *ctx); 1637 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1638 unsigned int slot_id, unsigned int ep_index, 1639 struct xhci_virt_ep *ep); 1640 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1641 const char *fmt, ...); 1642 1643 /* xHCI memory management */ 1644 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1645 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1646 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1647 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1648 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1649 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1650 struct usb_device *udev); 1651 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1652 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1653 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1654 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1655 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1656 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1657 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1658 struct xhci_bw_info *ep_bw, 1659 struct xhci_interval_bw_table *bw_table, 1660 struct usb_device *udev, 1661 struct xhci_virt_ep *virt_ep, 1662 struct xhci_tt_bw_info *tt_info); 1663 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1664 struct xhci_virt_device *virt_dev, 1665 int old_active_eps); 1666 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1667 void xhci_update_bw_info(struct xhci_hcd *xhci, 1668 struct xhci_container_ctx *in_ctx, 1669 struct xhci_input_control_ctx *ctrl_ctx, 1670 struct xhci_virt_device *virt_dev); 1671 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1672 struct xhci_container_ctx *in_ctx, 1673 struct xhci_container_ctx *out_ctx, 1674 unsigned int ep_index); 1675 void xhci_slot_copy(struct xhci_hcd *xhci, 1676 struct xhci_container_ctx *in_ctx, 1677 struct xhci_container_ctx *out_ctx); 1678 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1679 struct usb_device *udev, struct usb_host_endpoint *ep, 1680 gfp_t mem_flags); 1681 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1682 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1683 unsigned int num_trbs, gfp_t flags); 1684 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1685 struct xhci_virt_device *virt_dev, 1686 unsigned int ep_index); 1687 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1688 unsigned int num_stream_ctxs, 1689 unsigned int num_streams, gfp_t flags); 1690 void xhci_free_stream_info(struct xhci_hcd *xhci, 1691 struct xhci_stream_info *stream_info); 1692 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1693 struct xhci_ep_ctx *ep_ctx, 1694 struct xhci_stream_info *stream_info); 1695 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1696 struct xhci_ep_ctx *ep_ctx, 1697 struct xhci_virt_ep *ep); 1698 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1699 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1700 struct xhci_ring *xhci_dma_to_transfer_ring( 1701 struct xhci_virt_ep *ep, 1702 u64 address); 1703 struct xhci_ring *xhci_stream_id_to_ring( 1704 struct xhci_virt_device *dev, 1705 unsigned int ep_index, 1706 unsigned int stream_id); 1707 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1708 bool allocate_in_ctx, bool allocate_completion, 1709 gfp_t mem_flags); 1710 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv); 1711 void xhci_free_command(struct xhci_hcd *xhci, 1712 struct xhci_command *command); 1713 1714 #ifdef CONFIG_PCI 1715 /* xHCI PCI glue */ 1716 int xhci_register_pci(void); 1717 void xhci_unregister_pci(void); 1718 #else 1719 static inline int xhci_register_pci(void) { return 0; } 1720 static inline void xhci_unregister_pci(void) {} 1721 #endif 1722 1723 #if defined(CONFIG_USB_XHCI_PLATFORM) \ 1724 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE) 1725 int xhci_register_plat(void); 1726 void xhci_unregister_plat(void); 1727 #else 1728 static inline int xhci_register_plat(void) 1729 { return 0; } 1730 static inline void xhci_unregister_plat(void) 1731 { } 1732 #endif 1733 1734 /* xHCI host controller glue */ 1735 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1736 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr, 1737 u32 mask, u32 done, int usec); 1738 void xhci_quiesce(struct xhci_hcd *xhci); 1739 int xhci_halt(struct xhci_hcd *xhci); 1740 int xhci_reset(struct xhci_hcd *xhci); 1741 int xhci_init(struct usb_hcd *hcd); 1742 int xhci_run(struct usb_hcd *hcd); 1743 void xhci_stop(struct usb_hcd *hcd); 1744 void xhci_shutdown(struct usb_hcd *hcd); 1745 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1746 1747 #ifdef CONFIG_PM 1748 int xhci_suspend(struct xhci_hcd *xhci); 1749 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1750 #else 1751 #define xhci_suspend NULL 1752 #define xhci_resume NULL 1753 #endif 1754 1755 int xhci_get_frame(struct usb_hcd *hcd); 1756 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1757 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1758 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1759 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1760 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1761 struct xhci_virt_device *virt_dev, 1762 struct usb_device *hdev, 1763 struct usb_tt *tt, gfp_t mem_flags); 1764 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1765 struct usb_host_endpoint **eps, unsigned int num_eps, 1766 unsigned int num_streams, gfp_t mem_flags); 1767 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1768 struct usb_host_endpoint **eps, unsigned int num_eps, 1769 gfp_t mem_flags); 1770 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1771 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); 1772 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 1773 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 1774 struct usb_device *udev, int enable); 1775 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1776 struct usb_tt *tt, gfp_t mem_flags); 1777 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1778 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1779 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1780 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1781 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1782 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1783 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1784 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1785 1786 /* xHCI ring, segment, TRB, and TD functions */ 1787 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1788 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, 1789 union xhci_trb *start_trb, union xhci_trb *end_trb, 1790 dma_addr_t suspect_dma); 1791 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1792 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1793 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1794 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1795 u32 slot_id, enum xhci_setup_dev); 1796 int xhci_queue_vendor_command(struct xhci_hcd *xhci, 1797 u32 field1, u32 field2, u32 field3, u32 field4); 1798 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, 1799 unsigned int ep_index, int suspend); 1800 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1801 int slot_id, unsigned int ep_index); 1802 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1803 int slot_id, unsigned int ep_index); 1804 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1805 int slot_id, unsigned int ep_index); 1806 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1807 struct urb *urb, int slot_id, unsigned int ep_index); 1808 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1809 u32 slot_id, bool command_must_succeed); 1810 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1811 u32 slot_id, bool command_must_succeed); 1812 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, 1813 unsigned int ep_index); 1814 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id); 1815 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1816 unsigned int slot_id, unsigned int ep_index, 1817 unsigned int stream_id, struct xhci_td *cur_td, 1818 struct xhci_dequeue_state *state); 1819 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1820 unsigned int slot_id, unsigned int ep_index, 1821 unsigned int stream_id, 1822 struct xhci_dequeue_state *deq_state); 1823 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1824 struct usb_device *udev, unsigned int ep_index); 1825 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1826 unsigned int slot_id, unsigned int ep_index, 1827 struct xhci_dequeue_state *deq_state); 1828 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1829 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command, 1830 union xhci_trb *cmd_trb); 1831 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1832 unsigned int ep_index, unsigned int stream_id); 1833 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring); 1834 1835 /* xHCI roothub code */ 1836 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1837 int port_id, u32 link_state); 1838 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, 1839 struct usb_device *udev, enum usb3_link_state state); 1840 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, 1841 struct usb_device *udev, enum usb3_link_state state); 1842 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1843 int port_id, u32 port_bit); 1844 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1845 char *buf, u16 wLength); 1846 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1847 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1848 1849 #ifdef CONFIG_PM 1850 int xhci_bus_suspend(struct usb_hcd *hcd); 1851 int xhci_bus_resume(struct usb_hcd *hcd); 1852 #else 1853 #define xhci_bus_suspend NULL 1854 #define xhci_bus_resume NULL 1855 #endif /* CONFIG_PM */ 1856 1857 u32 xhci_port_state_to_neutral(u32 state); 1858 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1859 u16 port); 1860 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1861 1862 /* xHCI contexts */ 1863 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1864 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1865 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1866 1867 /* xHCI quirks */ 1868 bool xhci_compliance_mode_recovery_timer_quirk_check(void); 1869 1870 #endif /* __LINUX_XHCI_HCD_H */ 1871