1 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __LINUX_XHCI_HCD_H 25 #define __LINUX_XHCI_HCD_H 26 27 #include <linux/usb.h> 28 #include <linux/timer.h> 29 #include <linux/kernel.h> 30 #include <linux/usb/hcd.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 33 /* Code sharing between pci-quirks and xhci hcd */ 34 #include "xhci-ext-caps.h" 35 #include "pci-quirks.h" 36 37 /* xHCI PCI Configuration Registers */ 38 #define XHCI_SBRN_OFFSET (0x60) 39 40 /* Max number of USB devices for any host controller - limit in section 6.1 */ 41 #define MAX_HC_SLOTS 256 42 /* Section 5.3.3 - MaxPorts */ 43 #define MAX_HC_PORTS 127 44 45 /* 46 * xHCI register interface. 47 * This corresponds to the eXtensible Host Controller Interface (xHCI) 48 * Revision 0.95 specification 49 */ 50 51 /** 52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 53 * @hc_capbase: length of the capabilities register and HC version number 54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 57 * @hcc_params: HCCPARAMS - Capability Parameters 58 * @db_off: DBOFF - Doorbell array offset 59 * @run_regs_off: RTSOFF - Runtime register space offset 60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 61 */ 62 struct xhci_cap_regs { 63 __le32 hc_capbase; 64 __le32 hcs_params1; 65 __le32 hcs_params2; 66 __le32 hcs_params3; 67 __le32 hcc_params; 68 __le32 db_off; 69 __le32 run_regs_off; 70 __le32 hcc_params2; /* xhci 1.1 */ 71 /* Reserved up to (CAPLENGTH - 0x1C) */ 72 }; 73 74 /* hc_capbase bitmasks */ 75 /* bits 7:0 - how long is the Capabilities register */ 76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 77 /* bits 31:16 */ 78 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 79 80 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 81 /* bits 0:7, Max Device Slots */ 82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 83 #define HCS_SLOTS_MASK 0xff 84 /* bits 8:18, Max Interrupters */ 85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 88 89 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 90 /* bits 0:3, frames or uframes that SW needs to queue transactions 91 * ahead of the HW to meet periodic deadlines */ 92 #define HCS_IST(p) (((p) >> 0) & 0xf) 93 /* bits 4:7, max number of Event Ring segments */ 94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 99 100 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 105 106 /* HCCPARAMS - hcc_params - bitmasks */ 107 /* true: HC can use 64-bit address pointers */ 108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 109 /* true: HC can do bandwidth negotiation */ 110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 111 /* true: HC uses 64-byte Device Context structures 112 * FIXME 64-byte context structures aren't supported yet. 113 */ 114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 115 /* true: HC has port power switches */ 116 #define HCC_PPC(p) ((p) & (1 << 3)) 117 /* true: HC has port indicators */ 118 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 119 /* true: HC has Light HC Reset Capability */ 120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 121 /* true: HC supports latency tolerance messaging */ 122 #define HCC_LTC(p) ((p) & (1 << 6)) 123 /* true: no secondary Stream ID Support */ 124 #define HCC_NSS(p) ((p) & (1 << 7)) 125 /* true: HC supports Stopped - Short Packet */ 126 #define HCC_SPC(p) ((p) & (1 << 9)) 127 /* true: HC has Contiguous Frame ID Capability */ 128 #define HCC_CFC(p) ((p) & (1 << 11)) 129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 133 134 /* db_off bitmask - bits 0:1 reserved */ 135 #define DBOFF_MASK (~0x3) 136 137 /* run_regs_off bitmask - bits 0:4 reserved */ 138 #define RTSOFF_MASK (~0x1f) 139 140 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 141 /* true: HC supports U3 entry Capability */ 142 #define HCC2_U3C(p) ((p) & (1 << 0)) 143 /* true: HC supports Configure endpoint command Max exit latency too large */ 144 #define HCC2_CMC(p) ((p) & (1 << 1)) 145 /* true: HC supports Force Save context Capability */ 146 #define HCC2_FSC(p) ((p) & (1 << 2)) 147 /* true: HC supports Compliance Transition Capability */ 148 #define HCC2_CTC(p) ((p) & (1 << 3)) 149 /* true: HC support Large ESIT payload Capability > 48k */ 150 #define HCC2_LEC(p) ((p) & (1 << 4)) 151 /* true: HC support Configuration Information Capability */ 152 #define HCC2_CIC(p) ((p) & (1 << 5)) 153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 154 #define HCC2_ETC(p) ((p) & (1 << 6)) 155 156 /* Number of registers per port */ 157 #define NUM_PORT_REGS 4 158 159 #define PORTSC 0 160 #define PORTPMSC 1 161 #define PORTLI 2 162 #define PORTHLPMC 3 163 164 /** 165 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 166 * @command: USBCMD - xHC command register 167 * @status: USBSTS - xHC status register 168 * @page_size: This indicates the page size that the host controller 169 * supports. If bit n is set, the HC supports a page size 170 * of 2^(n+12), up to a 128MB page size. 171 * 4K is the minimum page size. 172 * @cmd_ring: CRP - 64-bit Command Ring Pointer 173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 174 * @config_reg: CONFIG - Configure Register 175 * @port_status_base: PORTSCn - base address for Port Status and Control 176 * Each port has a Port Status and Control register, 177 * followed by a Port Power Management Status and Control 178 * register, a Port Link Info register, and a reserved 179 * register. 180 * @port_power_base: PORTPMSCn - base address for 181 * Port Power Management Status and Control 182 * @port_link_base: PORTLIn - base address for Port Link Info (current 183 * Link PM state and control) for USB 2.1 and USB 3.0 184 * devices. 185 */ 186 struct xhci_op_regs { 187 __le32 command; 188 __le32 status; 189 __le32 page_size; 190 __le32 reserved1; 191 __le32 reserved2; 192 __le32 dev_notification; 193 __le64 cmd_ring; 194 /* rsvd: offset 0x20-2F */ 195 __le32 reserved3[4]; 196 __le64 dcbaa_ptr; 197 __le32 config_reg; 198 /* rsvd: offset 0x3C-3FF */ 199 __le32 reserved4[241]; 200 /* port 1 registers, which serve as a base address for other ports */ 201 __le32 port_status_base; 202 __le32 port_power_base; 203 __le32 port_link_base; 204 __le32 reserved5; 205 /* registers for ports 2-255 */ 206 __le32 reserved6[NUM_PORT_REGS*254]; 207 }; 208 209 /* USBCMD - USB command - command bitmasks */ 210 /* start/stop HC execution - do not write unless HC is halted*/ 211 #define CMD_RUN XHCI_CMD_RUN 212 /* Reset HC - resets internal HC state machine and all registers (except 213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 214 * The xHCI driver must reinitialize the xHC after setting this bit. 215 */ 216 #define CMD_RESET (1 << 1) 217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 218 #define CMD_EIE XHCI_CMD_EIE 219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 220 #define CMD_HSEIE XHCI_CMD_HSEIE 221 /* bits 4:6 are reserved (and should be preserved on writes). */ 222 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 223 #define CMD_LRESET (1 << 7) 224 /* host controller save/restore state. */ 225 #define CMD_CSS (1 << 8) 226 #define CMD_CRS (1 << 9) 227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 228 #define CMD_EWE XHCI_CMD_EWE 229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 231 * '0' means the xHC can power it off if all ports are in the disconnect, 232 * disabled, or powered-off state. 233 */ 234 #define CMD_PM_INDEX (1 << 11) 235 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 236 #define CMD_ETE (1 << 14) 237 /* bits 15:31 are reserved (and should be preserved on writes). */ 238 239 /* IMAN - Interrupt Management Register */ 240 #define IMAN_IE (1 << 1) 241 #define IMAN_IP (1 << 0) 242 243 /* USBSTS - USB status - status bitmasks */ 244 /* HC not running - set to 1 when run/stop bit is cleared. */ 245 #define STS_HALT XHCI_STS_HALT 246 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 247 #define STS_FATAL (1 << 2) 248 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 249 #define STS_EINT (1 << 3) 250 /* port change detect */ 251 #define STS_PORT (1 << 4) 252 /* bits 5:7 reserved and zeroed */ 253 /* save state status - '1' means xHC is saving state */ 254 #define STS_SAVE (1 << 8) 255 /* restore state status - '1' means xHC is restoring state */ 256 #define STS_RESTORE (1 << 9) 257 /* true: save or restore error */ 258 #define STS_SRE (1 << 10) 259 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 260 #define STS_CNR XHCI_STS_CNR 261 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 262 #define STS_HCE (1 << 12) 263 /* bits 13:31 reserved and should be preserved */ 264 265 /* 266 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 267 * Generate a device notification event when the HC sees a transaction with a 268 * notification type that matches a bit set in this bit field. 269 */ 270 #define DEV_NOTE_MASK (0xffff) 271 #define ENABLE_DEV_NOTE(x) (1 << (x)) 272 /* Most of the device notification types should only be used for debug. 273 * SW does need to pay attention to function wake notifications. 274 */ 275 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 276 277 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 278 /* bit 0 is the command ring cycle state */ 279 /* stop ring operation after completion of the currently executing command */ 280 #define CMD_RING_PAUSE (1 << 1) 281 /* stop ring immediately - abort the currently executing command */ 282 #define CMD_RING_ABORT (1 << 2) 283 /* true: command ring is running */ 284 #define CMD_RING_RUNNING (1 << 3) 285 /* bits 4:5 reserved and should be preserved */ 286 /* Command Ring pointer - bit mask for the lower 32 bits. */ 287 #define CMD_RING_RSVD_BITS (0x3f) 288 289 /* CONFIG - Configure Register - config_reg bitmasks */ 290 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 291 #define MAX_DEVS(p) ((p) & 0xff) 292 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 293 #define CONFIG_U3E (1 << 8) 294 /* bit 9: Configuration Information Enable, xhci 1.1 */ 295 #define CONFIG_CIE (1 << 9) 296 /* bits 10:31 - reserved and should be preserved */ 297 298 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 299 /* true: device connected */ 300 #define PORT_CONNECT (1 << 0) 301 /* true: port enabled */ 302 #define PORT_PE (1 << 1) 303 /* bit 2 reserved and zeroed */ 304 /* true: port has an over-current condition */ 305 #define PORT_OC (1 << 3) 306 /* true: port reset signaling asserted */ 307 #define PORT_RESET (1 << 4) 308 /* Port Link State - bits 5:8 309 * A read gives the current link PM state of the port, 310 * a write with Link State Write Strobe set sets the link state. 311 */ 312 #define PORT_PLS_MASK (0xf << 5) 313 #define XDEV_U0 (0x0 << 5) 314 #define XDEV_U2 (0x2 << 5) 315 #define XDEV_U3 (0x3 << 5) 316 #define XDEV_INACTIVE (0x6 << 5) 317 #define XDEV_POLLING (0x7 << 5) 318 #define XDEV_COMP_MODE (0xa << 5) 319 #define XDEV_RESUME (0xf << 5) 320 /* true: port has power (see HCC_PPC) */ 321 #define PORT_POWER (1 << 9) 322 /* bits 10:13 indicate device speed: 323 * 0 - undefined speed - port hasn't be initialized by a reset yet 324 * 1 - full speed 325 * 2 - low speed 326 * 3 - high speed 327 * 4 - super speed 328 * 5-15 reserved 329 */ 330 #define DEV_SPEED_MASK (0xf << 10) 331 #define XDEV_FS (0x1 << 10) 332 #define XDEV_LS (0x2 << 10) 333 #define XDEV_HS (0x3 << 10) 334 #define XDEV_SS (0x4 << 10) 335 #define XDEV_SSP (0x5 << 10) 336 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 337 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 338 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 339 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 340 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 341 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 342 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 343 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 344 345 /* Bits 20:23 in the Slot Context are the speed for the device */ 346 #define SLOT_SPEED_FS (XDEV_FS << 10) 347 #define SLOT_SPEED_LS (XDEV_LS << 10) 348 #define SLOT_SPEED_HS (XDEV_HS << 10) 349 #define SLOT_SPEED_SS (XDEV_SS << 10) 350 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 351 /* Port Indicator Control */ 352 #define PORT_LED_OFF (0 << 14) 353 #define PORT_LED_AMBER (1 << 14) 354 #define PORT_LED_GREEN (2 << 14) 355 #define PORT_LED_MASK (3 << 14) 356 /* Port Link State Write Strobe - set this when changing link state */ 357 #define PORT_LINK_STROBE (1 << 16) 358 /* true: connect status change */ 359 #define PORT_CSC (1 << 17) 360 /* true: port enable change */ 361 #define PORT_PEC (1 << 18) 362 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 363 * into an enabled state, and the device into the default state. A "warm" reset 364 * also resets the link, forcing the device through the link training sequence. 365 * SW can also look at the Port Reset register to see when warm reset is done. 366 */ 367 #define PORT_WRC (1 << 19) 368 /* true: over-current change */ 369 #define PORT_OCC (1 << 20) 370 /* true: reset change - 1 to 0 transition of PORT_RESET */ 371 #define PORT_RC (1 << 21) 372 /* port link status change - set on some port link state transitions: 373 * Transition Reason 374 * ------------------------------------------------------------------------------ 375 * - U3 to Resume Wakeup signaling from a device 376 * - Resume to Recovery to U0 USB 3.0 device resume 377 * - Resume to U0 USB 2.0 device resume 378 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 379 * - U3 to U0 Software resume of USB 2.0 device complete 380 * - U2 to U0 L1 resume of USB 2.1 device complete 381 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 382 * - U0 to disabled L1 entry error with USB 2.1 device 383 * - Any state to inactive Error on USB 3.0 port 384 */ 385 #define PORT_PLC (1 << 22) 386 /* port configure error change - port failed to configure its link partner */ 387 #define PORT_CEC (1 << 23) 388 /* Cold Attach Status - xHC can set this bit to report device attached during 389 * Sx state. Warm port reset should be perfomed to clear this bit and move port 390 * to connected state. 391 */ 392 #define PORT_CAS (1 << 24) 393 /* wake on connect (enable) */ 394 #define PORT_WKCONN_E (1 << 25) 395 /* wake on disconnect (enable) */ 396 #define PORT_WKDISC_E (1 << 26) 397 /* wake on over-current (enable) */ 398 #define PORT_WKOC_E (1 << 27) 399 /* bits 28:29 reserved */ 400 /* true: device is non-removable - for USB 3.0 roothub emulation */ 401 #define PORT_DEV_REMOVE (1 << 30) 402 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 403 #define PORT_WR (1 << 31) 404 405 /* We mark duplicate entries with -1 */ 406 #define DUPLICATE_ENTRY ((u8)(-1)) 407 408 /* Port Power Management Status and Control - port_power_base bitmasks */ 409 /* Inactivity timer value for transitions into U1, in microseconds. 410 * Timeout can be up to 127us. 0xFF means an infinite timeout. 411 */ 412 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 413 #define PORT_U1_TIMEOUT_MASK 0xff 414 /* Inactivity timer value for transitions into U2 */ 415 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 416 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 417 /* Bits 24:31 for port testing */ 418 419 /* USB2 Protocol PORTSPMSC */ 420 #define PORT_L1S_MASK 7 421 #define PORT_L1S_SUCCESS 1 422 #define PORT_RWE (1 << 3) 423 #define PORT_HIRD(p) (((p) & 0xf) << 4) 424 #define PORT_HIRD_MASK (0xf << 4) 425 #define PORT_L1DS_MASK (0xff << 8) 426 #define PORT_L1DS(p) (((p) & 0xff) << 8) 427 #define PORT_HLE (1 << 16) 428 429 /* USB3 Protocol PORTLI Port Link Information */ 430 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 431 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 432 433 /* USB2 Protocol PORTHLPMC */ 434 #define PORT_HIRDM(p)((p) & 3) 435 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 436 #define PORT_BESLD(p)(((p) & 0xf) << 10) 437 438 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 439 #define XHCI_L1_TIMEOUT 512 440 441 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 442 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 443 * by other operating systems. 444 * 445 * XHCI 1.0 errata 8/14/12 Table 13 notes: 446 * "Software should choose xHC BESL/BESLD field values that do not violate a 447 * device's resume latency requirements, 448 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 449 * or not program values < '4' if BLC = '0' and a BESL device is attached. 450 */ 451 #define XHCI_DEFAULT_BESL 4 452 453 /** 454 * struct xhci_intr_reg - Interrupt Register Set 455 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 456 * interrupts and check for pending interrupts. 457 * @irq_control: IMOD - Interrupt Moderation Register. 458 * Used to throttle interrupts. 459 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 460 * @erst_base: ERST base address. 461 * @erst_dequeue: Event ring dequeue pointer. 462 * 463 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 464 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 465 * multiple segments of the same size. The HC places events on the ring and 466 * "updates the Cycle bit in the TRBs to indicate to software the current 467 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 468 * updates the dequeue pointer. 469 */ 470 struct xhci_intr_reg { 471 __le32 irq_pending; 472 __le32 irq_control; 473 __le32 erst_size; 474 __le32 rsvd; 475 __le64 erst_base; 476 __le64 erst_dequeue; 477 }; 478 479 /* irq_pending bitmasks */ 480 #define ER_IRQ_PENDING(p) ((p) & 0x1) 481 /* bits 2:31 need to be preserved */ 482 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 483 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 484 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 485 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 486 487 /* irq_control bitmasks */ 488 /* Minimum interval between interrupts (in 250ns intervals). The interval 489 * between interrupts will be longer if there are no events on the event ring. 490 * Default is 4000 (1 ms). 491 */ 492 #define ER_IRQ_INTERVAL_MASK (0xffff) 493 /* Counter used to count down the time to the next interrupt - HW use only */ 494 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 495 496 /* erst_size bitmasks */ 497 /* Preserve bits 16:31 of erst_size */ 498 #define ERST_SIZE_MASK (0xffff << 16) 499 500 /* erst_dequeue bitmasks */ 501 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 502 * where the current dequeue pointer lies. This is an optional HW hint. 503 */ 504 #define ERST_DESI_MASK (0x7) 505 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 506 * a work queue (or delayed service routine)? 507 */ 508 #define ERST_EHB (1 << 3) 509 #define ERST_PTR_MASK (0xf) 510 511 /** 512 * struct xhci_run_regs 513 * @microframe_index: 514 * MFINDEX - current microframe number 515 * 516 * Section 5.5 Host Controller Runtime Registers: 517 * "Software should read and write these registers using only Dword (32 bit) 518 * or larger accesses" 519 */ 520 struct xhci_run_regs { 521 __le32 microframe_index; 522 __le32 rsvd[7]; 523 struct xhci_intr_reg ir_set[128]; 524 }; 525 526 /** 527 * struct doorbell_array 528 * 529 * Bits 0 - 7: Endpoint target 530 * Bits 8 - 15: RsvdZ 531 * Bits 16 - 31: Stream ID 532 * 533 * Section 5.6 534 */ 535 struct xhci_doorbell_array { 536 __le32 doorbell[256]; 537 }; 538 539 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 540 #define DB_VALUE_HOST 0x00000000 541 542 /** 543 * struct xhci_protocol_caps 544 * @revision: major revision, minor revision, capability ID, 545 * and next capability pointer. 546 * @name_string: Four ASCII characters to say which spec this xHC 547 * follows, typically "USB ". 548 * @port_info: Port offset, count, and protocol-defined information. 549 */ 550 struct xhci_protocol_caps { 551 u32 revision; 552 u32 name_string; 553 u32 port_info; 554 }; 555 556 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 557 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 558 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 559 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 560 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 561 562 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 563 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 564 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 565 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 566 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 567 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 568 569 #define PLT_MASK (0x03 << 6) 570 #define PLT_SYM (0x00 << 6) 571 #define PLT_ASYM_RX (0x02 << 6) 572 #define PLT_ASYM_TX (0x03 << 6) 573 574 /** 575 * struct xhci_container_ctx 576 * @type: Type of context. Used to calculated offsets to contained contexts. 577 * @size: Size of the context data 578 * @bytes: The raw context data given to HW 579 * @dma: dma address of the bytes 580 * 581 * Represents either a Device or Input context. Holds a pointer to the raw 582 * memory used for the context (bytes) and dma address of it (dma). 583 */ 584 struct xhci_container_ctx { 585 unsigned type; 586 #define XHCI_CTX_TYPE_DEVICE 0x1 587 #define XHCI_CTX_TYPE_INPUT 0x2 588 589 int size; 590 591 u8 *bytes; 592 dma_addr_t dma; 593 }; 594 595 /** 596 * struct xhci_slot_ctx 597 * @dev_info: Route string, device speed, hub info, and last valid endpoint 598 * @dev_info2: Max exit latency for device number, root hub port number 599 * @tt_info: tt_info is used to construct split transaction tokens 600 * @dev_state: slot state and device address 601 * 602 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 603 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 604 * reserved at the end of the slot context for HC internal use. 605 */ 606 struct xhci_slot_ctx { 607 __le32 dev_info; 608 __le32 dev_info2; 609 __le32 tt_info; 610 __le32 dev_state; 611 /* offset 0x10 to 0x1f reserved for HC internal use */ 612 __le32 reserved[4]; 613 }; 614 615 /* dev_info bitmasks */ 616 /* Route String - 0:19 */ 617 #define ROUTE_STRING_MASK (0xfffff) 618 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 619 #define DEV_SPEED (0xf << 20) 620 /* bit 24 reserved */ 621 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 622 #define DEV_MTT (0x1 << 25) 623 /* Set if the device is a hub - bit 26 */ 624 #define DEV_HUB (0x1 << 26) 625 /* Index of the last valid endpoint context in this device context - 27:31 */ 626 #define LAST_CTX_MASK (0x1f << 27) 627 #define LAST_CTX(p) ((p) << 27) 628 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 629 #define SLOT_FLAG (1 << 0) 630 #define EP0_FLAG (1 << 1) 631 632 /* dev_info2 bitmasks */ 633 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 634 #define MAX_EXIT (0xffff) 635 /* Root hub port number that is needed to access the USB device */ 636 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 637 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 638 /* Maximum number of ports under a hub device */ 639 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 640 641 /* tt_info bitmasks */ 642 /* 643 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 644 * The Slot ID of the hub that isolates the high speed signaling from 645 * this low or full-speed device. '0' if attached to root hub port. 646 */ 647 #define TT_SLOT (0xff) 648 /* 649 * The number of the downstream facing port of the high-speed hub 650 * '0' if the device is not low or full speed. 651 */ 652 #define TT_PORT (0xff << 8) 653 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 654 655 /* dev_state bitmasks */ 656 /* USB device address - assigned by the HC */ 657 #define DEV_ADDR_MASK (0xff) 658 /* bits 8:26 reserved */ 659 /* Slot state */ 660 #define SLOT_STATE (0x1f << 27) 661 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 662 663 #define SLOT_STATE_DISABLED 0 664 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 665 #define SLOT_STATE_DEFAULT 1 666 #define SLOT_STATE_ADDRESSED 2 667 #define SLOT_STATE_CONFIGURED 3 668 669 /** 670 * struct xhci_ep_ctx 671 * @ep_info: endpoint state, streams, mult, and interval information. 672 * @ep_info2: information on endpoint type, max packet size, max burst size, 673 * error count, and whether the HC will force an event for all 674 * transactions. 675 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 676 * defines one stream, this points to the endpoint transfer ring. 677 * Otherwise, it points to a stream context array, which has a 678 * ring pointer for each flow. 679 * @tx_info: 680 * Average TRB lengths for the endpoint ring and 681 * max payload within an Endpoint Service Interval Time (ESIT). 682 * 683 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 684 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 685 * reserved at the end of the endpoint context for HC internal use. 686 */ 687 struct xhci_ep_ctx { 688 __le32 ep_info; 689 __le32 ep_info2; 690 __le64 deq; 691 __le32 tx_info; 692 /* offset 0x14 - 0x1f reserved for HC internal use */ 693 __le32 reserved[3]; 694 }; 695 696 /* ep_info bitmasks */ 697 /* 698 * Endpoint State - bits 0:2 699 * 0 - disabled 700 * 1 - running 701 * 2 - halted due to halt condition - ok to manipulate endpoint ring 702 * 3 - stopped 703 * 4 - TRB error 704 * 5-7 - reserved 705 */ 706 #define EP_STATE_MASK (0xf) 707 #define EP_STATE_DISABLED 0 708 #define EP_STATE_RUNNING 1 709 #define EP_STATE_HALTED 2 710 #define EP_STATE_STOPPED 3 711 #define EP_STATE_ERROR 4 712 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 713 714 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 715 #define EP_MULT(p) (((p) & 0x3) << 8) 716 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 717 /* bits 10:14 are Max Primary Streams */ 718 /* bit 15 is Linear Stream Array */ 719 /* Interval - period between requests to an endpoint - 125u increments. */ 720 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 721 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 722 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 723 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 724 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 725 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 726 #define EP_HAS_LSA (1 << 15) 727 728 /* ep_info2 bitmasks */ 729 /* 730 * Force Event - generate transfer events for all TRBs for this endpoint 731 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 732 */ 733 #define FORCE_EVENT (0x1) 734 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 735 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 736 #define EP_TYPE(p) ((p) << 3) 737 #define ISOC_OUT_EP 1 738 #define BULK_OUT_EP 2 739 #define INT_OUT_EP 3 740 #define CTRL_EP 4 741 #define ISOC_IN_EP 5 742 #define BULK_IN_EP 6 743 #define INT_IN_EP 7 744 /* bit 6 reserved */ 745 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 746 #define MAX_BURST(p) (((p)&0xff) << 8) 747 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 748 #define MAX_PACKET(p) (((p)&0xffff) << 16) 749 #define MAX_PACKET_MASK (0xffff << 16) 750 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 751 752 /* tx_info bitmasks */ 753 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 754 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 755 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 756 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 757 758 /* deq bitmasks */ 759 #define EP_CTX_CYCLE_MASK (1 << 0) 760 #define SCTX_DEQ_MASK (~0xfL) 761 762 763 /** 764 * struct xhci_input_control_context 765 * Input control context; see section 6.2.5. 766 * 767 * @drop_context: set the bit of the endpoint context you want to disable 768 * @add_context: set the bit of the endpoint context you want to enable 769 */ 770 struct xhci_input_control_ctx { 771 __le32 drop_flags; 772 __le32 add_flags; 773 __le32 rsvd2[6]; 774 }; 775 776 #define EP_IS_ADDED(ctrl_ctx, i) \ 777 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 778 #define EP_IS_DROPPED(ctrl_ctx, i) \ 779 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 780 781 /* Represents everything that is needed to issue a command on the command ring. 782 * It's useful to pre-allocate these for commands that cannot fail due to 783 * out-of-memory errors, like freeing streams. 784 */ 785 struct xhci_command { 786 /* Input context for changing device state */ 787 struct xhci_container_ctx *in_ctx; 788 u32 status; 789 int slot_id; 790 /* If completion is null, no one is waiting on this command 791 * and the structure can be freed after the command completes. 792 */ 793 struct completion *completion; 794 union xhci_trb *command_trb; 795 struct list_head cmd_list; 796 }; 797 798 /* drop context bitmasks */ 799 #define DROP_EP(x) (0x1 << x) 800 /* add context bitmasks */ 801 #define ADD_EP(x) (0x1 << x) 802 803 struct xhci_stream_ctx { 804 /* 64-bit stream ring address, cycle state, and stream type */ 805 __le64 stream_ring; 806 /* offset 0x14 - 0x1f reserved for HC internal use */ 807 __le32 reserved[2]; 808 }; 809 810 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 811 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 812 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 813 #define SCT_SEC_TR 0 814 /* Primary stream array type, dequeue pointer is to a transfer ring */ 815 #define SCT_PRI_TR 1 816 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 817 #define SCT_SSA_8 2 818 #define SCT_SSA_16 3 819 #define SCT_SSA_32 4 820 #define SCT_SSA_64 5 821 #define SCT_SSA_128 6 822 #define SCT_SSA_256 7 823 824 /* Assume no secondary streams for now */ 825 struct xhci_stream_info { 826 struct xhci_ring **stream_rings; 827 /* Number of streams, including stream 0 (which drivers can't use) */ 828 unsigned int num_streams; 829 /* The stream context array may be bigger than 830 * the number of streams the driver asked for 831 */ 832 struct xhci_stream_ctx *stream_ctx_array; 833 unsigned int num_stream_ctxs; 834 dma_addr_t ctx_array_dma; 835 /* For mapping physical TRB addresses to segments in stream rings */ 836 struct radix_tree_root trb_address_map; 837 struct xhci_command *free_streams_command; 838 }; 839 840 #define SMALL_STREAM_ARRAY_SIZE 256 841 #define MEDIUM_STREAM_ARRAY_SIZE 1024 842 843 /* Some Intel xHCI host controllers need software to keep track of the bus 844 * bandwidth. Keep track of endpoint info here. Each root port is allocated 845 * the full bus bandwidth. We must also treat TTs (including each port under a 846 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 847 * (DMI) also limits the total bandwidth (across all domains) that can be used. 848 */ 849 struct xhci_bw_info { 850 /* ep_interval is zero-based */ 851 unsigned int ep_interval; 852 /* mult and num_packets are one-based */ 853 unsigned int mult; 854 unsigned int num_packets; 855 unsigned int max_packet_size; 856 unsigned int max_esit_payload; 857 unsigned int type; 858 }; 859 860 /* "Block" sizes in bytes the hardware uses for different device speeds. 861 * The logic in this part of the hardware limits the number of bits the hardware 862 * can use, so must represent bandwidth in a less precise manner to mimic what 863 * the scheduler hardware computes. 864 */ 865 #define FS_BLOCK 1 866 #define HS_BLOCK 4 867 #define SS_BLOCK 16 868 #define DMI_BLOCK 32 869 870 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 871 * with each byte transferred. SuperSpeed devices have an initial overhead to 872 * set up bursts. These are in blocks, see above. LS overhead has already been 873 * translated into FS blocks. 874 */ 875 #define DMI_OVERHEAD 8 876 #define DMI_OVERHEAD_BURST 4 877 #define SS_OVERHEAD 8 878 #define SS_OVERHEAD_BURST 32 879 #define HS_OVERHEAD 26 880 #define FS_OVERHEAD 20 881 #define LS_OVERHEAD 128 882 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 883 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 884 * of overhead associated with split transfers crossing microframe boundaries. 885 * 31 blocks is pure protocol overhead. 886 */ 887 #define TT_HS_OVERHEAD (31 + 94) 888 #define TT_DMI_OVERHEAD (25 + 12) 889 890 /* Bandwidth limits in blocks */ 891 #define FS_BW_LIMIT 1285 892 #define TT_BW_LIMIT 1320 893 #define HS_BW_LIMIT 1607 894 #define SS_BW_LIMIT_IN 3906 895 #define DMI_BW_LIMIT_IN 3906 896 #define SS_BW_LIMIT_OUT 3906 897 #define DMI_BW_LIMIT_OUT 3906 898 899 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 900 #define FS_BW_RESERVED 10 901 #define HS_BW_RESERVED 20 902 #define SS_BW_RESERVED 10 903 904 struct xhci_virt_ep { 905 struct xhci_ring *ring; 906 /* Related to endpoints that are configured to use stream IDs only */ 907 struct xhci_stream_info *stream_info; 908 /* Temporary storage in case the configure endpoint command fails and we 909 * have to restore the device state to the previous state 910 */ 911 struct xhci_ring *new_ring; 912 unsigned int ep_state; 913 #define SET_DEQ_PENDING (1 << 0) 914 #define EP_HALTED (1 << 1) /* For stall handling */ 915 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 916 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 917 #define EP_GETTING_STREAMS (1 << 3) 918 #define EP_HAS_STREAMS (1 << 4) 919 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 920 #define EP_GETTING_NO_STREAMS (1 << 5) 921 /* ---- Related to URB cancellation ---- */ 922 struct list_head cancelled_td_list; 923 struct xhci_td *stopped_td; 924 unsigned int stopped_stream; 925 /* Watchdog timer for stop endpoint command to cancel URBs */ 926 struct timer_list stop_cmd_timer; 927 struct xhci_hcd *xhci; 928 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 929 * command. We'll need to update the ring's dequeue segment and dequeue 930 * pointer after the command completes. 931 */ 932 struct xhci_segment *queued_deq_seg; 933 union xhci_trb *queued_deq_ptr; 934 /* 935 * Sometimes the xHC can not process isochronous endpoint ring quickly 936 * enough, and it will miss some isoc tds on the ring and generate 937 * a Missed Service Error Event. 938 * Set skip flag when receive a Missed Service Error Event and 939 * process the missed tds on the endpoint ring. 940 */ 941 bool skip; 942 /* Bandwidth checking storage */ 943 struct xhci_bw_info bw_info; 944 struct list_head bw_endpoint_list; 945 /* Isoch Frame ID checking storage */ 946 int next_frame_id; 947 /* Use new Isoch TRB layout needed for extended TBC support */ 948 bool use_extended_tbc; 949 }; 950 951 enum xhci_overhead_type { 952 LS_OVERHEAD_TYPE = 0, 953 FS_OVERHEAD_TYPE, 954 HS_OVERHEAD_TYPE, 955 }; 956 957 struct xhci_interval_bw { 958 unsigned int num_packets; 959 /* Sorted by max packet size. 960 * Head of the list is the greatest max packet size. 961 */ 962 struct list_head endpoints; 963 /* How many endpoints of each speed are present. */ 964 unsigned int overhead[3]; 965 }; 966 967 #define XHCI_MAX_INTERVAL 16 968 969 struct xhci_interval_bw_table { 970 unsigned int interval0_esit_payload; 971 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 972 /* Includes reserved bandwidth for async endpoints */ 973 unsigned int bw_used; 974 unsigned int ss_bw_in; 975 unsigned int ss_bw_out; 976 }; 977 978 979 struct xhci_virt_device { 980 struct usb_device *udev; 981 /* 982 * Commands to the hardware are passed an "input context" that 983 * tells the hardware what to change in its data structures. 984 * The hardware will return changes in an "output context" that 985 * software must allocate for the hardware. We need to keep 986 * track of input and output contexts separately because 987 * these commands might fail and we don't trust the hardware. 988 */ 989 struct xhci_container_ctx *out_ctx; 990 /* Used for addressing devices and configuration changes */ 991 struct xhci_container_ctx *in_ctx; 992 /* Rings saved to ensure old alt settings can be re-instated */ 993 struct xhci_ring **ring_cache; 994 int num_rings_cached; 995 #define XHCI_MAX_RINGS_CACHED 31 996 struct xhci_virt_ep eps[31]; 997 u8 fake_port; 998 u8 real_port; 999 struct xhci_interval_bw_table *bw_table; 1000 struct xhci_tt_bw_info *tt_info; 1001 /* The current max exit latency for the enabled USB3 link states. */ 1002 u16 current_mel; 1003 }; 1004 1005 /* 1006 * For each roothub, keep track of the bandwidth information for each periodic 1007 * interval. 1008 * 1009 * If a high speed hub is attached to the roothub, each TT associated with that 1010 * hub is a separate bandwidth domain. The interval information for the 1011 * endpoints on the devices under that TT will appear in the TT structure. 1012 */ 1013 struct xhci_root_port_bw_info { 1014 struct list_head tts; 1015 unsigned int num_active_tts; 1016 struct xhci_interval_bw_table bw_table; 1017 }; 1018 1019 struct xhci_tt_bw_info { 1020 struct list_head tt_list; 1021 int slot_id; 1022 int ttport; 1023 struct xhci_interval_bw_table bw_table; 1024 int active_eps; 1025 }; 1026 1027 1028 /** 1029 * struct xhci_device_context_array 1030 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1031 */ 1032 struct xhci_device_context_array { 1033 /* 64-bit device addresses; we only write 32-bit addresses */ 1034 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1035 /* private xHCD pointers */ 1036 dma_addr_t dma; 1037 }; 1038 /* TODO: write function to set the 64-bit device DMA address */ 1039 /* 1040 * TODO: change this to be dynamically sized at HC mem init time since the HC 1041 * might not be able to handle the maximum number of devices possible. 1042 */ 1043 1044 1045 struct xhci_transfer_event { 1046 /* 64-bit buffer address, or immediate data */ 1047 __le64 buffer; 1048 __le32 transfer_len; 1049 /* This field is interpreted differently based on the type of TRB */ 1050 __le32 flags; 1051 }; 1052 1053 /* Transfer event TRB length bit mask */ 1054 /* bits 0:23 */ 1055 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1056 1057 /** Transfer Event bit fields **/ 1058 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1059 1060 /* Completion Code - only applicable for some types of TRBs */ 1061 #define COMP_CODE_MASK (0xff << 24) 1062 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1063 #define COMP_INVALID 0 1064 #define COMP_SUCCESS 1 1065 #define COMP_DATA_BUFFER_ERROR 2 1066 #define COMP_BABBLE_DETECTED_ERROR 3 1067 #define COMP_USB_TRANSACTION_ERROR 4 1068 #define COMP_TRB_ERROR 5 1069 #define COMP_STALL_ERROR 6 1070 #define COMP_RESOURCE_ERROR 7 1071 #define COMP_BANDWIDTH_ERROR 8 1072 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1073 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1074 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1075 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1076 #define COMP_SHORT_PACKET 13 1077 #define COMP_RING_UNDERRUN 14 1078 #define COMP_RING_OVERRUN 15 1079 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1080 #define COMP_PARAMETER_ERROR 17 1081 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1082 #define COMP_CONTEXT_STATE_ERROR 19 1083 #define COMP_NO_PING_RESPONSE_ERROR 20 1084 #define COMP_EVENT_RING_FULL_ERROR 21 1085 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1086 #define COMP_MISSED_SERVICE_ERROR 23 1087 #define COMP_COMMAND_RING_STOPPED 24 1088 #define COMP_COMMAND_ABORTED 25 1089 #define COMP_STOPPED 26 1090 #define COMP_STOPPED_LENGTH_INVALID 27 1091 #define COMP_STOPPED_SHORT_PACKET 28 1092 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1093 #define COMP_ISOCH_BUFFER_OVERRUN 31 1094 #define COMP_EVENT_LOST_ERROR 32 1095 #define COMP_UNDEFINED_ERROR 33 1096 #define COMP_INVALID_STREAM_ID_ERROR 34 1097 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1098 #define COMP_SPLIT_TRANSACTION_ERROR 36 1099 1100 static inline const char *xhci_trb_comp_code_string(u8 status) 1101 { 1102 switch (status) { 1103 case COMP_INVALID: 1104 return "Invalid"; 1105 case COMP_SUCCESS: 1106 return "Success"; 1107 case COMP_DATA_BUFFER_ERROR: 1108 return "Data Buffer Error"; 1109 case COMP_BABBLE_DETECTED_ERROR: 1110 return "Babble Detected"; 1111 case COMP_USB_TRANSACTION_ERROR: 1112 return "USB Transaction Error"; 1113 case COMP_TRB_ERROR: 1114 return "TRB Error"; 1115 case COMP_STALL_ERROR: 1116 return "Stall Error"; 1117 case COMP_RESOURCE_ERROR: 1118 return "Resource Error"; 1119 case COMP_BANDWIDTH_ERROR: 1120 return "Bandwidth Error"; 1121 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1122 return "No Slots Available Error"; 1123 case COMP_INVALID_STREAM_TYPE_ERROR: 1124 return "Invalid Stream Type Error"; 1125 case COMP_SLOT_NOT_ENABLED_ERROR: 1126 return "Slot Not Enabled Error"; 1127 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1128 return "Endpoint Not Enabled Error"; 1129 case COMP_SHORT_PACKET: 1130 return "Short Packet"; 1131 case COMP_RING_UNDERRUN: 1132 return "Ring Underrun"; 1133 case COMP_RING_OVERRUN: 1134 return "Ring Overrun"; 1135 case COMP_VF_EVENT_RING_FULL_ERROR: 1136 return "VF Event Ring Full Error"; 1137 case COMP_PARAMETER_ERROR: 1138 return "Parameter Error"; 1139 case COMP_BANDWIDTH_OVERRUN_ERROR: 1140 return "Bandwidth Overrun Error"; 1141 case COMP_CONTEXT_STATE_ERROR: 1142 return "Context State Error"; 1143 case COMP_NO_PING_RESPONSE_ERROR: 1144 return "No Ping Response Error"; 1145 case COMP_EVENT_RING_FULL_ERROR: 1146 return "Event Ring Full Error"; 1147 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1148 return "Incompatible Device Error"; 1149 case COMP_MISSED_SERVICE_ERROR: 1150 return "Missed Service Error"; 1151 case COMP_COMMAND_RING_STOPPED: 1152 return "Command Ring Stopped"; 1153 case COMP_COMMAND_ABORTED: 1154 return "Command Aborted"; 1155 case COMP_STOPPED: 1156 return "Stopped"; 1157 case COMP_STOPPED_LENGTH_INVALID: 1158 return "Stopped - Length Invalid"; 1159 case COMP_STOPPED_SHORT_PACKET: 1160 return "Stopped - Short Packet"; 1161 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1162 return "Max Exit Latency Too Large Error"; 1163 case COMP_ISOCH_BUFFER_OVERRUN: 1164 return "Isoch Buffer Overrun"; 1165 case COMP_EVENT_LOST_ERROR: 1166 return "Event Lost Error"; 1167 case COMP_UNDEFINED_ERROR: 1168 return "Undefined Error"; 1169 case COMP_INVALID_STREAM_ID_ERROR: 1170 return "Invalid Stream ID Error"; 1171 case COMP_SECONDARY_BANDWIDTH_ERROR: 1172 return "Secondary Bandwidth Error"; 1173 case COMP_SPLIT_TRANSACTION_ERROR: 1174 return "Split Transaction Error"; 1175 default: 1176 return "Unknown!!"; 1177 } 1178 } 1179 1180 struct xhci_link_trb { 1181 /* 64-bit segment pointer*/ 1182 __le64 segment_ptr; 1183 __le32 intr_target; 1184 __le32 control; 1185 }; 1186 1187 /* control bitfields */ 1188 #define LINK_TOGGLE (0x1<<1) 1189 1190 /* Command completion event TRB */ 1191 struct xhci_event_cmd { 1192 /* Pointer to command TRB, or the value passed by the event data trb */ 1193 __le64 cmd_trb; 1194 __le32 status; 1195 __le32 flags; 1196 }; 1197 1198 /* flags bitmasks */ 1199 1200 /* Address device - disable SetAddress */ 1201 #define TRB_BSR (1<<9) 1202 1203 /* Configure Endpoint - Deconfigure */ 1204 #define TRB_DC (1<<9) 1205 1206 /* Stop Ring - Transfer State Preserve */ 1207 #define TRB_TSP (1<<9) 1208 1209 /* Force Event */ 1210 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1211 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1212 1213 /* Set Latency Tolerance Value */ 1214 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1215 1216 /* Get Port Bandwidth */ 1217 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1218 1219 /* Force Header */ 1220 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1221 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1222 1223 enum xhci_setup_dev { 1224 SETUP_CONTEXT_ONLY, 1225 SETUP_CONTEXT_ADDRESS, 1226 }; 1227 1228 /* bits 16:23 are the virtual function ID */ 1229 /* bits 24:31 are the slot ID */ 1230 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1231 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1232 1233 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1234 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1235 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1236 1237 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1238 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1239 #define LAST_EP_INDEX 30 1240 1241 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1242 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1243 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1244 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1245 1246 /* Link TRB specific fields */ 1247 #define TRB_TC (1<<1) 1248 1249 /* Port Status Change Event TRB fields */ 1250 /* Port ID - bits 31:24 */ 1251 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1252 1253 #define EVENT_DATA (1 << 2) 1254 1255 /* Normal TRB fields */ 1256 /* transfer_len bitmasks - bits 0:16 */ 1257 #define TRB_LEN(p) ((p) & 0x1ffff) 1258 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1259 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1260 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1261 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1262 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1263 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1264 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1265 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1266 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1267 #define TRB_TBC(p) (((p) & 0x3) << 7) 1268 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1269 1270 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1271 #define TRB_CYCLE (1<<0) 1272 /* 1273 * Force next event data TRB to be evaluated before task switch. 1274 * Used to pass OS data back after a TD completes. 1275 */ 1276 #define TRB_ENT (1<<1) 1277 /* Interrupt on short packet */ 1278 #define TRB_ISP (1<<2) 1279 /* Set PCIe no snoop attribute */ 1280 #define TRB_NO_SNOOP (1<<3) 1281 /* Chain multiple TRBs into a TD */ 1282 #define TRB_CHAIN (1<<4) 1283 /* Interrupt on completion */ 1284 #define TRB_IOC (1<<5) 1285 /* The buffer pointer contains immediate data */ 1286 #define TRB_IDT (1<<6) 1287 1288 /* Block Event Interrupt */ 1289 #define TRB_BEI (1<<9) 1290 1291 /* Control transfer TRB specific fields */ 1292 #define TRB_DIR_IN (1<<16) 1293 #define TRB_TX_TYPE(p) ((p) << 16) 1294 #define TRB_DATA_OUT 2 1295 #define TRB_DATA_IN 3 1296 1297 /* Isochronous TRB specific fields */ 1298 #define TRB_SIA (1<<31) 1299 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1300 1301 struct xhci_generic_trb { 1302 __le32 field[4]; 1303 }; 1304 1305 union xhci_trb { 1306 struct xhci_link_trb link; 1307 struct xhci_transfer_event trans_event; 1308 struct xhci_event_cmd event_cmd; 1309 struct xhci_generic_trb generic; 1310 }; 1311 1312 /* TRB bit mask */ 1313 #define TRB_TYPE_BITMASK (0xfc00) 1314 #define TRB_TYPE(p) ((p) << 10) 1315 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1316 /* TRB type IDs */ 1317 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1318 #define TRB_NORMAL 1 1319 /* setup stage for control transfers */ 1320 #define TRB_SETUP 2 1321 /* data stage for control transfers */ 1322 #define TRB_DATA 3 1323 /* status stage for control transfers */ 1324 #define TRB_STATUS 4 1325 /* isoc transfers */ 1326 #define TRB_ISOC 5 1327 /* TRB for linking ring segments */ 1328 #define TRB_LINK 6 1329 #define TRB_EVENT_DATA 7 1330 /* Transfer Ring No-op (not for the command ring) */ 1331 #define TRB_TR_NOOP 8 1332 /* Command TRBs */ 1333 /* Enable Slot Command */ 1334 #define TRB_ENABLE_SLOT 9 1335 /* Disable Slot Command */ 1336 #define TRB_DISABLE_SLOT 10 1337 /* Address Device Command */ 1338 #define TRB_ADDR_DEV 11 1339 /* Configure Endpoint Command */ 1340 #define TRB_CONFIG_EP 12 1341 /* Evaluate Context Command */ 1342 #define TRB_EVAL_CONTEXT 13 1343 /* Reset Endpoint Command */ 1344 #define TRB_RESET_EP 14 1345 /* Stop Transfer Ring Command */ 1346 #define TRB_STOP_RING 15 1347 /* Set Transfer Ring Dequeue Pointer Command */ 1348 #define TRB_SET_DEQ 16 1349 /* Reset Device Command */ 1350 #define TRB_RESET_DEV 17 1351 /* Force Event Command (opt) */ 1352 #define TRB_FORCE_EVENT 18 1353 /* Negotiate Bandwidth Command (opt) */ 1354 #define TRB_NEG_BANDWIDTH 19 1355 /* Set Latency Tolerance Value Command (opt) */ 1356 #define TRB_SET_LT 20 1357 /* Get port bandwidth Command */ 1358 #define TRB_GET_BW 21 1359 /* Force Header Command - generate a transaction or link management packet */ 1360 #define TRB_FORCE_HEADER 22 1361 /* No-op Command - not for transfer rings */ 1362 #define TRB_CMD_NOOP 23 1363 /* TRB IDs 24-31 reserved */ 1364 /* Event TRBS */ 1365 /* Transfer Event */ 1366 #define TRB_TRANSFER 32 1367 /* Command Completion Event */ 1368 #define TRB_COMPLETION 33 1369 /* Port Status Change Event */ 1370 #define TRB_PORT_STATUS 34 1371 /* Bandwidth Request Event (opt) */ 1372 #define TRB_BANDWIDTH_EVENT 35 1373 /* Doorbell Event (opt) */ 1374 #define TRB_DOORBELL 36 1375 /* Host Controller Event */ 1376 #define TRB_HC_EVENT 37 1377 /* Device Notification Event - device sent function wake notification */ 1378 #define TRB_DEV_NOTE 38 1379 /* MFINDEX Wrap Event - microframe counter wrapped */ 1380 #define TRB_MFINDEX_WRAP 39 1381 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1382 1383 /* Nec vendor-specific command completion event. */ 1384 #define TRB_NEC_CMD_COMP 48 1385 /* Get NEC firmware revision. */ 1386 #define TRB_NEC_GET_FW 49 1387 1388 static inline const char *xhci_trb_type_string(u8 type) 1389 { 1390 switch (type) { 1391 case TRB_NORMAL: 1392 return "Normal"; 1393 case TRB_SETUP: 1394 return "Setup Stage"; 1395 case TRB_DATA: 1396 return "Data Stage"; 1397 case TRB_STATUS: 1398 return "Status Stage"; 1399 case TRB_ISOC: 1400 return "Isoch"; 1401 case TRB_LINK: 1402 return "Link"; 1403 case TRB_EVENT_DATA: 1404 return "Event Data"; 1405 case TRB_TR_NOOP: 1406 return "No-Op"; 1407 case TRB_ENABLE_SLOT: 1408 return "Enable Slot Command"; 1409 case TRB_DISABLE_SLOT: 1410 return "Disable Slot Command"; 1411 case TRB_ADDR_DEV: 1412 return "Address Device Command"; 1413 case TRB_CONFIG_EP: 1414 return "Configure Endpoint Command"; 1415 case TRB_EVAL_CONTEXT: 1416 return "Evaluate Context Command"; 1417 case TRB_RESET_EP: 1418 return "Reset Endpoint Command"; 1419 case TRB_STOP_RING: 1420 return "Stop Ring Command"; 1421 case TRB_SET_DEQ: 1422 return "Set TR Dequeue Pointer Command"; 1423 case TRB_RESET_DEV: 1424 return "Reset Device Command"; 1425 case TRB_FORCE_EVENT: 1426 return "Force Event Command"; 1427 case TRB_NEG_BANDWIDTH: 1428 return "Negotiate Bandwidth Command"; 1429 case TRB_SET_LT: 1430 return "Set Latency Tolerance Value Command"; 1431 case TRB_GET_BW: 1432 return "Get Port Bandwidth Command"; 1433 case TRB_FORCE_HEADER: 1434 return "Force Header Command"; 1435 case TRB_CMD_NOOP: 1436 return "No-Op Command"; 1437 case TRB_TRANSFER: 1438 return "Transfer Event"; 1439 case TRB_COMPLETION: 1440 return "Command Completion Event"; 1441 case TRB_PORT_STATUS: 1442 return "Port Status Change Event"; 1443 case TRB_BANDWIDTH_EVENT: 1444 return "Bandwidth Request Event"; 1445 case TRB_DOORBELL: 1446 return "Doorbell Event"; 1447 case TRB_HC_EVENT: 1448 return "Host Controller Event"; 1449 case TRB_DEV_NOTE: 1450 return "Device Notification Event"; 1451 case TRB_MFINDEX_WRAP: 1452 return "MFINDEX Wrap Event"; 1453 case TRB_NEC_CMD_COMP: 1454 return "NEC Command Completion Event"; 1455 case TRB_NEC_GET_FW: 1456 return "NET Get Firmware Revision Command"; 1457 default: 1458 return "UNKNOWN"; 1459 } 1460 } 1461 1462 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1463 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1464 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1465 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1466 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1467 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1468 1469 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1470 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1471 1472 /* 1473 * TRBS_PER_SEGMENT must be a multiple of 4, 1474 * since the command ring is 64-byte aligned. 1475 * It must also be greater than 16. 1476 */ 1477 #define TRBS_PER_SEGMENT 256 1478 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1479 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1480 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1481 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1482 /* TRB buffer pointers can't cross 64KB boundaries */ 1483 #define TRB_MAX_BUFF_SHIFT 16 1484 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1485 /* How much data is left before the 64KB boundary? */ 1486 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1487 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1488 1489 struct xhci_segment { 1490 union xhci_trb *trbs; 1491 /* private to HCD */ 1492 struct xhci_segment *next; 1493 dma_addr_t dma; 1494 /* Max packet sized bounce buffer for td-fragmant alignment */ 1495 dma_addr_t bounce_dma; 1496 void *bounce_buf; 1497 unsigned int bounce_offs; 1498 unsigned int bounce_len; 1499 }; 1500 1501 struct xhci_td { 1502 struct list_head td_list; 1503 struct list_head cancelled_td_list; 1504 struct urb *urb; 1505 struct xhci_segment *start_seg; 1506 union xhci_trb *first_trb; 1507 union xhci_trb *last_trb; 1508 struct xhci_segment *bounce_seg; 1509 /* actual_length of the URB has already been set */ 1510 bool urb_length_set; 1511 }; 1512 1513 /* xHCI command default timeout value */ 1514 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1515 1516 /* command descriptor */ 1517 struct xhci_cd { 1518 struct xhci_command *command; 1519 union xhci_trb *cmd_trb; 1520 }; 1521 1522 struct xhci_dequeue_state { 1523 struct xhci_segment *new_deq_seg; 1524 union xhci_trb *new_deq_ptr; 1525 int new_cycle_state; 1526 }; 1527 1528 enum xhci_ring_type { 1529 TYPE_CTRL = 0, 1530 TYPE_ISOC, 1531 TYPE_BULK, 1532 TYPE_INTR, 1533 TYPE_STREAM, 1534 TYPE_COMMAND, 1535 TYPE_EVENT, 1536 }; 1537 1538 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1539 { 1540 switch (type) { 1541 case TYPE_CTRL: 1542 return "CTRL"; 1543 case TYPE_ISOC: 1544 return "ISOC"; 1545 case TYPE_BULK: 1546 return "BULK"; 1547 case TYPE_INTR: 1548 return "INTR"; 1549 case TYPE_STREAM: 1550 return "STREAM"; 1551 case TYPE_COMMAND: 1552 return "CMD"; 1553 case TYPE_EVENT: 1554 return "EVENT"; 1555 } 1556 1557 return "UNKNOWN"; 1558 } 1559 1560 struct xhci_ring { 1561 struct xhci_segment *first_seg; 1562 struct xhci_segment *last_seg; 1563 union xhci_trb *enqueue; 1564 struct xhci_segment *enq_seg; 1565 unsigned int enq_updates; 1566 union xhci_trb *dequeue; 1567 struct xhci_segment *deq_seg; 1568 unsigned int deq_updates; 1569 struct list_head td_list; 1570 /* 1571 * Write the cycle state into the TRB cycle field to give ownership of 1572 * the TRB to the host controller (if we are the producer), or to check 1573 * if we own the TRB (if we are the consumer). See section 4.9.1. 1574 */ 1575 u32 cycle_state; 1576 unsigned int stream_id; 1577 unsigned int num_segs; 1578 unsigned int num_trbs_free; 1579 unsigned int num_trbs_free_temp; 1580 unsigned int bounce_buf_len; 1581 enum xhci_ring_type type; 1582 bool last_td_was_short; 1583 struct radix_tree_root *trb_address_map; 1584 }; 1585 1586 struct xhci_erst_entry { 1587 /* 64-bit event ring segment address */ 1588 __le64 seg_addr; 1589 __le32 seg_size; 1590 /* Set to zero */ 1591 __le32 rsvd; 1592 }; 1593 1594 struct xhci_erst { 1595 struct xhci_erst_entry *entries; 1596 unsigned int num_entries; 1597 /* xhci->event_ring keeps track of segment dma addresses */ 1598 dma_addr_t erst_dma_addr; 1599 /* Num entries the ERST can contain */ 1600 unsigned int erst_size; 1601 }; 1602 1603 struct xhci_scratchpad { 1604 u64 *sp_array; 1605 dma_addr_t sp_dma; 1606 void **sp_buffers; 1607 dma_addr_t *sp_dma_buffers; 1608 }; 1609 1610 struct urb_priv { 1611 int num_tds; 1612 int num_tds_done; 1613 struct xhci_td td[0]; 1614 }; 1615 1616 /* 1617 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1618 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1619 * meaning 64 ring segments. 1620 * Initial allocated size of the ERST, in number of entries */ 1621 #define ERST_NUM_SEGS 1 1622 /* Initial allocated size of the ERST, in number of entries */ 1623 #define ERST_SIZE 64 1624 /* Initial number of event segment rings allocated */ 1625 #define ERST_ENTRIES 1 1626 /* Poll every 60 seconds */ 1627 #define POLL_TIMEOUT 60 1628 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1629 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1630 /* XXX: Make these module parameters */ 1631 1632 struct s3_save { 1633 u32 command; 1634 u32 dev_nt; 1635 u64 dcbaa_ptr; 1636 u32 config_reg; 1637 u32 irq_pending; 1638 u32 irq_control; 1639 u32 erst_size; 1640 u64 erst_base; 1641 u64 erst_dequeue; 1642 }; 1643 1644 /* Use for lpm */ 1645 struct dev_info { 1646 u32 dev_id; 1647 struct list_head list; 1648 }; 1649 1650 struct xhci_bus_state { 1651 unsigned long bus_suspended; 1652 unsigned long next_statechange; 1653 1654 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1655 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1656 u32 port_c_suspend; 1657 u32 suspended_ports; 1658 u32 port_remote_wakeup; 1659 unsigned long resume_done[USB_MAXCHILDREN]; 1660 /* which ports have started to resume */ 1661 unsigned long resuming_ports; 1662 /* Which ports are waiting on RExit to U0 transition. */ 1663 unsigned long rexit_ports; 1664 struct completion rexit_done[USB_MAXCHILDREN]; 1665 }; 1666 1667 1668 /* 1669 * It can take up to 20 ms to transition from RExit to U0 on the 1670 * Intel Lynx Point LP xHCI host. 1671 */ 1672 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1673 1674 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1675 { 1676 if (hcd->speed == HCD_USB3) 1677 return 0; 1678 else 1679 return 1; 1680 } 1681 1682 struct xhci_hub { 1683 u8 maj_rev; 1684 u8 min_rev; 1685 u32 *psi; /* array of protocol speed ID entries */ 1686 u8 psi_count; 1687 u8 psi_uid_count; 1688 }; 1689 1690 /* There is one xhci_hcd structure per controller */ 1691 struct xhci_hcd { 1692 struct usb_hcd *main_hcd; 1693 struct usb_hcd *shared_hcd; 1694 /* glue to PCI and HCD framework */ 1695 struct xhci_cap_regs __iomem *cap_regs; 1696 struct xhci_op_regs __iomem *op_regs; 1697 struct xhci_run_regs __iomem *run_regs; 1698 struct xhci_doorbell_array __iomem *dba; 1699 /* Our HCD's current interrupter register set */ 1700 struct xhci_intr_reg __iomem *ir_set; 1701 1702 /* Cached register copies of read-only HC data */ 1703 __u32 hcs_params1; 1704 __u32 hcs_params2; 1705 __u32 hcs_params3; 1706 __u32 hcc_params; 1707 __u32 hcc_params2; 1708 1709 spinlock_t lock; 1710 1711 /* packed release number */ 1712 u8 sbrn; 1713 u16 hci_version; 1714 u8 max_slots; 1715 u8 max_interrupters; 1716 u8 max_ports; 1717 u8 isoc_threshold; 1718 int event_ring_max; 1719 /* 4KB min, 128MB max */ 1720 int page_size; 1721 /* Valid values are 12 to 20, inclusive */ 1722 int page_shift; 1723 /* msi-x vectors */ 1724 int msix_count; 1725 struct msix_entry *msix_entries; 1726 /* optional clock */ 1727 struct clk *clk; 1728 /* data structures */ 1729 struct xhci_device_context_array *dcbaa; 1730 struct xhci_ring *cmd_ring; 1731 unsigned int cmd_ring_state; 1732 #define CMD_RING_STATE_RUNNING (1 << 0) 1733 #define CMD_RING_STATE_ABORTED (1 << 1) 1734 #define CMD_RING_STATE_STOPPED (1 << 2) 1735 struct list_head cmd_list; 1736 unsigned int cmd_ring_reserved_trbs; 1737 struct delayed_work cmd_timer; 1738 struct completion cmd_ring_stop_completion; 1739 struct xhci_command *current_cmd; 1740 struct xhci_ring *event_ring; 1741 struct xhci_erst erst; 1742 /* Scratchpad */ 1743 struct xhci_scratchpad *scratchpad; 1744 /* Store LPM test failed devices' information */ 1745 struct list_head lpm_failed_devs; 1746 1747 /* slot enabling and address device helpers */ 1748 /* these are not thread safe so use mutex */ 1749 struct mutex mutex; 1750 /* For USB 3.0 LPM enable/disable. */ 1751 struct xhci_command *lpm_command; 1752 /* Internal mirror of the HW's dcbaa */ 1753 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1754 /* For keeping track of bandwidth domains per roothub. */ 1755 struct xhci_root_port_bw_info *rh_bw; 1756 1757 /* DMA pools */ 1758 struct dma_pool *device_pool; 1759 struct dma_pool *segment_pool; 1760 struct dma_pool *small_streams_pool; 1761 struct dma_pool *medium_streams_pool; 1762 1763 /* Host controller watchdog timer structures */ 1764 unsigned int xhc_state; 1765 1766 u32 command; 1767 struct s3_save s3; 1768 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1769 * 1770 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1771 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1772 * that sees this status (other than the timer that set it) should stop touching 1773 * hardware immediately. Interrupt handlers should return immediately when 1774 * they see this status (any time they drop and re-acquire xhci->lock). 1775 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1776 * putting the TD on the canceled list, etc. 1777 * 1778 * There are no reports of xHCI host controllers that display this issue. 1779 */ 1780 #define XHCI_STATE_DYING (1 << 0) 1781 #define XHCI_STATE_HALTED (1 << 1) 1782 #define XHCI_STATE_REMOVING (1 << 2) 1783 unsigned int quirks; 1784 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1785 #define XHCI_RESET_EP_QUIRK (1 << 1) 1786 #define XHCI_NEC_HOST (1 << 2) 1787 #define XHCI_AMD_PLL_FIX (1 << 3) 1788 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1789 /* 1790 * Certain Intel host controllers have a limit to the number of endpoint 1791 * contexts they can handle. Ideally, they would signal that they can't handle 1792 * anymore endpoint contexts by returning a Resource Error for the Configure 1793 * Endpoint command, but they don't. Instead they expect software to keep track 1794 * of the number of active endpoints for them, across configure endpoint 1795 * commands, reset device commands, disable slot commands, and address device 1796 * commands. 1797 */ 1798 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1799 #define XHCI_BROKEN_MSI (1 << 6) 1800 #define XHCI_RESET_ON_RESUME (1 << 7) 1801 #define XHCI_SW_BW_CHECKING (1 << 8) 1802 #define XHCI_AMD_0x96_HOST (1 << 9) 1803 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1804 #define XHCI_LPM_SUPPORT (1 << 11) 1805 #define XHCI_INTEL_HOST (1 << 12) 1806 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1807 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1808 #define XHCI_AVOID_BEI (1 << 15) 1809 #define XHCI_PLAT (1 << 16) 1810 #define XHCI_SLOW_SUSPEND (1 << 17) 1811 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1812 /* For controllers with a broken beyond repair streams implementation */ 1813 #define XHCI_BROKEN_STREAMS (1 << 19) 1814 #define XHCI_PME_STUCK_QUIRK (1 << 20) 1815 #define XHCI_MTK_HOST (1 << 21) 1816 #define XHCI_SSIC_PORT_UNUSED (1 << 22) 1817 #define XHCI_NO_64BIT_SUPPORT (1 << 23) 1818 #define XHCI_MISSING_CAS (1 << 24) 1819 /* For controller with a broken Port Disable implementation */ 1820 #define XHCI_BROKEN_PORT_PED (1 << 25) 1821 1822 unsigned int num_active_eps; 1823 unsigned int limit_active_eps; 1824 /* There are two roothubs to keep track of bus suspend info for */ 1825 struct xhci_bus_state bus_state[2]; 1826 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1827 u8 *port_array; 1828 /* Array of pointers to USB 3.0 PORTSC registers */ 1829 __le32 __iomem **usb3_ports; 1830 unsigned int num_usb3_ports; 1831 /* Array of pointers to USB 2.0 PORTSC registers */ 1832 __le32 __iomem **usb2_ports; 1833 struct xhci_hub usb2_rhub; 1834 struct xhci_hub usb3_rhub; 1835 unsigned int num_usb2_ports; 1836 /* support xHCI 0.96 spec USB2 software LPM */ 1837 unsigned sw_lpm_support:1; 1838 /* support xHCI 1.0 spec USB2 hardware LPM */ 1839 unsigned hw_lpm_support:1; 1840 /* cached usb2 extened protocol capabilites */ 1841 u32 *ext_caps; 1842 unsigned int num_ext_caps; 1843 /* Compliance Mode Recovery Data */ 1844 struct timer_list comp_mode_recovery_timer; 1845 u32 port_status_u0; 1846 /* Compliance Mode Timer Triggered every 2 seconds */ 1847 #define COMP_MODE_RCVRY_MSECS 2000 1848 1849 /* platform-specific data -- must come last */ 1850 unsigned long priv[0] __aligned(sizeof(s64)); 1851 }; 1852 1853 /* Platform specific overrides to generic XHCI hc_driver ops */ 1854 struct xhci_driver_overrides { 1855 size_t extra_priv_size; 1856 int (*reset)(struct usb_hcd *hcd); 1857 int (*start)(struct usb_hcd *hcd); 1858 }; 1859 1860 #define XHCI_CFC_DELAY 10 1861 1862 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1863 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1864 { 1865 struct usb_hcd *primary_hcd; 1866 1867 if (usb_hcd_is_primary_hcd(hcd)) 1868 primary_hcd = hcd; 1869 else 1870 primary_hcd = hcd->primary_hcd; 1871 1872 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1873 } 1874 1875 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1876 { 1877 return xhci->main_hcd; 1878 } 1879 1880 #define xhci_dbg(xhci, fmt, args...) \ 1881 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1882 #define xhci_err(xhci, fmt, args...) \ 1883 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1884 #define xhci_warn(xhci, fmt, args...) \ 1885 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1886 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1887 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1888 #define xhci_info(xhci, fmt, args...) \ 1889 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1890 1891 /* 1892 * Registers should always be accessed with double word or quad word accesses. 1893 * 1894 * Some xHCI implementations may support 64-bit address pointers. Registers 1895 * with 64-bit address pointers should be written to with dword accesses by 1896 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1897 * xHCI implementations that do not support 64-bit address pointers will ignore 1898 * the high dword, and write order is irrelevant. 1899 */ 1900 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1901 __le64 __iomem *regs) 1902 { 1903 return lo_hi_readq(regs); 1904 } 1905 static inline void xhci_write_64(struct xhci_hcd *xhci, 1906 const u64 val, __le64 __iomem *regs) 1907 { 1908 lo_hi_writeq(val, regs); 1909 } 1910 1911 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1912 { 1913 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1914 } 1915 1916 /* xHCI debugging */ 1917 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1918 void xhci_print_registers(struct xhci_hcd *xhci); 1919 void xhci_dbg_regs(struct xhci_hcd *xhci); 1920 void xhci_print_run_regs(struct xhci_hcd *xhci); 1921 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1922 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1923 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1924 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1925 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1926 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1927 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1928 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1929 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1930 struct xhci_container_ctx *ctx); 1931 void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1932 unsigned int slot_id, unsigned int ep_index, 1933 struct xhci_virt_ep *ep); 1934 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1935 const char *fmt, ...); 1936 1937 /* xHCI memory management */ 1938 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1939 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1940 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1941 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1942 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1943 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1944 struct usb_device *udev); 1945 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1946 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1947 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1948 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1949 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1950 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1951 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1952 struct xhci_bw_info *ep_bw, 1953 struct xhci_interval_bw_table *bw_table, 1954 struct usb_device *udev, 1955 struct xhci_virt_ep *virt_ep, 1956 struct xhci_tt_bw_info *tt_info); 1957 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1958 struct xhci_virt_device *virt_dev, 1959 int old_active_eps); 1960 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1961 void xhci_update_bw_info(struct xhci_hcd *xhci, 1962 struct xhci_container_ctx *in_ctx, 1963 struct xhci_input_control_ctx *ctrl_ctx, 1964 struct xhci_virt_device *virt_dev); 1965 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1966 struct xhci_container_ctx *in_ctx, 1967 struct xhci_container_ctx *out_ctx, 1968 unsigned int ep_index); 1969 void xhci_slot_copy(struct xhci_hcd *xhci, 1970 struct xhci_container_ctx *in_ctx, 1971 struct xhci_container_ctx *out_ctx); 1972 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1973 struct usb_device *udev, struct usb_host_endpoint *ep, 1974 gfp_t mem_flags); 1975 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1976 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1977 unsigned int num_trbs, gfp_t flags); 1978 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1979 struct xhci_virt_device *virt_dev, 1980 unsigned int ep_index); 1981 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1982 unsigned int num_stream_ctxs, 1983 unsigned int num_streams, 1984 unsigned int max_packet, gfp_t flags); 1985 void xhci_free_stream_info(struct xhci_hcd *xhci, 1986 struct xhci_stream_info *stream_info); 1987 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1988 struct xhci_ep_ctx *ep_ctx, 1989 struct xhci_stream_info *stream_info); 1990 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1991 struct xhci_virt_ep *ep); 1992 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1993 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1994 struct xhci_ring *xhci_dma_to_transfer_ring( 1995 struct xhci_virt_ep *ep, 1996 u64 address); 1997 struct xhci_ring *xhci_stream_id_to_ring( 1998 struct xhci_virt_device *dev, 1999 unsigned int ep_index, 2000 unsigned int stream_id); 2001 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 2002 bool allocate_in_ctx, bool allocate_completion, 2003 gfp_t mem_flags); 2004 void xhci_urb_free_priv(struct urb_priv *urb_priv); 2005 void xhci_free_command(struct xhci_hcd *xhci, 2006 struct xhci_command *command); 2007 2008 /* xHCI host controller glue */ 2009 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 2010 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 2011 void xhci_quiesce(struct xhci_hcd *xhci); 2012 int xhci_halt(struct xhci_hcd *xhci); 2013 int xhci_reset(struct xhci_hcd *xhci); 2014 int xhci_init(struct usb_hcd *hcd); 2015 int xhci_run(struct usb_hcd *hcd); 2016 void xhci_stop(struct usb_hcd *hcd); 2017 void xhci_shutdown(struct usb_hcd *hcd); 2018 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2019 void xhci_init_driver(struct hc_driver *drv, 2020 const struct xhci_driver_overrides *over); 2021 2022 #ifdef CONFIG_PM 2023 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2024 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 2025 #else 2026 #define xhci_suspend NULL 2027 #define xhci_resume NULL 2028 #endif 2029 2030 int xhci_get_frame(struct usb_hcd *hcd); 2031 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2032 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2033 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2034 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 2035 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2036 struct xhci_virt_device *virt_dev, 2037 struct usb_device *hdev, 2038 struct usb_tt *tt, gfp_t mem_flags); 2039 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 2040 struct usb_host_endpoint **eps, unsigned int num_eps, 2041 unsigned int num_streams, gfp_t mem_flags); 2042 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 2043 struct usb_host_endpoint **eps, unsigned int num_eps, 2044 gfp_t mem_flags); 2045 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 2046 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); 2047 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 2048 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 2049 struct usb_device *udev, int enable); 2050 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 2051 struct usb_tt *tt, gfp_t mem_flags); 2052 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 2053 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 2054 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 2055 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 2056 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 2057 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 2058 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2059 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 2060 2061 /* xHCI ring, segment, TRB, and TD functions */ 2062 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2063 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2064 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2065 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2066 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2067 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2068 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2069 u32 trb_type, u32 slot_id); 2070 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2071 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2072 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2073 u32 field1, u32 field2, u32 field3, u32 field4); 2074 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2075 int slot_id, unsigned int ep_index, int suspend); 2076 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2077 int slot_id, unsigned int ep_index); 2078 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2079 int slot_id, unsigned int ep_index); 2080 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2081 int slot_id, unsigned int ep_index); 2082 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2083 struct urb *urb, int slot_id, unsigned int ep_index); 2084 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2085 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2086 bool command_must_succeed); 2087 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2088 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2089 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2090 int slot_id, unsigned int ep_index); 2091 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2092 u32 slot_id); 2093 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 2094 unsigned int slot_id, unsigned int ep_index, 2095 unsigned int stream_id, struct xhci_td *cur_td, 2096 struct xhci_dequeue_state *state); 2097 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 2098 unsigned int slot_id, unsigned int ep_index, 2099 unsigned int stream_id, 2100 struct xhci_dequeue_state *deq_state); 2101 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 2102 unsigned int ep_index, struct xhci_td *td); 2103 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 2104 unsigned int slot_id, unsigned int ep_index, 2105 struct xhci_dequeue_state *deq_state); 2106 void xhci_stop_endpoint_command_watchdog(unsigned long arg); 2107 void xhci_handle_command_timeout(struct work_struct *work); 2108 2109 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2110 unsigned int ep_index, unsigned int stream_id); 2111 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2112 2113 /* xHCI roothub code */ 2114 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2115 int port_id, u32 link_state); 2116 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, 2117 struct usb_device *udev, enum usb3_link_state state); 2118 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, 2119 struct usb_device *udev, enum usb3_link_state state); 2120 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2121 int port_id, u32 port_bit); 2122 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2123 char *buf, u16 wLength); 2124 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2125 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2126 2127 #ifdef CONFIG_PM 2128 int xhci_bus_suspend(struct usb_hcd *hcd); 2129 int xhci_bus_resume(struct usb_hcd *hcd); 2130 #else 2131 #define xhci_bus_suspend NULL 2132 #define xhci_bus_resume NULL 2133 #endif /* CONFIG_PM */ 2134 2135 u32 xhci_port_state_to_neutral(u32 state); 2136 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2137 u16 port); 2138 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2139 2140 /* xHCI contexts */ 2141 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2142 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2143 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2144 2145 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2146 unsigned int slot_id, unsigned int ep_index, 2147 unsigned int stream_id); 2148 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2149 struct urb *urb) 2150 { 2151 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2152 xhci_get_endpoint_index(&urb->ep->desc), 2153 urb->stream_id); 2154 } 2155 2156 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, 2157 u32 field3) 2158 { 2159 static char str[256]; 2160 int type = TRB_FIELD_TO_TYPE(field3); 2161 2162 switch (type) { 2163 case TRB_LINK: 2164 sprintf(str, 2165 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2166 field1, field0, 2167 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2168 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2169 /* Macro decrements 1, maybe it shouldn't?!? */ 2170 TRB_TO_EP_INDEX(field3) + 1, 2171 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2172 field3 & EVENT_DATA ? 'E' : 'e', 2173 field3 & TRB_CYCLE ? 'C' : 'c'); 2174 break; 2175 case TRB_TRANSFER: 2176 case TRB_COMPLETION: 2177 case TRB_PORT_STATUS: 2178 case TRB_BANDWIDTH_EVENT: 2179 case TRB_DOORBELL: 2180 case TRB_HC_EVENT: 2181 case TRB_DEV_NOTE: 2182 case TRB_MFINDEX_WRAP: 2183 sprintf(str, 2184 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2185 field1, field0, 2186 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2187 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2188 /* Macro decrements 1, maybe it shouldn't?!? */ 2189 TRB_TO_EP_INDEX(field3) + 1, 2190 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2191 field3 & EVENT_DATA ? 'E' : 'e', 2192 field3 & TRB_CYCLE ? 'C' : 'c'); 2193 2194 break; 2195 case TRB_SETUP: 2196 sprintf(str, 2197 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2198 field0 & 0xff, 2199 (field0 & 0xff00) >> 8, 2200 (field0 & 0xff000000) >> 24, 2201 (field0 & 0xff0000) >> 16, 2202 (field1 & 0xff00) >> 8, 2203 field1 & 0xff, 2204 (field1 & 0xff000000) >> 16 | 2205 (field1 & 0xff0000) >> 16, 2206 TRB_LEN(field2), GET_TD_SIZE(field2), 2207 GET_INTR_TARGET(field2), 2208 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2209 field3 & TRB_BEI ? 'B' : 'b', 2210 field3 & TRB_IDT ? 'I' : 'i', 2211 field3 & TRB_IOC ? 'I' : 'i', 2212 field3 & TRB_CHAIN ? 'C' : 'c', 2213 field3 & TRB_NO_SNOOP ? 'S' : 's', 2214 field3 & TRB_ISP ? 'I' : 'i', 2215 field3 & TRB_ENT ? 'E' : 'e', 2216 field3 & TRB_CYCLE ? 'C' : 'c'); 2217 break; 2218 case TRB_NORMAL: 2219 case TRB_DATA: 2220 case TRB_STATUS: 2221 case TRB_ISOC: 2222 case TRB_EVENT_DATA: 2223 case TRB_TR_NOOP: 2224 sprintf(str, 2225 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2226 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2227 GET_INTR_TARGET(field2), 2228 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2229 field3 & TRB_BEI ? 'B' : 'b', 2230 field3 & TRB_IDT ? 'I' : 'i', 2231 field3 & TRB_IOC ? 'I' : 'i', 2232 field3 & TRB_CHAIN ? 'C' : 'c', 2233 field3 & TRB_NO_SNOOP ? 'S' : 's', 2234 field3 & TRB_ISP ? 'I' : 'i', 2235 field3 & TRB_ENT ? 'E' : 'e', 2236 field3 & TRB_CYCLE ? 'C' : 'c'); 2237 break; 2238 2239 case TRB_CMD_NOOP: 2240 case TRB_ENABLE_SLOT: 2241 sprintf(str, 2242 "%s: flags %c", 2243 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2244 field3 & TRB_CYCLE ? 'C' : 'c'); 2245 break; 2246 case TRB_DISABLE_SLOT: 2247 case TRB_NEG_BANDWIDTH: 2248 sprintf(str, 2249 "%s: slot %d flags %c", 2250 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2251 TRB_TO_SLOT_ID(field3), 2252 field3 & TRB_CYCLE ? 'C' : 'c'); 2253 break; 2254 case TRB_ADDR_DEV: 2255 sprintf(str, 2256 "%s: ctx %08x%08x slot %d flags %c:%c", 2257 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2258 field1, field0, 2259 TRB_TO_SLOT_ID(field3), 2260 field3 & TRB_BSR ? 'B' : 'b', 2261 field3 & TRB_CYCLE ? 'C' : 'c'); 2262 break; 2263 case TRB_CONFIG_EP: 2264 sprintf(str, 2265 "%s: ctx %08x%08x slot %d flags %c:%c", 2266 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2267 field1, field0, 2268 TRB_TO_SLOT_ID(field3), 2269 field3 & TRB_DC ? 'D' : 'd', 2270 field3 & TRB_CYCLE ? 'C' : 'c'); 2271 break; 2272 case TRB_EVAL_CONTEXT: 2273 sprintf(str, 2274 "%s: ctx %08x%08x slot %d flags %c", 2275 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2276 field1, field0, 2277 TRB_TO_SLOT_ID(field3), 2278 field3 & TRB_CYCLE ? 'C' : 'c'); 2279 break; 2280 case TRB_RESET_EP: 2281 sprintf(str, 2282 "%s: ctx %08x%08x slot %d ep %d flags %c", 2283 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2284 field1, field0, 2285 TRB_TO_SLOT_ID(field3), 2286 /* Macro decrements 1, maybe it shouldn't?!? */ 2287 TRB_TO_EP_INDEX(field3) + 1, 2288 field3 & TRB_CYCLE ? 'C' : 'c'); 2289 break; 2290 case TRB_STOP_RING: 2291 sprintf(str, 2292 "%s: slot %d sp %d ep %d flags %c", 2293 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2294 TRB_TO_SLOT_ID(field3), 2295 TRB_TO_SUSPEND_PORT(field3), 2296 /* Macro decrements 1, maybe it shouldn't?!? */ 2297 TRB_TO_EP_INDEX(field3) + 1, 2298 field3 & TRB_CYCLE ? 'C' : 'c'); 2299 break; 2300 case TRB_SET_DEQ: 2301 sprintf(str, 2302 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2303 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2304 field1, field0, 2305 TRB_TO_STREAM_ID(field2), 2306 TRB_TO_SLOT_ID(field3), 2307 /* Macro decrements 1, maybe it shouldn't?!? */ 2308 TRB_TO_EP_INDEX(field3) + 1, 2309 field3 & TRB_CYCLE ? 'C' : 'c'); 2310 break; 2311 case TRB_RESET_DEV: 2312 sprintf(str, 2313 "%s: slot %d flags %c", 2314 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2315 TRB_TO_SLOT_ID(field3), 2316 field3 & TRB_CYCLE ? 'C' : 'c'); 2317 break; 2318 case TRB_FORCE_EVENT: 2319 sprintf(str, 2320 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2321 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2322 field1, field0, 2323 TRB_TO_VF_INTR_TARGET(field2), 2324 TRB_TO_VF_ID(field3), 2325 field3 & TRB_CYCLE ? 'C' : 'c'); 2326 break; 2327 case TRB_SET_LT: 2328 sprintf(str, 2329 "%s: belt %d flags %c", 2330 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2331 TRB_TO_BELT(field3), 2332 field3 & TRB_CYCLE ? 'C' : 'c'); 2333 break; 2334 case TRB_GET_BW: 2335 sprintf(str, 2336 "%s: ctx %08x%08x slot %d speed %d flags %c", 2337 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2338 field1, field0, 2339 TRB_TO_SLOT_ID(field3), 2340 TRB_TO_DEV_SPEED(field3), 2341 field3 & TRB_CYCLE ? 'C' : 'c'); 2342 break; 2343 case TRB_FORCE_HEADER: 2344 sprintf(str, 2345 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2346 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2347 field2, field1, field0 & 0xffffffe0, 2348 TRB_TO_PACKET_TYPE(field0), 2349 TRB_TO_ROOTHUB_PORT(field3), 2350 field3 & TRB_CYCLE ? 'C' : 'c'); 2351 break; 2352 default: 2353 sprintf(str, 2354 "type '%s' -> raw %08x %08x %08x %08x", 2355 xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), 2356 field0, field1, field2, field3); 2357 } 2358 2359 return str; 2360 } 2361 2362 2363 #endif /* __LINUX_XHCI_HCD_H */ 2364