1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVIDIA Tegra xHCI host controller driver 4 * 5 * Copyright (C) 2014 NVIDIA Corporation 6 * Copyright (C) 2014 Google, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/firmware.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/phy/phy.h> 18 #include <linux/phy/tegra/xusb.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/pm_domain.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/reset.h> 25 #include <linux/slab.h> 26 #include <soc/tegra/pmc.h> 27 28 #include "xhci.h" 29 30 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 31 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 32 33 /* FPCI CFG registers */ 34 #define XUSB_CFG_1 0x004 35 #define XUSB_IO_SPACE_EN BIT(0) 36 #define XUSB_MEM_SPACE_EN BIT(1) 37 #define XUSB_BUS_MASTER_EN BIT(2) 38 #define XUSB_CFG_4 0x010 39 #define XUSB_BASE_ADDR_SHIFT 15 40 #define XUSB_BASE_ADDR_MASK 0x1ffff 41 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c 42 #define XUSB_CFG_CSB_BASE_ADDR 0x800 43 44 /* FPCI mailbox registers */ 45 #define XUSB_CFG_ARU_MBOX_CMD 0x0e4 46 #define MBOX_DEST_FALC BIT(27) 47 #define MBOX_DEST_PME BIT(28) 48 #define MBOX_DEST_SMI BIT(29) 49 #define MBOX_DEST_XHCI BIT(30) 50 #define MBOX_INT_EN BIT(31) 51 #define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8 52 #define CMD_DATA_SHIFT 0 53 #define CMD_DATA_MASK 0xffffff 54 #define CMD_TYPE_SHIFT 24 55 #define CMD_TYPE_MASK 0xff 56 #define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec 57 #define XUSB_CFG_ARU_MBOX_OWNER 0x0f0 58 #define MBOX_OWNER_NONE 0 59 #define MBOX_OWNER_FW 1 60 #define MBOX_OWNER_SW 2 61 #define XUSB_CFG_ARU_SMI_INTR 0x428 62 #define MBOX_SMI_INTR_FW_HANG BIT(1) 63 #define MBOX_SMI_INTR_EN BIT(3) 64 65 /* IPFS registers */ 66 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 67 #define IPFS_EN_FPCI BIT(0) 68 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188 69 #define IPFS_IP_INT_MASK BIT(16) 70 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc 71 72 #define CSB_PAGE_SELECT_MASK 0x7fffff 73 #define CSB_PAGE_SELECT_SHIFT 9 74 #define CSB_PAGE_OFFSET_MASK 0x1ff 75 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ 76 CSB_PAGE_SELECT_MASK) 77 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) 78 79 /* Falcon CSB registers */ 80 #define XUSB_FALC_CPUCTL 0x100 81 #define CPUCTL_STARTCPU BIT(1) 82 #define CPUCTL_STATE_HALTED BIT(4) 83 #define CPUCTL_STATE_STOPPED BIT(5) 84 #define XUSB_FALC_BOOTVEC 0x104 85 #define XUSB_FALC_DMACTL 0x10c 86 #define XUSB_FALC_IMFILLRNG1 0x154 87 #define IMFILLRNG1_TAG_MASK 0xffff 88 #define IMFILLRNG1_TAG_LO_SHIFT 0 89 #define IMFILLRNG1_TAG_HI_SHIFT 16 90 #define XUSB_FALC_IMFILLCTL 0x158 91 92 /* MP CSB registers */ 93 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 94 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 95 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 96 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 97 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 98 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff 99 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 100 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff 101 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 102 #define L2IMEMOP_ACTION_SHIFT 24 103 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) 104 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) 105 #define XUSB_CSB_MP_APMAP 0x10181c 106 #define APMAP_BOOTPATH BIT(31) 107 108 #define IMEM_BLOCK_SIZE 256 109 110 struct tegra_xusb_fw_header { 111 __le32 boot_loadaddr_in_imem; 112 __le32 boot_codedfi_offset; 113 __le32 boot_codetag; 114 __le32 boot_codesize; 115 __le32 phys_memaddr; 116 __le16 reqphys_memsize; 117 __le16 alloc_phys_memsize; 118 __le32 rodata_img_offset; 119 __le32 rodata_section_start; 120 __le32 rodata_section_end; 121 __le32 main_fnaddr; 122 __le32 fwimg_cksum; 123 __le32 fwimg_created_time; 124 __le32 imem_resident_start; 125 __le32 imem_resident_end; 126 __le32 idirect_start; 127 __le32 idirect_end; 128 __le32 l2_imem_start; 129 __le32 l2_imem_end; 130 __le32 version_id; 131 u8 init_ddirect; 132 u8 reserved[3]; 133 __le32 phys_addr_log_buffer; 134 __le32 total_log_entries; 135 __le32 dequeue_ptr; 136 __le32 dummy_var[2]; 137 __le32 fwimg_len; 138 u8 magic[8]; 139 __le32 ss_low_power_entry_timeout; 140 u8 num_hsic_port; 141 u8 padding[139]; /* Pad to 256 bytes */ 142 }; 143 144 struct tegra_xusb_phy_type { 145 const char *name; 146 unsigned int num; 147 }; 148 149 struct tegra_xusb_soc { 150 const char *firmware; 151 const char * const *supply_names; 152 unsigned int num_supplies; 153 const struct tegra_xusb_phy_type *phy_types; 154 unsigned int num_types; 155 156 struct { 157 struct { 158 unsigned int offset; 159 unsigned int count; 160 } usb2, ulpi, hsic, usb3; 161 } ports; 162 163 bool scale_ss_clock; 164 bool has_ipfs; 165 }; 166 167 struct tegra_xusb { 168 struct device *dev; 169 void __iomem *regs; 170 struct usb_hcd *hcd; 171 172 struct mutex lock; 173 174 int xhci_irq; 175 int mbox_irq; 176 177 void __iomem *ipfs_base; 178 void __iomem *fpci_base; 179 180 const struct tegra_xusb_soc *soc; 181 182 struct regulator_bulk_data *supplies; 183 184 struct tegra_xusb_padctl *padctl; 185 186 struct clk *host_clk; 187 struct clk *falcon_clk; 188 struct clk *ss_clk; 189 struct clk *ss_src_clk; 190 struct clk *hs_src_clk; 191 struct clk *fs_src_clk; 192 struct clk *pll_u_480m; 193 struct clk *clk_m; 194 struct clk *pll_e; 195 196 struct reset_control *host_rst; 197 struct reset_control *ss_rst; 198 199 struct device *genpd_dev_host; 200 struct device *genpd_dev_ss; 201 struct device_link *genpd_dl_host; 202 struct device_link *genpd_dl_ss; 203 204 struct phy **phys; 205 unsigned int num_phys; 206 207 /* Firmware loading related */ 208 struct { 209 size_t size; 210 void *virt; 211 dma_addr_t phys; 212 } fw; 213 }; 214 215 static struct hc_driver __read_mostly tegra_xhci_hc_driver; 216 217 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) 218 { 219 return readl(tegra->fpci_base + offset); 220 } 221 222 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, 223 unsigned int offset) 224 { 225 writel(value, tegra->fpci_base + offset); 226 } 227 228 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) 229 { 230 return readl(tegra->ipfs_base + offset); 231 } 232 233 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, 234 unsigned int offset) 235 { 236 writel(value, tegra->ipfs_base + offset); 237 } 238 239 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) 240 { 241 u32 page = CSB_PAGE_SELECT(offset); 242 u32 ofs = CSB_PAGE_OFFSET(offset); 243 244 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 245 246 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); 247 } 248 249 static void csb_writel(struct tegra_xusb *tegra, u32 value, 250 unsigned int offset) 251 { 252 u32 page = CSB_PAGE_SELECT(offset); 253 u32 ofs = CSB_PAGE_OFFSET(offset); 254 255 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 256 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); 257 } 258 259 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, 260 unsigned long rate) 261 { 262 unsigned long new_parent_rate, old_parent_rate; 263 struct clk *clk = tegra->ss_src_clk; 264 unsigned int div; 265 int err; 266 267 if (clk_get_rate(clk) == rate) 268 return 0; 269 270 switch (rate) { 271 case TEGRA_XHCI_SS_HIGH_SPEED: 272 /* 273 * Reparent to PLLU_480M. Set divider first to avoid 274 * overclocking. 275 */ 276 old_parent_rate = clk_get_rate(clk_get_parent(clk)); 277 new_parent_rate = clk_get_rate(tegra->pll_u_480m); 278 div = new_parent_rate / rate; 279 280 err = clk_set_rate(clk, old_parent_rate / div); 281 if (err) 282 return err; 283 284 err = clk_set_parent(clk, tegra->pll_u_480m); 285 if (err) 286 return err; 287 288 /* 289 * The rate should already be correct, but set it again just 290 * to be sure. 291 */ 292 err = clk_set_rate(clk, rate); 293 if (err) 294 return err; 295 296 break; 297 298 case TEGRA_XHCI_SS_LOW_SPEED: 299 /* Reparent to CLK_M */ 300 err = clk_set_parent(clk, tegra->clk_m); 301 if (err) 302 return err; 303 304 err = clk_set_rate(clk, rate); 305 if (err) 306 return err; 307 308 break; 309 310 default: 311 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); 312 return -EINVAL; 313 } 314 315 if (clk_get_rate(clk) != rate) { 316 dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); 317 return -EINVAL; 318 } 319 320 return 0; 321 } 322 323 static unsigned long extract_field(u32 value, unsigned int start, 324 unsigned int count) 325 { 326 return (value >> start) & ((1 << count) - 1); 327 } 328 329 /* Command requests from the firmware */ 330 enum tegra_xusb_mbox_cmd { 331 MBOX_CMD_MSG_ENABLED = 1, 332 MBOX_CMD_INC_FALC_CLOCK, 333 MBOX_CMD_DEC_FALC_CLOCK, 334 MBOX_CMD_INC_SSPI_CLOCK, 335 MBOX_CMD_DEC_SSPI_CLOCK, 336 MBOX_CMD_SET_BW, /* no ACK/NAK required */ 337 MBOX_CMD_SET_SS_PWR_GATING, 338 MBOX_CMD_SET_SS_PWR_UNGATING, 339 MBOX_CMD_SAVE_DFE_CTLE_CTX, 340 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ 341 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ 342 MBOX_CMD_START_HSIC_IDLE, 343 MBOX_CMD_STOP_HSIC_IDLE, 344 MBOX_CMD_DBC_WAKE_STACK, /* unused */ 345 MBOX_CMD_HSIC_PRETEND_CONNECT, 346 MBOX_CMD_RESET_SSPI, 347 MBOX_CMD_DISABLE_SS_LFPS_DETECTION, 348 MBOX_CMD_ENABLE_SS_LFPS_DETECTION, 349 350 MBOX_CMD_MAX, 351 352 /* Response message to above commands */ 353 MBOX_CMD_ACK = 128, 354 MBOX_CMD_NAK 355 }; 356 357 static const char * const mbox_cmd_name[] = { 358 [ 1] = "MSG_ENABLE", 359 [ 2] = "INC_FALCON_CLOCK", 360 [ 3] = "DEC_FALCON_CLOCK", 361 [ 4] = "INC_SSPI_CLOCK", 362 [ 5] = "DEC_SSPI_CLOCK", 363 [ 6] = "SET_BW", 364 [ 7] = "SET_SS_PWR_GATING", 365 [ 8] = "SET_SS_PWR_UNGATING", 366 [ 9] = "SAVE_DFE_CTLE_CTX", 367 [ 10] = "AIRPLANE_MODE_ENABLED", 368 [ 11] = "AIRPLANE_MODE_DISABLED", 369 [ 12] = "START_HSIC_IDLE", 370 [ 13] = "STOP_HSIC_IDLE", 371 [ 14] = "DBC_WAKE_STACK", 372 [ 15] = "HSIC_PRETEND_CONNECT", 373 [ 16] = "RESET_SSPI", 374 [ 17] = "DISABLE_SS_LFPS_DETECTION", 375 [ 18] = "ENABLE_SS_LFPS_DETECTION", 376 [128] = "ACK", 377 [129] = "NAK", 378 }; 379 380 struct tegra_xusb_mbox_msg { 381 u32 cmd; 382 u32 data; 383 }; 384 385 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) 386 { 387 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | 388 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; 389 } 390 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, 391 u32 value) 392 { 393 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; 394 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; 395 } 396 397 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) 398 { 399 switch (cmd) { 400 case MBOX_CMD_SET_BW: 401 case MBOX_CMD_ACK: 402 case MBOX_CMD_NAK: 403 return false; 404 405 default: 406 return true; 407 } 408 } 409 410 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, 411 const struct tegra_xusb_mbox_msg *msg) 412 { 413 bool wait_for_idle = false; 414 u32 value; 415 416 /* 417 * Acquire the mailbox. The firmware still owns the mailbox for 418 * ACK/NAK messages. 419 */ 420 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { 421 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 422 if (value != MBOX_OWNER_NONE) { 423 dev_err(tegra->dev, "mailbox is busy\n"); 424 return -EBUSY; 425 } 426 427 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER); 428 429 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 430 if (value != MBOX_OWNER_SW) { 431 dev_err(tegra->dev, "failed to acquire mailbox\n"); 432 return -EBUSY; 433 } 434 435 wait_for_idle = true; 436 } 437 438 value = tegra_xusb_mbox_pack(msg); 439 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN); 440 441 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); 442 value |= MBOX_INT_EN | MBOX_DEST_FALC; 443 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); 444 445 if (wait_for_idle) { 446 unsigned long timeout = jiffies + msecs_to_jiffies(250); 447 448 while (time_before(jiffies, timeout)) { 449 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 450 if (value == MBOX_OWNER_NONE) 451 break; 452 453 usleep_range(10, 20); 454 } 455 456 if (time_after(jiffies, timeout)) 457 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); 458 459 if (value != MBOX_OWNER_NONE) 460 return -ETIMEDOUT; 461 } 462 463 return 0; 464 } 465 466 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) 467 { 468 struct tegra_xusb *tegra = data; 469 u32 value; 470 471 /* clear mailbox interrupts */ 472 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); 473 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); 474 475 if (value & MBOX_SMI_INTR_FW_HANG) 476 dev_err(tegra->dev, "controller firmware hang\n"); 477 478 return IRQ_WAKE_THREAD; 479 } 480 481 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, 482 const struct tegra_xusb_mbox_msg *msg) 483 { 484 struct tegra_xusb_padctl *padctl = tegra->padctl; 485 const struct tegra_xusb_soc *soc = tegra->soc; 486 struct device *dev = tegra->dev; 487 struct tegra_xusb_mbox_msg rsp; 488 unsigned long mask; 489 unsigned int port; 490 bool idle, enable; 491 int err = 0; 492 493 memset(&rsp, 0, sizeof(rsp)); 494 495 switch (msg->cmd) { 496 case MBOX_CMD_INC_FALC_CLOCK: 497 case MBOX_CMD_DEC_FALC_CLOCK: 498 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; 499 if (rsp.data != msg->data) 500 rsp.cmd = MBOX_CMD_NAK; 501 else 502 rsp.cmd = MBOX_CMD_ACK; 503 504 break; 505 506 case MBOX_CMD_INC_SSPI_CLOCK: 507 case MBOX_CMD_DEC_SSPI_CLOCK: 508 if (tegra->soc->scale_ss_clock) { 509 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); 510 if (err < 0) 511 rsp.cmd = MBOX_CMD_NAK; 512 else 513 rsp.cmd = MBOX_CMD_ACK; 514 515 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; 516 } else { 517 rsp.cmd = MBOX_CMD_ACK; 518 rsp.data = msg->data; 519 } 520 521 break; 522 523 case MBOX_CMD_SET_BW: 524 /* 525 * TODO: Request bandwidth once EMC scaling is supported. 526 * Ignore for now since ACK/NAK is not required for SET_BW 527 * messages. 528 */ 529 break; 530 531 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 532 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); 533 if (err < 0) { 534 dev_err(dev, "failed to save context for USB3#%u: %d\n", 535 msg->data, err); 536 rsp.cmd = MBOX_CMD_NAK; 537 } else { 538 rsp.cmd = MBOX_CMD_ACK; 539 } 540 541 rsp.data = msg->data; 542 break; 543 544 case MBOX_CMD_START_HSIC_IDLE: 545 case MBOX_CMD_STOP_HSIC_IDLE: 546 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) 547 idle = false; 548 else 549 idle = true; 550 551 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, 552 soc->ports.hsic.count); 553 554 for_each_set_bit(port, &mask, 32) { 555 err = tegra_xusb_padctl_hsic_set_idle(padctl, port, 556 idle); 557 if (err < 0) 558 break; 559 } 560 561 if (err < 0) { 562 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, 563 idle ? "idle" : "busy", err); 564 rsp.cmd = MBOX_CMD_NAK; 565 } else { 566 rsp.cmd = MBOX_CMD_ACK; 567 } 568 569 rsp.data = msg->data; 570 break; 571 572 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 573 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 574 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) 575 enable = false; 576 else 577 enable = true; 578 579 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, 580 soc->ports.usb3.count); 581 582 for_each_set_bit(port, &mask, soc->ports.usb3.count) { 583 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, 584 port, 585 enable); 586 if (err < 0) 587 break; 588 } 589 590 if (err < 0) { 591 dev_err(dev, 592 "failed to %s LFPS detection on USB3#%u: %d\n", 593 enable ? "enable" : "disable", port, err); 594 rsp.cmd = MBOX_CMD_NAK; 595 } else { 596 rsp.cmd = MBOX_CMD_ACK; 597 } 598 599 rsp.data = msg->data; 600 break; 601 602 default: 603 dev_warn(dev, "unknown message: %#x\n", msg->cmd); 604 break; 605 } 606 607 if (rsp.cmd) { 608 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; 609 610 err = tegra_xusb_mbox_send(tegra, &rsp); 611 if (err < 0) 612 dev_err(dev, "failed to send %s: %d\n", cmd, err); 613 } 614 } 615 616 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) 617 { 618 struct tegra_xusb *tegra = data; 619 struct tegra_xusb_mbox_msg msg; 620 u32 value; 621 622 mutex_lock(&tegra->lock); 623 624 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT); 625 tegra_xusb_mbox_unpack(&msg, value); 626 627 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); 628 value &= ~MBOX_DEST_SMI; 629 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); 630 631 /* clear mailbox owner if no ACK/NAK is required */ 632 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) 633 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER); 634 635 tegra_xusb_mbox_handle(tegra, &msg); 636 637 mutex_unlock(&tegra->lock); 638 return IRQ_HANDLED; 639 } 640 641 static void tegra_xusb_config(struct tegra_xusb *tegra, 642 struct resource *regs) 643 { 644 u32 value; 645 646 if (tegra->soc->has_ipfs) { 647 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); 648 value |= IPFS_EN_FPCI; 649 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); 650 651 usleep_range(10, 20); 652 } 653 654 /* Program BAR0 space */ 655 value = fpci_readl(tegra, XUSB_CFG_4); 656 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 657 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 658 fpci_writel(tegra, value, XUSB_CFG_4); 659 660 usleep_range(100, 200); 661 662 /* Enable bus master */ 663 value = fpci_readl(tegra, XUSB_CFG_1); 664 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; 665 fpci_writel(tegra, value, XUSB_CFG_1); 666 667 if (tegra->soc->has_ipfs) { 668 /* Enable interrupt assertion */ 669 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); 670 value |= IPFS_IP_INT_MASK; 671 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); 672 673 /* Set hysteresis */ 674 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); 675 } 676 } 677 678 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) 679 { 680 int err; 681 682 err = clk_prepare_enable(tegra->pll_e); 683 if (err < 0) 684 return err; 685 686 err = clk_prepare_enable(tegra->host_clk); 687 if (err < 0) 688 goto disable_plle; 689 690 err = clk_prepare_enable(tegra->ss_clk); 691 if (err < 0) 692 goto disable_host; 693 694 err = clk_prepare_enable(tegra->falcon_clk); 695 if (err < 0) 696 goto disable_ss; 697 698 err = clk_prepare_enable(tegra->fs_src_clk); 699 if (err < 0) 700 goto disable_falc; 701 702 err = clk_prepare_enable(tegra->hs_src_clk); 703 if (err < 0) 704 goto disable_fs_src; 705 706 if (tegra->soc->scale_ss_clock) { 707 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); 708 if (err < 0) 709 goto disable_hs_src; 710 } 711 712 return 0; 713 714 disable_hs_src: 715 clk_disable_unprepare(tegra->hs_src_clk); 716 disable_fs_src: 717 clk_disable_unprepare(tegra->fs_src_clk); 718 disable_falc: 719 clk_disable_unprepare(tegra->falcon_clk); 720 disable_ss: 721 clk_disable_unprepare(tegra->ss_clk); 722 disable_host: 723 clk_disable_unprepare(tegra->host_clk); 724 disable_plle: 725 clk_disable_unprepare(tegra->pll_e); 726 return err; 727 } 728 729 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) 730 { 731 clk_disable_unprepare(tegra->pll_e); 732 clk_disable_unprepare(tegra->host_clk); 733 clk_disable_unprepare(tegra->ss_clk); 734 clk_disable_unprepare(tegra->falcon_clk); 735 clk_disable_unprepare(tegra->fs_src_clk); 736 clk_disable_unprepare(tegra->hs_src_clk); 737 } 738 739 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) 740 { 741 unsigned int i; 742 int err; 743 744 for (i = 0; i < tegra->num_phys; i++) { 745 err = phy_init(tegra->phys[i]); 746 if (err) 747 goto disable_phy; 748 749 err = phy_power_on(tegra->phys[i]); 750 if (err) { 751 phy_exit(tegra->phys[i]); 752 goto disable_phy; 753 } 754 } 755 756 return 0; 757 758 disable_phy: 759 while (i--) { 760 phy_power_off(tegra->phys[i]); 761 phy_exit(tegra->phys[i]); 762 } 763 764 return err; 765 } 766 767 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) 768 { 769 unsigned int i; 770 771 for (i = 0; i < tegra->num_phys; i++) { 772 phy_power_off(tegra->phys[i]); 773 phy_exit(tegra->phys[i]); 774 } 775 } 776 777 static int tegra_xusb_runtime_suspend(struct device *dev) 778 { 779 struct tegra_xusb *tegra = dev_get_drvdata(dev); 780 781 tegra_xusb_phy_disable(tegra); 782 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 783 tegra_xusb_clk_disable(tegra); 784 785 return 0; 786 } 787 788 static int tegra_xusb_runtime_resume(struct device *dev) 789 { 790 struct tegra_xusb *tegra = dev_get_drvdata(dev); 791 int err; 792 793 err = tegra_xusb_clk_enable(tegra); 794 if (err) { 795 dev_err(dev, "failed to enable clocks: %d\n", err); 796 return err; 797 } 798 799 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); 800 if (err) { 801 dev_err(dev, "failed to enable regulators: %d\n", err); 802 goto disable_clk; 803 } 804 805 err = tegra_xusb_phy_enable(tegra); 806 if (err < 0) { 807 dev_err(dev, "failed to enable PHYs: %d\n", err); 808 goto disable_regulator; 809 } 810 811 return 0; 812 813 disable_regulator: 814 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 815 disable_clk: 816 tegra_xusb_clk_disable(tegra); 817 return err; 818 } 819 820 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) 821 { 822 unsigned int code_tag_blocks, code_size_blocks, code_blocks; 823 struct tegra_xusb_fw_header *header; 824 struct device *dev = tegra->dev; 825 const struct firmware *fw; 826 unsigned long timeout; 827 time64_t timestamp; 828 struct tm time; 829 u64 address; 830 u32 value; 831 int err; 832 833 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); 834 if (err < 0) { 835 dev_err(tegra->dev, "failed to request firmware: %d\n", err); 836 return err; 837 } 838 839 /* Load Falcon controller with its firmware. */ 840 header = (struct tegra_xusb_fw_header *)fw->data; 841 tegra->fw.size = le32_to_cpu(header->fwimg_len); 842 843 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, 844 &tegra->fw.phys, GFP_KERNEL); 845 if (!tegra->fw.virt) { 846 dev_err(tegra->dev, "failed to allocate memory for firmware\n"); 847 release_firmware(fw); 848 return -ENOMEM; 849 } 850 851 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 852 memcpy(tegra->fw.virt, fw->data, tegra->fw.size); 853 release_firmware(fw); 854 855 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { 856 dev_info(dev, "Firmware already loaded, Falcon state %#x\n", 857 csb_readl(tegra, XUSB_FALC_CPUCTL)); 858 return 0; 859 } 860 861 /* Program the size of DFI into ILOAD_ATTR. */ 862 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); 863 864 /* 865 * Boot code of the firmware reads the ILOAD_BASE registers 866 * to get to the start of the DFI in system memory. 867 */ 868 address = tegra->fw.phys + sizeof(*header); 869 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); 870 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); 871 872 /* Set BOOTPATH to 1 in APMAP. */ 873 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); 874 875 /* Invalidate L2IMEM. */ 876 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); 877 878 /* 879 * Initiate fetch of bootcode from system memory into L2IMEM. 880 * Program bootcode location and size in system memory. 881 */ 882 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), 883 IMEM_BLOCK_SIZE); 884 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), 885 IMEM_BLOCK_SIZE); 886 code_blocks = code_tag_blocks + code_size_blocks; 887 888 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << 889 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | 890 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << 891 L2IMEMOP_SIZE_SRC_COUNT_SHIFT); 892 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); 893 894 /* Trigger L2IMEM load operation. */ 895 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, 896 XUSB_CSB_MP_L2IMEMOP_TRIG); 897 898 /* Setup Falcon auto-fill. */ 899 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); 900 901 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << 902 IMFILLRNG1_TAG_LO_SHIFT) | 903 ((code_blocks & IMFILLRNG1_TAG_MASK) << 904 IMFILLRNG1_TAG_HI_SHIFT); 905 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); 906 907 csb_writel(tegra, 0, XUSB_FALC_DMACTL); 908 909 msleep(50); 910 911 csb_writel(tegra, le32_to_cpu(header->boot_codetag), 912 XUSB_FALC_BOOTVEC); 913 914 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */ 915 timeout = jiffies + msecs_to_jiffies(5); 916 917 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); 918 919 while (time_before(jiffies, timeout)) { 920 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED) 921 break; 922 923 usleep_range(100, 200); 924 } 925 926 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) { 927 dev_err(dev, "Falcon failed to start, state: %#x\n", 928 csb_readl(tegra, XUSB_FALC_CPUCTL)); 929 return -EIO; 930 } 931 932 timestamp = le32_to_cpu(header->fwimg_created_time); 933 time64_to_tm(timestamp, 0, &time); 934 935 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n", 936 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday, 937 time.tm_hour, time.tm_min, time.tm_sec); 938 939 return 0; 940 } 941 942 static void tegra_xusb_powerdomain_remove(struct device *dev, 943 struct tegra_xusb *tegra) 944 { 945 if (tegra->genpd_dl_ss) 946 device_link_del(tegra->genpd_dl_ss); 947 if (tegra->genpd_dl_host) 948 device_link_del(tegra->genpd_dl_host); 949 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss)) 950 dev_pm_domain_detach(tegra->genpd_dev_ss, true); 951 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host)) 952 dev_pm_domain_detach(tegra->genpd_dev_host, true); 953 } 954 955 static int tegra_xusb_powerdomain_init(struct device *dev, 956 struct tegra_xusb *tegra) 957 { 958 int err; 959 960 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host"); 961 if (IS_ERR(tegra->genpd_dev_host)) { 962 err = PTR_ERR(tegra->genpd_dev_host); 963 dev_err(dev, "failed to get host pm-domain: %d\n", err); 964 return err; 965 } 966 967 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss"); 968 if (IS_ERR(tegra->genpd_dev_ss)) { 969 err = PTR_ERR(tegra->genpd_dev_ss); 970 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err); 971 return err; 972 } 973 974 tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host, 975 DL_FLAG_PM_RUNTIME | 976 DL_FLAG_STATELESS); 977 if (!tegra->genpd_dl_host) { 978 dev_err(dev, "adding host device link failed!\n"); 979 return -ENODEV; 980 } 981 982 tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss, 983 DL_FLAG_PM_RUNTIME | 984 DL_FLAG_STATELESS); 985 if (!tegra->genpd_dl_ss) { 986 dev_err(dev, "adding superspeed device link failed!\n"); 987 return -ENODEV; 988 } 989 990 return 0; 991 } 992 993 static int tegra_xusb_probe(struct platform_device *pdev) 994 { 995 struct tegra_xusb_mbox_msg msg; 996 struct resource *res, *regs; 997 struct tegra_xusb *tegra; 998 struct xhci_hcd *xhci; 999 unsigned int i, j, k; 1000 struct phy *phy; 1001 int err; 1002 1003 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); 1004 1005 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 1006 if (!tegra) 1007 return -ENOMEM; 1008 1009 tegra->soc = of_device_get_match_data(&pdev->dev); 1010 mutex_init(&tegra->lock); 1011 tegra->dev = &pdev->dev; 1012 1013 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1014 tegra->regs = devm_ioremap_resource(&pdev->dev, regs); 1015 if (IS_ERR(tegra->regs)) 1016 return PTR_ERR(tegra->regs); 1017 1018 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1019 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res); 1020 if (IS_ERR(tegra->fpci_base)) 1021 return PTR_ERR(tegra->fpci_base); 1022 1023 if (tegra->soc->has_ipfs) { 1024 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1025 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res); 1026 if (IS_ERR(tegra->ipfs_base)) 1027 return PTR_ERR(tegra->ipfs_base); 1028 } 1029 1030 tegra->xhci_irq = platform_get_irq(pdev, 0); 1031 if (tegra->xhci_irq < 0) 1032 return tegra->xhci_irq; 1033 1034 tegra->mbox_irq = platform_get_irq(pdev, 1); 1035 if (tegra->mbox_irq < 0) 1036 return tegra->mbox_irq; 1037 1038 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); 1039 if (IS_ERR(tegra->padctl)) 1040 return PTR_ERR(tegra->padctl); 1041 1042 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); 1043 if (IS_ERR(tegra->host_clk)) { 1044 err = PTR_ERR(tegra->host_clk); 1045 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); 1046 goto put_padctl; 1047 } 1048 1049 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); 1050 if (IS_ERR(tegra->falcon_clk)) { 1051 err = PTR_ERR(tegra->falcon_clk); 1052 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); 1053 goto put_padctl; 1054 } 1055 1056 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); 1057 if (IS_ERR(tegra->ss_clk)) { 1058 err = PTR_ERR(tegra->ss_clk); 1059 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); 1060 goto put_padctl; 1061 } 1062 1063 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); 1064 if (IS_ERR(tegra->ss_src_clk)) { 1065 err = PTR_ERR(tegra->ss_src_clk); 1066 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); 1067 goto put_padctl; 1068 } 1069 1070 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); 1071 if (IS_ERR(tegra->hs_src_clk)) { 1072 err = PTR_ERR(tegra->hs_src_clk); 1073 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); 1074 goto put_padctl; 1075 } 1076 1077 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); 1078 if (IS_ERR(tegra->fs_src_clk)) { 1079 err = PTR_ERR(tegra->fs_src_clk); 1080 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); 1081 goto put_padctl; 1082 } 1083 1084 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); 1085 if (IS_ERR(tegra->pll_u_480m)) { 1086 err = PTR_ERR(tegra->pll_u_480m); 1087 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); 1088 goto put_padctl; 1089 } 1090 1091 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); 1092 if (IS_ERR(tegra->clk_m)) { 1093 err = PTR_ERR(tegra->clk_m); 1094 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); 1095 goto put_padctl; 1096 } 1097 1098 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); 1099 if (IS_ERR(tegra->pll_e)) { 1100 err = PTR_ERR(tegra->pll_e); 1101 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); 1102 goto put_padctl; 1103 } 1104 1105 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1106 tegra->host_rst = devm_reset_control_get(&pdev->dev, 1107 "xusb_host"); 1108 if (IS_ERR(tegra->host_rst)) { 1109 err = PTR_ERR(tegra->host_rst); 1110 dev_err(&pdev->dev, 1111 "failed to get xusb_host reset: %d\n", err); 1112 goto put_padctl; 1113 } 1114 1115 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); 1116 if (IS_ERR(tegra->ss_rst)) { 1117 err = PTR_ERR(tegra->ss_rst); 1118 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", 1119 err); 1120 goto put_padctl; 1121 } 1122 1123 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 1124 tegra->ss_clk, 1125 tegra->ss_rst); 1126 if (err) { 1127 dev_err(&pdev->dev, 1128 "failed to enable XUSBA domain: %d\n", err); 1129 goto put_padctl; 1130 } 1131 1132 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 1133 tegra->host_clk, 1134 tegra->host_rst); 1135 if (err) { 1136 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1137 dev_err(&pdev->dev, 1138 "failed to enable XUSBC domain: %d\n", err); 1139 goto put_padctl; 1140 } 1141 } else { 1142 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra); 1143 if (err) 1144 goto put_powerdomains; 1145 } 1146 1147 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, 1148 sizeof(*tegra->supplies), GFP_KERNEL); 1149 if (!tegra->supplies) { 1150 err = -ENOMEM; 1151 goto put_powerdomains; 1152 } 1153 1154 for (i = 0; i < tegra->soc->num_supplies; i++) 1155 tegra->supplies[i].supply = tegra->soc->supply_names[i]; 1156 1157 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, 1158 tegra->supplies); 1159 if (err) { 1160 dev_err(&pdev->dev, "failed to get regulators: %d\n", err); 1161 goto put_powerdomains; 1162 } 1163 1164 for (i = 0; i < tegra->soc->num_types; i++) 1165 tegra->num_phys += tegra->soc->phy_types[i].num; 1166 1167 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, 1168 sizeof(*tegra->phys), GFP_KERNEL); 1169 if (!tegra->phys) { 1170 err = -ENOMEM; 1171 goto put_powerdomains; 1172 } 1173 1174 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 1175 char prop[8]; 1176 1177 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 1178 snprintf(prop, sizeof(prop), "%s-%d", 1179 tegra->soc->phy_types[i].name, j); 1180 1181 phy = devm_phy_optional_get(&pdev->dev, prop); 1182 if (IS_ERR(phy)) { 1183 dev_err(&pdev->dev, 1184 "failed to get PHY %s: %ld\n", prop, 1185 PTR_ERR(phy)); 1186 err = PTR_ERR(phy); 1187 goto put_powerdomains; 1188 } 1189 1190 tegra->phys[k++] = phy; 1191 } 1192 } 1193 1194 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, 1195 dev_name(&pdev->dev)); 1196 if (!tegra->hcd) { 1197 err = -ENOMEM; 1198 goto put_powerdomains; 1199 } 1200 1201 /* 1202 * This must happen after usb_create_hcd(), because usb_create_hcd() 1203 * will overwrite the drvdata of the device with the hcd it creates. 1204 */ 1205 platform_set_drvdata(pdev, tegra); 1206 1207 pm_runtime_enable(&pdev->dev); 1208 if (pm_runtime_enabled(&pdev->dev)) 1209 err = pm_runtime_get_sync(&pdev->dev); 1210 else 1211 err = tegra_xusb_runtime_resume(&pdev->dev); 1212 1213 if (err < 0) { 1214 dev_err(&pdev->dev, "failed to enable device: %d\n", err); 1215 goto disable_rpm; 1216 } 1217 1218 tegra_xusb_config(tegra, regs); 1219 1220 err = tegra_xusb_load_firmware(tegra); 1221 if (err < 0) { 1222 dev_err(&pdev->dev, "failed to load firmware: %d\n", err); 1223 goto put_rpm; 1224 } 1225 1226 tegra->hcd->regs = tegra->regs; 1227 tegra->hcd->rsrc_start = regs->start; 1228 tegra->hcd->rsrc_len = resource_size(regs); 1229 1230 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); 1231 if (err < 0) { 1232 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); 1233 goto put_rpm; 1234 } 1235 1236 device_wakeup_enable(tegra->hcd->self.controller); 1237 1238 xhci = hcd_to_xhci(tegra->hcd); 1239 1240 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, 1241 &pdev->dev, 1242 dev_name(&pdev->dev), 1243 tegra->hcd); 1244 if (!xhci->shared_hcd) { 1245 dev_err(&pdev->dev, "failed to create shared HCD\n"); 1246 err = -ENOMEM; 1247 goto remove_usb2; 1248 } 1249 1250 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); 1251 if (err < 0) { 1252 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); 1253 goto put_usb3; 1254 } 1255 1256 mutex_lock(&tegra->lock); 1257 1258 /* Enable firmware messages from controller. */ 1259 msg.cmd = MBOX_CMD_MSG_ENABLED; 1260 msg.data = 0; 1261 1262 err = tegra_xusb_mbox_send(tegra, &msg); 1263 if (err < 0) { 1264 dev_err(&pdev->dev, "failed to enable messages: %d\n", err); 1265 mutex_unlock(&tegra->lock); 1266 goto remove_usb3; 1267 } 1268 1269 mutex_unlock(&tegra->lock); 1270 1271 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, 1272 tegra_xusb_mbox_irq, 1273 tegra_xusb_mbox_thread, 0, 1274 dev_name(&pdev->dev), tegra); 1275 if (err < 0) { 1276 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 1277 goto remove_usb3; 1278 } 1279 1280 return 0; 1281 1282 remove_usb3: 1283 usb_remove_hcd(xhci->shared_hcd); 1284 put_usb3: 1285 usb_put_hcd(xhci->shared_hcd); 1286 remove_usb2: 1287 usb_remove_hcd(tegra->hcd); 1288 put_rpm: 1289 if (!pm_runtime_status_suspended(&pdev->dev)) 1290 tegra_xusb_runtime_suspend(&pdev->dev); 1291 disable_rpm: 1292 pm_runtime_disable(&pdev->dev); 1293 usb_put_hcd(tegra->hcd); 1294 put_powerdomains: 1295 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1296 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1297 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1298 } else { 1299 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1300 } 1301 put_padctl: 1302 tegra_xusb_padctl_put(tegra->padctl); 1303 return err; 1304 } 1305 1306 static int tegra_xusb_remove(struct platform_device *pdev) 1307 { 1308 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 1309 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1310 1311 usb_remove_hcd(xhci->shared_hcd); 1312 usb_put_hcd(xhci->shared_hcd); 1313 xhci->shared_hcd = NULL; 1314 usb_remove_hcd(tegra->hcd); 1315 usb_put_hcd(tegra->hcd); 1316 1317 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1318 tegra->fw.phys); 1319 1320 pm_runtime_put_sync(&pdev->dev); 1321 pm_runtime_disable(&pdev->dev); 1322 1323 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1324 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1325 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1326 } else { 1327 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1328 } 1329 1330 tegra_xusb_padctl_put(tegra->padctl); 1331 1332 return 0; 1333 } 1334 1335 #ifdef CONFIG_PM_SLEEP 1336 static int tegra_xusb_suspend(struct device *dev) 1337 { 1338 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1339 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1340 bool wakeup = device_may_wakeup(dev); 1341 1342 /* TODO: Powergate controller across suspend/resume. */ 1343 return xhci_suspend(xhci, wakeup); 1344 } 1345 1346 static int tegra_xusb_resume(struct device *dev) 1347 { 1348 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1349 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1350 1351 return xhci_resume(xhci, 0); 1352 } 1353 #endif 1354 1355 static const struct dev_pm_ops tegra_xusb_pm_ops = { 1356 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend, 1357 tegra_xusb_runtime_resume, NULL) 1358 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) 1359 }; 1360 1361 static const char * const tegra124_supply_names[] = { 1362 "avddio-pex", 1363 "dvddio-pex", 1364 "avdd-usb", 1365 "avdd-pll-utmip", 1366 "avdd-pll-erefe", 1367 "avdd-usb-ss-pll", 1368 "hvdd-usb-ss", 1369 "hvdd-usb-ss-pll-e", 1370 }; 1371 1372 static const struct tegra_xusb_phy_type tegra124_phy_types[] = { 1373 { .name = "usb3", .num = 2, }, 1374 { .name = "usb2", .num = 3, }, 1375 { .name = "hsic", .num = 2, }, 1376 }; 1377 1378 static const struct tegra_xusb_soc tegra124_soc = { 1379 .firmware = "nvidia/tegra124/xusb.bin", 1380 .supply_names = tegra124_supply_names, 1381 .num_supplies = ARRAY_SIZE(tegra124_supply_names), 1382 .phy_types = tegra124_phy_types, 1383 .num_types = ARRAY_SIZE(tegra124_phy_types), 1384 .ports = { 1385 .usb2 = { .offset = 4, .count = 4, }, 1386 .hsic = { .offset = 6, .count = 2, }, 1387 .usb3 = { .offset = 0, .count = 2, }, 1388 }, 1389 .scale_ss_clock = true, 1390 .has_ipfs = true, 1391 }; 1392 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); 1393 1394 static const char * const tegra210_supply_names[] = { 1395 "dvddio-pex", 1396 "hvddio-pex", 1397 "avdd-usb", 1398 "avdd-pll-utmip", 1399 "avdd-pll-uerefe", 1400 "dvdd-pex-pll", 1401 "hvdd-pex-pll-e", 1402 }; 1403 1404 static const struct tegra_xusb_phy_type tegra210_phy_types[] = { 1405 { .name = "usb3", .num = 4, }, 1406 { .name = "usb2", .num = 4, }, 1407 { .name = "hsic", .num = 1, }, 1408 }; 1409 1410 static const struct tegra_xusb_soc tegra210_soc = { 1411 .firmware = "nvidia/tegra210/xusb.bin", 1412 .supply_names = tegra210_supply_names, 1413 .num_supplies = ARRAY_SIZE(tegra210_supply_names), 1414 .phy_types = tegra210_phy_types, 1415 .num_types = ARRAY_SIZE(tegra210_phy_types), 1416 .ports = { 1417 .usb2 = { .offset = 4, .count = 4, }, 1418 .hsic = { .offset = 8, .count = 1, }, 1419 .usb3 = { .offset = 0, .count = 4, }, 1420 }, 1421 .scale_ss_clock = false, 1422 .has_ipfs = true, 1423 }; 1424 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); 1425 1426 static const char * const tegra186_supply_names[] = { 1427 }; 1428 1429 static const struct tegra_xusb_phy_type tegra186_phy_types[] = { 1430 { .name = "usb3", .num = 3, }, 1431 { .name = "usb2", .num = 3, }, 1432 { .name = "hsic", .num = 1, }, 1433 }; 1434 1435 static const struct tegra_xusb_soc tegra186_soc = { 1436 .firmware = "nvidia/tegra186/xusb.bin", 1437 .supply_names = tegra186_supply_names, 1438 .num_supplies = ARRAY_SIZE(tegra186_supply_names), 1439 .phy_types = tegra186_phy_types, 1440 .num_types = ARRAY_SIZE(tegra186_phy_types), 1441 .ports = { 1442 .usb3 = { .offset = 0, .count = 3, }, 1443 .usb2 = { .offset = 3, .count = 3, }, 1444 .hsic = { .offset = 6, .count = 1, }, 1445 }, 1446 .scale_ss_clock = false, 1447 .has_ipfs = false, 1448 }; 1449 1450 static const struct of_device_id tegra_xusb_of_match[] = { 1451 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, 1452 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, 1453 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, 1454 { }, 1455 }; 1456 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); 1457 1458 static struct platform_driver tegra_xusb_driver = { 1459 .probe = tegra_xusb_probe, 1460 .remove = tegra_xusb_remove, 1461 .driver = { 1462 .name = "tegra-xusb", 1463 .pm = &tegra_xusb_pm_ops, 1464 .of_match_table = tegra_xusb_of_match, 1465 }, 1466 }; 1467 1468 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) 1469 { 1470 xhci->quirks |= XHCI_PLAT; 1471 } 1472 1473 static int tegra_xhci_setup(struct usb_hcd *hcd) 1474 { 1475 return xhci_gen_setup(hcd, tegra_xhci_quirks); 1476 } 1477 1478 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { 1479 .reset = tegra_xhci_setup, 1480 }; 1481 1482 static int __init tegra_xusb_init(void) 1483 { 1484 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); 1485 1486 return platform_driver_register(&tegra_xusb_driver); 1487 } 1488 module_init(tegra_xusb_init); 1489 1490 static void __exit tegra_xusb_exit(void) 1491 { 1492 platform_driver_unregister(&tegra_xusb_driver); 1493 } 1494 module_exit(tegra_xusb_exit); 1495 1496 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 1497 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); 1498 MODULE_LICENSE("GPL v2"); 1499