1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 /* 12 * Ring initialization rules: 13 * 1. Each segment is initialized to zero, except for link TRBs. 14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or 15 * Consumer Cycle State (CCS), depending on ring function. 16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. 17 * 18 * Ring behavior rules: 19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at 20 * least one free TRB in the ring. This is useful if you want to turn that 21 * into a link TRB and expand the ring. 22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a 23 * link TRB, then load the pointer with the address in the link TRB. If the 24 * link TRB had its toggle bit set, you may need to update the ring cycle 25 * state (see cycle bit rules). You may have to do this multiple times 26 * until you reach a non-link TRB. 27 * 3. A ring is full if enqueue++ (for the definition of increment above) 28 * equals the dequeue pointer. 29 * 30 * Cycle bit rules: 31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit 32 * in a link TRB, it must toggle the ring cycle state. 33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit 34 * in a link TRB, it must toggle the ring cycle state. 35 * 36 * Producer rules: 37 * 1. Check if ring is full before you enqueue. 38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. 39 * Update enqueue pointer between each write (which may update the ring 40 * cycle state). 41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command 42 * and endpoint rings. If HC is the producer for the event ring, 43 * and it generates an interrupt according to interrupt modulation rules. 44 * 45 * Consumer rules: 46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, 47 * the TRB is owned by the consumer. 48 * 2. Update dequeue pointer (which may update the ring cycle state) and 49 * continue processing TRBs until you reach a TRB which is not owned by you. 50 * 3. Notify the producer. SW is the consumer for the event ring, and it 51 * updates event ring dequeue pointer. HC is the consumer for the command and 52 * endpoint rings; it generates events on the event ring for these. 53 */ 54 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/dma-mapping.h> 58 #include "xhci.h" 59 #include "xhci-trace.h" 60 61 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 62 u32 field1, u32 field2, 63 u32 field3, u32 field4, bool command_must_succeed); 64 65 /* 66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA 67 * address of the TRB. 68 */ 69 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, 70 union xhci_trb *trb) 71 { 72 unsigned long segment_offset; 73 74 if (!seg || !trb || trb < seg->trbs) 75 return 0; 76 /* offset in TRBs */ 77 segment_offset = trb - seg->trbs; 78 if (segment_offset >= TRBS_PER_SEGMENT) 79 return 0; 80 return seg->dma + (segment_offset * sizeof(*trb)); 81 } 82 83 static bool trb_is_noop(union xhci_trb *trb) 84 { 85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); 86 } 87 88 static bool trb_is_link(union xhci_trb *trb) 89 { 90 return TRB_TYPE_LINK_LE32(trb->link.control); 91 } 92 93 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) 94 { 95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; 96 } 97 98 static bool last_trb_on_ring(struct xhci_ring *ring, 99 struct xhci_segment *seg, union xhci_trb *trb) 100 { 101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); 102 } 103 104 static bool link_trb_toggles_cycle(union xhci_trb *trb) 105 { 106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE; 107 } 108 109 static bool last_td_in_urb(struct xhci_td *td) 110 { 111 struct urb_priv *urb_priv = td->urb->hcpriv; 112 113 return urb_priv->num_tds_done == urb_priv->num_tds; 114 } 115 116 static void inc_td_cnt(struct urb *urb) 117 { 118 struct urb_priv *urb_priv = urb->hcpriv; 119 120 urb_priv->num_tds_done++; 121 } 122 123 static void trb_to_noop(union xhci_trb *trb, u32 noop_type) 124 { 125 if (trb_is_link(trb)) { 126 /* unchain chained link TRBs */ 127 trb->link.control &= cpu_to_le32(~TRB_CHAIN); 128 } else { 129 trb->generic.field[0] = 0; 130 trb->generic.field[1] = 0; 131 trb->generic.field[2] = 0; 132 /* Preserve only the cycle bit of this TRB */ 133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); 134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); 135 } 136 } 137 138 /* Updates trb to point to the next TRB in the ring, and updates seg if the next 139 * TRB is in a new segment. This does not skip over link TRBs, and it does not 140 * effect the ring dequeue or enqueue pointers. 141 */ 142 static void next_trb(struct xhci_hcd *xhci, 143 struct xhci_ring *ring, 144 struct xhci_segment **seg, 145 union xhci_trb **trb) 146 { 147 if (trb_is_link(*trb)) { 148 *seg = (*seg)->next; 149 *trb = ((*seg)->trbs); 150 } else { 151 (*trb)++; 152 } 153 } 154 155 /* 156 * See Cycle bit rules. SW is the consumer for the event ring only. 157 */ 158 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) 159 { 160 unsigned int link_trb_count = 0; 161 162 /* event ring doesn't have link trbs, check for last trb */ 163 if (ring->type == TYPE_EVENT) { 164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { 165 ring->dequeue++; 166 goto out; 167 } 168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) 169 ring->cycle_state ^= 1; 170 ring->deq_seg = ring->deq_seg->next; 171 ring->dequeue = ring->deq_seg->trbs; 172 goto out; 173 } 174 175 /* All other rings have link trbs */ 176 if (!trb_is_link(ring->dequeue)) { 177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) { 178 xhci_warn(xhci, "Missing link TRB at end of segment\n"); 179 } else { 180 ring->dequeue++; 181 ring->num_trbs_free++; 182 } 183 } 184 185 while (trb_is_link(ring->dequeue)) { 186 ring->deq_seg = ring->deq_seg->next; 187 ring->dequeue = ring->deq_seg->trbs; 188 189 if (link_trb_count++ > ring->num_segs) { 190 xhci_warn(xhci, "Ring is an endless link TRB loop\n"); 191 break; 192 } 193 } 194 out: 195 trace_xhci_inc_deq(ring); 196 197 return; 198 } 199 200 /* 201 * See Cycle bit rules. SW is the consumer for the event ring only. 202 * 203 * If we've just enqueued a TRB that is in the middle of a TD (meaning the 204 * chain bit is set), then set the chain bit in all the following link TRBs. 205 * If we've enqueued the last TRB in a TD, make sure the following link TRBs 206 * have their chain bit cleared (so that each Link TRB is a separate TD). 207 * 208 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit 209 * set, but other sections talk about dealing with the chain bit set. This was 210 * fixed in the 0.96 specification errata, but we have to assume that all 0.95 211 * xHCI hardware can't handle the chain bit being cleared on a link TRB. 212 * 213 * @more_trbs_coming: Will you enqueue more TRBs before calling 214 * prepare_transfer()? 215 */ 216 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, 217 bool more_trbs_coming) 218 { 219 u32 chain; 220 union xhci_trb *next; 221 unsigned int link_trb_count = 0; 222 223 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; 224 /* If this is not event ring, there is one less usable TRB */ 225 if (!trb_is_link(ring->enqueue)) 226 ring->num_trbs_free--; 227 228 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) { 229 xhci_err(xhci, "Tried to move enqueue past ring segment\n"); 230 return; 231 } 232 233 next = ++(ring->enqueue); 234 235 /* Update the dequeue pointer further if that was a link TRB */ 236 while (trb_is_link(next)) { 237 238 /* 239 * If the caller doesn't plan on enqueueing more TDs before 240 * ringing the doorbell, then we don't want to give the link TRB 241 * to the hardware just yet. We'll give the link TRB back in 242 * prepare_ring() just before we enqueue the TD at the top of 243 * the ring. 244 */ 245 if (!chain && !more_trbs_coming) 246 break; 247 248 /* If we're not dealing with 0.95 hardware or isoc rings on 249 * AMD 0.96 host, carry over the chain bit of the previous TRB 250 * (which may mean the chain bit is cleared). 251 */ 252 if (!(ring->type == TYPE_ISOC && 253 (xhci->quirks & XHCI_AMD_0x96_HOST)) && 254 !xhci_link_trb_quirk(xhci)) { 255 next->link.control &= cpu_to_le32(~TRB_CHAIN); 256 next->link.control |= cpu_to_le32(chain); 257 } 258 /* Give this link TRB to the hardware */ 259 wmb(); 260 next->link.control ^= cpu_to_le32(TRB_CYCLE); 261 262 /* Toggle the cycle bit after the last ring segment. */ 263 if (link_trb_toggles_cycle(next)) 264 ring->cycle_state ^= 1; 265 266 ring->enq_seg = ring->enq_seg->next; 267 ring->enqueue = ring->enq_seg->trbs; 268 next = ring->enqueue; 269 270 if (link_trb_count++ > ring->num_segs) { 271 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__); 272 break; 273 } 274 } 275 276 trace_xhci_inc_enq(ring); 277 } 278 279 static int xhci_num_trbs_to(struct xhci_segment *start_seg, union xhci_trb *start, 280 struct xhci_segment *end_seg, union xhci_trb *end, 281 unsigned int num_segs) 282 { 283 union xhci_trb *last_on_seg; 284 int num = 0; 285 int i = 0; 286 287 do { 288 if (start_seg == end_seg && end >= start) 289 return num + (end - start); 290 last_on_seg = &start_seg->trbs[TRBS_PER_SEGMENT - 1]; 291 num += last_on_seg - start; 292 start_seg = start_seg->next; 293 start = start_seg->trbs; 294 } while (i++ <= num_segs); 295 296 return -EINVAL; 297 } 298 299 /* 300 * Check to see if there's room to enqueue num_trbs on the ring and make sure 301 * enqueue pointer will not advance into dequeue segment. See rules above. 302 */ 303 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, 304 unsigned int num_trbs) 305 { 306 int num_trbs_in_deq_seg; 307 308 if (ring->num_trbs_free < num_trbs) 309 return 0; 310 311 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { 312 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; 313 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) 314 return 0; 315 } 316 317 return 1; 318 } 319 320 /* Ring the host controller doorbell after placing a command on the ring */ 321 void xhci_ring_cmd_db(struct xhci_hcd *xhci) 322 { 323 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) 324 return; 325 326 xhci_dbg(xhci, "// Ding dong!\n"); 327 328 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST); 329 330 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); 331 /* Flush PCI posted writes */ 332 readl(&xhci->dba->doorbell[0]); 333 } 334 335 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) 336 { 337 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); 338 } 339 340 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) 341 { 342 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, 343 cmd_list); 344 } 345 346 /* 347 * Turn all commands on command ring with status set to "aborted" to no-op trbs. 348 * If there are other commands waiting then restart the ring and kick the timer. 349 * This must be called with command ring stopped and xhci->lock held. 350 */ 351 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, 352 struct xhci_command *cur_cmd) 353 { 354 struct xhci_command *i_cmd; 355 356 /* Turn all aborted commands in list to no-ops, then restart */ 357 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { 358 359 if (i_cmd->status != COMP_COMMAND_ABORTED) 360 continue; 361 362 i_cmd->status = COMP_COMMAND_RING_STOPPED; 363 364 xhci_dbg(xhci, "Turn aborted command %p to no-op\n", 365 i_cmd->command_trb); 366 367 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); 368 369 /* 370 * caller waiting for completion is called when command 371 * completion event is received for these no-op commands 372 */ 373 } 374 375 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; 376 377 /* ring command ring doorbell to restart the command ring */ 378 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && 379 !(xhci->xhc_state & XHCI_STATE_DYING)) { 380 xhci->current_cmd = cur_cmd; 381 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 382 xhci_ring_cmd_db(xhci); 383 } 384 } 385 386 /* Must be called with xhci->lock held, releases and aquires lock back */ 387 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) 388 { 389 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg; 390 union xhci_trb *new_deq = xhci->cmd_ring->dequeue; 391 u64 crcr; 392 int ret; 393 394 xhci_dbg(xhci, "Abort command ring\n"); 395 396 reinit_completion(&xhci->cmd_ring_stop_completion); 397 398 /* 399 * The control bits like command stop, abort are located in lower 400 * dword of the command ring control register. 401 * Some controllers require all 64 bits to be written to abort the ring. 402 * Make sure the upper dword is valid, pointing to the next command, 403 * avoiding corrupting the command ring pointer in case the command ring 404 * is stopped by the time the upper dword is written. 405 */ 406 next_trb(xhci, NULL, &new_seg, &new_deq); 407 if (trb_is_link(new_deq)) 408 next_trb(xhci, NULL, &new_seg, &new_deq); 409 410 crcr = xhci_trb_virt_to_dma(new_seg, new_deq); 411 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring); 412 413 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the 414 * completion of the Command Abort operation. If CRR is not negated in 5 415 * seconds then driver handles it as if host died (-ENODEV). 416 * In the future we should distinguish between -ENODEV and -ETIMEDOUT 417 * and try to recover a -ETIMEDOUT with a host controller reset. 418 */ 419 ret = xhci_handshake(&xhci->op_regs->cmd_ring, 420 CMD_RING_RUNNING, 0, 5 * 1000 * 1000); 421 if (ret < 0) { 422 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); 423 xhci_halt(xhci); 424 xhci_hc_died(xhci); 425 return ret; 426 } 427 /* 428 * Writing the CMD_RING_ABORT bit should cause a cmd completion event, 429 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared 430 * but the completion event in never sent. Wait 2 secs (arbitrary 431 * number) to handle those cases after negation of CMD_RING_RUNNING. 432 */ 433 spin_unlock_irqrestore(&xhci->lock, flags); 434 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, 435 msecs_to_jiffies(2000)); 436 spin_lock_irqsave(&xhci->lock, flags); 437 if (!ret) { 438 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); 439 xhci_cleanup_command_queue(xhci); 440 } else { 441 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); 442 } 443 return 0; 444 } 445 446 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, 447 unsigned int slot_id, 448 unsigned int ep_index, 449 unsigned int stream_id) 450 { 451 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; 452 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 453 unsigned int ep_state = ep->ep_state; 454 455 /* Don't ring the doorbell for this endpoint if there are pending 456 * cancellations because we don't want to interrupt processing. 457 * We don't want to restart any stream rings if there's a set dequeue 458 * pointer command pending because the device can choose to start any 459 * stream once the endpoint is on the HW schedule. 460 */ 461 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || 462 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT)) 463 return; 464 465 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id)); 466 467 writel(DB_VALUE(ep_index, stream_id), db_addr); 468 /* flush the write */ 469 readl(db_addr); 470 } 471 472 /* Ring the doorbell for any rings with pending URBs */ 473 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 474 unsigned int slot_id, 475 unsigned int ep_index) 476 { 477 unsigned int stream_id; 478 struct xhci_virt_ep *ep; 479 480 ep = &xhci->devs[slot_id]->eps[ep_index]; 481 482 /* A ring has pending URBs if its TD list is not empty */ 483 if (!(ep->ep_state & EP_HAS_STREAMS)) { 484 if (ep->ring && !(list_empty(&ep->ring->td_list))) 485 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); 486 return; 487 } 488 489 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 490 stream_id++) { 491 struct xhci_stream_info *stream_info = ep->stream_info; 492 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) 493 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 494 stream_id); 495 } 496 } 497 498 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 499 unsigned int slot_id, 500 unsigned int ep_index) 501 { 502 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 503 } 504 505 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci, 506 unsigned int slot_id, 507 unsigned int ep_index) 508 { 509 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) { 510 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); 511 return NULL; 512 } 513 if (ep_index >= EP_CTX_PER_DEV) { 514 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index); 515 return NULL; 516 } 517 if (!xhci->devs[slot_id]) { 518 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id); 519 return NULL; 520 } 521 522 return &xhci->devs[slot_id]->eps[ep_index]; 523 } 524 525 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci, 526 struct xhci_virt_ep *ep, 527 unsigned int stream_id) 528 { 529 /* common case, no streams */ 530 if (!(ep->ep_state & EP_HAS_STREAMS)) 531 return ep->ring; 532 533 if (!ep->stream_info) 534 return NULL; 535 536 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) { 537 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n", 538 stream_id, ep->vdev->slot_id, ep->ep_index); 539 return NULL; 540 } 541 542 return ep->stream_info->stream_rings[stream_id]; 543 } 544 545 /* Get the right ring for the given slot_id, ep_index and stream_id. 546 * If the endpoint supports streams, boundary check the URB's stream ID. 547 * If the endpoint doesn't support streams, return the singular endpoint ring. 548 */ 549 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 550 unsigned int slot_id, unsigned int ep_index, 551 unsigned int stream_id) 552 { 553 struct xhci_virt_ep *ep; 554 555 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 556 if (!ep) 557 return NULL; 558 559 return xhci_virt_ep_to_ring(xhci, ep, stream_id); 560 } 561 562 563 /* 564 * Get the hw dequeue pointer xHC stopped on, either directly from the 565 * endpoint context, or if streams are in use from the stream context. 566 * The returned hw_dequeue contains the lowest four bits with cycle state 567 * and possbile stream context type. 568 */ 569 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, 570 unsigned int ep_index, unsigned int stream_id) 571 { 572 struct xhci_ep_ctx *ep_ctx; 573 struct xhci_stream_ctx *st_ctx; 574 struct xhci_virt_ep *ep; 575 576 ep = &vdev->eps[ep_index]; 577 578 if (ep->ep_state & EP_HAS_STREAMS) { 579 st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; 580 return le64_to_cpu(st_ctx->stream_ring); 581 } 582 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 583 return le64_to_cpu(ep_ctx->deq); 584 } 585 586 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci, 587 unsigned int slot_id, unsigned int ep_index, 588 unsigned int stream_id, struct xhci_td *td) 589 { 590 struct xhci_virt_device *dev = xhci->devs[slot_id]; 591 struct xhci_virt_ep *ep = &dev->eps[ep_index]; 592 struct xhci_ring *ep_ring; 593 struct xhci_command *cmd; 594 struct xhci_segment *new_seg; 595 struct xhci_segment *halted_seg = NULL; 596 union xhci_trb *new_deq; 597 int new_cycle; 598 union xhci_trb *halted_trb; 599 int index = 0; 600 dma_addr_t addr; 601 u64 hw_dequeue; 602 bool cycle_found = false; 603 bool td_last_trb_found = false; 604 u32 trb_sct = 0; 605 int ret; 606 607 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, 608 ep_index, stream_id); 609 if (!ep_ring) { 610 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n", 611 stream_id); 612 return -ENODEV; 613 } 614 /* 615 * A cancelled TD can complete with a stall if HW cached the trb. 616 * In this case driver can't find td, but if the ring is empty we 617 * can move the dequeue pointer to the current enqueue position. 618 * We shouldn't hit this anymore as cached cancelled TRBs are given back 619 * after clearing the cache, but be on the safe side and keep it anyway 620 */ 621 if (!td) { 622 if (list_empty(&ep_ring->td_list)) { 623 new_seg = ep_ring->enq_seg; 624 new_deq = ep_ring->enqueue; 625 new_cycle = ep_ring->cycle_state; 626 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue"); 627 goto deq_found; 628 } else { 629 xhci_warn(xhci, "Can't find new dequeue state, missing td\n"); 630 return -EINVAL; 631 } 632 } 633 634 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); 635 new_seg = ep_ring->deq_seg; 636 new_deq = ep_ring->dequeue; 637 638 /* 639 * Quirk: xHC write-back of the DCS field in the hardware dequeue 640 * pointer is wrong - use the cycle state of the TRB pointed to by 641 * the dequeue pointer. 642 */ 643 if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS && 644 !(ep->ep_state & EP_HAS_STREAMS)) 645 halted_seg = trb_in_td(xhci, td->start_seg, 646 td->first_trb, td->last_trb, 647 hw_dequeue & ~0xf, false); 648 if (halted_seg) { 649 index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) / 650 sizeof(*halted_trb); 651 halted_trb = &halted_seg->trbs[index]; 652 new_cycle = halted_trb->generic.field[3] & 0x1; 653 xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n", 654 (u8)(hw_dequeue & 0x1), index, new_cycle); 655 } else { 656 new_cycle = hw_dequeue & 0x1; 657 } 658 659 /* 660 * We want to find the pointer, segment and cycle state of the new trb 661 * (the one after current TD's last_trb). We know the cycle state at 662 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are 663 * found. 664 */ 665 do { 666 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) 667 == (dma_addr_t)(hw_dequeue & ~0xf)) { 668 cycle_found = true; 669 if (td_last_trb_found) 670 break; 671 } 672 if (new_deq == td->last_trb) 673 td_last_trb_found = true; 674 675 if (cycle_found && trb_is_link(new_deq) && 676 link_trb_toggles_cycle(new_deq)) 677 new_cycle ^= 0x1; 678 679 next_trb(xhci, ep_ring, &new_seg, &new_deq); 680 681 /* Search wrapped around, bail out */ 682 if (new_deq == ep->ring->dequeue) { 683 xhci_err(xhci, "Error: Failed finding new dequeue state\n"); 684 return -EINVAL; 685 } 686 687 } while (!cycle_found || !td_last_trb_found); 688 689 deq_found: 690 691 /* Don't update the ring cycle state for the producer (us). */ 692 addr = xhci_trb_virt_to_dma(new_seg, new_deq); 693 if (addr == 0) { 694 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n"); 695 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq); 696 return -EINVAL; 697 } 698 699 if ((ep->ep_state & SET_DEQ_PENDING)) { 700 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n", 701 &addr); 702 return -EBUSY; 703 } 704 705 /* This function gets called from contexts where it cannot sleep */ 706 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC); 707 if (!cmd) { 708 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr); 709 return -ENOMEM; 710 } 711 712 if (stream_id) 713 trb_sct = SCT_FOR_TRB(SCT_PRI_TR); 714 ret = queue_command(xhci, cmd, 715 lower_32_bits(addr) | trb_sct | new_cycle, 716 upper_32_bits(addr), 717 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) | 718 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false); 719 if (ret < 0) { 720 xhci_free_command(xhci, cmd); 721 return ret; 722 } 723 ep->queued_deq_seg = new_seg; 724 ep->queued_deq_ptr = new_deq; 725 726 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 727 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle); 728 729 /* Stop the TD queueing code from ringing the doorbell until 730 * this command completes. The HC won't set the dequeue pointer 731 * if the ring is running, and ringing the doorbell starts the 732 * ring running. 733 */ 734 ep->ep_state |= SET_DEQ_PENDING; 735 xhci_ring_cmd_db(xhci); 736 return 0; 737 } 738 739 /* flip_cycle means flip the cycle bit of all but the first and last TRB. 740 * (The last TRB actually points to the ring enqueue pointer, which is not part 741 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. 742 */ 743 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 744 struct xhci_td *td, bool flip_cycle) 745 { 746 struct xhci_segment *seg = td->start_seg; 747 union xhci_trb *trb = td->first_trb; 748 749 while (1) { 750 trb_to_noop(trb, TRB_TR_NOOP); 751 752 /* flip cycle if asked to */ 753 if (flip_cycle && trb != td->first_trb && trb != td->last_trb) 754 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); 755 756 if (trb == td->last_trb) 757 break; 758 759 next_trb(xhci, ep_ring, &seg, &trb); 760 } 761 } 762 763 /* 764 * Must be called with xhci->lock held in interrupt context, 765 * releases and re-acquires xhci->lock 766 */ 767 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 768 struct xhci_td *cur_td, int status) 769 { 770 struct urb *urb = cur_td->urb; 771 struct urb_priv *urb_priv = urb->hcpriv; 772 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); 773 774 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 775 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 776 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 777 if (xhci->quirks & XHCI_AMD_PLL_FIX) 778 usb_amd_quirk_pll_enable(); 779 } 780 } 781 xhci_urb_free_priv(urb_priv); 782 usb_hcd_unlink_urb_from_ep(hcd, urb); 783 trace_xhci_urb_giveback(urb); 784 usb_hcd_giveback_urb(hcd, urb, status); 785 } 786 787 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, 788 struct xhci_ring *ring, struct xhci_td *td) 789 { 790 struct device *dev = xhci_to_hcd(xhci)->self.controller; 791 struct xhci_segment *seg = td->bounce_seg; 792 struct urb *urb = td->urb; 793 size_t len; 794 795 if (!ring || !seg || !urb) 796 return; 797 798 if (usb_urb_dir_out(urb)) { 799 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 800 DMA_TO_DEVICE); 801 return; 802 } 803 804 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 805 DMA_FROM_DEVICE); 806 /* for in tranfers we need to copy the data from bounce to sg */ 807 if (urb->num_sgs) { 808 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf, 809 seg->bounce_len, seg->bounce_offs); 810 if (len != seg->bounce_len) 811 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n", 812 len, seg->bounce_len); 813 } else { 814 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf, 815 seg->bounce_len); 816 } 817 seg->bounce_len = 0; 818 seg->bounce_offs = 0; 819 } 820 821 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, 822 struct xhci_ring *ep_ring, int status) 823 { 824 struct urb *urb = NULL; 825 826 /* Clean up the endpoint's TD list */ 827 urb = td->urb; 828 829 /* if a bounce buffer was used to align this td then unmap it */ 830 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); 831 832 /* Do one last check of the actual transfer length. 833 * If the host controller said we transferred more data than the buffer 834 * length, urb->actual_length will be a very big number (since it's 835 * unsigned). Play it safe and say we didn't transfer anything. 836 */ 837 if (urb->actual_length > urb->transfer_buffer_length) { 838 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", 839 urb->transfer_buffer_length, urb->actual_length); 840 urb->actual_length = 0; 841 status = 0; 842 } 843 /* TD might be removed from td_list if we are giving back a cancelled URB */ 844 if (!list_empty(&td->td_list)) 845 list_del_init(&td->td_list); 846 /* Giving back a cancelled URB, or if a slated TD completed anyway */ 847 if (!list_empty(&td->cancelled_td_list)) 848 list_del_init(&td->cancelled_td_list); 849 850 inc_td_cnt(urb); 851 /* Giveback the urb when all the tds are completed */ 852 if (last_td_in_urb(td)) { 853 if ((urb->actual_length != urb->transfer_buffer_length && 854 (urb->transfer_flags & URB_SHORT_NOT_OK)) || 855 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) 856 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", 857 urb, urb->actual_length, 858 urb->transfer_buffer_length, status); 859 860 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ 861 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 862 status = 0; 863 xhci_giveback_urb_in_irq(xhci, td, status); 864 } 865 866 return 0; 867 } 868 869 870 /* Complete the cancelled URBs we unlinked from td_list. */ 871 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep) 872 { 873 struct xhci_ring *ring; 874 struct xhci_td *td, *tmp_td; 875 876 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, 877 cancelled_td_list) { 878 879 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); 880 881 if (td->cancel_status == TD_CLEARED) { 882 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", 883 __func__, td->urb); 884 xhci_td_cleanup(ep->xhci, td, ring, td->status); 885 } else { 886 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", 887 __func__, td->urb, td->cancel_status); 888 } 889 if (ep->xhci->xhc_state & XHCI_STATE_DYING) 890 return; 891 } 892 } 893 894 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id, 895 unsigned int ep_index, enum xhci_ep_reset_type reset_type) 896 { 897 struct xhci_command *command; 898 int ret = 0; 899 900 command = xhci_alloc_command(xhci, false, GFP_ATOMIC); 901 if (!command) { 902 ret = -ENOMEM; 903 goto done; 904 } 905 906 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n", 907 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft", 908 ep_index, slot_id); 909 910 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); 911 done: 912 if (ret) 913 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n", 914 slot_id, ep_index, ret); 915 return ret; 916 } 917 918 static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci, 919 struct xhci_virt_ep *ep, 920 struct xhci_td *td, 921 enum xhci_ep_reset_type reset_type) 922 { 923 unsigned int slot_id = ep->vdev->slot_id; 924 int err; 925 926 /* 927 * Avoid resetting endpoint if link is inactive. Can cause host hang. 928 * Device will be reset soon to recover the link so don't do anything 929 */ 930 if (ep->vdev->flags & VDEV_PORT_ERROR) 931 return -ENODEV; 932 933 /* add td to cancelled list and let reset ep handler take care of it */ 934 if (reset_type == EP_HARD_RESET) { 935 ep->ep_state |= EP_HARD_CLEAR_TOGGLE; 936 if (td && list_empty(&td->cancelled_td_list)) { 937 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); 938 td->cancel_status = TD_HALTED; 939 } 940 } 941 942 if (ep->ep_state & EP_HALTED) { 943 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n", 944 ep->ep_index); 945 return 0; 946 } 947 948 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type); 949 if (err) 950 return err; 951 952 ep->ep_state |= EP_HALTED; 953 954 xhci_ring_cmd_db(xhci); 955 956 return 0; 957 } 958 959 /* 960 * Fix up the ep ring first, so HW stops executing cancelled TDs. 961 * We have the xHCI lock, so nothing can modify this list until we drop it. 962 * We're also in the event handler, so we can't get re-interrupted if another 963 * Stop Endpoint command completes. 964 * 965 * only call this when ring is not in a running state 966 */ 967 968 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep) 969 { 970 struct xhci_hcd *xhci; 971 struct xhci_td *td = NULL; 972 struct xhci_td *tmp_td = NULL; 973 struct xhci_td *cached_td = NULL; 974 struct xhci_ring *ring; 975 u64 hw_deq; 976 unsigned int slot_id = ep->vdev->slot_id; 977 int err; 978 979 xhci = ep->xhci; 980 981 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { 982 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 983 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p", 984 (unsigned long long)xhci_trb_virt_to_dma( 985 td->start_seg, td->first_trb), 986 td->urb->stream_id, td->urb); 987 list_del_init(&td->td_list); 988 ring = xhci_urb_to_transfer_ring(xhci, td->urb); 989 if (!ring) { 990 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n", 991 td->urb, td->urb->stream_id); 992 continue; 993 } 994 /* 995 * If a ring stopped on the TD we need to cancel then we have to 996 * move the xHC endpoint ring dequeue pointer past this TD. 997 * Rings halted due to STALL may show hw_deq is past the stalled 998 * TD, but still require a set TR Deq command to flush xHC cache. 999 */ 1000 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index, 1001 td->urb->stream_id); 1002 hw_deq &= ~0xf; 1003 1004 if (td->cancel_status == TD_HALTED || 1005 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) { 1006 switch (td->cancel_status) { 1007 case TD_CLEARED: /* TD is already no-op */ 1008 case TD_CLEARING_CACHE: /* set TR deq command already queued */ 1009 break; 1010 case TD_DIRTY: /* TD is cached, clear it */ 1011 case TD_HALTED: 1012 td->cancel_status = TD_CLEARING_CACHE; 1013 if (cached_td) 1014 /* FIXME stream case, several stopped rings */ 1015 xhci_dbg(xhci, 1016 "Move dq past stream %u URB %p instead of stream %u URB %p\n", 1017 td->urb->stream_id, td->urb, 1018 cached_td->urb->stream_id, cached_td->urb); 1019 cached_td = td; 1020 break; 1021 } 1022 } else { 1023 td_to_noop(xhci, ring, td, false); 1024 td->cancel_status = TD_CLEARED; 1025 } 1026 } 1027 1028 /* If there's no need to move the dequeue pointer then we're done */ 1029 if (!cached_td) 1030 return 0; 1031 1032 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index, 1033 cached_td->urb->stream_id, 1034 cached_td); 1035 if (err) { 1036 /* Failed to move past cached td, just set cached TDs to no-op */ 1037 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { 1038 if (td->cancel_status != TD_CLEARING_CACHE) 1039 continue; 1040 xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n", 1041 td->urb); 1042 td_to_noop(xhci, ring, td, false); 1043 td->cancel_status = TD_CLEARED; 1044 } 1045 } 1046 return 0; 1047 } 1048 1049 /* 1050 * Returns the TD the endpoint ring halted on. 1051 * Only call for non-running rings without streams. 1052 */ 1053 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep) 1054 { 1055 struct xhci_td *td; 1056 u64 hw_deq; 1057 1058 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */ 1059 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0); 1060 hw_deq &= ~0xf; 1061 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list); 1062 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb, 1063 td->last_trb, hw_deq, false)) 1064 return td; 1065 } 1066 return NULL; 1067 } 1068 1069 /* 1070 * When we get a command completion for a Stop Endpoint Command, we need to 1071 * unlink any cancelled TDs from the ring. There are two ways to do that: 1072 * 1073 * 1. If the HW was in the middle of processing the TD that needs to be 1074 * cancelled, then we must move the ring's dequeue pointer past the last TRB 1075 * in the TD with a Set Dequeue Pointer Command. 1076 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain 1077 * bit cleared) so that the HW will skip over them. 1078 */ 1079 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, 1080 union xhci_trb *trb, u32 comp_code) 1081 { 1082 unsigned int ep_index; 1083 struct xhci_virt_ep *ep; 1084 struct xhci_ep_ctx *ep_ctx; 1085 struct xhci_td *td = NULL; 1086 enum xhci_ep_reset_type reset_type; 1087 struct xhci_command *command; 1088 int err; 1089 1090 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { 1091 if (!xhci->devs[slot_id]) 1092 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n", 1093 slot_id); 1094 return; 1095 } 1096 1097 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1098 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1099 if (!ep) 1100 return; 1101 1102 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 1103 1104 trace_xhci_handle_cmd_stop_ep(ep_ctx); 1105 1106 if (comp_code == COMP_CONTEXT_STATE_ERROR) { 1107 /* 1108 * If stop endpoint command raced with a halting endpoint we need to 1109 * reset the host side endpoint first. 1110 * If the TD we halted on isn't cancelled the TD should be given back 1111 * with a proper error code, and the ring dequeue moved past the TD. 1112 * If streams case we can't find hw_deq, or the TD we halted on so do a 1113 * soft reset. 1114 * 1115 * Proper error code is unknown here, it would be -EPIPE if device side 1116 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error) 1117 * We use -EPROTO, if device is stalled it should return a stall error on 1118 * next transfer, which then will return -EPIPE, and device side stall is 1119 * noted and cleared by class driver. 1120 */ 1121 switch (GET_EP_CTX_STATE(ep_ctx)) { 1122 case EP_STATE_HALTED: 1123 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n"); 1124 if (ep->ep_state & EP_HAS_STREAMS) { 1125 reset_type = EP_SOFT_RESET; 1126 } else { 1127 reset_type = EP_HARD_RESET; 1128 td = find_halted_td(ep); 1129 if (td) 1130 td->status = -EPROTO; 1131 } 1132 /* reset ep, reset handler cleans up cancelled tds */ 1133 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type); 1134 if (err) 1135 break; 1136 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1137 return; 1138 case EP_STATE_RUNNING: 1139 /* Race, HW handled stop ep cmd before ep was running */ 1140 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n"); 1141 1142 command = xhci_alloc_command(xhci, false, GFP_ATOMIC); 1143 if (!command) { 1144 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1145 return; 1146 } 1147 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0); 1148 xhci_ring_cmd_db(xhci); 1149 1150 return; 1151 default: 1152 break; 1153 } 1154 } 1155 1156 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */ 1157 xhci_invalidate_cancelled_tds(ep); 1158 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1159 1160 /* Otherwise ring the doorbell(s) to restart queued transfers */ 1161 xhci_giveback_invalidated_tds(ep); 1162 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1163 } 1164 1165 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) 1166 { 1167 struct xhci_td *cur_td; 1168 struct xhci_td *tmp; 1169 1170 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { 1171 list_del_init(&cur_td->td_list); 1172 1173 if (!list_empty(&cur_td->cancelled_td_list)) 1174 list_del_init(&cur_td->cancelled_td_list); 1175 1176 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); 1177 1178 inc_td_cnt(cur_td->urb); 1179 if (last_td_in_urb(cur_td)) 1180 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 1181 } 1182 } 1183 1184 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, 1185 int slot_id, int ep_index) 1186 { 1187 struct xhci_td *cur_td; 1188 struct xhci_td *tmp; 1189 struct xhci_virt_ep *ep; 1190 struct xhci_ring *ring; 1191 1192 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1193 if (!ep) 1194 return; 1195 1196 if ((ep->ep_state & EP_HAS_STREAMS) || 1197 (ep->ep_state & EP_GETTING_NO_STREAMS)) { 1198 int stream_id; 1199 1200 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 1201 stream_id++) { 1202 ring = ep->stream_info->stream_rings[stream_id]; 1203 if (!ring) 1204 continue; 1205 1206 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1207 "Killing URBs for slot ID %u, ep index %u, stream %u", 1208 slot_id, ep_index, stream_id); 1209 xhci_kill_ring_urbs(xhci, ring); 1210 } 1211 } else { 1212 ring = ep->ring; 1213 if (!ring) 1214 return; 1215 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1216 "Killing URBs for slot ID %u, ep index %u", 1217 slot_id, ep_index); 1218 xhci_kill_ring_urbs(xhci, ring); 1219 } 1220 1221 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, 1222 cancelled_td_list) { 1223 list_del_init(&cur_td->cancelled_td_list); 1224 inc_td_cnt(cur_td->urb); 1225 1226 if (last_td_in_urb(cur_td)) 1227 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 1228 } 1229 } 1230 1231 /* 1232 * host controller died, register read returns 0xffffffff 1233 * Complete pending commands, mark them ABORTED. 1234 * URBs need to be given back as usb core might be waiting with device locks 1235 * held for the URBs to finish during device disconnect, blocking host remove. 1236 * 1237 * Call with xhci->lock held. 1238 * lock is relased and re-acquired while giving back urb. 1239 */ 1240 void xhci_hc_died(struct xhci_hcd *xhci) 1241 { 1242 int i, j; 1243 1244 if (xhci->xhc_state & XHCI_STATE_DYING) 1245 return; 1246 1247 xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); 1248 xhci->xhc_state |= XHCI_STATE_DYING; 1249 1250 xhci_cleanup_command_queue(xhci); 1251 1252 /* return any pending urbs, remove may be waiting for them */ 1253 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 1254 if (!xhci->devs[i]) 1255 continue; 1256 for (j = 0; j < 31; j++) 1257 xhci_kill_endpoint_urbs(xhci, i, j); 1258 } 1259 1260 /* inform usb core hc died if PCI remove isn't already handling it */ 1261 if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) 1262 usb_hc_died(xhci_to_hcd(xhci)); 1263 } 1264 1265 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, 1266 struct xhci_virt_device *dev, 1267 struct xhci_ring *ep_ring, 1268 unsigned int ep_index) 1269 { 1270 union xhci_trb *dequeue_temp; 1271 int num_trbs_free_temp; 1272 bool revert = false; 1273 1274 num_trbs_free_temp = ep_ring->num_trbs_free; 1275 dequeue_temp = ep_ring->dequeue; 1276 1277 /* If we get two back-to-back stalls, and the first stalled transfer 1278 * ends just before a link TRB, the dequeue pointer will be left on 1279 * the link TRB by the code in the while loop. So we have to update 1280 * the dequeue pointer one segment further, or we'll jump off 1281 * the segment into la-la-land. 1282 */ 1283 if (trb_is_link(ep_ring->dequeue)) { 1284 ep_ring->deq_seg = ep_ring->deq_seg->next; 1285 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1286 } 1287 1288 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { 1289 /* We have more usable TRBs */ 1290 ep_ring->num_trbs_free++; 1291 ep_ring->dequeue++; 1292 if (trb_is_link(ep_ring->dequeue)) { 1293 if (ep_ring->dequeue == 1294 dev->eps[ep_index].queued_deq_ptr) 1295 break; 1296 ep_ring->deq_seg = ep_ring->deq_seg->next; 1297 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1298 } 1299 if (ep_ring->dequeue == dequeue_temp) { 1300 revert = true; 1301 break; 1302 } 1303 } 1304 1305 if (revert) { 1306 xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); 1307 ep_ring->num_trbs_free = num_trbs_free_temp; 1308 } 1309 } 1310 1311 /* 1312 * When we get a completion for a Set Transfer Ring Dequeue Pointer command, 1313 * we need to clear the set deq pending flag in the endpoint ring state, so that 1314 * the TD queueing code can ring the doorbell again. We also need to ring the 1315 * endpoint doorbell to restart the ring, but only if there aren't more 1316 * cancellations pending. 1317 */ 1318 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, 1319 union xhci_trb *trb, u32 cmd_comp_code) 1320 { 1321 unsigned int ep_index; 1322 unsigned int stream_id; 1323 struct xhci_ring *ep_ring; 1324 struct xhci_virt_ep *ep; 1325 struct xhci_ep_ctx *ep_ctx; 1326 struct xhci_slot_ctx *slot_ctx; 1327 struct xhci_td *td, *tmp_td; 1328 1329 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1330 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); 1331 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1332 if (!ep) 1333 return; 1334 1335 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id); 1336 if (!ep_ring) { 1337 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", 1338 stream_id); 1339 /* XXX: Harmless??? */ 1340 goto cleanup; 1341 } 1342 1343 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 1344 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); 1345 trace_xhci_handle_cmd_set_deq(slot_ctx); 1346 trace_xhci_handle_cmd_set_deq_ep(ep_ctx); 1347 1348 if (cmd_comp_code != COMP_SUCCESS) { 1349 unsigned int ep_state; 1350 unsigned int slot_state; 1351 1352 switch (cmd_comp_code) { 1353 case COMP_TRB_ERROR: 1354 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); 1355 break; 1356 case COMP_CONTEXT_STATE_ERROR: 1357 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); 1358 ep_state = GET_EP_CTX_STATE(ep_ctx); 1359 slot_state = le32_to_cpu(slot_ctx->dev_state); 1360 slot_state = GET_SLOT_STATE(slot_state); 1361 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1362 "Slot state = %u, EP state = %u", 1363 slot_state, ep_state); 1364 break; 1365 case COMP_SLOT_NOT_ENABLED_ERROR: 1366 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", 1367 slot_id); 1368 break; 1369 default: 1370 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", 1371 cmd_comp_code); 1372 break; 1373 } 1374 /* OK what do we do now? The endpoint state is hosed, and we 1375 * should never get to this point if the synchronization between 1376 * queueing, and endpoint state are correct. This might happen 1377 * if the device gets disconnected after we've finished 1378 * cancelling URBs, which might not be an error... 1379 */ 1380 } else { 1381 u64 deq; 1382 /* 4.6.10 deq ptr is written to the stream ctx for streams */ 1383 if (ep->ep_state & EP_HAS_STREAMS) { 1384 struct xhci_stream_ctx *ctx = 1385 &ep->stream_info->stream_ctx_array[stream_id]; 1386 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; 1387 } else { 1388 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; 1389 } 1390 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1391 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); 1392 if (xhci_trb_virt_to_dma(ep->queued_deq_seg, 1393 ep->queued_deq_ptr) == deq) { 1394 /* Update the ring's dequeue segment and dequeue pointer 1395 * to reflect the new position. 1396 */ 1397 update_ring_for_set_deq_completion(xhci, ep->vdev, 1398 ep_ring, ep_index); 1399 } else { 1400 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); 1401 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", 1402 ep->queued_deq_seg, ep->queued_deq_ptr); 1403 } 1404 } 1405 /* HW cached TDs cleared from cache, give them back */ 1406 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, 1407 cancelled_td_list) { 1408 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); 1409 if (td->cancel_status == TD_CLEARING_CACHE) { 1410 td->cancel_status = TD_CLEARED; 1411 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", 1412 __func__, td->urb); 1413 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status); 1414 } else { 1415 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", 1416 __func__, td->urb, td->cancel_status); 1417 } 1418 } 1419 cleanup: 1420 ep->ep_state &= ~SET_DEQ_PENDING; 1421 ep->queued_deq_seg = NULL; 1422 ep->queued_deq_ptr = NULL; 1423 /* Restart any rings with pending URBs */ 1424 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1425 } 1426 1427 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, 1428 union xhci_trb *trb, u32 cmd_comp_code) 1429 { 1430 struct xhci_virt_ep *ep; 1431 struct xhci_ep_ctx *ep_ctx; 1432 unsigned int ep_index; 1433 1434 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1435 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 1436 if (!ep) 1437 return; 1438 1439 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 1440 trace_xhci_handle_cmd_reset_ep(ep_ctx); 1441 1442 /* This command will only fail if the endpoint wasn't halted, 1443 * but we don't care. 1444 */ 1445 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, 1446 "Ignoring reset ep completion code of %u", cmd_comp_code); 1447 1448 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */ 1449 xhci_invalidate_cancelled_tds(ep); 1450 1451 /* Clear our internal halted state */ 1452 ep->ep_state &= ~EP_HALTED; 1453 1454 xhci_giveback_invalidated_tds(ep); 1455 1456 /* if this was a soft reset, then restart */ 1457 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP) 1458 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1459 } 1460 1461 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, 1462 struct xhci_command *command, u32 cmd_comp_code) 1463 { 1464 if (cmd_comp_code == COMP_SUCCESS) 1465 command->slot_id = slot_id; 1466 else 1467 command->slot_id = 0; 1468 } 1469 1470 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) 1471 { 1472 struct xhci_virt_device *virt_dev; 1473 struct xhci_slot_ctx *slot_ctx; 1474 1475 virt_dev = xhci->devs[slot_id]; 1476 if (!virt_dev) 1477 return; 1478 1479 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); 1480 trace_xhci_handle_cmd_disable_slot(slot_ctx); 1481 1482 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) 1483 /* Delete default control endpoint resources */ 1484 xhci_free_device_endpoint_resources(xhci, virt_dev, true); 1485 } 1486 1487 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, 1488 u32 cmd_comp_code) 1489 { 1490 struct xhci_virt_device *virt_dev; 1491 struct xhci_input_control_ctx *ctrl_ctx; 1492 struct xhci_ep_ctx *ep_ctx; 1493 unsigned int ep_index; 1494 u32 add_flags; 1495 1496 /* 1497 * Configure endpoint commands can come from the USB core configuration 1498 * or alt setting changes, or when streams were being configured. 1499 */ 1500 1501 virt_dev = xhci->devs[slot_id]; 1502 if (!virt_dev) 1503 return; 1504 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); 1505 if (!ctrl_ctx) { 1506 xhci_warn(xhci, "Could not get input context, bad type.\n"); 1507 return; 1508 } 1509 1510 add_flags = le32_to_cpu(ctrl_ctx->add_flags); 1511 1512 /* Input ctx add_flags are the endpoint index plus one */ 1513 ep_index = xhci_last_valid_endpoint(add_flags) - 1; 1514 1515 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); 1516 trace_xhci_handle_cmd_config_ep(ep_ctx); 1517 1518 return; 1519 } 1520 1521 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) 1522 { 1523 struct xhci_virt_device *vdev; 1524 struct xhci_slot_ctx *slot_ctx; 1525 1526 vdev = xhci->devs[slot_id]; 1527 if (!vdev) 1528 return; 1529 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1530 trace_xhci_handle_cmd_addr_dev(slot_ctx); 1531 } 1532 1533 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id) 1534 { 1535 struct xhci_virt_device *vdev; 1536 struct xhci_slot_ctx *slot_ctx; 1537 1538 vdev = xhci->devs[slot_id]; 1539 if (!vdev) { 1540 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n", 1541 slot_id); 1542 return; 1543 } 1544 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1545 trace_xhci_handle_cmd_reset_dev(slot_ctx); 1546 1547 xhci_dbg(xhci, "Completed reset device command.\n"); 1548 } 1549 1550 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, 1551 struct xhci_event_cmd *event) 1552 { 1553 if (!(xhci->quirks & XHCI_NEC_HOST)) { 1554 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); 1555 return; 1556 } 1557 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1558 "NEC firmware version %2x.%02x", 1559 NEC_FW_MAJOR(le32_to_cpu(event->status)), 1560 NEC_FW_MINOR(le32_to_cpu(event->status))); 1561 } 1562 1563 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) 1564 { 1565 list_del(&cmd->cmd_list); 1566 1567 if (cmd->completion) { 1568 cmd->status = status; 1569 complete(cmd->completion); 1570 } else { 1571 kfree(cmd); 1572 } 1573 } 1574 1575 void xhci_cleanup_command_queue(struct xhci_hcd *xhci) 1576 { 1577 struct xhci_command *cur_cmd, *tmp_cmd; 1578 xhci->current_cmd = NULL; 1579 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) 1580 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); 1581 } 1582 1583 void xhci_handle_command_timeout(struct work_struct *work) 1584 { 1585 struct xhci_hcd *xhci; 1586 unsigned long flags; 1587 char str[XHCI_MSG_MAX]; 1588 u64 hw_ring_state; 1589 u32 cmd_field3; 1590 u32 usbsts; 1591 1592 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); 1593 1594 spin_lock_irqsave(&xhci->lock, flags); 1595 1596 /* 1597 * If timeout work is pending, or current_cmd is NULL, it means we 1598 * raced with command completion. Command is handled so just return. 1599 */ 1600 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { 1601 spin_unlock_irqrestore(&xhci->lock, flags); 1602 return; 1603 } 1604 1605 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]); 1606 usbsts = readl(&xhci->op_regs->status); 1607 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts)); 1608 1609 /* Bail out and tear down xhci if a stop endpoint command failed */ 1610 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) { 1611 struct xhci_virt_ep *ep; 1612 1613 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n"); 1614 1615 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3), 1616 TRB_TO_EP_INDEX(cmd_field3)); 1617 if (ep) 1618 ep->ep_state &= ~EP_STOP_CMD_PENDING; 1619 1620 xhci_halt(xhci); 1621 xhci_hc_died(xhci); 1622 goto time_out_completed; 1623 } 1624 1625 /* mark this command to be cancelled */ 1626 xhci->current_cmd->status = COMP_COMMAND_ABORTED; 1627 1628 /* Make sure command ring is running before aborting it */ 1629 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 1630 if (hw_ring_state == ~(u64)0) { 1631 xhci_hc_died(xhci); 1632 goto time_out_completed; 1633 } 1634 1635 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && 1636 (hw_ring_state & CMD_RING_RUNNING)) { 1637 /* Prevent new doorbell, and start command abort */ 1638 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; 1639 xhci_dbg(xhci, "Command timeout\n"); 1640 xhci_abort_cmd_ring(xhci, flags); 1641 goto time_out_completed; 1642 } 1643 1644 /* host removed. Bail out */ 1645 if (xhci->xhc_state & XHCI_STATE_REMOVING) { 1646 xhci_dbg(xhci, "host removed, ring start fail?\n"); 1647 xhci_cleanup_command_queue(xhci); 1648 1649 goto time_out_completed; 1650 } 1651 1652 /* command timeout on stopped ring, ring can't be aborted */ 1653 xhci_dbg(xhci, "Command timeout on stopped ring\n"); 1654 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); 1655 1656 time_out_completed: 1657 spin_unlock_irqrestore(&xhci->lock, flags); 1658 return; 1659 } 1660 1661 static void handle_cmd_completion(struct xhci_hcd *xhci, 1662 struct xhci_event_cmd *event) 1663 { 1664 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1665 u64 cmd_dma; 1666 dma_addr_t cmd_dequeue_dma; 1667 u32 cmd_comp_code; 1668 union xhci_trb *cmd_trb; 1669 struct xhci_command *cmd; 1670 u32 cmd_type; 1671 1672 if (slot_id >= MAX_HC_SLOTS) { 1673 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); 1674 return; 1675 } 1676 1677 cmd_dma = le64_to_cpu(event->cmd_trb); 1678 cmd_trb = xhci->cmd_ring->dequeue; 1679 1680 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); 1681 1682 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 1683 cmd_trb); 1684 /* 1685 * Check whether the completion event is for our internal kept 1686 * command. 1687 */ 1688 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { 1689 xhci_warn(xhci, 1690 "ERROR mismatched command completion event\n"); 1691 return; 1692 } 1693 1694 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); 1695 1696 cancel_delayed_work(&xhci->cmd_timer); 1697 1698 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); 1699 1700 /* If CMD ring stopped we own the trbs between enqueue and dequeue */ 1701 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { 1702 complete_all(&xhci->cmd_ring_stop_completion); 1703 return; 1704 } 1705 1706 if (cmd->command_trb != xhci->cmd_ring->dequeue) { 1707 xhci_err(xhci, 1708 "Command completion event does not match command\n"); 1709 return; 1710 } 1711 1712 /* 1713 * Host aborted the command ring, check if the current command was 1714 * supposed to be aborted, otherwise continue normally. 1715 * The command ring is stopped now, but the xHC will issue a Command 1716 * Ring Stopped event which will cause us to restart it. 1717 */ 1718 if (cmd_comp_code == COMP_COMMAND_ABORTED) { 1719 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; 1720 if (cmd->status == COMP_COMMAND_ABORTED) { 1721 if (xhci->current_cmd == cmd) 1722 xhci->current_cmd = NULL; 1723 goto event_handled; 1724 } 1725 } 1726 1727 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); 1728 switch (cmd_type) { 1729 case TRB_ENABLE_SLOT: 1730 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); 1731 break; 1732 case TRB_DISABLE_SLOT: 1733 xhci_handle_cmd_disable_slot(xhci, slot_id); 1734 break; 1735 case TRB_CONFIG_EP: 1736 if (!cmd->completion) 1737 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code); 1738 break; 1739 case TRB_EVAL_CONTEXT: 1740 break; 1741 case TRB_ADDR_DEV: 1742 xhci_handle_cmd_addr_dev(xhci, slot_id); 1743 break; 1744 case TRB_STOP_RING: 1745 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1746 le32_to_cpu(cmd_trb->generic.field[3]))); 1747 if (!cmd->completion) 1748 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, 1749 cmd_comp_code); 1750 break; 1751 case TRB_SET_DEQ: 1752 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1753 le32_to_cpu(cmd_trb->generic.field[3]))); 1754 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); 1755 break; 1756 case TRB_CMD_NOOP: 1757 /* Is this an aborted command turned to NO-OP? */ 1758 if (cmd->status == COMP_COMMAND_RING_STOPPED) 1759 cmd_comp_code = COMP_COMMAND_RING_STOPPED; 1760 break; 1761 case TRB_RESET_EP: 1762 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1763 le32_to_cpu(cmd_trb->generic.field[3]))); 1764 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); 1765 break; 1766 case TRB_RESET_DEV: 1767 /* SLOT_ID field in reset device cmd completion event TRB is 0. 1768 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) 1769 */ 1770 slot_id = TRB_TO_SLOT_ID( 1771 le32_to_cpu(cmd_trb->generic.field[3])); 1772 xhci_handle_cmd_reset_dev(xhci, slot_id); 1773 break; 1774 case TRB_NEC_GET_FW: 1775 xhci_handle_cmd_nec_get_fw(xhci, event); 1776 break; 1777 default: 1778 /* Skip over unknown commands on the event ring */ 1779 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); 1780 break; 1781 } 1782 1783 /* restart timer if this wasn't the last command */ 1784 if (!list_is_singular(&xhci->cmd_list)) { 1785 xhci->current_cmd = list_first_entry(&cmd->cmd_list, 1786 struct xhci_command, cmd_list); 1787 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 1788 } else if (xhci->current_cmd == cmd) { 1789 xhci->current_cmd = NULL; 1790 } 1791 1792 event_handled: 1793 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); 1794 1795 inc_deq(xhci, xhci->cmd_ring); 1796 } 1797 1798 static void handle_vendor_event(struct xhci_hcd *xhci, 1799 union xhci_trb *event, u32 trb_type) 1800 { 1801 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); 1802 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) 1803 handle_cmd_completion(xhci, &event->event_cmd); 1804 } 1805 1806 static void handle_device_notification(struct xhci_hcd *xhci, 1807 union xhci_trb *event) 1808 { 1809 u32 slot_id; 1810 struct usb_device *udev; 1811 1812 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); 1813 if (!xhci->devs[slot_id]) { 1814 xhci_warn(xhci, "Device Notification event for " 1815 "unused slot %u\n", slot_id); 1816 return; 1817 } 1818 1819 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", 1820 slot_id); 1821 udev = xhci->devs[slot_id]->udev; 1822 if (udev && udev->parent) 1823 usb_wakeup_notification(udev->parent, udev->portnum); 1824 } 1825 1826 /* 1827 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI 1828 * Controller. 1829 * As per ThunderX2errata-129 USB 2 device may come up as USB 1 1830 * If a connection to a USB 1 device is followed by another connection 1831 * to a USB 2 device. 1832 * 1833 * Reset the PHY after the USB device is disconnected if device speed 1834 * is less than HCD_USB3. 1835 * Retry the reset sequence max of 4 times checking the PLL lock status. 1836 * 1837 */ 1838 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) 1839 { 1840 struct usb_hcd *hcd = xhci_to_hcd(xhci); 1841 u32 pll_lock_check; 1842 u32 retry_count = 4; 1843 1844 do { 1845 /* Assert PHY reset */ 1846 writel(0x6F, hcd->regs + 0x1048); 1847 udelay(10); 1848 /* De-assert the PHY reset */ 1849 writel(0x7F, hcd->regs + 0x1048); 1850 udelay(200); 1851 pll_lock_check = readl(hcd->regs + 0x1070); 1852 } while (!(pll_lock_check & 0x1) && --retry_count); 1853 } 1854 1855 static void handle_port_status(struct xhci_hcd *xhci, 1856 struct xhci_interrupter *ir, 1857 union xhci_trb *event) 1858 { 1859 struct usb_hcd *hcd; 1860 u32 port_id; 1861 u32 portsc, cmd_reg; 1862 int max_ports; 1863 int slot_id; 1864 unsigned int hcd_portnum; 1865 struct xhci_bus_state *bus_state; 1866 bool bogus_port_status = false; 1867 struct xhci_port *port; 1868 1869 /* Port status change events always have a successful completion code */ 1870 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) 1871 xhci_warn(xhci, 1872 "WARN: xHC returned failed port status event\n"); 1873 1874 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); 1875 max_ports = HCS_MAX_PORTS(xhci->hcs_params1); 1876 1877 if ((port_id <= 0) || (port_id > max_ports)) { 1878 xhci_warn(xhci, "Port change event with invalid port ID %d\n", 1879 port_id); 1880 inc_deq(xhci, ir->event_ring); 1881 return; 1882 } 1883 1884 port = &xhci->hw_ports[port_id - 1]; 1885 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) { 1886 xhci_warn(xhci, "Port change event, no port for port ID %u\n", 1887 port_id); 1888 bogus_port_status = true; 1889 goto cleanup; 1890 } 1891 1892 /* We might get interrupts after shared_hcd is removed */ 1893 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) { 1894 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n"); 1895 bogus_port_status = true; 1896 goto cleanup; 1897 } 1898 1899 hcd = port->rhub->hcd; 1900 bus_state = &port->rhub->bus_state; 1901 hcd_portnum = port->hcd_portnum; 1902 portsc = readl(port->addr); 1903 1904 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n", 1905 hcd->self.busnum, hcd_portnum + 1, port_id, portsc); 1906 1907 trace_xhci_handle_port_status(hcd_portnum, portsc); 1908 1909 if (hcd->state == HC_STATE_SUSPENDED) { 1910 xhci_dbg(xhci, "resume root hub\n"); 1911 usb_hcd_resume_root_hub(hcd); 1912 } 1913 1914 if (hcd->speed >= HCD_USB3 && 1915 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) { 1916 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); 1917 if (slot_id && xhci->devs[slot_id]) 1918 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR; 1919 } 1920 1921 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) { 1922 xhci_dbg(xhci, "port resume event for port %d\n", port_id); 1923 1924 cmd_reg = readl(&xhci->op_regs->command); 1925 if (!(cmd_reg & CMD_RUN)) { 1926 xhci_warn(xhci, "xHC is not running.\n"); 1927 goto cleanup; 1928 } 1929 1930 if (DEV_SUPERSPEED_ANY(portsc)) { 1931 xhci_dbg(xhci, "remote wake SS port %d\n", port_id); 1932 /* Set a flag to say the port signaled remote wakeup, 1933 * so we can tell the difference between the end of 1934 * device and host initiated resume. 1935 */ 1936 bus_state->port_remote_wakeup |= 1 << hcd_portnum; 1937 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 1938 usb_hcd_start_port_resume(&hcd->self, hcd_portnum); 1939 xhci_set_link_state(xhci, port, XDEV_U0); 1940 /* Need to wait until the next link state change 1941 * indicates the device is actually in U0. 1942 */ 1943 bogus_port_status = true; 1944 goto cleanup; 1945 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) { 1946 xhci_dbg(xhci, "resume HS port %d\n", port_id); 1947 port->resume_timestamp = jiffies + 1948 msecs_to_jiffies(USB_RESUME_TIMEOUT); 1949 set_bit(hcd_portnum, &bus_state->resuming_ports); 1950 /* Do the rest in GetPortStatus after resume time delay. 1951 * Avoid polling roothub status before that so that a 1952 * usb device auto-resume latency around ~40ms. 1953 */ 1954 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1955 mod_timer(&hcd->rh_timer, 1956 port->resume_timestamp); 1957 usb_hcd_start_port_resume(&hcd->self, hcd_portnum); 1958 bogus_port_status = true; 1959 } 1960 } 1961 1962 if ((portsc & PORT_PLC) && 1963 DEV_SUPERSPEED_ANY(portsc) && 1964 ((portsc & PORT_PLS_MASK) == XDEV_U0 || 1965 (portsc & PORT_PLS_MASK) == XDEV_U1 || 1966 (portsc & PORT_PLS_MASK) == XDEV_U2)) { 1967 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); 1968 complete(&port->u3exit_done); 1969 /* We've just brought the device into U0/1/2 through either the 1970 * Resume state after a device remote wakeup, or through the 1971 * U3Exit state after a host-initiated resume. If it's a device 1972 * initiated remote wake, don't pass up the link state change, 1973 * so the roothub behavior is consistent with external 1974 * USB 3.0 hub behavior. 1975 */ 1976 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); 1977 if (slot_id && xhci->devs[slot_id]) 1978 xhci_ring_device(xhci, slot_id); 1979 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) { 1980 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 1981 usb_wakeup_notification(hcd->self.root_hub, 1982 hcd_portnum + 1); 1983 bogus_port_status = true; 1984 goto cleanup; 1985 } 1986 } 1987 1988 /* 1989 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or 1990 * RExit to a disconnect state). If so, let the driver know it's 1991 * out of the RExit state. 1992 */ 1993 if (hcd->speed < HCD_USB3 && port->rexit_active) { 1994 complete(&port->rexit_done); 1995 port->rexit_active = false; 1996 bogus_port_status = true; 1997 goto cleanup; 1998 } 1999 2000 if (hcd->speed < HCD_USB3) { 2001 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 2002 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && 2003 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) 2004 xhci_cavium_reset_phy_quirk(xhci); 2005 } 2006 2007 cleanup: 2008 /* Update event ring dequeue pointer before dropping the lock */ 2009 inc_deq(xhci, ir->event_ring); 2010 2011 /* Don't make the USB core poll the roothub if we got a bad port status 2012 * change event. Besides, at that point we can't tell which roothub 2013 * (USB 2.0 or USB 3.0) to kick. 2014 */ 2015 if (bogus_port_status) 2016 return; 2017 2018 /* 2019 * xHCI port-status-change events occur when the "or" of all the 2020 * status-change bits in the portsc register changes from 0 to 1. 2021 * New status changes won't cause an event if any other change 2022 * bits are still set. When an event occurs, switch over to 2023 * polling to avoid losing status changes. 2024 */ 2025 xhci_dbg(xhci, "%s: starting usb%d port polling.\n", 2026 __func__, hcd->self.busnum); 2027 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 2028 spin_unlock(&xhci->lock); 2029 /* Pass this up to the core */ 2030 usb_hcd_poll_rh_status(hcd); 2031 spin_lock(&xhci->lock); 2032 } 2033 2034 /* 2035 * This TD is defined by the TRBs starting at start_trb in start_seg and ending 2036 * at end_trb, which may be in another segment. If the suspect DMA address is a 2037 * TRB in this TD, this function returns that TRB's segment. Otherwise it 2038 * returns 0. 2039 */ 2040 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2041 struct xhci_segment *start_seg, 2042 union xhci_trb *start_trb, 2043 union xhci_trb *end_trb, 2044 dma_addr_t suspect_dma, 2045 bool debug) 2046 { 2047 dma_addr_t start_dma; 2048 dma_addr_t end_seg_dma; 2049 dma_addr_t end_trb_dma; 2050 struct xhci_segment *cur_seg; 2051 2052 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); 2053 cur_seg = start_seg; 2054 2055 do { 2056 if (start_dma == 0) 2057 return NULL; 2058 /* We may get an event for a Link TRB in the middle of a TD */ 2059 end_seg_dma = xhci_trb_virt_to_dma(cur_seg, 2060 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); 2061 /* If the end TRB isn't in this segment, this is set to 0 */ 2062 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); 2063 2064 if (debug) 2065 xhci_warn(xhci, 2066 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", 2067 (unsigned long long)suspect_dma, 2068 (unsigned long long)start_dma, 2069 (unsigned long long)end_trb_dma, 2070 (unsigned long long)cur_seg->dma, 2071 (unsigned long long)end_seg_dma); 2072 2073 if (end_trb_dma > 0) { 2074 /* The end TRB is in this segment, so suspect should be here */ 2075 if (start_dma <= end_trb_dma) { 2076 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) 2077 return cur_seg; 2078 } else { 2079 /* Case for one segment with 2080 * a TD wrapped around to the top 2081 */ 2082 if ((suspect_dma >= start_dma && 2083 suspect_dma <= end_seg_dma) || 2084 (suspect_dma >= cur_seg->dma && 2085 suspect_dma <= end_trb_dma)) 2086 return cur_seg; 2087 } 2088 return NULL; 2089 } else { 2090 /* Might still be somewhere in this segment */ 2091 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) 2092 return cur_seg; 2093 } 2094 cur_seg = cur_seg->next; 2095 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); 2096 } while (cur_seg != start_seg); 2097 2098 return NULL; 2099 } 2100 2101 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td, 2102 struct xhci_virt_ep *ep) 2103 { 2104 /* 2105 * As part of low/full-speed endpoint-halt processing 2106 * we must clear the TT buffer (USB 2.0 specification 11.17.5). 2107 */ 2108 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) && 2109 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) && 2110 !(ep->ep_state & EP_CLEARING_TT)) { 2111 ep->ep_state |= EP_CLEARING_TT; 2112 td->urb->ep->hcpriv = td->urb->dev; 2113 if (usb_hub_clear_tt_buffer(td->urb)) 2114 ep->ep_state &= ~EP_CLEARING_TT; 2115 } 2116 } 2117 2118 /* Check if an error has halted the endpoint ring. The class driver will 2119 * cleanup the halt for a non-default control endpoint if we indicate a stall. 2120 * However, a babble and other errors also halt the endpoint ring, and the class 2121 * driver won't clear the halt in that case, so we need to issue a Set Transfer 2122 * Ring Dequeue Pointer command manually. 2123 */ 2124 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, 2125 struct xhci_ep_ctx *ep_ctx, 2126 unsigned int trb_comp_code) 2127 { 2128 /* TRB completion codes that may require a manual halt cleanup */ 2129 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || 2130 trb_comp_code == COMP_BABBLE_DETECTED_ERROR || 2131 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) 2132 /* The 0.95 spec says a babbling control endpoint 2133 * is not halted. The 0.96 spec says it is. Some HW 2134 * claims to be 0.95 compliant, but it halts the control 2135 * endpoint anyway. Check if a babble halted the 2136 * endpoint. 2137 */ 2138 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) 2139 return 1; 2140 2141 return 0; 2142 } 2143 2144 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) 2145 { 2146 if (trb_comp_code >= 224 && trb_comp_code <= 255) { 2147 /* Vendor defined "informational" completion code, 2148 * treat as not-an-error. 2149 */ 2150 xhci_dbg(xhci, "Vendor defined info completion code %u\n", 2151 trb_comp_code); 2152 xhci_dbg(xhci, "Treating code as success.\n"); 2153 return 1; 2154 } 2155 return 0; 2156 } 2157 2158 static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2159 struct xhci_ring *ep_ring, struct xhci_td *td, 2160 u32 trb_comp_code) 2161 { 2162 struct xhci_ep_ctx *ep_ctx; 2163 int trbs_freed; 2164 2165 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); 2166 2167 switch (trb_comp_code) { 2168 case COMP_STOPPED_LENGTH_INVALID: 2169 case COMP_STOPPED_SHORT_PACKET: 2170 case COMP_STOPPED: 2171 /* 2172 * The "Stop Endpoint" completion will take care of any 2173 * stopped TDs. A stopped TD may be restarted, so don't update 2174 * the ring dequeue pointer or take this TD off any lists yet. 2175 */ 2176 return 0; 2177 case COMP_USB_TRANSACTION_ERROR: 2178 case COMP_BABBLE_DETECTED_ERROR: 2179 case COMP_SPLIT_TRANSACTION_ERROR: 2180 /* 2181 * If endpoint context state is not halted we might be 2182 * racing with a reset endpoint command issued by a unsuccessful 2183 * stop endpoint completion (context error). In that case the 2184 * td should be on the cancelled list, and EP_HALTED flag set. 2185 * 2186 * Or then it's not halted due to the 0.95 spec stating that a 2187 * babbling control endpoint should not halt. The 0.96 spec 2188 * again says it should. Some HW claims to be 0.95 compliant, 2189 * but it halts the control endpoint anyway. 2190 */ 2191 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) { 2192 /* 2193 * If EP_HALTED is set and TD is on the cancelled list 2194 * the TD and dequeue pointer will be handled by reset 2195 * ep command completion 2196 */ 2197 if ((ep->ep_state & EP_HALTED) && 2198 !list_empty(&td->cancelled_td_list)) { 2199 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n", 2200 (unsigned long long)xhci_trb_virt_to_dma( 2201 td->start_seg, td->first_trb)); 2202 return 0; 2203 } 2204 /* endpoint not halted, don't reset it */ 2205 break; 2206 } 2207 /* Almost same procedure as for STALL_ERROR below */ 2208 xhci_clear_hub_tt_buffer(xhci, td, ep); 2209 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET); 2210 return 0; 2211 case COMP_STALL_ERROR: 2212 /* 2213 * xhci internal endpoint state will go to a "halt" state for 2214 * any stall, including default control pipe protocol stall. 2215 * To clear the host side halt we need to issue a reset endpoint 2216 * command, followed by a set dequeue command to move past the 2217 * TD. 2218 * Class drivers clear the device side halt from a functional 2219 * stall later. Hub TT buffer should only be cleared for FS/LS 2220 * devices behind HS hubs for functional stalls. 2221 */ 2222 if (ep->ep_index != 0) 2223 xhci_clear_hub_tt_buffer(xhci, td, ep); 2224 2225 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET); 2226 2227 return 0; /* xhci_handle_halted_endpoint marked td cancelled */ 2228 default: 2229 break; 2230 } 2231 2232 /* Update ring dequeue pointer */ 2233 trbs_freed = xhci_num_trbs_to(ep_ring->deq_seg, ep_ring->dequeue, 2234 td->last_trb_seg, td->last_trb, 2235 ep_ring->num_segs); 2236 if (trbs_freed < 0) 2237 xhci_dbg(xhci, "Failed to count freed trbs at TD finish\n"); 2238 else 2239 ep_ring->num_trbs_free += trbs_freed; 2240 ep_ring->dequeue = td->last_trb; 2241 ep_ring->deq_seg = td->last_trb_seg; 2242 inc_deq(xhci, ep_ring); 2243 2244 return xhci_td_cleanup(xhci, td, ep_ring, td->status); 2245 } 2246 2247 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ 2248 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, 2249 union xhci_trb *stop_trb) 2250 { 2251 u32 sum; 2252 union xhci_trb *trb = ring->dequeue; 2253 struct xhci_segment *seg = ring->deq_seg; 2254 2255 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { 2256 if (!trb_is_noop(trb) && !trb_is_link(trb)) 2257 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); 2258 } 2259 return sum; 2260 } 2261 2262 /* 2263 * Process control tds, update urb status and actual_length. 2264 */ 2265 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2266 struct xhci_ring *ep_ring, struct xhci_td *td, 2267 union xhci_trb *ep_trb, struct xhci_transfer_event *event) 2268 { 2269 struct xhci_ep_ctx *ep_ctx; 2270 u32 trb_comp_code; 2271 u32 remaining, requested; 2272 u32 trb_type; 2273 2274 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); 2275 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); 2276 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2277 requested = td->urb->transfer_buffer_length; 2278 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2279 2280 switch (trb_comp_code) { 2281 case COMP_SUCCESS: 2282 if (trb_type != TRB_STATUS) { 2283 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", 2284 (trb_type == TRB_DATA) ? "data" : "setup"); 2285 td->status = -ESHUTDOWN; 2286 break; 2287 } 2288 td->status = 0; 2289 break; 2290 case COMP_SHORT_PACKET: 2291 td->status = 0; 2292 break; 2293 case COMP_STOPPED_SHORT_PACKET: 2294 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2295 td->urb->actual_length = remaining; 2296 else 2297 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); 2298 goto finish_td; 2299 case COMP_STOPPED: 2300 switch (trb_type) { 2301 case TRB_SETUP: 2302 td->urb->actual_length = 0; 2303 goto finish_td; 2304 case TRB_DATA: 2305 case TRB_NORMAL: 2306 td->urb->actual_length = requested - remaining; 2307 goto finish_td; 2308 case TRB_STATUS: 2309 td->urb->actual_length = requested; 2310 goto finish_td; 2311 default: 2312 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", 2313 trb_type); 2314 goto finish_td; 2315 } 2316 case COMP_STOPPED_LENGTH_INVALID: 2317 goto finish_td; 2318 default: 2319 if (!xhci_requires_manual_halt_cleanup(xhci, 2320 ep_ctx, trb_comp_code)) 2321 break; 2322 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", 2323 trb_comp_code, ep->ep_index); 2324 fallthrough; 2325 case COMP_STALL_ERROR: 2326 /* Did we transfer part of the data (middle) phase? */ 2327 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2328 td->urb->actual_length = requested - remaining; 2329 else if (!td->urb_length_set) 2330 td->urb->actual_length = 0; 2331 goto finish_td; 2332 } 2333 2334 /* stopped at setup stage, no data transferred */ 2335 if (trb_type == TRB_SETUP) 2336 goto finish_td; 2337 2338 /* 2339 * if on data stage then update the actual_length of the URB and flag it 2340 * as set, so it won't be overwritten in the event for the last TRB. 2341 */ 2342 if (trb_type == TRB_DATA || 2343 trb_type == TRB_NORMAL) { 2344 td->urb_length_set = true; 2345 td->urb->actual_length = requested - remaining; 2346 xhci_dbg(xhci, "Waiting for status stage event\n"); 2347 return 0; 2348 } 2349 2350 /* at status stage */ 2351 if (!td->urb_length_set) 2352 td->urb->actual_length = requested; 2353 2354 finish_td: 2355 return finish_td(xhci, ep, ep_ring, td, trb_comp_code); 2356 } 2357 2358 /* 2359 * Process isochronous tds, update urb packet status and actual_length. 2360 */ 2361 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2362 struct xhci_ring *ep_ring, struct xhci_td *td, 2363 union xhci_trb *ep_trb, struct xhci_transfer_event *event) 2364 { 2365 struct urb_priv *urb_priv; 2366 int idx; 2367 struct usb_iso_packet_descriptor *frame; 2368 u32 trb_comp_code; 2369 bool sum_trbs_for_length = false; 2370 u32 remaining, requested, ep_trb_len; 2371 int short_framestatus; 2372 2373 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2374 urb_priv = td->urb->hcpriv; 2375 idx = urb_priv->num_tds_done; 2376 frame = &td->urb->iso_frame_desc[idx]; 2377 requested = frame->length; 2378 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2379 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2380 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? 2381 -EREMOTEIO : 0; 2382 2383 /* handle completion code */ 2384 switch (trb_comp_code) { 2385 case COMP_SUCCESS: 2386 if (remaining) { 2387 frame->status = short_framestatus; 2388 if (xhci->quirks & XHCI_TRUST_TX_LENGTH) 2389 sum_trbs_for_length = true; 2390 break; 2391 } 2392 frame->status = 0; 2393 break; 2394 case COMP_SHORT_PACKET: 2395 frame->status = short_framestatus; 2396 sum_trbs_for_length = true; 2397 break; 2398 case COMP_BANDWIDTH_OVERRUN_ERROR: 2399 frame->status = -ECOMM; 2400 break; 2401 case COMP_ISOCH_BUFFER_OVERRUN: 2402 case COMP_BABBLE_DETECTED_ERROR: 2403 frame->status = -EOVERFLOW; 2404 break; 2405 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2406 case COMP_STALL_ERROR: 2407 frame->status = -EPROTO; 2408 break; 2409 case COMP_USB_TRANSACTION_ERROR: 2410 frame->status = -EPROTO; 2411 if (ep_trb != td->last_trb) 2412 return 0; 2413 break; 2414 case COMP_STOPPED: 2415 sum_trbs_for_length = true; 2416 break; 2417 case COMP_STOPPED_SHORT_PACKET: 2418 /* field normally containing residue now contains tranferred */ 2419 frame->status = short_framestatus; 2420 requested = remaining; 2421 break; 2422 case COMP_STOPPED_LENGTH_INVALID: 2423 requested = 0; 2424 remaining = 0; 2425 break; 2426 default: 2427 sum_trbs_for_length = true; 2428 frame->status = -1; 2429 break; 2430 } 2431 2432 if (sum_trbs_for_length) 2433 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) + 2434 ep_trb_len - remaining; 2435 else 2436 frame->actual_length = requested; 2437 2438 td->urb->actual_length += frame->actual_length; 2439 2440 return finish_td(xhci, ep, ep_ring, td, trb_comp_code); 2441 } 2442 2443 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2444 struct xhci_virt_ep *ep, int status) 2445 { 2446 struct urb_priv *urb_priv; 2447 struct usb_iso_packet_descriptor *frame; 2448 int idx; 2449 2450 urb_priv = td->urb->hcpriv; 2451 idx = urb_priv->num_tds_done; 2452 frame = &td->urb->iso_frame_desc[idx]; 2453 2454 /* The transfer is partly done. */ 2455 frame->status = -EXDEV; 2456 2457 /* calc actual length */ 2458 frame->actual_length = 0; 2459 2460 /* Update ring dequeue pointer */ 2461 ep->ring->dequeue = td->last_trb; 2462 ep->ring->deq_seg = td->last_trb_seg; 2463 ep->ring->num_trbs_free += td->num_trbs - 1; 2464 inc_deq(xhci, ep->ring); 2465 2466 return xhci_td_cleanup(xhci, td, ep->ring, status); 2467 } 2468 2469 /* 2470 * Process bulk and interrupt tds, update urb status and actual_length. 2471 */ 2472 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 2473 struct xhci_ring *ep_ring, struct xhci_td *td, 2474 union xhci_trb *ep_trb, struct xhci_transfer_event *event) 2475 { 2476 struct xhci_slot_ctx *slot_ctx; 2477 u32 trb_comp_code; 2478 u32 remaining, requested, ep_trb_len; 2479 2480 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); 2481 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2482 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2483 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2484 requested = td->urb->transfer_buffer_length; 2485 2486 switch (trb_comp_code) { 2487 case COMP_SUCCESS: 2488 ep->err_count = 0; 2489 /* handle success with untransferred data as short packet */ 2490 if (ep_trb != td->last_trb || remaining) { 2491 xhci_warn(xhci, "WARN Successful completion on short TX\n"); 2492 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", 2493 td->urb->ep->desc.bEndpointAddress, 2494 requested, remaining); 2495 } 2496 td->status = 0; 2497 break; 2498 case COMP_SHORT_PACKET: 2499 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", 2500 td->urb->ep->desc.bEndpointAddress, 2501 requested, remaining); 2502 td->status = 0; 2503 break; 2504 case COMP_STOPPED_SHORT_PACKET: 2505 td->urb->actual_length = remaining; 2506 goto finish_td; 2507 case COMP_STOPPED_LENGTH_INVALID: 2508 /* stopped on ep trb with invalid length, exclude it */ 2509 ep_trb_len = 0; 2510 remaining = 0; 2511 break; 2512 case COMP_USB_TRANSACTION_ERROR: 2513 if (xhci->quirks & XHCI_NO_SOFT_RETRY || 2514 (ep->err_count++ > MAX_SOFT_RETRY) || 2515 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT) 2516 break; 2517 2518 td->status = 0; 2519 2520 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET); 2521 return 0; 2522 default: 2523 /* do nothing */ 2524 break; 2525 } 2526 2527 if (ep_trb == td->last_trb) 2528 td->urb->actual_length = requested - remaining; 2529 else 2530 td->urb->actual_length = 2531 sum_trb_lengths(xhci, ep_ring, ep_trb) + 2532 ep_trb_len - remaining; 2533 finish_td: 2534 if (remaining > requested) { 2535 xhci_warn(xhci, "bad transfer trb length %d in event trb\n", 2536 remaining); 2537 td->urb->actual_length = 0; 2538 } 2539 2540 return finish_td(xhci, ep, ep_ring, td, trb_comp_code); 2541 } 2542 2543 /* 2544 * If this function returns an error condition, it means it got a Transfer 2545 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. 2546 * At this point, the host controller is probably hosed and should be reset. 2547 */ 2548 static int handle_tx_event(struct xhci_hcd *xhci, 2549 struct xhci_interrupter *ir, 2550 struct xhci_transfer_event *event) 2551 { 2552 struct xhci_virt_ep *ep; 2553 struct xhci_ring *ep_ring; 2554 unsigned int slot_id; 2555 int ep_index; 2556 struct xhci_td *td = NULL; 2557 dma_addr_t ep_trb_dma; 2558 struct xhci_segment *ep_seg; 2559 union xhci_trb *ep_trb; 2560 int status = -EINPROGRESS; 2561 struct xhci_ep_ctx *ep_ctx; 2562 u32 trb_comp_code; 2563 int td_num = 0; 2564 bool handling_skipped_tds = false; 2565 2566 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2567 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2568 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2569 ep_trb_dma = le64_to_cpu(event->buffer); 2570 2571 ep = xhci_get_virt_ep(xhci, slot_id, ep_index); 2572 if (!ep) { 2573 xhci_err(xhci, "ERROR Invalid Transfer event\n"); 2574 goto err_out; 2575 } 2576 2577 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); 2578 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); 2579 2580 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { 2581 xhci_err(xhci, 2582 "ERROR Transfer event for disabled endpoint slot %u ep %u\n", 2583 slot_id, ep_index); 2584 goto err_out; 2585 } 2586 2587 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */ 2588 if (!ep_ring) { 2589 switch (trb_comp_code) { 2590 case COMP_STALL_ERROR: 2591 case COMP_USB_TRANSACTION_ERROR: 2592 case COMP_INVALID_STREAM_TYPE_ERROR: 2593 case COMP_INVALID_STREAM_ID_ERROR: 2594 xhci_dbg(xhci, "Stream transaction error ep %u no id\n", 2595 ep_index); 2596 if (ep->err_count++ > MAX_SOFT_RETRY) 2597 xhci_handle_halted_endpoint(xhci, ep, NULL, 2598 EP_HARD_RESET); 2599 else 2600 xhci_handle_halted_endpoint(xhci, ep, NULL, 2601 EP_SOFT_RESET); 2602 goto cleanup; 2603 case COMP_RING_UNDERRUN: 2604 case COMP_RING_OVERRUN: 2605 case COMP_STOPPED_LENGTH_INVALID: 2606 goto cleanup; 2607 default: 2608 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", 2609 slot_id, ep_index); 2610 goto err_out; 2611 } 2612 } 2613 2614 /* Count current td numbers if ep->skip is set */ 2615 if (ep->skip) 2616 td_num += list_count_nodes(&ep_ring->td_list); 2617 2618 /* Look for common error cases */ 2619 switch (trb_comp_code) { 2620 /* Skip codes that require special handling depending on 2621 * transfer type 2622 */ 2623 case COMP_SUCCESS: 2624 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) 2625 break; 2626 if (xhci->quirks & XHCI_TRUST_TX_LENGTH || 2627 ep_ring->last_td_was_short) 2628 trb_comp_code = COMP_SHORT_PACKET; 2629 else 2630 xhci_warn_ratelimited(xhci, 2631 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", 2632 slot_id, ep_index); 2633 break; 2634 case COMP_SHORT_PACKET: 2635 break; 2636 /* Completion codes for endpoint stopped state */ 2637 case COMP_STOPPED: 2638 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", 2639 slot_id, ep_index); 2640 break; 2641 case COMP_STOPPED_LENGTH_INVALID: 2642 xhci_dbg(xhci, 2643 "Stopped on No-op or Link TRB for slot %u ep %u\n", 2644 slot_id, ep_index); 2645 break; 2646 case COMP_STOPPED_SHORT_PACKET: 2647 xhci_dbg(xhci, 2648 "Stopped with short packet transfer detected for slot %u ep %u\n", 2649 slot_id, ep_index); 2650 break; 2651 /* Completion codes for endpoint halted state */ 2652 case COMP_STALL_ERROR: 2653 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, 2654 ep_index); 2655 status = -EPIPE; 2656 break; 2657 case COMP_SPLIT_TRANSACTION_ERROR: 2658 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n", 2659 slot_id, ep_index); 2660 status = -EPROTO; 2661 break; 2662 case COMP_USB_TRANSACTION_ERROR: 2663 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", 2664 slot_id, ep_index); 2665 status = -EPROTO; 2666 break; 2667 case COMP_BABBLE_DETECTED_ERROR: 2668 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", 2669 slot_id, ep_index); 2670 status = -EOVERFLOW; 2671 break; 2672 /* Completion codes for endpoint error state */ 2673 case COMP_TRB_ERROR: 2674 xhci_warn(xhci, 2675 "WARN: TRB error for slot %u ep %u on endpoint\n", 2676 slot_id, ep_index); 2677 status = -EILSEQ; 2678 break; 2679 /* completion codes not indicating endpoint state change */ 2680 case COMP_DATA_BUFFER_ERROR: 2681 xhci_warn(xhci, 2682 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", 2683 slot_id, ep_index); 2684 status = -ENOSR; 2685 break; 2686 case COMP_BANDWIDTH_OVERRUN_ERROR: 2687 xhci_warn(xhci, 2688 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", 2689 slot_id, ep_index); 2690 break; 2691 case COMP_ISOCH_BUFFER_OVERRUN: 2692 xhci_warn(xhci, 2693 "WARN: buffer overrun event for slot %u ep %u on endpoint", 2694 slot_id, ep_index); 2695 break; 2696 case COMP_RING_UNDERRUN: 2697 /* 2698 * When the Isoch ring is empty, the xHC will generate 2699 * a Ring Overrun Event for IN Isoch endpoint or Ring 2700 * Underrun Event for OUT Isoch endpoint. 2701 */ 2702 xhci_dbg(xhci, "underrun event on endpoint\n"); 2703 if (!list_empty(&ep_ring->td_list)) 2704 xhci_dbg(xhci, "Underrun Event for slot %d ep %d " 2705 "still with TDs queued?\n", 2706 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2707 ep_index); 2708 goto cleanup; 2709 case COMP_RING_OVERRUN: 2710 xhci_dbg(xhci, "overrun event on endpoint\n"); 2711 if (!list_empty(&ep_ring->td_list)) 2712 xhci_dbg(xhci, "Overrun Event for slot %d ep %d " 2713 "still with TDs queued?\n", 2714 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2715 ep_index); 2716 goto cleanup; 2717 case COMP_MISSED_SERVICE_ERROR: 2718 /* 2719 * When encounter missed service error, one or more isoc tds 2720 * may be missed by xHC. 2721 * Set skip flag of the ep_ring; Complete the missed tds as 2722 * short transfer when process the ep_ring next time. 2723 */ 2724 ep->skip = true; 2725 xhci_dbg(xhci, 2726 "Miss service interval error for slot %u ep %u, set skip flag\n", 2727 slot_id, ep_index); 2728 goto cleanup; 2729 case COMP_NO_PING_RESPONSE_ERROR: 2730 ep->skip = true; 2731 xhci_dbg(xhci, 2732 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", 2733 slot_id, ep_index); 2734 goto cleanup; 2735 2736 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2737 /* needs disable slot command to recover */ 2738 xhci_warn(xhci, 2739 "WARN: detect an incompatible device for slot %u ep %u", 2740 slot_id, ep_index); 2741 status = -EPROTO; 2742 break; 2743 default: 2744 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { 2745 status = 0; 2746 break; 2747 } 2748 xhci_warn(xhci, 2749 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", 2750 trb_comp_code, slot_id, ep_index); 2751 goto cleanup; 2752 } 2753 2754 do { 2755 /* This TRB should be in the TD at the head of this ring's 2756 * TD list. 2757 */ 2758 if (list_empty(&ep_ring->td_list)) { 2759 /* 2760 * Don't print wanings if it's due to a stopped endpoint 2761 * generating an extra completion event if the device 2762 * was suspended. Or, a event for the last TRB of a 2763 * short TD we already got a short event for. 2764 * The short TD is already removed from the TD list. 2765 */ 2766 2767 if (!(trb_comp_code == COMP_STOPPED || 2768 trb_comp_code == COMP_STOPPED_LENGTH_INVALID || 2769 ep_ring->last_td_was_short)) { 2770 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", 2771 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2772 ep_index); 2773 } 2774 if (ep->skip) { 2775 ep->skip = false; 2776 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", 2777 slot_id, ep_index); 2778 } 2779 if (trb_comp_code == COMP_STALL_ERROR || 2780 xhci_requires_manual_halt_cleanup(xhci, ep_ctx, 2781 trb_comp_code)) { 2782 xhci_handle_halted_endpoint(xhci, ep, NULL, 2783 EP_HARD_RESET); 2784 } 2785 goto cleanup; 2786 } 2787 2788 /* We've skipped all the TDs on the ep ring when ep->skip set */ 2789 if (ep->skip && td_num == 0) { 2790 ep->skip = false; 2791 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", 2792 slot_id, ep_index); 2793 goto cleanup; 2794 } 2795 2796 td = list_first_entry(&ep_ring->td_list, struct xhci_td, 2797 td_list); 2798 if (ep->skip) 2799 td_num--; 2800 2801 /* Is this a TRB in the currently executing TD? */ 2802 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, 2803 td->last_trb, ep_trb_dma, false); 2804 2805 /* 2806 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE 2807 * is not in the current TD pointed by ep_ring->dequeue because 2808 * that the hardware dequeue pointer still at the previous TRB 2809 * of the current TD. The previous TRB maybe a Link TD or the 2810 * last TRB of the previous TD. The command completion handle 2811 * will take care the rest. 2812 */ 2813 if (!ep_seg && (trb_comp_code == COMP_STOPPED || 2814 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { 2815 goto cleanup; 2816 } 2817 2818 if (!ep_seg) { 2819 if (!ep->skip || 2820 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { 2821 /* Some host controllers give a spurious 2822 * successful event after a short transfer. 2823 * Ignore it. 2824 */ 2825 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 2826 ep_ring->last_td_was_short) { 2827 ep_ring->last_td_was_short = false; 2828 goto cleanup; 2829 } 2830 /* HC is busted, give up! */ 2831 xhci_err(xhci, 2832 "ERROR Transfer event TRB DMA ptr not " 2833 "part of current TD ep_index %d " 2834 "comp_code %u\n", ep_index, 2835 trb_comp_code); 2836 trb_in_td(xhci, ep_ring->deq_seg, 2837 ep_ring->dequeue, td->last_trb, 2838 ep_trb_dma, true); 2839 return -ESHUTDOWN; 2840 } 2841 2842 skip_isoc_td(xhci, td, ep, status); 2843 goto cleanup; 2844 } 2845 if (trb_comp_code == COMP_SHORT_PACKET) 2846 ep_ring->last_td_was_short = true; 2847 else 2848 ep_ring->last_td_was_short = false; 2849 2850 if (ep->skip) { 2851 xhci_dbg(xhci, 2852 "Found td. Clear skip flag for slot %u ep %u.\n", 2853 slot_id, ep_index); 2854 ep->skip = false; 2855 } 2856 2857 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / 2858 sizeof(*ep_trb)]; 2859 2860 trace_xhci_handle_transfer(ep_ring, 2861 (struct xhci_generic_trb *) ep_trb); 2862 2863 /* 2864 * No-op TRB could trigger interrupts in a case where 2865 * a URB was killed and a STALL_ERROR happens right 2866 * after the endpoint ring stopped. Reset the halted 2867 * endpoint. Otherwise, the endpoint remains stalled 2868 * indefinitely. 2869 */ 2870 2871 if (trb_is_noop(ep_trb)) { 2872 if (trb_comp_code == COMP_STALL_ERROR || 2873 xhci_requires_manual_halt_cleanup(xhci, ep_ctx, 2874 trb_comp_code)) 2875 xhci_handle_halted_endpoint(xhci, ep, td, 2876 EP_HARD_RESET); 2877 goto cleanup; 2878 } 2879 2880 td->status = status; 2881 2882 /* update the urb's actual_length and give back to the core */ 2883 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) 2884 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event); 2885 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) 2886 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event); 2887 else 2888 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event); 2889 cleanup: 2890 handling_skipped_tds = ep->skip && 2891 trb_comp_code != COMP_MISSED_SERVICE_ERROR && 2892 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; 2893 2894 /* 2895 * Do not update event ring dequeue pointer if we're in a loop 2896 * processing missed tds. 2897 */ 2898 if (!handling_skipped_tds) 2899 inc_deq(xhci, ir->event_ring); 2900 2901 /* 2902 * If ep->skip is set, it means there are missed tds on the 2903 * endpoint ring need to take care of. 2904 * Process them as short transfer until reach the td pointed by 2905 * the event. 2906 */ 2907 } while (handling_skipped_tds); 2908 2909 return 0; 2910 2911 err_out: 2912 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2913 (unsigned long long) xhci_trb_virt_to_dma( 2914 ir->event_ring->deq_seg, 2915 ir->event_ring->dequeue), 2916 lower_32_bits(le64_to_cpu(event->buffer)), 2917 upper_32_bits(le64_to_cpu(event->buffer)), 2918 le32_to_cpu(event->transfer_len), 2919 le32_to_cpu(event->flags)); 2920 return -ENODEV; 2921 } 2922 2923 /* 2924 * This function handles all OS-owned events on the event ring. It may drop 2925 * xhci->lock between event processing (e.g. to pass up port status changes). 2926 * Returns >0 for "possibly more events to process" (caller should call again), 2927 * otherwise 0 if done. In future, <0 returns should indicate error code. 2928 */ 2929 static int xhci_handle_event(struct xhci_hcd *xhci, struct xhci_interrupter *ir) 2930 { 2931 union xhci_trb *event; 2932 int update_ptrs = 1; 2933 u32 trb_type; 2934 int ret; 2935 2936 /* Event ring hasn't been allocated yet. */ 2937 if (!ir || !ir->event_ring || !ir->event_ring->dequeue) { 2938 xhci_err(xhci, "ERROR interrupter not ready\n"); 2939 return -ENOMEM; 2940 } 2941 2942 event = ir->event_ring->dequeue; 2943 /* Does the HC or OS own the TRB? */ 2944 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != 2945 ir->event_ring->cycle_state) 2946 return 0; 2947 2948 trace_xhci_handle_event(ir->event_ring, &event->generic); 2949 2950 /* 2951 * Barrier between reading the TRB_CYCLE (valid) flag above and any 2952 * speculative reads of the event's flags/data below. 2953 */ 2954 rmb(); 2955 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags)); 2956 /* FIXME: Handle more event types. */ 2957 2958 switch (trb_type) { 2959 case TRB_COMPLETION: 2960 handle_cmd_completion(xhci, &event->event_cmd); 2961 break; 2962 case TRB_PORT_STATUS: 2963 handle_port_status(xhci, ir, event); 2964 update_ptrs = 0; 2965 break; 2966 case TRB_TRANSFER: 2967 ret = handle_tx_event(xhci, ir, &event->trans_event); 2968 if (ret >= 0) 2969 update_ptrs = 0; 2970 break; 2971 case TRB_DEV_NOTE: 2972 handle_device_notification(xhci, event); 2973 break; 2974 default: 2975 if (trb_type >= TRB_VENDOR_DEFINED_LOW) 2976 handle_vendor_event(xhci, event, trb_type); 2977 else 2978 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type); 2979 } 2980 /* Any of the above functions may drop and re-acquire the lock, so check 2981 * to make sure a watchdog timer didn't mark the host as non-responsive. 2982 */ 2983 if (xhci->xhc_state & XHCI_STATE_DYING) { 2984 xhci_dbg(xhci, "xHCI host dying, returning from " 2985 "event handler.\n"); 2986 return 0; 2987 } 2988 2989 if (update_ptrs) 2990 /* Update SW event ring dequeue pointer */ 2991 inc_deq(xhci, ir->event_ring); 2992 2993 /* Are there more items on the event ring? Caller will call us again to 2994 * check. 2995 */ 2996 return 1; 2997 } 2998 2999 /* 3000 * Update Event Ring Dequeue Pointer: 3001 * - When all events have finished 3002 * - To avoid "Event Ring Full Error" condition 3003 */ 3004 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci, 3005 struct xhci_interrupter *ir, 3006 union xhci_trb *event_ring_deq) 3007 { 3008 u64 temp_64; 3009 dma_addr_t deq; 3010 3011 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue); 3012 /* If necessary, update the HW's version of the event ring deq ptr. */ 3013 if (event_ring_deq != ir->event_ring->dequeue) { 3014 deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg, 3015 ir->event_ring->dequeue); 3016 if (deq == 0) 3017 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n"); 3018 /* 3019 * Per 4.9.4, Software writes to the ERDP register shall 3020 * always advance the Event Ring Dequeue Pointer value. 3021 */ 3022 if ((temp_64 & (u64) ~ERST_PTR_MASK) == 3023 ((u64) deq & (u64) ~ERST_PTR_MASK)) 3024 return; 3025 3026 /* Update HC event ring dequeue pointer */ 3027 temp_64 &= ERST_PTR_MASK; 3028 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); 3029 } 3030 3031 /* Clear the event handler busy flag (RW1C) */ 3032 temp_64 |= ERST_EHB; 3033 xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue); 3034 } 3035 3036 /* 3037 * xHCI spec says we can get an interrupt, and if the HC has an error condition, 3038 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of 3039 * indicators of an event TRB error, but we check the status *first* to be safe. 3040 */ 3041 irqreturn_t xhci_irq(struct usb_hcd *hcd) 3042 { 3043 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 3044 union xhci_trb *event_ring_deq; 3045 struct xhci_interrupter *ir; 3046 irqreturn_t ret = IRQ_NONE; 3047 u64 temp_64; 3048 u32 status; 3049 int event_loop = 0; 3050 3051 spin_lock(&xhci->lock); 3052 /* Check if the xHC generated the interrupt, or the irq is shared */ 3053 status = readl(&xhci->op_regs->status); 3054 if (status == ~(u32)0) { 3055 xhci_hc_died(xhci); 3056 ret = IRQ_HANDLED; 3057 goto out; 3058 } 3059 3060 if (!(status & STS_EINT)) 3061 goto out; 3062 3063 if (status & STS_HCE) { 3064 xhci_warn(xhci, "WARNING: Host Controller Error\n"); 3065 goto out; 3066 } 3067 3068 if (status & STS_FATAL) { 3069 xhci_warn(xhci, "WARNING: Host System Error\n"); 3070 xhci_halt(xhci); 3071 ret = IRQ_HANDLED; 3072 goto out; 3073 } 3074 3075 /* 3076 * Clear the op reg interrupt status first, 3077 * so we can receive interrupts from other MSI-X interrupters. 3078 * Write 1 to clear the interrupt status. 3079 */ 3080 status |= STS_EINT; 3081 writel(status, &xhci->op_regs->status); 3082 3083 /* This is the handler of the primary interrupter */ 3084 ir = xhci->interrupter; 3085 if (!hcd->msi_enabled) { 3086 u32 irq_pending; 3087 irq_pending = readl(&ir->ir_set->irq_pending); 3088 irq_pending |= IMAN_IP; 3089 writel(irq_pending, &ir->ir_set->irq_pending); 3090 } 3091 3092 if (xhci->xhc_state & XHCI_STATE_DYING || 3093 xhci->xhc_state & XHCI_STATE_HALTED) { 3094 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " 3095 "Shouldn't IRQs be disabled?\n"); 3096 /* Clear the event handler busy flag (RW1C); 3097 * the event ring should be empty. 3098 */ 3099 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue); 3100 xhci_write_64(xhci, temp_64 | ERST_EHB, 3101 &ir->ir_set->erst_dequeue); 3102 ret = IRQ_HANDLED; 3103 goto out; 3104 } 3105 3106 event_ring_deq = ir->event_ring->dequeue; 3107 /* FIXME this should be a delayed service routine 3108 * that clears the EHB. 3109 */ 3110 while (xhci_handle_event(xhci, ir) > 0) { 3111 if (event_loop++ < TRBS_PER_SEGMENT / 2) 3112 continue; 3113 xhci_update_erst_dequeue(xhci, ir, event_ring_deq); 3114 event_ring_deq = ir->event_ring->dequeue; 3115 3116 /* ring is half-full, force isoc trbs to interrupt more often */ 3117 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN) 3118 xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2; 3119 3120 event_loop = 0; 3121 } 3122 3123 xhci_update_erst_dequeue(xhci, ir, event_ring_deq); 3124 ret = IRQ_HANDLED; 3125 3126 out: 3127 spin_unlock(&xhci->lock); 3128 3129 return ret; 3130 } 3131 3132 irqreturn_t xhci_msi_irq(int irq, void *hcd) 3133 { 3134 return xhci_irq(hcd); 3135 } 3136 EXPORT_SYMBOL_GPL(xhci_msi_irq); 3137 3138 /**** Endpoint Ring Operations ****/ 3139 3140 /* 3141 * Generic function for queueing a TRB on a ring. 3142 * The caller must have checked to make sure there's room on the ring. 3143 * 3144 * @more_trbs_coming: Will you enqueue more TRBs before calling 3145 * prepare_transfer()? 3146 */ 3147 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 3148 bool more_trbs_coming, 3149 u32 field1, u32 field2, u32 field3, u32 field4) 3150 { 3151 struct xhci_generic_trb *trb; 3152 3153 trb = &ring->enqueue->generic; 3154 trb->field[0] = cpu_to_le32(field1); 3155 trb->field[1] = cpu_to_le32(field2); 3156 trb->field[2] = cpu_to_le32(field3); 3157 /* make sure TRB is fully written before giving it to the controller */ 3158 wmb(); 3159 trb->field[3] = cpu_to_le32(field4); 3160 3161 trace_xhci_queue_trb(ring, trb); 3162 3163 inc_enq(xhci, ring, more_trbs_coming); 3164 } 3165 3166 /* 3167 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. 3168 * FIXME allocate segments if the ring is full. 3169 */ 3170 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 3171 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 3172 { 3173 unsigned int num_trbs_needed; 3174 unsigned int link_trb_count = 0; 3175 3176 /* Make sure the endpoint has been added to xHC schedule */ 3177 switch (ep_state) { 3178 case EP_STATE_DISABLED: 3179 /* 3180 * USB core changed config/interfaces without notifying us, 3181 * or hardware is reporting the wrong state. 3182 */ 3183 xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); 3184 return -ENOENT; 3185 case EP_STATE_ERROR: 3186 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); 3187 /* FIXME event handling code for error needs to clear it */ 3188 /* XXX not sure if this should be -ENOENT or not */ 3189 return -EINVAL; 3190 case EP_STATE_HALTED: 3191 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); 3192 break; 3193 case EP_STATE_STOPPED: 3194 case EP_STATE_RUNNING: 3195 break; 3196 default: 3197 xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); 3198 /* 3199 * FIXME issue Configure Endpoint command to try to get the HC 3200 * back into a known state. 3201 */ 3202 return -EINVAL; 3203 } 3204 3205 while (1) { 3206 if (room_on_ring(xhci, ep_ring, num_trbs)) 3207 break; 3208 3209 if (ep_ring == xhci->cmd_ring) { 3210 xhci_err(xhci, "Do not support expand command ring\n"); 3211 return -ENOMEM; 3212 } 3213 3214 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, 3215 "ERROR no room on ep ring, try ring expansion"); 3216 num_trbs_needed = num_trbs - ep_ring->num_trbs_free; 3217 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, 3218 mem_flags)) { 3219 xhci_err(xhci, "Ring expansion failed\n"); 3220 return -ENOMEM; 3221 } 3222 } 3223 3224 while (trb_is_link(ep_ring->enqueue)) { 3225 /* If we're not dealing with 0.95 hardware or isoc rings 3226 * on AMD 0.96 host, clear the chain bit. 3227 */ 3228 if (!xhci_link_trb_quirk(xhci) && 3229 !(ep_ring->type == TYPE_ISOC && 3230 (xhci->quirks & XHCI_AMD_0x96_HOST))) 3231 ep_ring->enqueue->link.control &= 3232 cpu_to_le32(~TRB_CHAIN); 3233 else 3234 ep_ring->enqueue->link.control |= 3235 cpu_to_le32(TRB_CHAIN); 3236 3237 wmb(); 3238 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); 3239 3240 /* Toggle the cycle bit after the last ring segment. */ 3241 if (link_trb_toggles_cycle(ep_ring->enqueue)) 3242 ep_ring->cycle_state ^= 1; 3243 3244 ep_ring->enq_seg = ep_ring->enq_seg->next; 3245 ep_ring->enqueue = ep_ring->enq_seg->trbs; 3246 3247 /* prevent infinite loop if all first trbs are link trbs */ 3248 if (link_trb_count++ > ep_ring->num_segs) { 3249 xhci_warn(xhci, "Ring is an endless link TRB loop\n"); 3250 return -EINVAL; 3251 } 3252 } 3253 3254 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) { 3255 xhci_warn(xhci, "Missing link TRB at end of ring segment\n"); 3256 return -EINVAL; 3257 } 3258 3259 return 0; 3260 } 3261 3262 static int prepare_transfer(struct xhci_hcd *xhci, 3263 struct xhci_virt_device *xdev, 3264 unsigned int ep_index, 3265 unsigned int stream_id, 3266 unsigned int num_trbs, 3267 struct urb *urb, 3268 unsigned int td_index, 3269 gfp_t mem_flags) 3270 { 3271 int ret; 3272 struct urb_priv *urb_priv; 3273 struct xhci_td *td; 3274 struct xhci_ring *ep_ring; 3275 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 3276 3277 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index, 3278 stream_id); 3279 if (!ep_ring) { 3280 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", 3281 stream_id); 3282 return -EINVAL; 3283 } 3284 3285 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 3286 num_trbs, mem_flags); 3287 if (ret) 3288 return ret; 3289 3290 urb_priv = urb->hcpriv; 3291 td = &urb_priv->td[td_index]; 3292 3293 INIT_LIST_HEAD(&td->td_list); 3294 INIT_LIST_HEAD(&td->cancelled_td_list); 3295 3296 if (td_index == 0) { 3297 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); 3298 if (unlikely(ret)) 3299 return ret; 3300 } 3301 3302 td->urb = urb; 3303 /* Add this TD to the tail of the endpoint ring's TD list */ 3304 list_add_tail(&td->td_list, &ep_ring->td_list); 3305 td->start_seg = ep_ring->enq_seg; 3306 td->first_trb = ep_ring->enqueue; 3307 3308 return 0; 3309 } 3310 3311 unsigned int count_trbs(u64 addr, u64 len) 3312 { 3313 unsigned int num_trbs; 3314 3315 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), 3316 TRB_MAX_BUFF_SIZE); 3317 if (num_trbs == 0) 3318 num_trbs++; 3319 3320 return num_trbs; 3321 } 3322 3323 static inline unsigned int count_trbs_needed(struct urb *urb) 3324 { 3325 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); 3326 } 3327 3328 static unsigned int count_sg_trbs_needed(struct urb *urb) 3329 { 3330 struct scatterlist *sg; 3331 unsigned int i, len, full_len, num_trbs = 0; 3332 3333 full_len = urb->transfer_buffer_length; 3334 3335 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { 3336 len = sg_dma_len(sg); 3337 num_trbs += count_trbs(sg_dma_address(sg), len); 3338 len = min_t(unsigned int, len, full_len); 3339 full_len -= len; 3340 if (full_len == 0) 3341 break; 3342 } 3343 3344 return num_trbs; 3345 } 3346 3347 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) 3348 { 3349 u64 addr, len; 3350 3351 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); 3352 len = urb->iso_frame_desc[i].length; 3353 3354 return count_trbs(addr, len); 3355 } 3356 3357 static void check_trb_math(struct urb *urb, int running_total) 3358 { 3359 if (unlikely(running_total != urb->transfer_buffer_length)) 3360 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " 3361 "queued %#x (%d), asked for %#x (%d)\n", 3362 __func__, 3363 urb->ep->desc.bEndpointAddress, 3364 running_total, running_total, 3365 urb->transfer_buffer_length, 3366 urb->transfer_buffer_length); 3367 } 3368 3369 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, 3370 unsigned int ep_index, unsigned int stream_id, int start_cycle, 3371 struct xhci_generic_trb *start_trb) 3372 { 3373 /* 3374 * Pass all the TRBs to the hardware at once and make sure this write 3375 * isn't reordered. 3376 */ 3377 wmb(); 3378 if (start_cycle) 3379 start_trb->field[3] |= cpu_to_le32(start_cycle); 3380 else 3381 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 3382 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 3383 } 3384 3385 static void check_interval(struct xhci_hcd *xhci, struct urb *urb, 3386 struct xhci_ep_ctx *ep_ctx) 3387 { 3388 int xhci_interval; 3389 int ep_interval; 3390 3391 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); 3392 ep_interval = urb->interval; 3393 3394 /* Convert to microframes */ 3395 if (urb->dev->speed == USB_SPEED_LOW || 3396 urb->dev->speed == USB_SPEED_FULL) 3397 ep_interval *= 8; 3398 3399 /* FIXME change this to a warning and a suggestion to use the new API 3400 * to set the polling interval (once the API is added). 3401 */ 3402 if (xhci_interval != ep_interval) { 3403 dev_dbg_ratelimited(&urb->dev->dev, 3404 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", 3405 ep_interval, ep_interval == 1 ? "" : "s", 3406 xhci_interval, xhci_interval == 1 ? "" : "s"); 3407 urb->interval = xhci_interval; 3408 /* Convert back to frames for LS/FS devices */ 3409 if (urb->dev->speed == USB_SPEED_LOW || 3410 urb->dev->speed == USB_SPEED_FULL) 3411 urb->interval /= 8; 3412 } 3413 } 3414 3415 /* 3416 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt 3417 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD 3418 * (comprised of sg list entries) can take several service intervals to 3419 * transmit. 3420 */ 3421 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3422 struct urb *urb, int slot_id, unsigned int ep_index) 3423 { 3424 struct xhci_ep_ctx *ep_ctx; 3425 3426 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); 3427 check_interval(xhci, urb, ep_ctx); 3428 3429 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); 3430 } 3431 3432 /* 3433 * For xHCI 1.0 host controllers, TD size is the number of max packet sized 3434 * packets remaining in the TD (*not* including this TRB). 3435 * 3436 * Total TD packet count = total_packet_count = 3437 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) 3438 * 3439 * Packets transferred up to and including this TRB = packets_transferred = 3440 * rounddown(total bytes transferred including this TRB / wMaxPacketSize) 3441 * 3442 * TD size = total_packet_count - packets_transferred 3443 * 3444 * For xHCI 0.96 and older, TD size field should be the remaining bytes 3445 * including this TRB, right shifted by 10 3446 * 3447 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. 3448 * This is taken care of in the TRB_TD_SIZE() macro 3449 * 3450 * The last TRB in a TD must have the TD size set to zero. 3451 */ 3452 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, 3453 int trb_buff_len, unsigned int td_total_len, 3454 struct urb *urb, bool more_trbs_coming) 3455 { 3456 u32 maxp, total_packet_count; 3457 3458 /* MTK xHCI 0.96 contains some features from 1.0 */ 3459 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) 3460 return ((td_total_len - transferred) >> 10); 3461 3462 /* One TRB with a zero-length data packet. */ 3463 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || 3464 trb_buff_len == td_total_len) 3465 return 0; 3466 3467 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ 3468 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) 3469 trb_buff_len = 0; 3470 3471 maxp = usb_endpoint_maxp(&urb->ep->desc); 3472 total_packet_count = DIV_ROUND_UP(td_total_len, maxp); 3473 3474 /* Queueing functions don't count the current TRB into transferred */ 3475 return (total_packet_count - ((transferred + trb_buff_len) / maxp)); 3476 } 3477 3478 3479 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, 3480 u32 *trb_buff_len, struct xhci_segment *seg) 3481 { 3482 struct device *dev = xhci_to_hcd(xhci)->self.controller; 3483 unsigned int unalign; 3484 unsigned int max_pkt; 3485 u32 new_buff_len; 3486 size_t len; 3487 3488 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 3489 unalign = (enqd_len + *trb_buff_len) % max_pkt; 3490 3491 /* we got lucky, last normal TRB data on segment is packet aligned */ 3492 if (unalign == 0) 3493 return 0; 3494 3495 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", 3496 unalign, *trb_buff_len); 3497 3498 /* is the last nornal TRB alignable by splitting it */ 3499 if (*trb_buff_len > unalign) { 3500 *trb_buff_len -= unalign; 3501 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); 3502 return 0; 3503 } 3504 3505 /* 3506 * We want enqd_len + trb_buff_len to sum up to a number aligned to 3507 * number which is divisible by the endpoint's wMaxPacketSize. IOW: 3508 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. 3509 */ 3510 new_buff_len = max_pkt - (enqd_len % max_pkt); 3511 3512 if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) 3513 new_buff_len = (urb->transfer_buffer_length - enqd_len); 3514 3515 /* create a max max_pkt sized bounce buffer pointed to by last trb */ 3516 if (usb_urb_dir_out(urb)) { 3517 if (urb->num_sgs) { 3518 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs, 3519 seg->bounce_buf, new_buff_len, enqd_len); 3520 if (len != new_buff_len) 3521 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n", 3522 len, new_buff_len); 3523 } else { 3524 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len); 3525 } 3526 3527 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3528 max_pkt, DMA_TO_DEVICE); 3529 } else { 3530 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3531 max_pkt, DMA_FROM_DEVICE); 3532 } 3533 3534 if (dma_mapping_error(dev, seg->bounce_dma)) { 3535 /* try without aligning. Some host controllers survive */ 3536 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); 3537 return 0; 3538 } 3539 *trb_buff_len = new_buff_len; 3540 seg->bounce_len = new_buff_len; 3541 seg->bounce_offs = enqd_len; 3542 3543 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); 3544 3545 return 1; 3546 } 3547 3548 /* This is very similar to what ehci-q.c qtd_fill() does */ 3549 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3550 struct urb *urb, int slot_id, unsigned int ep_index) 3551 { 3552 struct xhci_ring *ring; 3553 struct urb_priv *urb_priv; 3554 struct xhci_td *td; 3555 struct xhci_generic_trb *start_trb; 3556 struct scatterlist *sg = NULL; 3557 bool more_trbs_coming = true; 3558 bool need_zero_pkt = false; 3559 bool first_trb = true; 3560 unsigned int num_trbs; 3561 unsigned int start_cycle, num_sgs = 0; 3562 unsigned int enqd_len, block_len, trb_buff_len, full_len; 3563 int sent_len, ret; 3564 u32 field, length_field, remainder; 3565 u64 addr, send_addr; 3566 3567 ring = xhci_urb_to_transfer_ring(xhci, urb); 3568 if (!ring) 3569 return -EINVAL; 3570 3571 full_len = urb->transfer_buffer_length; 3572 /* If we have scatter/gather list, we use it. */ 3573 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { 3574 num_sgs = urb->num_mapped_sgs; 3575 sg = urb->sg; 3576 addr = (u64) sg_dma_address(sg); 3577 block_len = sg_dma_len(sg); 3578 num_trbs = count_sg_trbs_needed(urb); 3579 } else { 3580 num_trbs = count_trbs_needed(urb); 3581 addr = (u64) urb->transfer_dma; 3582 block_len = full_len; 3583 } 3584 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3585 ep_index, urb->stream_id, 3586 num_trbs, urb, 0, mem_flags); 3587 if (unlikely(ret < 0)) 3588 return ret; 3589 3590 urb_priv = urb->hcpriv; 3591 3592 /* Deal with URB_ZERO_PACKET - need one more td/trb */ 3593 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) 3594 need_zero_pkt = true; 3595 3596 td = &urb_priv->td[0]; 3597 3598 /* 3599 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3600 * until we've finished creating all the other TRBs. The ring's cycle 3601 * state may change as we enqueue the other TRBs, so save it too. 3602 */ 3603 start_trb = &ring->enqueue->generic; 3604 start_cycle = ring->cycle_state; 3605 send_addr = addr; 3606 3607 /* Queue the TRBs, even if they are zero-length */ 3608 for (enqd_len = 0; first_trb || enqd_len < full_len; 3609 enqd_len += trb_buff_len) { 3610 field = TRB_TYPE(TRB_NORMAL); 3611 3612 /* TRB buffer should not cross 64KB boundaries */ 3613 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3614 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); 3615 3616 if (enqd_len + trb_buff_len > full_len) 3617 trb_buff_len = full_len - enqd_len; 3618 3619 /* Don't change the cycle bit of the first TRB until later */ 3620 if (first_trb) { 3621 first_trb = false; 3622 if (start_cycle == 0) 3623 field |= TRB_CYCLE; 3624 } else 3625 field |= ring->cycle_state; 3626 3627 /* Chain all the TRBs together; clear the chain bit in the last 3628 * TRB to indicate it's the last TRB in the chain. 3629 */ 3630 if (enqd_len + trb_buff_len < full_len) { 3631 field |= TRB_CHAIN; 3632 if (trb_is_link(ring->enqueue + 1)) { 3633 if (xhci_align_td(xhci, urb, enqd_len, 3634 &trb_buff_len, 3635 ring->enq_seg)) { 3636 send_addr = ring->enq_seg->bounce_dma; 3637 /* assuming TD won't span 2 segs */ 3638 td->bounce_seg = ring->enq_seg; 3639 } 3640 } 3641 } 3642 if (enqd_len + trb_buff_len >= full_len) { 3643 field &= ~TRB_CHAIN; 3644 field |= TRB_IOC; 3645 more_trbs_coming = false; 3646 td->last_trb = ring->enqueue; 3647 td->last_trb_seg = ring->enq_seg; 3648 if (xhci_urb_suitable_for_idt(urb)) { 3649 memcpy(&send_addr, urb->transfer_buffer, 3650 trb_buff_len); 3651 le64_to_cpus(&send_addr); 3652 field |= TRB_IDT; 3653 } 3654 } 3655 3656 /* Only set interrupt on short packet for IN endpoints */ 3657 if (usb_urb_dir_in(urb)) 3658 field |= TRB_ISP; 3659 3660 /* Set the TRB length, TD size, and interrupter fields. */ 3661 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, 3662 full_len, urb, more_trbs_coming); 3663 3664 length_field = TRB_LEN(trb_buff_len) | 3665 TRB_TD_SIZE(remainder) | 3666 TRB_INTR_TARGET(0); 3667 3668 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, 3669 lower_32_bits(send_addr), 3670 upper_32_bits(send_addr), 3671 length_field, 3672 field); 3673 td->num_trbs++; 3674 addr += trb_buff_len; 3675 sent_len = trb_buff_len; 3676 3677 while (sg && sent_len >= block_len) { 3678 /* New sg entry */ 3679 --num_sgs; 3680 sent_len -= block_len; 3681 sg = sg_next(sg); 3682 if (num_sgs != 0 && sg) { 3683 block_len = sg_dma_len(sg); 3684 addr = (u64) sg_dma_address(sg); 3685 addr += sent_len; 3686 } 3687 } 3688 block_len -= sent_len; 3689 send_addr = addr; 3690 } 3691 3692 if (need_zero_pkt) { 3693 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3694 ep_index, urb->stream_id, 3695 1, urb, 1, mem_flags); 3696 urb_priv->td[1].last_trb = ring->enqueue; 3697 urb_priv->td[1].last_trb_seg = ring->enq_seg; 3698 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; 3699 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); 3700 urb_priv->td[1].num_trbs++; 3701 } 3702 3703 check_trb_math(urb, enqd_len); 3704 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3705 start_cycle, start_trb); 3706 return 0; 3707 } 3708 3709 /* Caller must have locked xhci->lock */ 3710 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3711 struct urb *urb, int slot_id, unsigned int ep_index) 3712 { 3713 struct xhci_ring *ep_ring; 3714 int num_trbs; 3715 int ret; 3716 struct usb_ctrlrequest *setup; 3717 struct xhci_generic_trb *start_trb; 3718 int start_cycle; 3719 u32 field; 3720 struct urb_priv *urb_priv; 3721 struct xhci_td *td; 3722 3723 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3724 if (!ep_ring) 3725 return -EINVAL; 3726 3727 /* 3728 * Need to copy setup packet into setup TRB, so we can't use the setup 3729 * DMA address. 3730 */ 3731 if (!urb->setup_packet) 3732 return -EINVAL; 3733 3734 /* 1 TRB for setup, 1 for status */ 3735 num_trbs = 2; 3736 /* 3737 * Don't need to check if we need additional event data and normal TRBs, 3738 * since data in control transfers will never get bigger than 16MB 3739 * XXX: can we get a buffer that crosses 64KB boundaries? 3740 */ 3741 if (urb->transfer_buffer_length > 0) 3742 num_trbs++; 3743 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3744 ep_index, urb->stream_id, 3745 num_trbs, urb, 0, mem_flags); 3746 if (ret < 0) 3747 return ret; 3748 3749 urb_priv = urb->hcpriv; 3750 td = &urb_priv->td[0]; 3751 td->num_trbs = num_trbs; 3752 3753 /* 3754 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3755 * until we've finished creating all the other TRBs. The ring's cycle 3756 * state may change as we enqueue the other TRBs, so save it too. 3757 */ 3758 start_trb = &ep_ring->enqueue->generic; 3759 start_cycle = ep_ring->cycle_state; 3760 3761 /* Queue setup TRB - see section 6.4.1.2.1 */ 3762 /* FIXME better way to translate setup_packet into two u32 fields? */ 3763 setup = (struct usb_ctrlrequest *) urb->setup_packet; 3764 field = 0; 3765 field |= TRB_IDT | TRB_TYPE(TRB_SETUP); 3766 if (start_cycle == 0) 3767 field |= 0x1; 3768 3769 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ 3770 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { 3771 if (urb->transfer_buffer_length > 0) { 3772 if (setup->bRequestType & USB_DIR_IN) 3773 field |= TRB_TX_TYPE(TRB_DATA_IN); 3774 else 3775 field |= TRB_TX_TYPE(TRB_DATA_OUT); 3776 } 3777 } 3778 3779 queue_trb(xhci, ep_ring, true, 3780 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, 3781 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, 3782 TRB_LEN(8) | TRB_INTR_TARGET(0), 3783 /* Immediate data in pointer */ 3784 field); 3785 3786 /* If there's data, queue data TRBs */ 3787 /* Only set interrupt on short packet for IN endpoints */ 3788 if (usb_urb_dir_in(urb)) 3789 field = TRB_ISP | TRB_TYPE(TRB_DATA); 3790 else 3791 field = TRB_TYPE(TRB_DATA); 3792 3793 if (urb->transfer_buffer_length > 0) { 3794 u32 length_field, remainder; 3795 u64 addr; 3796 3797 if (xhci_urb_suitable_for_idt(urb)) { 3798 memcpy(&addr, urb->transfer_buffer, 3799 urb->transfer_buffer_length); 3800 le64_to_cpus(&addr); 3801 field |= TRB_IDT; 3802 } else { 3803 addr = (u64) urb->transfer_dma; 3804 } 3805 3806 remainder = xhci_td_remainder(xhci, 0, 3807 urb->transfer_buffer_length, 3808 urb->transfer_buffer_length, 3809 urb, 1); 3810 length_field = TRB_LEN(urb->transfer_buffer_length) | 3811 TRB_TD_SIZE(remainder) | 3812 TRB_INTR_TARGET(0); 3813 if (setup->bRequestType & USB_DIR_IN) 3814 field |= TRB_DIR_IN; 3815 queue_trb(xhci, ep_ring, true, 3816 lower_32_bits(addr), 3817 upper_32_bits(addr), 3818 length_field, 3819 field | ep_ring->cycle_state); 3820 } 3821 3822 /* Save the DMA address of the last TRB in the TD */ 3823 td->last_trb = ep_ring->enqueue; 3824 td->last_trb_seg = ep_ring->enq_seg; 3825 3826 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ 3827 /* If the device sent data, the status stage is an OUT transfer */ 3828 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) 3829 field = 0; 3830 else 3831 field = TRB_DIR_IN; 3832 queue_trb(xhci, ep_ring, false, 3833 0, 3834 0, 3835 TRB_INTR_TARGET(0), 3836 /* Event on completion */ 3837 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); 3838 3839 giveback_first_trb(xhci, slot_id, ep_index, 0, 3840 start_cycle, start_trb); 3841 return 0; 3842 } 3843 3844 /* 3845 * The transfer burst count field of the isochronous TRB defines the number of 3846 * bursts that are required to move all packets in this TD. Only SuperSpeed 3847 * devices can burst up to bMaxBurst number of packets per service interval. 3848 * This field is zero based, meaning a value of zero in the field means one 3849 * burst. Basically, for everything but SuperSpeed devices, this field will be 3850 * zero. Only xHCI 1.0 host controllers support this field. 3851 */ 3852 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, 3853 struct urb *urb, unsigned int total_packet_count) 3854 { 3855 unsigned int max_burst; 3856 3857 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) 3858 return 0; 3859 3860 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3861 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; 3862 } 3863 3864 /* 3865 * Returns the number of packets in the last "burst" of packets. This field is 3866 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so 3867 * the last burst packet count is equal to the total number of packets in the 3868 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst 3869 * must contain (bMaxBurst + 1) number of packets, but the last burst can 3870 * contain 1 to (bMaxBurst + 1) packets. 3871 */ 3872 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, 3873 struct urb *urb, unsigned int total_packet_count) 3874 { 3875 unsigned int max_burst; 3876 unsigned int residue; 3877 3878 if (xhci->hci_version < 0x100) 3879 return 0; 3880 3881 if (urb->dev->speed >= USB_SPEED_SUPER) { 3882 /* bMaxBurst is zero based: 0 means 1 packet per burst */ 3883 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3884 residue = total_packet_count % (max_burst + 1); 3885 /* If residue is zero, the last burst contains (max_burst + 1) 3886 * number of packets, but the TLBPC field is zero-based. 3887 */ 3888 if (residue == 0) 3889 return max_burst; 3890 return residue - 1; 3891 } 3892 if (total_packet_count == 0) 3893 return 0; 3894 return total_packet_count - 1; 3895 } 3896 3897 /* 3898 * Calculates Frame ID field of the isochronous TRB identifies the 3899 * target frame that the Interval associated with this Isochronous 3900 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. 3901 * 3902 * Returns actual frame id on success, negative value on error. 3903 */ 3904 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, 3905 struct urb *urb, int index) 3906 { 3907 int start_frame, ist, ret = 0; 3908 int start_frame_id, end_frame_id, current_frame_id; 3909 3910 if (urb->dev->speed == USB_SPEED_LOW || 3911 urb->dev->speed == USB_SPEED_FULL) 3912 start_frame = urb->start_frame + index * urb->interval; 3913 else 3914 start_frame = (urb->start_frame + index * urb->interval) >> 3; 3915 3916 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): 3917 * 3918 * If bit [3] of IST is cleared to '0', software can add a TRB no 3919 * later than IST[2:0] Microframes before that TRB is scheduled to 3920 * be executed. 3921 * If bit [3] of IST is set to '1', software can add a TRB no later 3922 * than IST[2:0] Frames before that TRB is scheduled to be executed. 3923 */ 3924 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3925 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3926 ist <<= 3; 3927 3928 /* Software shall not schedule an Isoch TD with a Frame ID value that 3929 * is less than the Start Frame ID or greater than the End Frame ID, 3930 * where: 3931 * 3932 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 3933 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 3934 * 3935 * Both the End Frame ID and Start Frame ID values are calculated 3936 * in microframes. When software determines the valid Frame ID value; 3937 * The End Frame ID value should be rounded down to the nearest Frame 3938 * boundary, and the Start Frame ID value should be rounded up to the 3939 * nearest Frame boundary. 3940 */ 3941 current_frame_id = readl(&xhci->run_regs->microframe_index); 3942 start_frame_id = roundup(current_frame_id + ist + 1, 8); 3943 end_frame_id = rounddown(current_frame_id + 895 * 8, 8); 3944 3945 start_frame &= 0x7ff; 3946 start_frame_id = (start_frame_id >> 3) & 0x7ff; 3947 end_frame_id = (end_frame_id >> 3) & 0x7ff; 3948 3949 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", 3950 __func__, index, readl(&xhci->run_regs->microframe_index), 3951 start_frame_id, end_frame_id, start_frame); 3952 3953 if (start_frame_id < end_frame_id) { 3954 if (start_frame > end_frame_id || 3955 start_frame < start_frame_id) 3956 ret = -EINVAL; 3957 } else if (start_frame_id > end_frame_id) { 3958 if ((start_frame > end_frame_id && 3959 start_frame < start_frame_id)) 3960 ret = -EINVAL; 3961 } else { 3962 ret = -EINVAL; 3963 } 3964 3965 if (index == 0) { 3966 if (ret == -EINVAL || start_frame == start_frame_id) { 3967 start_frame = start_frame_id + 1; 3968 if (urb->dev->speed == USB_SPEED_LOW || 3969 urb->dev->speed == USB_SPEED_FULL) 3970 urb->start_frame = start_frame; 3971 else 3972 urb->start_frame = start_frame << 3; 3973 ret = 0; 3974 } 3975 } 3976 3977 if (ret) { 3978 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", 3979 start_frame, current_frame_id, index, 3980 start_frame_id, end_frame_id); 3981 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); 3982 return ret; 3983 } 3984 3985 return start_frame; 3986 } 3987 3988 /* Check if we should generate event interrupt for a TD in an isoc URB */ 3989 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i) 3990 { 3991 if (xhci->hci_version < 0x100) 3992 return false; 3993 /* always generate an event interrupt for the last TD */ 3994 if (i == num_tds - 1) 3995 return false; 3996 /* 3997 * If AVOID_BEI is set the host handles full event rings poorly, 3998 * generate an event at least every 8th TD to clear the event ring 3999 */ 4000 if (i && xhci->quirks & XHCI_AVOID_BEI) 4001 return !!(i % xhci->isoc_bei_interval); 4002 4003 return true; 4004 } 4005 4006 /* This is for isoc transfer */ 4007 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 4008 struct urb *urb, int slot_id, unsigned int ep_index) 4009 { 4010 struct xhci_ring *ep_ring; 4011 struct urb_priv *urb_priv; 4012 struct xhci_td *td; 4013 int num_tds, trbs_per_td; 4014 struct xhci_generic_trb *start_trb; 4015 bool first_trb; 4016 int start_cycle; 4017 u32 field, length_field; 4018 int running_total, trb_buff_len, td_len, td_remain_len, ret; 4019 u64 start_addr, addr; 4020 int i, j; 4021 bool more_trbs_coming; 4022 struct xhci_virt_ep *xep; 4023 int frame_id; 4024 4025 xep = &xhci->devs[slot_id]->eps[ep_index]; 4026 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 4027 4028 num_tds = urb->number_of_packets; 4029 if (num_tds < 1) { 4030 xhci_dbg(xhci, "Isoc URB with zero packets?\n"); 4031 return -EINVAL; 4032 } 4033 start_addr = (u64) urb->transfer_dma; 4034 start_trb = &ep_ring->enqueue->generic; 4035 start_cycle = ep_ring->cycle_state; 4036 4037 urb_priv = urb->hcpriv; 4038 /* Queue the TRBs for each TD, even if they are zero-length */ 4039 for (i = 0; i < num_tds; i++) { 4040 unsigned int total_pkt_count, max_pkt; 4041 unsigned int burst_count, last_burst_pkt_count; 4042 u32 sia_frame_id; 4043 4044 first_trb = true; 4045 running_total = 0; 4046 addr = start_addr + urb->iso_frame_desc[i].offset; 4047 td_len = urb->iso_frame_desc[i].length; 4048 td_remain_len = td_len; 4049 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 4050 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); 4051 4052 /* A zero-length transfer still involves at least one packet. */ 4053 if (total_pkt_count == 0) 4054 total_pkt_count++; 4055 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); 4056 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, 4057 urb, total_pkt_count); 4058 4059 trbs_per_td = count_isoc_trbs_needed(urb, i); 4060 4061 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, 4062 urb->stream_id, trbs_per_td, urb, i, mem_flags); 4063 if (ret < 0) { 4064 if (i == 0) 4065 return ret; 4066 goto cleanup; 4067 } 4068 td = &urb_priv->td[i]; 4069 td->num_trbs = trbs_per_td; 4070 /* use SIA as default, if frame id is used overwrite it */ 4071 sia_frame_id = TRB_SIA; 4072 if (!(urb->transfer_flags & URB_ISO_ASAP) && 4073 HCC_CFC(xhci->hcc_params)) { 4074 frame_id = xhci_get_isoc_frame_id(xhci, urb, i); 4075 if (frame_id >= 0) 4076 sia_frame_id = TRB_FRAME_ID(frame_id); 4077 } 4078 /* 4079 * Set isoc specific data for the first TRB in a TD. 4080 * Prevent HW from getting the TRBs by keeping the cycle state 4081 * inverted in the first TDs isoc TRB. 4082 */ 4083 field = TRB_TYPE(TRB_ISOC) | 4084 TRB_TLBPC(last_burst_pkt_count) | 4085 sia_frame_id | 4086 (i ? ep_ring->cycle_state : !start_cycle); 4087 4088 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ 4089 if (!xep->use_extended_tbc) 4090 field |= TRB_TBC(burst_count); 4091 4092 /* fill the rest of the TRB fields, and remaining normal TRBs */ 4093 for (j = 0; j < trbs_per_td; j++) { 4094 u32 remainder = 0; 4095 4096 /* only first TRB is isoc, overwrite otherwise */ 4097 if (!first_trb) 4098 field = TRB_TYPE(TRB_NORMAL) | 4099 ep_ring->cycle_state; 4100 4101 /* Only set interrupt on short packet for IN EPs */ 4102 if (usb_urb_dir_in(urb)) 4103 field |= TRB_ISP; 4104 4105 /* Set the chain bit for all except the last TRB */ 4106 if (j < trbs_per_td - 1) { 4107 more_trbs_coming = true; 4108 field |= TRB_CHAIN; 4109 } else { 4110 more_trbs_coming = false; 4111 td->last_trb = ep_ring->enqueue; 4112 td->last_trb_seg = ep_ring->enq_seg; 4113 field |= TRB_IOC; 4114 if (trb_block_event_intr(xhci, num_tds, i)) 4115 field |= TRB_BEI; 4116 } 4117 /* Calculate TRB length */ 4118 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 4119 if (trb_buff_len > td_remain_len) 4120 trb_buff_len = td_remain_len; 4121 4122 /* Set the TRB length, TD size, & interrupter fields. */ 4123 remainder = xhci_td_remainder(xhci, running_total, 4124 trb_buff_len, td_len, 4125 urb, more_trbs_coming); 4126 4127 length_field = TRB_LEN(trb_buff_len) | 4128 TRB_INTR_TARGET(0); 4129 4130 /* xhci 1.1 with ETE uses TD Size field for TBC */ 4131 if (first_trb && xep->use_extended_tbc) 4132 length_field |= TRB_TD_SIZE_TBC(burst_count); 4133 else 4134 length_field |= TRB_TD_SIZE(remainder); 4135 first_trb = false; 4136 4137 queue_trb(xhci, ep_ring, more_trbs_coming, 4138 lower_32_bits(addr), 4139 upper_32_bits(addr), 4140 length_field, 4141 field); 4142 running_total += trb_buff_len; 4143 4144 addr += trb_buff_len; 4145 td_remain_len -= trb_buff_len; 4146 } 4147 4148 /* Check TD length */ 4149 if (running_total != td_len) { 4150 xhci_err(xhci, "ISOC TD length unmatch\n"); 4151 ret = -EINVAL; 4152 goto cleanup; 4153 } 4154 } 4155 4156 /* store the next frame id */ 4157 if (HCC_CFC(xhci->hcc_params)) 4158 xep->next_frame_id = urb->start_frame + num_tds * urb->interval; 4159 4160 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 4161 if (xhci->quirks & XHCI_AMD_PLL_FIX) 4162 usb_amd_quirk_pll_disable(); 4163 } 4164 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; 4165 4166 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 4167 start_cycle, start_trb); 4168 return 0; 4169 cleanup: 4170 /* Clean up a partially enqueued isoc transfer. */ 4171 4172 for (i--; i >= 0; i--) 4173 list_del_init(&urb_priv->td[i].td_list); 4174 4175 /* Use the first TD as a temporary variable to turn the TDs we've queued 4176 * into No-ops with a software-owned cycle bit. That way the hardware 4177 * won't accidentally start executing bogus TDs when we partially 4178 * overwrite them. td->first_trb and td->start_seg are already set. 4179 */ 4180 urb_priv->td[0].last_trb = ep_ring->enqueue; 4181 /* Every TRB except the first & last will have its cycle bit flipped. */ 4182 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); 4183 4184 /* Reset the ring enqueue back to the first TRB and its cycle bit. */ 4185 ep_ring->enqueue = urb_priv->td[0].first_trb; 4186 ep_ring->enq_seg = urb_priv->td[0].start_seg; 4187 ep_ring->cycle_state = start_cycle; 4188 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; 4189 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 4190 return ret; 4191 } 4192 4193 /* 4194 * Check transfer ring to guarantee there is enough room for the urb. 4195 * Update ISO URB start_frame and interval. 4196 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to 4197 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or 4198 * Contiguous Frame ID is not supported by HC. 4199 */ 4200 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 4201 struct urb *urb, int slot_id, unsigned int ep_index) 4202 { 4203 struct xhci_virt_device *xdev; 4204 struct xhci_ring *ep_ring; 4205 struct xhci_ep_ctx *ep_ctx; 4206 int start_frame; 4207 int num_tds, num_trbs, i; 4208 int ret; 4209 struct xhci_virt_ep *xep; 4210 int ist; 4211 4212 xdev = xhci->devs[slot_id]; 4213 xep = &xhci->devs[slot_id]->eps[ep_index]; 4214 ep_ring = xdev->eps[ep_index].ring; 4215 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 4216 4217 num_trbs = 0; 4218 num_tds = urb->number_of_packets; 4219 for (i = 0; i < num_tds; i++) 4220 num_trbs += count_isoc_trbs_needed(urb, i); 4221 4222 /* Check the ring to guarantee there is enough room for the whole urb. 4223 * Do not insert any td of the urb to the ring if the check failed. 4224 */ 4225 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 4226 num_trbs, mem_flags); 4227 if (ret) 4228 return ret; 4229 4230 /* 4231 * Check interval value. This should be done before we start to 4232 * calculate the start frame value. 4233 */ 4234 check_interval(xhci, urb, ep_ctx); 4235 4236 /* Calculate the start frame and put it in urb->start_frame. */ 4237 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { 4238 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { 4239 urb->start_frame = xep->next_frame_id; 4240 goto skip_start_over; 4241 } 4242 } 4243 4244 start_frame = readl(&xhci->run_regs->microframe_index); 4245 start_frame &= 0x3fff; 4246 /* 4247 * Round up to the next frame and consider the time before trb really 4248 * gets scheduled by hardare. 4249 */ 4250 ist = HCS_IST(xhci->hcs_params2) & 0x7; 4251 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 4252 ist <<= 3; 4253 start_frame += ist + XHCI_CFC_DELAY; 4254 start_frame = roundup(start_frame, 8); 4255 4256 /* 4257 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT 4258 * is greate than 8 microframes. 4259 */ 4260 if (urb->dev->speed == USB_SPEED_LOW || 4261 urb->dev->speed == USB_SPEED_FULL) { 4262 start_frame = roundup(start_frame, urb->interval << 3); 4263 urb->start_frame = start_frame >> 3; 4264 } else { 4265 start_frame = roundup(start_frame, urb->interval); 4266 urb->start_frame = start_frame; 4267 } 4268 4269 skip_start_over: 4270 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; 4271 4272 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); 4273 } 4274 4275 /**** Command Ring Operations ****/ 4276 4277 /* Generic function for queueing a command TRB on the command ring. 4278 * Check to make sure there's room on the command ring for one command TRB. 4279 * Also check that there's room reserved for commands that must not fail. 4280 * If this is a command that must not fail, meaning command_must_succeed = TRUE, 4281 * then only check for the number of reserved spots. 4282 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB 4283 * because the command event handler may want to resubmit a failed command. 4284 */ 4285 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 4286 u32 field1, u32 field2, 4287 u32 field3, u32 field4, bool command_must_succeed) 4288 { 4289 int reserved_trbs = xhci->cmd_ring_reserved_trbs; 4290 int ret; 4291 4292 if ((xhci->xhc_state & XHCI_STATE_DYING) || 4293 (xhci->xhc_state & XHCI_STATE_HALTED)) { 4294 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); 4295 return -ESHUTDOWN; 4296 } 4297 4298 if (!command_must_succeed) 4299 reserved_trbs++; 4300 4301 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, 4302 reserved_trbs, GFP_ATOMIC); 4303 if (ret < 0) { 4304 xhci_err(xhci, "ERR: No room for command on command ring\n"); 4305 if (command_must_succeed) 4306 xhci_err(xhci, "ERR: Reserved TRB counting for " 4307 "unfailable commands failed.\n"); 4308 return ret; 4309 } 4310 4311 cmd->command_trb = xhci->cmd_ring->enqueue; 4312 4313 /* if there are no other commands queued we start the timeout timer */ 4314 if (list_empty(&xhci->cmd_list)) { 4315 xhci->current_cmd = cmd; 4316 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 4317 } 4318 4319 list_add_tail(&cmd->cmd_list, &xhci->cmd_list); 4320 4321 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, 4322 field4 | xhci->cmd_ring->cycle_state); 4323 return 0; 4324 } 4325 4326 /* Queue a slot enable or disable request on the command ring */ 4327 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 4328 u32 trb_type, u32 slot_id) 4329 { 4330 return queue_command(xhci, cmd, 0, 0, 0, 4331 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); 4332 } 4333 4334 /* Queue an address device command TRB */ 4335 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 4336 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) 4337 { 4338 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4339 upper_32_bits(in_ctx_ptr), 0, 4340 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) 4341 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); 4342 } 4343 4344 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 4345 u32 field1, u32 field2, u32 field3, u32 field4) 4346 { 4347 return queue_command(xhci, cmd, field1, field2, field3, field4, false); 4348 } 4349 4350 /* Queue a reset device command TRB */ 4351 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 4352 u32 slot_id) 4353 { 4354 return queue_command(xhci, cmd, 0, 0, 0, 4355 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), 4356 false); 4357 } 4358 4359 /* Queue a configure endpoint command TRB */ 4360 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 4361 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 4362 u32 slot_id, bool command_must_succeed) 4363 { 4364 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4365 upper_32_bits(in_ctx_ptr), 0, 4366 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), 4367 command_must_succeed); 4368 } 4369 4370 /* Queue an evaluate context command TRB */ 4371 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 4372 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) 4373 { 4374 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4375 upper_32_bits(in_ctx_ptr), 0, 4376 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), 4377 command_must_succeed); 4378 } 4379 4380 /* 4381 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop 4382 * activity on an endpoint that is about to be suspended. 4383 */ 4384 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 4385 int slot_id, unsigned int ep_index, int suspend) 4386 { 4387 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4388 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4389 u32 type = TRB_TYPE(TRB_STOP_RING); 4390 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); 4391 4392 return queue_command(xhci, cmd, 0, 0, 0, 4393 trb_slot_id | trb_ep_index | type | trb_suspend, false); 4394 } 4395 4396 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 4397 int slot_id, unsigned int ep_index, 4398 enum xhci_ep_reset_type reset_type) 4399 { 4400 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4401 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4402 u32 type = TRB_TYPE(TRB_RESET_EP); 4403 4404 if (reset_type == EP_SOFT_RESET) 4405 type |= TRB_TSP; 4406 4407 return queue_command(xhci, cmd, 0, 0, 0, 4408 trb_slot_id | trb_ep_index | type, false); 4409 } 4410