1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 /* 24 * Ring initialization rules: 25 * 1. Each segment is initialized to zero, except for link TRBs. 26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or 27 * Consumer Cycle State (CCS), depending on ring function. 28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. 29 * 30 * Ring behavior rules: 31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at 32 * least one free TRB in the ring. This is useful if you want to turn that 33 * into a link TRB and expand the ring. 34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a 35 * link TRB, then load the pointer with the address in the link TRB. If the 36 * link TRB had its toggle bit set, you may need to update the ring cycle 37 * state (see cycle bit rules). You may have to do this multiple times 38 * until you reach a non-link TRB. 39 * 3. A ring is full if enqueue++ (for the definition of increment above) 40 * equals the dequeue pointer. 41 * 42 * Cycle bit rules: 43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit 44 * in a link TRB, it must toggle the ring cycle state. 45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit 46 * in a link TRB, it must toggle the ring cycle state. 47 * 48 * Producer rules: 49 * 1. Check if ring is full before you enqueue. 50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. 51 * Update enqueue pointer between each write (which may update the ring 52 * cycle state). 53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command 54 * and endpoint rings. If HC is the producer for the event ring, 55 * and it generates an interrupt according to interrupt modulation rules. 56 * 57 * Consumer rules: 58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, 59 * the TRB is owned by the consumer. 60 * 2. Update dequeue pointer (which may update the ring cycle state) and 61 * continue processing TRBs until you reach a TRB which is not owned by you. 62 * 3. Notify the producer. SW is the consumer for the event ring, and it 63 * updates event ring dequeue pointer. HC is the consumer for the command and 64 * endpoint rings; it generates events on the event ring for these. 65 */ 66 67 #include <linux/scatterlist.h> 68 #include <linux/slab.h> 69 #include <linux/dma-mapping.h> 70 #include "xhci.h" 71 #include "xhci-trace.h" 72 #include "xhci-mtk.h" 73 74 /* 75 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA 76 * address of the TRB. 77 */ 78 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, 79 union xhci_trb *trb) 80 { 81 unsigned long segment_offset; 82 83 if (!seg || !trb || trb < seg->trbs) 84 return 0; 85 /* offset in TRBs */ 86 segment_offset = trb - seg->trbs; 87 if (segment_offset >= TRBS_PER_SEGMENT) 88 return 0; 89 return seg->dma + (segment_offset * sizeof(*trb)); 90 } 91 92 static bool trb_is_noop(union xhci_trb *trb) 93 { 94 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); 95 } 96 97 static bool trb_is_link(union xhci_trb *trb) 98 { 99 return TRB_TYPE_LINK_LE32(trb->link.control); 100 } 101 102 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) 103 { 104 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; 105 } 106 107 static bool last_trb_on_ring(struct xhci_ring *ring, 108 struct xhci_segment *seg, union xhci_trb *trb) 109 { 110 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); 111 } 112 113 static bool link_trb_toggles_cycle(union xhci_trb *trb) 114 { 115 return le32_to_cpu(trb->link.control) & LINK_TOGGLE; 116 } 117 118 static bool last_td_in_urb(struct xhci_td *td) 119 { 120 struct urb_priv *urb_priv = td->urb->hcpriv; 121 122 return urb_priv->num_tds_done == urb_priv->num_tds; 123 } 124 125 static void inc_td_cnt(struct urb *urb) 126 { 127 struct urb_priv *urb_priv = urb->hcpriv; 128 129 urb_priv->num_tds_done++; 130 } 131 132 static void trb_to_noop(union xhci_trb *trb, u32 noop_type) 133 { 134 if (trb_is_link(trb)) { 135 /* unchain chained link TRBs */ 136 trb->link.control &= cpu_to_le32(~TRB_CHAIN); 137 } else { 138 trb->generic.field[0] = 0; 139 trb->generic.field[1] = 0; 140 trb->generic.field[2] = 0; 141 /* Preserve only the cycle bit of this TRB */ 142 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); 143 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); 144 } 145 } 146 147 /* Updates trb to point to the next TRB in the ring, and updates seg if the next 148 * TRB is in a new segment. This does not skip over link TRBs, and it does not 149 * effect the ring dequeue or enqueue pointers. 150 */ 151 static void next_trb(struct xhci_hcd *xhci, 152 struct xhci_ring *ring, 153 struct xhci_segment **seg, 154 union xhci_trb **trb) 155 { 156 if (trb_is_link(*trb)) { 157 *seg = (*seg)->next; 158 *trb = ((*seg)->trbs); 159 } else { 160 (*trb)++; 161 } 162 } 163 164 /* 165 * See Cycle bit rules. SW is the consumer for the event ring only. 166 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 167 */ 168 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) 169 { 170 /* event ring doesn't have link trbs, check for last trb */ 171 if (ring->type == TYPE_EVENT) { 172 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { 173 ring->dequeue++; 174 return; 175 } 176 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) 177 ring->cycle_state ^= 1; 178 ring->deq_seg = ring->deq_seg->next; 179 ring->dequeue = ring->deq_seg->trbs; 180 return; 181 } 182 183 /* All other rings have link trbs */ 184 if (!trb_is_link(ring->dequeue)) { 185 ring->dequeue++; 186 ring->num_trbs_free++; 187 } 188 while (trb_is_link(ring->dequeue)) { 189 ring->deq_seg = ring->deq_seg->next; 190 ring->dequeue = ring->deq_seg->trbs; 191 } 192 193 trace_xhci_inc_deq(ring); 194 195 return; 196 } 197 198 /* 199 * See Cycle bit rules. SW is the consumer for the event ring only. 200 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 201 * 202 * If we've just enqueued a TRB that is in the middle of a TD (meaning the 203 * chain bit is set), then set the chain bit in all the following link TRBs. 204 * If we've enqueued the last TRB in a TD, make sure the following link TRBs 205 * have their chain bit cleared (so that each Link TRB is a separate TD). 206 * 207 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit 208 * set, but other sections talk about dealing with the chain bit set. This was 209 * fixed in the 0.96 specification errata, but we have to assume that all 0.95 210 * xHCI hardware can't handle the chain bit being cleared on a link TRB. 211 * 212 * @more_trbs_coming: Will you enqueue more TRBs before calling 213 * prepare_transfer()? 214 */ 215 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, 216 bool more_trbs_coming) 217 { 218 u32 chain; 219 union xhci_trb *next; 220 221 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; 222 /* If this is not event ring, there is one less usable TRB */ 223 if (!trb_is_link(ring->enqueue)) 224 ring->num_trbs_free--; 225 next = ++(ring->enqueue); 226 227 /* Update the dequeue pointer further if that was a link TRB */ 228 while (trb_is_link(next)) { 229 230 /* 231 * If the caller doesn't plan on enqueueing more TDs before 232 * ringing the doorbell, then we don't want to give the link TRB 233 * to the hardware just yet. We'll give the link TRB back in 234 * prepare_ring() just before we enqueue the TD at the top of 235 * the ring. 236 */ 237 if (!chain && !more_trbs_coming) 238 break; 239 240 /* If we're not dealing with 0.95 hardware or isoc rings on 241 * AMD 0.96 host, carry over the chain bit of the previous TRB 242 * (which may mean the chain bit is cleared). 243 */ 244 if (!(ring->type == TYPE_ISOC && 245 (xhci->quirks & XHCI_AMD_0x96_HOST)) && 246 !xhci_link_trb_quirk(xhci)) { 247 next->link.control &= cpu_to_le32(~TRB_CHAIN); 248 next->link.control |= cpu_to_le32(chain); 249 } 250 /* Give this link TRB to the hardware */ 251 wmb(); 252 next->link.control ^= cpu_to_le32(TRB_CYCLE); 253 254 /* Toggle the cycle bit after the last ring segment. */ 255 if (link_trb_toggles_cycle(next)) 256 ring->cycle_state ^= 1; 257 258 ring->enq_seg = ring->enq_seg->next; 259 ring->enqueue = ring->enq_seg->trbs; 260 next = ring->enqueue; 261 } 262 263 trace_xhci_inc_enq(ring); 264 } 265 266 /* 267 * Check to see if there's room to enqueue num_trbs on the ring and make sure 268 * enqueue pointer will not advance into dequeue segment. See rules above. 269 */ 270 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, 271 unsigned int num_trbs) 272 { 273 int num_trbs_in_deq_seg; 274 275 if (ring->num_trbs_free < num_trbs) 276 return 0; 277 278 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { 279 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; 280 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) 281 return 0; 282 } 283 284 return 1; 285 } 286 287 /* Ring the host controller doorbell after placing a command on the ring */ 288 void xhci_ring_cmd_db(struct xhci_hcd *xhci) 289 { 290 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) 291 return; 292 293 xhci_dbg(xhci, "// Ding dong!\n"); 294 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); 295 /* Flush PCI posted writes */ 296 readl(&xhci->dba->doorbell[0]); 297 } 298 299 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) 300 { 301 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); 302 } 303 304 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) 305 { 306 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, 307 cmd_list); 308 } 309 310 /* 311 * Turn all commands on command ring with status set to "aborted" to no-op trbs. 312 * If there are other commands waiting then restart the ring and kick the timer. 313 * This must be called with command ring stopped and xhci->lock held. 314 */ 315 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, 316 struct xhci_command *cur_cmd) 317 { 318 struct xhci_command *i_cmd; 319 320 /* Turn all aborted commands in list to no-ops, then restart */ 321 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { 322 323 if (i_cmd->status != COMP_COMMAND_ABORTED) 324 continue; 325 326 i_cmd->status = COMP_COMMAND_RING_STOPPED; 327 328 xhci_dbg(xhci, "Turn aborted command %p to no-op\n", 329 i_cmd->command_trb); 330 331 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); 332 333 /* 334 * caller waiting for completion is called when command 335 * completion event is received for these no-op commands 336 */ 337 } 338 339 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; 340 341 /* ring command ring doorbell to restart the command ring */ 342 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && 343 !(xhci->xhc_state & XHCI_STATE_DYING)) { 344 xhci->current_cmd = cur_cmd; 345 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 346 xhci_ring_cmd_db(xhci); 347 } 348 } 349 350 /* Must be called with xhci->lock held, releases and aquires lock back */ 351 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) 352 { 353 u64 temp_64; 354 int ret; 355 356 xhci_dbg(xhci, "Abort command ring\n"); 357 358 reinit_completion(&xhci->cmd_ring_stop_completion); 359 360 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 361 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, 362 &xhci->op_regs->cmd_ring); 363 364 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the 365 * completion of the Command Abort operation. If CRR is not negated in 5 366 * seconds then driver handles it as if host died (-ENODEV). 367 * In the future we should distinguish between -ENODEV and -ETIMEDOUT 368 * and try to recover a -ETIMEDOUT with a host controller reset. 369 */ 370 ret = xhci_handshake(&xhci->op_regs->cmd_ring, 371 CMD_RING_RUNNING, 0, 5 * 1000 * 1000); 372 if (ret < 0) { 373 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); 374 xhci_halt(xhci); 375 xhci_hc_died(xhci); 376 return ret; 377 } 378 /* 379 * Writing the CMD_RING_ABORT bit should cause a cmd completion event, 380 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared 381 * but the completion event in never sent. Wait 2 secs (arbitrary 382 * number) to handle those cases after negation of CMD_RING_RUNNING. 383 */ 384 spin_unlock_irqrestore(&xhci->lock, flags); 385 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, 386 msecs_to_jiffies(2000)); 387 spin_lock_irqsave(&xhci->lock, flags); 388 if (!ret) { 389 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); 390 xhci_cleanup_command_queue(xhci); 391 } else { 392 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); 393 } 394 return 0; 395 } 396 397 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, 398 unsigned int slot_id, 399 unsigned int ep_index, 400 unsigned int stream_id) 401 { 402 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; 403 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 404 unsigned int ep_state = ep->ep_state; 405 406 /* Don't ring the doorbell for this endpoint if there are pending 407 * cancellations because we don't want to interrupt processing. 408 * We don't want to restart any stream rings if there's a set dequeue 409 * pointer command pending because the device can choose to start any 410 * stream once the endpoint is on the HW schedule. 411 */ 412 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || 413 (ep_state & EP_HALTED)) 414 return; 415 writel(DB_VALUE(ep_index, stream_id), db_addr); 416 /* The CPU has better things to do at this point than wait for a 417 * write-posting flush. It'll get there soon enough. 418 */ 419 } 420 421 /* Ring the doorbell for any rings with pending URBs */ 422 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 423 unsigned int slot_id, 424 unsigned int ep_index) 425 { 426 unsigned int stream_id; 427 struct xhci_virt_ep *ep; 428 429 ep = &xhci->devs[slot_id]->eps[ep_index]; 430 431 /* A ring has pending URBs if its TD list is not empty */ 432 if (!(ep->ep_state & EP_HAS_STREAMS)) { 433 if (ep->ring && !(list_empty(&ep->ring->td_list))) 434 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); 435 return; 436 } 437 438 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 439 stream_id++) { 440 struct xhci_stream_info *stream_info = ep->stream_info; 441 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) 442 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 443 stream_id); 444 } 445 } 446 447 /* Get the right ring for the given slot_id, ep_index and stream_id. 448 * If the endpoint supports streams, boundary check the URB's stream ID. 449 * If the endpoint doesn't support streams, return the singular endpoint ring. 450 */ 451 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 452 unsigned int slot_id, unsigned int ep_index, 453 unsigned int stream_id) 454 { 455 struct xhci_virt_ep *ep; 456 457 ep = &xhci->devs[slot_id]->eps[ep_index]; 458 /* Common case: no streams */ 459 if (!(ep->ep_state & EP_HAS_STREAMS)) 460 return ep->ring; 461 462 if (stream_id == 0) { 463 xhci_warn(xhci, 464 "WARN: Slot ID %u, ep index %u has streams, " 465 "but URB has no stream ID.\n", 466 slot_id, ep_index); 467 return NULL; 468 } 469 470 if (stream_id < ep->stream_info->num_streams) 471 return ep->stream_info->stream_rings[stream_id]; 472 473 xhci_warn(xhci, 474 "WARN: Slot ID %u, ep index %u has " 475 "stream IDs 1 to %u allocated, " 476 "but stream ID %u is requested.\n", 477 slot_id, ep_index, 478 ep->stream_info->num_streams - 1, 479 stream_id); 480 return NULL; 481 } 482 483 484 /* 485 * Get the hw dequeue pointer xHC stopped on, either directly from the 486 * endpoint context, or if streams are in use from the stream context. 487 * The returned hw_dequeue contains the lowest four bits with cycle state 488 * and possbile stream context type. 489 */ 490 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, 491 unsigned int ep_index, unsigned int stream_id) 492 { 493 struct xhci_ep_ctx *ep_ctx; 494 struct xhci_stream_ctx *st_ctx; 495 struct xhci_virt_ep *ep; 496 497 ep = &vdev->eps[ep_index]; 498 499 if (ep->ep_state & EP_HAS_STREAMS) { 500 st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; 501 return le64_to_cpu(st_ctx->stream_ring); 502 } 503 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 504 return le64_to_cpu(ep_ctx->deq); 505 } 506 507 /* 508 * Move the xHC's endpoint ring dequeue pointer past cur_td. 509 * Record the new state of the xHC's endpoint ring dequeue segment, 510 * dequeue pointer, stream id, and new consumer cycle state in state. 511 * Update our internal representation of the ring's dequeue pointer. 512 * 513 * We do this in three jumps: 514 * - First we update our new ring state to be the same as when the xHC stopped. 515 * - Then we traverse the ring to find the segment that contains 516 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass 517 * any link TRBs with the toggle cycle bit set. 518 * - Finally we move the dequeue state one TRB further, toggling the cycle bit 519 * if we've moved it past a link TRB with the toggle cycle bit set. 520 * 521 * Some of the uses of xhci_generic_trb are grotty, but if they're done 522 * with correct __le32 accesses they should work fine. Only users of this are 523 * in here. 524 */ 525 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 526 unsigned int slot_id, unsigned int ep_index, 527 unsigned int stream_id, struct xhci_td *cur_td, 528 struct xhci_dequeue_state *state) 529 { 530 struct xhci_virt_device *dev = xhci->devs[slot_id]; 531 struct xhci_virt_ep *ep = &dev->eps[ep_index]; 532 struct xhci_ring *ep_ring; 533 struct xhci_segment *new_seg; 534 union xhci_trb *new_deq; 535 dma_addr_t addr; 536 u64 hw_dequeue; 537 bool cycle_found = false; 538 bool td_last_trb_found = false; 539 540 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, 541 ep_index, stream_id); 542 if (!ep_ring) { 543 xhci_warn(xhci, "WARN can't find new dequeue state " 544 "for invalid stream ID %u.\n", 545 stream_id); 546 return; 547 } 548 /* Dig out the cycle state saved by the xHC during the stop ep cmd */ 549 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 550 "Finding endpoint context"); 551 552 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); 553 new_seg = ep_ring->deq_seg; 554 new_deq = ep_ring->dequeue; 555 state->new_cycle_state = hw_dequeue & 0x1; 556 state->stream_id = stream_id; 557 558 /* 559 * We want to find the pointer, segment and cycle state of the new trb 560 * (the one after current TD's last_trb). We know the cycle state at 561 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are 562 * found. 563 */ 564 do { 565 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) 566 == (dma_addr_t)(hw_dequeue & ~0xf)) { 567 cycle_found = true; 568 if (td_last_trb_found) 569 break; 570 } 571 if (new_deq == cur_td->last_trb) 572 td_last_trb_found = true; 573 574 if (cycle_found && trb_is_link(new_deq) && 575 link_trb_toggles_cycle(new_deq)) 576 state->new_cycle_state ^= 0x1; 577 578 next_trb(xhci, ep_ring, &new_seg, &new_deq); 579 580 /* Search wrapped around, bail out */ 581 if (new_deq == ep->ring->dequeue) { 582 xhci_err(xhci, "Error: Failed finding new dequeue state\n"); 583 state->new_deq_seg = NULL; 584 state->new_deq_ptr = NULL; 585 return; 586 } 587 588 } while (!cycle_found || !td_last_trb_found); 589 590 state->new_deq_seg = new_seg; 591 state->new_deq_ptr = new_deq; 592 593 /* Don't update the ring cycle state for the producer (us). */ 594 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 595 "Cycle state = 0x%x", state->new_cycle_state); 596 597 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 598 "New dequeue segment = %p (virtual)", 599 state->new_deq_seg); 600 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); 601 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 602 "New dequeue pointer = 0x%llx (DMA)", 603 (unsigned long long) addr); 604 } 605 606 /* flip_cycle means flip the cycle bit of all but the first and last TRB. 607 * (The last TRB actually points to the ring enqueue pointer, which is not part 608 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. 609 */ 610 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 611 struct xhci_td *td, bool flip_cycle) 612 { 613 struct xhci_segment *seg = td->start_seg; 614 union xhci_trb *trb = td->first_trb; 615 616 while (1) { 617 trb_to_noop(trb, TRB_TR_NOOP); 618 619 /* flip cycle if asked to */ 620 if (flip_cycle && trb != td->first_trb && trb != td->last_trb) 621 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); 622 623 if (trb == td->last_trb) 624 break; 625 626 next_trb(xhci, ep_ring, &seg, &trb); 627 } 628 } 629 630 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, 631 struct xhci_virt_ep *ep) 632 { 633 ep->ep_state &= ~EP_STOP_CMD_PENDING; 634 /* Can't del_timer_sync in interrupt */ 635 del_timer(&ep->stop_cmd_timer); 636 } 637 638 /* 639 * Must be called with xhci->lock held in interrupt context, 640 * releases and re-acquires xhci->lock 641 */ 642 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 643 struct xhci_td *cur_td, int status) 644 { 645 struct urb *urb = cur_td->urb; 646 struct urb_priv *urb_priv = urb->hcpriv; 647 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); 648 649 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 650 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 651 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 652 if (xhci->quirks & XHCI_AMD_PLL_FIX) 653 usb_amd_quirk_pll_enable(); 654 } 655 } 656 xhci_urb_free_priv(urb_priv); 657 usb_hcd_unlink_urb_from_ep(hcd, urb); 658 spin_unlock(&xhci->lock); 659 trace_xhci_urb_giveback(urb); 660 usb_hcd_giveback_urb(hcd, urb, status); 661 spin_lock(&xhci->lock); 662 } 663 664 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, 665 struct xhci_ring *ring, struct xhci_td *td) 666 { 667 struct device *dev = xhci_to_hcd(xhci)->self.controller; 668 struct xhci_segment *seg = td->bounce_seg; 669 struct urb *urb = td->urb; 670 671 if (!ring || !seg || !urb) 672 return; 673 674 if (usb_urb_dir_out(urb)) { 675 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 676 DMA_TO_DEVICE); 677 return; 678 } 679 680 /* for in tranfers we need to copy the data from bounce to sg */ 681 sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, 682 seg->bounce_len, seg->bounce_offs); 683 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 684 DMA_FROM_DEVICE); 685 seg->bounce_len = 0; 686 seg->bounce_offs = 0; 687 } 688 689 /* 690 * When we get a command completion for a Stop Endpoint Command, we need to 691 * unlink any cancelled TDs from the ring. There are two ways to do that: 692 * 693 * 1. If the HW was in the middle of processing the TD that needs to be 694 * cancelled, then we must move the ring's dequeue pointer past the last TRB 695 * in the TD with a Set Dequeue Pointer Command. 696 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain 697 * bit cleared) so that the HW will skip over them. 698 */ 699 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, 700 union xhci_trb *trb, struct xhci_event_cmd *event) 701 { 702 unsigned int ep_index; 703 struct xhci_ring *ep_ring; 704 struct xhci_virt_ep *ep; 705 struct xhci_td *cur_td = NULL; 706 struct xhci_td *last_unlinked_td; 707 struct xhci_ep_ctx *ep_ctx; 708 struct xhci_virt_device *vdev; 709 u64 hw_deq; 710 struct xhci_dequeue_state deq_state; 711 712 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { 713 if (!xhci->devs[slot_id]) 714 xhci_warn(xhci, "Stop endpoint command " 715 "completion for disabled slot %u\n", 716 slot_id); 717 return; 718 } 719 720 memset(&deq_state, 0, sizeof(deq_state)); 721 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 722 723 vdev = xhci->devs[slot_id]; 724 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 725 trace_xhci_handle_cmd_stop_ep(ep_ctx); 726 727 ep = &xhci->devs[slot_id]->eps[ep_index]; 728 last_unlinked_td = list_last_entry(&ep->cancelled_td_list, 729 struct xhci_td, cancelled_td_list); 730 731 if (list_empty(&ep->cancelled_td_list)) { 732 xhci_stop_watchdog_timer_in_irq(xhci, ep); 733 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 734 return; 735 } 736 737 /* Fix up the ep ring first, so HW stops executing cancelled TDs. 738 * We have the xHCI lock, so nothing can modify this list until we drop 739 * it. We're also in the event handler, so we can't get re-interrupted 740 * if another Stop Endpoint command completes 741 */ 742 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) { 743 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 744 "Removing canceled TD starting at 0x%llx (dma).", 745 (unsigned long long)xhci_trb_virt_to_dma( 746 cur_td->start_seg, cur_td->first_trb)); 747 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 748 if (!ep_ring) { 749 /* This shouldn't happen unless a driver is mucking 750 * with the stream ID after submission. This will 751 * leave the TD on the hardware ring, and the hardware 752 * will try to execute it, and may access a buffer 753 * that has already been freed. In the best case, the 754 * hardware will execute it, and the event handler will 755 * ignore the completion event for that TD, since it was 756 * removed from the td_list for that endpoint. In 757 * short, don't muck with the stream ID after 758 * submission. 759 */ 760 xhci_warn(xhci, "WARN Cancelled URB %p " 761 "has invalid stream ID %u.\n", 762 cur_td->urb, 763 cur_td->urb->stream_id); 764 goto remove_finished_td; 765 } 766 /* 767 * If we stopped on the TD we need to cancel, then we have to 768 * move the xHC endpoint ring dequeue pointer past this TD. 769 */ 770 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index, 771 cur_td->urb->stream_id); 772 hw_deq &= ~0xf; 773 774 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb, 775 cur_td->last_trb, hw_deq, false)) { 776 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, 777 cur_td->urb->stream_id, 778 cur_td, &deq_state); 779 } else { 780 td_to_noop(xhci, ep_ring, cur_td, false); 781 } 782 783 remove_finished_td: 784 /* 785 * The event handler won't see a completion for this TD anymore, 786 * so remove it from the endpoint ring's TD list. Keep it in 787 * the cancelled TD list for URB completion later. 788 */ 789 list_del_init(&cur_td->td_list); 790 } 791 792 xhci_stop_watchdog_timer_in_irq(xhci, ep); 793 794 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ 795 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { 796 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, 797 &deq_state); 798 xhci_ring_cmd_db(xhci); 799 } else { 800 /* Otherwise ring the doorbell(s) to restart queued transfers */ 801 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 802 } 803 804 /* 805 * Drop the lock and complete the URBs in the cancelled TD list. 806 * New TDs to be cancelled might be added to the end of the list before 807 * we can complete all the URBs for the TDs we already unlinked. 808 * So stop when we've completed the URB for the last TD we unlinked. 809 */ 810 do { 811 cur_td = list_first_entry(&ep->cancelled_td_list, 812 struct xhci_td, cancelled_td_list); 813 list_del_init(&cur_td->cancelled_td_list); 814 815 /* Clean up the cancelled URB */ 816 /* Doesn't matter what we pass for status, since the core will 817 * just overwrite it (because the URB has been unlinked). 818 */ 819 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 820 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); 821 inc_td_cnt(cur_td->urb); 822 if (last_td_in_urb(cur_td)) 823 xhci_giveback_urb_in_irq(xhci, cur_td, 0); 824 825 /* Stop processing the cancelled list if the watchdog timer is 826 * running. 827 */ 828 if (xhci->xhc_state & XHCI_STATE_DYING) 829 return; 830 } while (cur_td != last_unlinked_td); 831 832 /* Return to the event handler with xhci->lock re-acquired */ 833 } 834 835 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) 836 { 837 struct xhci_td *cur_td; 838 struct xhci_td *tmp; 839 840 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { 841 list_del_init(&cur_td->td_list); 842 843 if (!list_empty(&cur_td->cancelled_td_list)) 844 list_del_init(&cur_td->cancelled_td_list); 845 846 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); 847 848 inc_td_cnt(cur_td->urb); 849 if (last_td_in_urb(cur_td)) 850 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 851 } 852 } 853 854 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, 855 int slot_id, int ep_index) 856 { 857 struct xhci_td *cur_td; 858 struct xhci_td *tmp; 859 struct xhci_virt_ep *ep; 860 struct xhci_ring *ring; 861 862 ep = &xhci->devs[slot_id]->eps[ep_index]; 863 if ((ep->ep_state & EP_HAS_STREAMS) || 864 (ep->ep_state & EP_GETTING_NO_STREAMS)) { 865 int stream_id; 866 867 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 868 stream_id++) { 869 ring = ep->stream_info->stream_rings[stream_id]; 870 if (!ring) 871 continue; 872 873 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 874 "Killing URBs for slot ID %u, ep index %u, stream %u", 875 slot_id, ep_index, stream_id); 876 xhci_kill_ring_urbs(xhci, ring); 877 } 878 } else { 879 ring = ep->ring; 880 if (!ring) 881 return; 882 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 883 "Killing URBs for slot ID %u, ep index %u", 884 slot_id, ep_index); 885 xhci_kill_ring_urbs(xhci, ring); 886 } 887 888 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, 889 cancelled_td_list) { 890 list_del_init(&cur_td->cancelled_td_list); 891 inc_td_cnt(cur_td->urb); 892 893 if (last_td_in_urb(cur_td)) 894 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 895 } 896 } 897 898 /* 899 * host controller died, register read returns 0xffffffff 900 * Complete pending commands, mark them ABORTED. 901 * URBs need to be given back as usb core might be waiting with device locks 902 * held for the URBs to finish during device disconnect, blocking host remove. 903 * 904 * Call with xhci->lock held. 905 * lock is relased and re-acquired while giving back urb. 906 */ 907 void xhci_hc_died(struct xhci_hcd *xhci) 908 { 909 int i, j; 910 911 if (xhci->xhc_state & XHCI_STATE_DYING) 912 return; 913 914 xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); 915 xhci->xhc_state |= XHCI_STATE_DYING; 916 917 xhci_cleanup_command_queue(xhci); 918 919 /* return any pending urbs, remove may be waiting for them */ 920 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 921 if (!xhci->devs[i]) 922 continue; 923 for (j = 0; j < 31; j++) 924 xhci_kill_endpoint_urbs(xhci, i, j); 925 } 926 927 /* inform usb core hc died if PCI remove isn't already handling it */ 928 if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) 929 usb_hc_died(xhci_to_hcd(xhci)); 930 } 931 932 /* Watchdog timer function for when a stop endpoint command fails to complete. 933 * In this case, we assume the host controller is broken or dying or dead. The 934 * host may still be completing some other events, so we have to be careful to 935 * let the event ring handler and the URB dequeueing/enqueueing functions know 936 * through xhci->state. 937 * 938 * The timer may also fire if the host takes a very long time to respond to the 939 * command, and the stop endpoint command completion handler cannot delete the 940 * timer before the timer function is called. Another endpoint cancellation may 941 * sneak in before the timer function can grab the lock, and that may queue 942 * another stop endpoint command and add the timer back. So we cannot use a 943 * simple flag to say whether there is a pending stop endpoint command for a 944 * particular endpoint. 945 * 946 * Instead we use a combination of that flag and checking if a new timer is 947 * pending. 948 */ 949 void xhci_stop_endpoint_command_watchdog(unsigned long arg) 950 { 951 struct xhci_hcd *xhci; 952 struct xhci_virt_ep *ep; 953 unsigned long flags; 954 955 ep = (struct xhci_virt_ep *) arg; 956 xhci = ep->xhci; 957 958 spin_lock_irqsave(&xhci->lock, flags); 959 960 /* bail out if cmd completed but raced with stop ep watchdog timer.*/ 961 if (!(ep->ep_state & EP_STOP_CMD_PENDING) || 962 timer_pending(&ep->stop_cmd_timer)) { 963 spin_unlock_irqrestore(&xhci->lock, flags); 964 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); 965 return; 966 } 967 968 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); 969 ep->ep_state &= ~EP_STOP_CMD_PENDING; 970 971 xhci_halt(xhci); 972 973 /* 974 * handle a stop endpoint cmd timeout as if host died (-ENODEV). 975 * In the future we could distinguish between -ENODEV and -ETIMEDOUT 976 * and try to recover a -ETIMEDOUT with a host controller reset 977 */ 978 xhci_hc_died(xhci); 979 980 spin_unlock_irqrestore(&xhci->lock, flags); 981 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 982 "xHCI host controller is dead."); 983 } 984 985 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, 986 struct xhci_virt_device *dev, 987 struct xhci_ring *ep_ring, 988 unsigned int ep_index) 989 { 990 union xhci_trb *dequeue_temp; 991 int num_trbs_free_temp; 992 bool revert = false; 993 994 num_trbs_free_temp = ep_ring->num_trbs_free; 995 dequeue_temp = ep_ring->dequeue; 996 997 /* If we get two back-to-back stalls, and the first stalled transfer 998 * ends just before a link TRB, the dequeue pointer will be left on 999 * the link TRB by the code in the while loop. So we have to update 1000 * the dequeue pointer one segment further, or we'll jump off 1001 * the segment into la-la-land. 1002 */ 1003 if (trb_is_link(ep_ring->dequeue)) { 1004 ep_ring->deq_seg = ep_ring->deq_seg->next; 1005 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1006 } 1007 1008 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { 1009 /* We have more usable TRBs */ 1010 ep_ring->num_trbs_free++; 1011 ep_ring->dequeue++; 1012 if (trb_is_link(ep_ring->dequeue)) { 1013 if (ep_ring->dequeue == 1014 dev->eps[ep_index].queued_deq_ptr) 1015 break; 1016 ep_ring->deq_seg = ep_ring->deq_seg->next; 1017 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1018 } 1019 if (ep_ring->dequeue == dequeue_temp) { 1020 revert = true; 1021 break; 1022 } 1023 } 1024 1025 if (revert) { 1026 xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); 1027 ep_ring->num_trbs_free = num_trbs_free_temp; 1028 } 1029 } 1030 1031 /* 1032 * When we get a completion for a Set Transfer Ring Dequeue Pointer command, 1033 * we need to clear the set deq pending flag in the endpoint ring state, so that 1034 * the TD queueing code can ring the doorbell again. We also need to ring the 1035 * endpoint doorbell to restart the ring, but only if there aren't more 1036 * cancellations pending. 1037 */ 1038 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, 1039 union xhci_trb *trb, u32 cmd_comp_code) 1040 { 1041 unsigned int ep_index; 1042 unsigned int stream_id; 1043 struct xhci_ring *ep_ring; 1044 struct xhci_virt_device *dev; 1045 struct xhci_virt_ep *ep; 1046 struct xhci_ep_ctx *ep_ctx; 1047 struct xhci_slot_ctx *slot_ctx; 1048 1049 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1050 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); 1051 dev = xhci->devs[slot_id]; 1052 ep = &dev->eps[ep_index]; 1053 1054 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); 1055 if (!ep_ring) { 1056 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", 1057 stream_id); 1058 /* XXX: Harmless??? */ 1059 goto cleanup; 1060 } 1061 1062 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 1063 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); 1064 trace_xhci_handle_cmd_set_deq(slot_ctx); 1065 trace_xhci_handle_cmd_set_deq_ep(ep_ctx); 1066 1067 if (cmd_comp_code != COMP_SUCCESS) { 1068 unsigned int ep_state; 1069 unsigned int slot_state; 1070 1071 switch (cmd_comp_code) { 1072 case COMP_TRB_ERROR: 1073 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); 1074 break; 1075 case COMP_CONTEXT_STATE_ERROR: 1076 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); 1077 ep_state = GET_EP_CTX_STATE(ep_ctx); 1078 slot_state = le32_to_cpu(slot_ctx->dev_state); 1079 slot_state = GET_SLOT_STATE(slot_state); 1080 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1081 "Slot state = %u, EP state = %u", 1082 slot_state, ep_state); 1083 break; 1084 case COMP_SLOT_NOT_ENABLED_ERROR: 1085 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", 1086 slot_id); 1087 break; 1088 default: 1089 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", 1090 cmd_comp_code); 1091 break; 1092 } 1093 /* OK what do we do now? The endpoint state is hosed, and we 1094 * should never get to this point if the synchronization between 1095 * queueing, and endpoint state are correct. This might happen 1096 * if the device gets disconnected after we've finished 1097 * cancelling URBs, which might not be an error... 1098 */ 1099 } else { 1100 u64 deq; 1101 /* 4.6.10 deq ptr is written to the stream ctx for streams */ 1102 if (ep->ep_state & EP_HAS_STREAMS) { 1103 struct xhci_stream_ctx *ctx = 1104 &ep->stream_info->stream_ctx_array[stream_id]; 1105 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; 1106 } else { 1107 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; 1108 } 1109 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1110 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); 1111 if (xhci_trb_virt_to_dma(ep->queued_deq_seg, 1112 ep->queued_deq_ptr) == deq) { 1113 /* Update the ring's dequeue segment and dequeue pointer 1114 * to reflect the new position. 1115 */ 1116 update_ring_for_set_deq_completion(xhci, dev, 1117 ep_ring, ep_index); 1118 } else { 1119 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); 1120 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", 1121 ep->queued_deq_seg, ep->queued_deq_ptr); 1122 } 1123 } 1124 1125 cleanup: 1126 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 1127 dev->eps[ep_index].queued_deq_seg = NULL; 1128 dev->eps[ep_index].queued_deq_ptr = NULL; 1129 /* Restart any rings with pending URBs */ 1130 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1131 } 1132 1133 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, 1134 union xhci_trb *trb, u32 cmd_comp_code) 1135 { 1136 struct xhci_virt_device *vdev; 1137 struct xhci_ep_ctx *ep_ctx; 1138 unsigned int ep_index; 1139 1140 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1141 vdev = xhci->devs[slot_id]; 1142 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 1143 trace_xhci_handle_cmd_reset_ep(ep_ctx); 1144 1145 /* This command will only fail if the endpoint wasn't halted, 1146 * but we don't care. 1147 */ 1148 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, 1149 "Ignoring reset ep completion code of %u", cmd_comp_code); 1150 1151 /* HW with the reset endpoint quirk needs to have a configure endpoint 1152 * command complete before the endpoint can be used. Queue that here 1153 * because the HW can't handle two commands being queued in a row. 1154 */ 1155 if (xhci->quirks & XHCI_RESET_EP_QUIRK) { 1156 struct xhci_command *command; 1157 1158 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); 1159 if (!command) 1160 return; 1161 1162 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1163 "Queueing configure endpoint command"); 1164 xhci_queue_configure_endpoint(xhci, command, 1165 xhci->devs[slot_id]->in_ctx->dma, slot_id, 1166 false); 1167 xhci_ring_cmd_db(xhci); 1168 } else { 1169 /* Clear our internal halted state */ 1170 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; 1171 } 1172 } 1173 1174 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, 1175 struct xhci_command *command, u32 cmd_comp_code) 1176 { 1177 if (cmd_comp_code == COMP_SUCCESS) 1178 command->slot_id = slot_id; 1179 else 1180 command->slot_id = 0; 1181 } 1182 1183 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) 1184 { 1185 struct xhci_virt_device *virt_dev; 1186 struct xhci_slot_ctx *slot_ctx; 1187 1188 virt_dev = xhci->devs[slot_id]; 1189 if (!virt_dev) 1190 return; 1191 1192 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); 1193 trace_xhci_handle_cmd_disable_slot(slot_ctx); 1194 1195 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) 1196 /* Delete default control endpoint resources */ 1197 xhci_free_device_endpoint_resources(xhci, virt_dev, true); 1198 xhci_free_virt_device(xhci, slot_id); 1199 } 1200 1201 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, 1202 struct xhci_event_cmd *event, u32 cmd_comp_code) 1203 { 1204 struct xhci_virt_device *virt_dev; 1205 struct xhci_input_control_ctx *ctrl_ctx; 1206 struct xhci_ep_ctx *ep_ctx; 1207 unsigned int ep_index; 1208 unsigned int ep_state; 1209 u32 add_flags, drop_flags; 1210 1211 /* 1212 * Configure endpoint commands can come from the USB core 1213 * configuration or alt setting changes, or because the HW 1214 * needed an extra configure endpoint command after a reset 1215 * endpoint command or streams were being configured. 1216 * If the command was for a halted endpoint, the xHCI driver 1217 * is not waiting on the configure endpoint command. 1218 */ 1219 virt_dev = xhci->devs[slot_id]; 1220 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); 1221 if (!ctrl_ctx) { 1222 xhci_warn(xhci, "Could not get input context, bad type.\n"); 1223 return; 1224 } 1225 1226 add_flags = le32_to_cpu(ctrl_ctx->add_flags); 1227 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); 1228 /* Input ctx add_flags are the endpoint index plus one */ 1229 ep_index = xhci_last_valid_endpoint(add_flags) - 1; 1230 1231 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); 1232 trace_xhci_handle_cmd_config_ep(ep_ctx); 1233 1234 /* A usb_set_interface() call directly after clearing a halted 1235 * condition may race on this quirky hardware. Not worth 1236 * worrying about, since this is prototype hardware. Not sure 1237 * if this will work for streams, but streams support was 1238 * untested on this prototype. 1239 */ 1240 if (xhci->quirks & XHCI_RESET_EP_QUIRK && 1241 ep_index != (unsigned int) -1 && 1242 add_flags - SLOT_FLAG == drop_flags) { 1243 ep_state = virt_dev->eps[ep_index].ep_state; 1244 if (!(ep_state & EP_HALTED)) 1245 return; 1246 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1247 "Completed config ep cmd - " 1248 "last ep index = %d, state = %d", 1249 ep_index, ep_state); 1250 /* Clear internal halted state and restart ring(s) */ 1251 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; 1252 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1253 return; 1254 } 1255 return; 1256 } 1257 1258 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) 1259 { 1260 struct xhci_virt_device *vdev; 1261 struct xhci_slot_ctx *slot_ctx; 1262 1263 vdev = xhci->devs[slot_id]; 1264 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1265 trace_xhci_handle_cmd_addr_dev(slot_ctx); 1266 } 1267 1268 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, 1269 struct xhci_event_cmd *event) 1270 { 1271 struct xhci_virt_device *vdev; 1272 struct xhci_slot_ctx *slot_ctx; 1273 1274 vdev = xhci->devs[slot_id]; 1275 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1276 trace_xhci_handle_cmd_reset_dev(slot_ctx); 1277 1278 xhci_dbg(xhci, "Completed reset device command.\n"); 1279 if (!xhci->devs[slot_id]) 1280 xhci_warn(xhci, "Reset device command completion " 1281 "for disabled slot %u\n", slot_id); 1282 } 1283 1284 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, 1285 struct xhci_event_cmd *event) 1286 { 1287 if (!(xhci->quirks & XHCI_NEC_HOST)) { 1288 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); 1289 return; 1290 } 1291 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1292 "NEC firmware version %2x.%02x", 1293 NEC_FW_MAJOR(le32_to_cpu(event->status)), 1294 NEC_FW_MINOR(le32_to_cpu(event->status))); 1295 } 1296 1297 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) 1298 { 1299 list_del(&cmd->cmd_list); 1300 1301 if (cmd->completion) { 1302 cmd->status = status; 1303 complete(cmd->completion); 1304 } else { 1305 kfree(cmd); 1306 } 1307 } 1308 1309 void xhci_cleanup_command_queue(struct xhci_hcd *xhci) 1310 { 1311 struct xhci_command *cur_cmd, *tmp_cmd; 1312 xhci->current_cmd = NULL; 1313 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) 1314 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); 1315 } 1316 1317 void xhci_handle_command_timeout(struct work_struct *work) 1318 { 1319 struct xhci_hcd *xhci; 1320 unsigned long flags; 1321 u64 hw_ring_state; 1322 1323 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); 1324 1325 spin_lock_irqsave(&xhci->lock, flags); 1326 1327 /* 1328 * If timeout work is pending, or current_cmd is NULL, it means we 1329 * raced with command completion. Command is handled so just return. 1330 */ 1331 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { 1332 spin_unlock_irqrestore(&xhci->lock, flags); 1333 return; 1334 } 1335 /* mark this command to be cancelled */ 1336 xhci->current_cmd->status = COMP_COMMAND_ABORTED; 1337 1338 /* Make sure command ring is running before aborting it */ 1339 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 1340 if (hw_ring_state == ~(u64)0) { 1341 xhci_hc_died(xhci); 1342 goto time_out_completed; 1343 } 1344 1345 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && 1346 (hw_ring_state & CMD_RING_RUNNING)) { 1347 /* Prevent new doorbell, and start command abort */ 1348 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; 1349 xhci_dbg(xhci, "Command timeout\n"); 1350 xhci_abort_cmd_ring(xhci, flags); 1351 goto time_out_completed; 1352 } 1353 1354 /* host removed. Bail out */ 1355 if (xhci->xhc_state & XHCI_STATE_REMOVING) { 1356 xhci_dbg(xhci, "host removed, ring start fail?\n"); 1357 xhci_cleanup_command_queue(xhci); 1358 1359 goto time_out_completed; 1360 } 1361 1362 /* command timeout on stopped ring, ring can't be aborted */ 1363 xhci_dbg(xhci, "Command timeout on stopped ring\n"); 1364 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); 1365 1366 time_out_completed: 1367 spin_unlock_irqrestore(&xhci->lock, flags); 1368 return; 1369 } 1370 1371 static void handle_cmd_completion(struct xhci_hcd *xhci, 1372 struct xhci_event_cmd *event) 1373 { 1374 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1375 u64 cmd_dma; 1376 dma_addr_t cmd_dequeue_dma; 1377 u32 cmd_comp_code; 1378 union xhci_trb *cmd_trb; 1379 struct xhci_command *cmd; 1380 u32 cmd_type; 1381 1382 cmd_dma = le64_to_cpu(event->cmd_trb); 1383 cmd_trb = xhci->cmd_ring->dequeue; 1384 1385 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); 1386 1387 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 1388 cmd_trb); 1389 /* 1390 * Check whether the completion event is for our internal kept 1391 * command. 1392 */ 1393 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { 1394 xhci_warn(xhci, 1395 "ERROR mismatched command completion event\n"); 1396 return; 1397 } 1398 1399 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); 1400 1401 cancel_delayed_work(&xhci->cmd_timer); 1402 1403 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); 1404 1405 /* If CMD ring stopped we own the trbs between enqueue and dequeue */ 1406 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { 1407 complete_all(&xhci->cmd_ring_stop_completion); 1408 return; 1409 } 1410 1411 if (cmd->command_trb != xhci->cmd_ring->dequeue) { 1412 xhci_err(xhci, 1413 "Command completion event does not match command\n"); 1414 return; 1415 } 1416 1417 /* 1418 * Host aborted the command ring, check if the current command was 1419 * supposed to be aborted, otherwise continue normally. 1420 * The command ring is stopped now, but the xHC will issue a Command 1421 * Ring Stopped event which will cause us to restart it. 1422 */ 1423 if (cmd_comp_code == COMP_COMMAND_ABORTED) { 1424 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; 1425 if (cmd->status == COMP_COMMAND_ABORTED) { 1426 if (xhci->current_cmd == cmd) 1427 xhci->current_cmd = NULL; 1428 goto event_handled; 1429 } 1430 } 1431 1432 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); 1433 switch (cmd_type) { 1434 case TRB_ENABLE_SLOT: 1435 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); 1436 break; 1437 case TRB_DISABLE_SLOT: 1438 xhci_handle_cmd_disable_slot(xhci, slot_id); 1439 break; 1440 case TRB_CONFIG_EP: 1441 if (!cmd->completion) 1442 xhci_handle_cmd_config_ep(xhci, slot_id, event, 1443 cmd_comp_code); 1444 break; 1445 case TRB_EVAL_CONTEXT: 1446 break; 1447 case TRB_ADDR_DEV: 1448 xhci_handle_cmd_addr_dev(xhci, slot_id); 1449 break; 1450 case TRB_STOP_RING: 1451 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1452 le32_to_cpu(cmd_trb->generic.field[3]))); 1453 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); 1454 break; 1455 case TRB_SET_DEQ: 1456 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1457 le32_to_cpu(cmd_trb->generic.field[3]))); 1458 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); 1459 break; 1460 case TRB_CMD_NOOP: 1461 /* Is this an aborted command turned to NO-OP? */ 1462 if (cmd->status == COMP_COMMAND_RING_STOPPED) 1463 cmd_comp_code = COMP_COMMAND_RING_STOPPED; 1464 break; 1465 case TRB_RESET_EP: 1466 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1467 le32_to_cpu(cmd_trb->generic.field[3]))); 1468 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); 1469 break; 1470 case TRB_RESET_DEV: 1471 /* SLOT_ID field in reset device cmd completion event TRB is 0. 1472 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) 1473 */ 1474 slot_id = TRB_TO_SLOT_ID( 1475 le32_to_cpu(cmd_trb->generic.field[3])); 1476 xhci_handle_cmd_reset_dev(xhci, slot_id, event); 1477 break; 1478 case TRB_NEC_GET_FW: 1479 xhci_handle_cmd_nec_get_fw(xhci, event); 1480 break; 1481 default: 1482 /* Skip over unknown commands on the event ring */ 1483 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); 1484 break; 1485 } 1486 1487 /* restart timer if this wasn't the last command */ 1488 if (!list_is_singular(&xhci->cmd_list)) { 1489 xhci->current_cmd = list_first_entry(&cmd->cmd_list, 1490 struct xhci_command, cmd_list); 1491 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 1492 } else if (xhci->current_cmd == cmd) { 1493 xhci->current_cmd = NULL; 1494 } 1495 1496 event_handled: 1497 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); 1498 1499 inc_deq(xhci, xhci->cmd_ring); 1500 } 1501 1502 static void handle_vendor_event(struct xhci_hcd *xhci, 1503 union xhci_trb *event) 1504 { 1505 u32 trb_type; 1506 1507 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); 1508 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); 1509 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) 1510 handle_cmd_completion(xhci, &event->event_cmd); 1511 } 1512 1513 /* @port_id: the one-based port ID from the hardware (indexed from array of all 1514 * port registers -- USB 3.0 and USB 2.0). 1515 * 1516 * Returns a zero-based port number, which is suitable for indexing into each of 1517 * the split roothubs' port arrays and bus state arrays. 1518 * Add one to it in order to call xhci_find_slot_id_by_port. 1519 */ 1520 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, 1521 struct xhci_hcd *xhci, u32 port_id) 1522 { 1523 unsigned int i; 1524 unsigned int num_similar_speed_ports = 0; 1525 1526 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], 1527 * and usb2_ports are 0-based indexes. Count the number of similar 1528 * speed ports, up to 1 port before this port. 1529 */ 1530 for (i = 0; i < (port_id - 1); i++) { 1531 u8 port_speed = xhci->port_array[i]; 1532 1533 /* 1534 * Skip ports that don't have known speeds, or have duplicate 1535 * Extended Capabilities port speed entries. 1536 */ 1537 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) 1538 continue; 1539 1540 /* 1541 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and 1542 * 1.1 ports are under the USB 2.0 hub. If the port speed 1543 * matches the device speed, it's a similar speed port. 1544 */ 1545 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) 1546 num_similar_speed_ports++; 1547 } 1548 return num_similar_speed_ports; 1549 } 1550 1551 static void handle_device_notification(struct xhci_hcd *xhci, 1552 union xhci_trb *event) 1553 { 1554 u32 slot_id; 1555 struct usb_device *udev; 1556 1557 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); 1558 if (!xhci->devs[slot_id]) { 1559 xhci_warn(xhci, "Device Notification event for " 1560 "unused slot %u\n", slot_id); 1561 return; 1562 } 1563 1564 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", 1565 slot_id); 1566 udev = xhci->devs[slot_id]->udev; 1567 if (udev && udev->parent) 1568 usb_wakeup_notification(udev->parent, udev->portnum); 1569 } 1570 1571 static void handle_port_status(struct xhci_hcd *xhci, 1572 union xhci_trb *event) 1573 { 1574 struct usb_hcd *hcd; 1575 u32 port_id; 1576 u32 portsc, cmd_reg; 1577 int max_ports; 1578 int slot_id; 1579 unsigned int faked_port_index; 1580 u8 major_revision; 1581 struct xhci_bus_state *bus_state; 1582 __le32 __iomem **port_array; 1583 bool bogus_port_status = false; 1584 1585 /* Port status change events always have a successful completion code */ 1586 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) 1587 xhci_warn(xhci, 1588 "WARN: xHC returned failed port status event\n"); 1589 1590 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); 1591 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); 1592 1593 max_ports = HCS_MAX_PORTS(xhci->hcs_params1); 1594 if ((port_id <= 0) || (port_id > max_ports)) { 1595 xhci_warn(xhci, "Invalid port id %d\n", port_id); 1596 inc_deq(xhci, xhci->event_ring); 1597 return; 1598 } 1599 1600 /* Figure out which usb_hcd this port is attached to: 1601 * is it a USB 3.0 port or a USB 2.0/1.1 port? 1602 */ 1603 major_revision = xhci->port_array[port_id - 1]; 1604 1605 /* Find the right roothub. */ 1606 hcd = xhci_to_hcd(xhci); 1607 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) 1608 hcd = xhci->shared_hcd; 1609 1610 if (major_revision == 0) { 1611 xhci_warn(xhci, "Event for port %u not in " 1612 "Extended Capabilities, ignoring.\n", 1613 port_id); 1614 bogus_port_status = true; 1615 goto cleanup; 1616 } 1617 if (major_revision == DUPLICATE_ENTRY) { 1618 xhci_warn(xhci, "Event for port %u duplicated in" 1619 "Extended Capabilities, ignoring.\n", 1620 port_id); 1621 bogus_port_status = true; 1622 goto cleanup; 1623 } 1624 1625 /* 1626 * Hardware port IDs reported by a Port Status Change Event include USB 1627 * 3.0 and USB 2.0 ports. We want to check if the port has reported a 1628 * resume event, but we first need to translate the hardware port ID 1629 * into the index into the ports on the correct split roothub, and the 1630 * correct bus_state structure. 1631 */ 1632 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1633 if (hcd->speed >= HCD_USB3) 1634 port_array = xhci->usb3_ports; 1635 else 1636 port_array = xhci->usb2_ports; 1637 /* Find the faked port hub number */ 1638 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, 1639 port_id); 1640 portsc = readl(port_array[faked_port_index]); 1641 1642 trace_xhci_handle_port_status(faked_port_index, portsc); 1643 1644 if (hcd->state == HC_STATE_SUSPENDED) { 1645 xhci_dbg(xhci, "resume root hub\n"); 1646 usb_hcd_resume_root_hub(hcd); 1647 } 1648 1649 if (hcd->speed >= HCD_USB3 && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) 1650 bus_state->port_remote_wakeup &= ~(1 << faked_port_index); 1651 1652 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) { 1653 xhci_dbg(xhci, "port resume event for port %d\n", port_id); 1654 1655 cmd_reg = readl(&xhci->op_regs->command); 1656 if (!(cmd_reg & CMD_RUN)) { 1657 xhci_warn(xhci, "xHC is not running.\n"); 1658 goto cleanup; 1659 } 1660 1661 if (DEV_SUPERSPEED_ANY(portsc)) { 1662 xhci_dbg(xhci, "remote wake SS port %d\n", port_id); 1663 /* Set a flag to say the port signaled remote wakeup, 1664 * so we can tell the difference between the end of 1665 * device and host initiated resume. 1666 */ 1667 bus_state->port_remote_wakeup |= 1 << faked_port_index; 1668 xhci_test_and_clear_bit(xhci, port_array, 1669 faked_port_index, PORT_PLC); 1670 xhci_set_link_state(xhci, port_array, faked_port_index, 1671 XDEV_U0); 1672 /* Need to wait until the next link state change 1673 * indicates the device is actually in U0. 1674 */ 1675 bogus_port_status = true; 1676 goto cleanup; 1677 } else if (!test_bit(faked_port_index, 1678 &bus_state->resuming_ports)) { 1679 xhci_dbg(xhci, "resume HS port %d\n", port_id); 1680 bus_state->resume_done[faked_port_index] = jiffies + 1681 msecs_to_jiffies(USB_RESUME_TIMEOUT); 1682 set_bit(faked_port_index, &bus_state->resuming_ports); 1683 mod_timer(&hcd->rh_timer, 1684 bus_state->resume_done[faked_port_index]); 1685 /* Do the rest in GetPortStatus */ 1686 } 1687 } 1688 1689 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_U0 && 1690 DEV_SUPERSPEED_ANY(portsc)) { 1691 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); 1692 /* We've just brought the device into U0 through either the 1693 * Resume state after a device remote wakeup, or through the 1694 * U3Exit state after a host-initiated resume. If it's a device 1695 * initiated remote wake, don't pass up the link state change, 1696 * so the roothub behavior is consistent with external 1697 * USB 3.0 hub behavior. 1698 */ 1699 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1700 faked_port_index + 1); 1701 if (slot_id && xhci->devs[slot_id]) 1702 xhci_ring_device(xhci, slot_id); 1703 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { 1704 bus_state->port_remote_wakeup &= 1705 ~(1 << faked_port_index); 1706 xhci_test_and_clear_bit(xhci, port_array, 1707 faked_port_index, PORT_PLC); 1708 usb_wakeup_notification(hcd->self.root_hub, 1709 faked_port_index + 1); 1710 bogus_port_status = true; 1711 goto cleanup; 1712 } 1713 } 1714 1715 /* 1716 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or 1717 * RExit to a disconnect state). If so, let the the driver know it's 1718 * out of the RExit state. 1719 */ 1720 if (!DEV_SUPERSPEED_ANY(portsc) && 1721 test_and_clear_bit(faked_port_index, 1722 &bus_state->rexit_ports)) { 1723 complete(&bus_state->rexit_done[faked_port_index]); 1724 bogus_port_status = true; 1725 goto cleanup; 1726 } 1727 1728 if (hcd->speed < HCD_USB3) 1729 xhci_test_and_clear_bit(xhci, port_array, faked_port_index, 1730 PORT_PLC); 1731 1732 cleanup: 1733 /* Update event ring dequeue pointer before dropping the lock */ 1734 inc_deq(xhci, xhci->event_ring); 1735 1736 /* Don't make the USB core poll the roothub if we got a bad port status 1737 * change event. Besides, at that point we can't tell which roothub 1738 * (USB 2.0 or USB 3.0) to kick. 1739 */ 1740 if (bogus_port_status) 1741 return; 1742 1743 /* 1744 * xHCI port-status-change events occur when the "or" of all the 1745 * status-change bits in the portsc register changes from 0 to 1. 1746 * New status changes won't cause an event if any other change 1747 * bits are still set. When an event occurs, switch over to 1748 * polling to avoid losing status changes. 1749 */ 1750 xhci_dbg(xhci, "%s: starting port polling.\n", __func__); 1751 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1752 spin_unlock(&xhci->lock); 1753 /* Pass this up to the core */ 1754 usb_hcd_poll_rh_status(hcd); 1755 spin_lock(&xhci->lock); 1756 } 1757 1758 /* 1759 * This TD is defined by the TRBs starting at start_trb in start_seg and ending 1760 * at end_trb, which may be in another segment. If the suspect DMA address is a 1761 * TRB in this TD, this function returns that TRB's segment. Otherwise it 1762 * returns 0. 1763 */ 1764 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 1765 struct xhci_segment *start_seg, 1766 union xhci_trb *start_trb, 1767 union xhci_trb *end_trb, 1768 dma_addr_t suspect_dma, 1769 bool debug) 1770 { 1771 dma_addr_t start_dma; 1772 dma_addr_t end_seg_dma; 1773 dma_addr_t end_trb_dma; 1774 struct xhci_segment *cur_seg; 1775 1776 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); 1777 cur_seg = start_seg; 1778 1779 do { 1780 if (start_dma == 0) 1781 return NULL; 1782 /* We may get an event for a Link TRB in the middle of a TD */ 1783 end_seg_dma = xhci_trb_virt_to_dma(cur_seg, 1784 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); 1785 /* If the end TRB isn't in this segment, this is set to 0 */ 1786 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); 1787 1788 if (debug) 1789 xhci_warn(xhci, 1790 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", 1791 (unsigned long long)suspect_dma, 1792 (unsigned long long)start_dma, 1793 (unsigned long long)end_trb_dma, 1794 (unsigned long long)cur_seg->dma, 1795 (unsigned long long)end_seg_dma); 1796 1797 if (end_trb_dma > 0) { 1798 /* The end TRB is in this segment, so suspect should be here */ 1799 if (start_dma <= end_trb_dma) { 1800 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) 1801 return cur_seg; 1802 } else { 1803 /* Case for one segment with 1804 * a TD wrapped around to the top 1805 */ 1806 if ((suspect_dma >= start_dma && 1807 suspect_dma <= end_seg_dma) || 1808 (suspect_dma >= cur_seg->dma && 1809 suspect_dma <= end_trb_dma)) 1810 return cur_seg; 1811 } 1812 return NULL; 1813 } else { 1814 /* Might still be somewhere in this segment */ 1815 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) 1816 return cur_seg; 1817 } 1818 cur_seg = cur_seg->next; 1819 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); 1820 } while (cur_seg != start_seg); 1821 1822 return NULL; 1823 } 1824 1825 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, 1826 unsigned int slot_id, unsigned int ep_index, 1827 unsigned int stream_id, 1828 struct xhci_td *td, union xhci_trb *ep_trb, 1829 enum xhci_ep_reset_type reset_type) 1830 { 1831 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 1832 struct xhci_command *command; 1833 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); 1834 if (!command) 1835 return; 1836 1837 ep->ep_state |= EP_HALTED; 1838 1839 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); 1840 1841 if (reset_type == EP_HARD_RESET) 1842 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td); 1843 1844 xhci_ring_cmd_db(xhci); 1845 } 1846 1847 /* Check if an error has halted the endpoint ring. The class driver will 1848 * cleanup the halt for a non-default control endpoint if we indicate a stall. 1849 * However, a babble and other errors also halt the endpoint ring, and the class 1850 * driver won't clear the halt in that case, so we need to issue a Set Transfer 1851 * Ring Dequeue Pointer command manually. 1852 */ 1853 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, 1854 struct xhci_ep_ctx *ep_ctx, 1855 unsigned int trb_comp_code) 1856 { 1857 /* TRB completion codes that may require a manual halt cleanup */ 1858 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || 1859 trb_comp_code == COMP_BABBLE_DETECTED_ERROR || 1860 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) 1861 /* The 0.95 spec says a babbling control endpoint 1862 * is not halted. The 0.96 spec says it is. Some HW 1863 * claims to be 0.95 compliant, but it halts the control 1864 * endpoint anyway. Check if a babble halted the 1865 * endpoint. 1866 */ 1867 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) 1868 return 1; 1869 1870 return 0; 1871 } 1872 1873 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) 1874 { 1875 if (trb_comp_code >= 224 && trb_comp_code <= 255) { 1876 /* Vendor defined "informational" completion code, 1877 * treat as not-an-error. 1878 */ 1879 xhci_dbg(xhci, "Vendor defined info completion code %u\n", 1880 trb_comp_code); 1881 xhci_dbg(xhci, "Treating code as success.\n"); 1882 return 1; 1883 } 1884 return 0; 1885 } 1886 1887 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, 1888 struct xhci_ring *ep_ring, int *status) 1889 { 1890 struct urb_priv *urb_priv; 1891 struct urb *urb = NULL; 1892 1893 /* Clean up the endpoint's TD list */ 1894 urb = td->urb; 1895 urb_priv = urb->hcpriv; 1896 1897 /* if a bounce buffer was used to align this td then unmap it */ 1898 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); 1899 1900 /* Do one last check of the actual transfer length. 1901 * If the host controller said we transferred more data than the buffer 1902 * length, urb->actual_length will be a very big number (since it's 1903 * unsigned). Play it safe and say we didn't transfer anything. 1904 */ 1905 if (urb->actual_length > urb->transfer_buffer_length) { 1906 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", 1907 urb->transfer_buffer_length, urb->actual_length); 1908 urb->actual_length = 0; 1909 *status = 0; 1910 } 1911 list_del_init(&td->td_list); 1912 /* Was this TD slated to be cancelled but completed anyway? */ 1913 if (!list_empty(&td->cancelled_td_list)) 1914 list_del_init(&td->cancelled_td_list); 1915 1916 inc_td_cnt(urb); 1917 /* Giveback the urb when all the tds are completed */ 1918 if (last_td_in_urb(td)) { 1919 if ((urb->actual_length != urb->transfer_buffer_length && 1920 (urb->transfer_flags & URB_SHORT_NOT_OK)) || 1921 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) 1922 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", 1923 urb, urb->actual_length, 1924 urb->transfer_buffer_length, *status); 1925 1926 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ 1927 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 1928 *status = 0; 1929 xhci_giveback_urb_in_irq(xhci, td, *status); 1930 } 1931 1932 return 0; 1933 } 1934 1935 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, 1936 union xhci_trb *ep_trb, struct xhci_transfer_event *event, 1937 struct xhci_virt_ep *ep, int *status) 1938 { 1939 struct xhci_virt_device *xdev; 1940 struct xhci_ep_ctx *ep_ctx; 1941 struct xhci_ring *ep_ring; 1942 unsigned int slot_id; 1943 u32 trb_comp_code; 1944 int ep_index; 1945 1946 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1947 xdev = xhci->devs[slot_id]; 1948 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1949 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 1950 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1951 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 1952 1953 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID || 1954 trb_comp_code == COMP_STOPPED || 1955 trb_comp_code == COMP_STOPPED_SHORT_PACKET) { 1956 /* The Endpoint Stop Command completion will take care of any 1957 * stopped TDs. A stopped TD may be restarted, so don't update 1958 * the ring dequeue pointer or take this TD off any lists yet. 1959 */ 1960 return 0; 1961 } 1962 if (trb_comp_code == COMP_STALL_ERROR || 1963 xhci_requires_manual_halt_cleanup(xhci, ep_ctx, 1964 trb_comp_code)) { 1965 /* Issue a reset endpoint command to clear the host side 1966 * halt, followed by a set dequeue command to move the 1967 * dequeue pointer past the TD. 1968 * The class driver clears the device side halt later. 1969 */ 1970 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 1971 ep_ring->stream_id, td, ep_trb, 1972 EP_HARD_RESET); 1973 } else { 1974 /* Update ring dequeue pointer */ 1975 while (ep_ring->dequeue != td->last_trb) 1976 inc_deq(xhci, ep_ring); 1977 inc_deq(xhci, ep_ring); 1978 } 1979 1980 return xhci_td_cleanup(xhci, td, ep_ring, status); 1981 } 1982 1983 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ 1984 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, 1985 union xhci_trb *stop_trb) 1986 { 1987 u32 sum; 1988 union xhci_trb *trb = ring->dequeue; 1989 struct xhci_segment *seg = ring->deq_seg; 1990 1991 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { 1992 if (!trb_is_noop(trb) && !trb_is_link(trb)) 1993 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); 1994 } 1995 return sum; 1996 } 1997 1998 /* 1999 * Process control tds, update urb status and actual_length. 2000 */ 2001 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, 2002 union xhci_trb *ep_trb, struct xhci_transfer_event *event, 2003 struct xhci_virt_ep *ep, int *status) 2004 { 2005 struct xhci_virt_device *xdev; 2006 struct xhci_ring *ep_ring; 2007 unsigned int slot_id; 2008 int ep_index; 2009 struct xhci_ep_ctx *ep_ctx; 2010 u32 trb_comp_code; 2011 u32 remaining, requested; 2012 u32 trb_type; 2013 2014 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); 2015 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2016 xdev = xhci->devs[slot_id]; 2017 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2018 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2019 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2020 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2021 requested = td->urb->transfer_buffer_length; 2022 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2023 2024 switch (trb_comp_code) { 2025 case COMP_SUCCESS: 2026 if (trb_type != TRB_STATUS) { 2027 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", 2028 (trb_type == TRB_DATA) ? "data" : "setup"); 2029 *status = -ESHUTDOWN; 2030 break; 2031 } 2032 *status = 0; 2033 break; 2034 case COMP_SHORT_PACKET: 2035 *status = 0; 2036 break; 2037 case COMP_STOPPED_SHORT_PACKET: 2038 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2039 td->urb->actual_length = remaining; 2040 else 2041 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); 2042 goto finish_td; 2043 case COMP_STOPPED: 2044 switch (trb_type) { 2045 case TRB_SETUP: 2046 td->urb->actual_length = 0; 2047 goto finish_td; 2048 case TRB_DATA: 2049 case TRB_NORMAL: 2050 td->urb->actual_length = requested - remaining; 2051 goto finish_td; 2052 case TRB_STATUS: 2053 td->urb->actual_length = requested; 2054 goto finish_td; 2055 default: 2056 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", 2057 trb_type); 2058 goto finish_td; 2059 } 2060 case COMP_STOPPED_LENGTH_INVALID: 2061 goto finish_td; 2062 default: 2063 if (!xhci_requires_manual_halt_cleanup(xhci, 2064 ep_ctx, trb_comp_code)) 2065 break; 2066 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", 2067 trb_comp_code, ep_index); 2068 /* else fall through */ 2069 case COMP_STALL_ERROR: 2070 /* Did we transfer part of the data (middle) phase? */ 2071 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2072 td->urb->actual_length = requested - remaining; 2073 else if (!td->urb_length_set) 2074 td->urb->actual_length = 0; 2075 goto finish_td; 2076 } 2077 2078 /* stopped at setup stage, no data transferred */ 2079 if (trb_type == TRB_SETUP) 2080 goto finish_td; 2081 2082 /* 2083 * if on data stage then update the actual_length of the URB and flag it 2084 * as set, so it won't be overwritten in the event for the last TRB. 2085 */ 2086 if (trb_type == TRB_DATA || 2087 trb_type == TRB_NORMAL) { 2088 td->urb_length_set = true; 2089 td->urb->actual_length = requested - remaining; 2090 xhci_dbg(xhci, "Waiting for status stage event\n"); 2091 return 0; 2092 } 2093 2094 /* at status stage */ 2095 if (!td->urb_length_set) 2096 td->urb->actual_length = requested; 2097 2098 finish_td: 2099 return finish_td(xhci, td, ep_trb, event, ep, status); 2100 } 2101 2102 /* 2103 * Process isochronous tds, update urb packet status and actual_length. 2104 */ 2105 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2106 union xhci_trb *ep_trb, struct xhci_transfer_event *event, 2107 struct xhci_virt_ep *ep, int *status) 2108 { 2109 struct xhci_ring *ep_ring; 2110 struct urb_priv *urb_priv; 2111 int idx; 2112 struct usb_iso_packet_descriptor *frame; 2113 u32 trb_comp_code; 2114 bool sum_trbs_for_length = false; 2115 u32 remaining, requested, ep_trb_len; 2116 int short_framestatus; 2117 2118 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2119 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2120 urb_priv = td->urb->hcpriv; 2121 idx = urb_priv->num_tds_done; 2122 frame = &td->urb->iso_frame_desc[idx]; 2123 requested = frame->length; 2124 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2125 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2126 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? 2127 -EREMOTEIO : 0; 2128 2129 /* handle completion code */ 2130 switch (trb_comp_code) { 2131 case COMP_SUCCESS: 2132 if (remaining) { 2133 frame->status = short_framestatus; 2134 if (xhci->quirks & XHCI_TRUST_TX_LENGTH) 2135 sum_trbs_for_length = true; 2136 break; 2137 } 2138 frame->status = 0; 2139 break; 2140 case COMP_SHORT_PACKET: 2141 frame->status = short_framestatus; 2142 sum_trbs_for_length = true; 2143 break; 2144 case COMP_BANDWIDTH_OVERRUN_ERROR: 2145 frame->status = -ECOMM; 2146 break; 2147 case COMP_ISOCH_BUFFER_OVERRUN: 2148 case COMP_BABBLE_DETECTED_ERROR: 2149 frame->status = -EOVERFLOW; 2150 break; 2151 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2152 case COMP_STALL_ERROR: 2153 frame->status = -EPROTO; 2154 break; 2155 case COMP_USB_TRANSACTION_ERROR: 2156 frame->status = -EPROTO; 2157 if (ep_trb != td->last_trb) 2158 return 0; 2159 break; 2160 case COMP_STOPPED: 2161 sum_trbs_for_length = true; 2162 break; 2163 case COMP_STOPPED_SHORT_PACKET: 2164 /* field normally containing residue now contains tranferred */ 2165 frame->status = short_framestatus; 2166 requested = remaining; 2167 break; 2168 case COMP_STOPPED_LENGTH_INVALID: 2169 requested = 0; 2170 remaining = 0; 2171 break; 2172 default: 2173 sum_trbs_for_length = true; 2174 frame->status = -1; 2175 break; 2176 } 2177 2178 if (sum_trbs_for_length) 2179 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) + 2180 ep_trb_len - remaining; 2181 else 2182 frame->actual_length = requested; 2183 2184 td->urb->actual_length += frame->actual_length; 2185 2186 return finish_td(xhci, td, ep_trb, event, ep, status); 2187 } 2188 2189 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2190 struct xhci_transfer_event *event, 2191 struct xhci_virt_ep *ep, int *status) 2192 { 2193 struct xhci_ring *ep_ring; 2194 struct urb_priv *urb_priv; 2195 struct usb_iso_packet_descriptor *frame; 2196 int idx; 2197 2198 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2199 urb_priv = td->urb->hcpriv; 2200 idx = urb_priv->num_tds_done; 2201 frame = &td->urb->iso_frame_desc[idx]; 2202 2203 /* The transfer is partly done. */ 2204 frame->status = -EXDEV; 2205 2206 /* calc actual length */ 2207 frame->actual_length = 0; 2208 2209 /* Update ring dequeue pointer */ 2210 while (ep_ring->dequeue != td->last_trb) 2211 inc_deq(xhci, ep_ring); 2212 inc_deq(xhci, ep_ring); 2213 2214 return xhci_td_cleanup(xhci, td, ep_ring, status); 2215 } 2216 2217 /* 2218 * Process bulk and interrupt tds, update urb status and actual_length. 2219 */ 2220 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, 2221 union xhci_trb *ep_trb, struct xhci_transfer_event *event, 2222 struct xhci_virt_ep *ep, int *status) 2223 { 2224 struct xhci_ring *ep_ring; 2225 u32 trb_comp_code; 2226 u32 remaining, requested, ep_trb_len; 2227 2228 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2229 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2230 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2231 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2232 requested = td->urb->transfer_buffer_length; 2233 2234 switch (trb_comp_code) { 2235 case COMP_SUCCESS: 2236 /* handle success with untransferred data as short packet */ 2237 if (ep_trb != td->last_trb || remaining) { 2238 xhci_warn(xhci, "WARN Successful completion on short TX\n"); 2239 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", 2240 td->urb->ep->desc.bEndpointAddress, 2241 requested, remaining); 2242 } 2243 *status = 0; 2244 break; 2245 case COMP_SHORT_PACKET: 2246 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", 2247 td->urb->ep->desc.bEndpointAddress, 2248 requested, remaining); 2249 *status = 0; 2250 break; 2251 case COMP_STOPPED_SHORT_PACKET: 2252 td->urb->actual_length = remaining; 2253 goto finish_td; 2254 case COMP_STOPPED_LENGTH_INVALID: 2255 /* stopped on ep trb with invalid length, exclude it */ 2256 ep_trb_len = 0; 2257 remaining = 0; 2258 break; 2259 default: 2260 /* do nothing */ 2261 break; 2262 } 2263 2264 if (ep_trb == td->last_trb) 2265 td->urb->actual_length = requested - remaining; 2266 else 2267 td->urb->actual_length = 2268 sum_trb_lengths(xhci, ep_ring, ep_trb) + 2269 ep_trb_len - remaining; 2270 finish_td: 2271 if (remaining > requested) { 2272 xhci_warn(xhci, "bad transfer trb length %d in event trb\n", 2273 remaining); 2274 td->urb->actual_length = 0; 2275 } 2276 return finish_td(xhci, td, ep_trb, event, ep, status); 2277 } 2278 2279 /* 2280 * If this function returns an error condition, it means it got a Transfer 2281 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. 2282 * At this point, the host controller is probably hosed and should be reset. 2283 */ 2284 static int handle_tx_event(struct xhci_hcd *xhci, 2285 struct xhci_transfer_event *event) 2286 { 2287 struct xhci_virt_device *xdev; 2288 struct xhci_virt_ep *ep; 2289 struct xhci_ring *ep_ring; 2290 unsigned int slot_id; 2291 int ep_index; 2292 struct xhci_td *td = NULL; 2293 dma_addr_t ep_trb_dma; 2294 struct xhci_segment *ep_seg; 2295 union xhci_trb *ep_trb; 2296 int status = -EINPROGRESS; 2297 struct xhci_ep_ctx *ep_ctx; 2298 struct list_head *tmp; 2299 u32 trb_comp_code; 2300 int td_num = 0; 2301 bool handling_skipped_tds = false; 2302 2303 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2304 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2305 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2306 ep_trb_dma = le64_to_cpu(event->buffer); 2307 2308 xdev = xhci->devs[slot_id]; 2309 if (!xdev) { 2310 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n", 2311 slot_id); 2312 goto err_out; 2313 } 2314 2315 ep = &xdev->eps[ep_index]; 2316 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); 2317 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2318 2319 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { 2320 xhci_err(xhci, 2321 "ERROR Transfer event for disabled endpoint slot %u ep %u\n", 2322 slot_id, ep_index); 2323 goto err_out; 2324 } 2325 2326 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */ 2327 if (!ep_ring) { 2328 switch (trb_comp_code) { 2329 case COMP_STALL_ERROR: 2330 case COMP_USB_TRANSACTION_ERROR: 2331 case COMP_INVALID_STREAM_TYPE_ERROR: 2332 case COMP_INVALID_STREAM_ID_ERROR: 2333 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0, 2334 NULL, NULL, EP_SOFT_RESET); 2335 goto cleanup; 2336 case COMP_RING_UNDERRUN: 2337 case COMP_RING_OVERRUN: 2338 goto cleanup; 2339 default: 2340 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", 2341 slot_id, ep_index); 2342 goto err_out; 2343 } 2344 } 2345 2346 /* Count current td numbers if ep->skip is set */ 2347 if (ep->skip) { 2348 list_for_each(tmp, &ep_ring->td_list) 2349 td_num++; 2350 } 2351 2352 /* Look for common error cases */ 2353 switch (trb_comp_code) { 2354 /* Skip codes that require special handling depending on 2355 * transfer type 2356 */ 2357 case COMP_SUCCESS: 2358 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) 2359 break; 2360 if (xhci->quirks & XHCI_TRUST_TX_LENGTH) 2361 trb_comp_code = COMP_SHORT_PACKET; 2362 else 2363 xhci_warn_ratelimited(xhci, 2364 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", 2365 slot_id, ep_index); 2366 case COMP_SHORT_PACKET: 2367 break; 2368 /* Completion codes for endpoint stopped state */ 2369 case COMP_STOPPED: 2370 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", 2371 slot_id, ep_index); 2372 break; 2373 case COMP_STOPPED_LENGTH_INVALID: 2374 xhci_dbg(xhci, 2375 "Stopped on No-op or Link TRB for slot %u ep %u\n", 2376 slot_id, ep_index); 2377 break; 2378 case COMP_STOPPED_SHORT_PACKET: 2379 xhci_dbg(xhci, 2380 "Stopped with short packet transfer detected for slot %u ep %u\n", 2381 slot_id, ep_index); 2382 break; 2383 /* Completion codes for endpoint halted state */ 2384 case COMP_STALL_ERROR: 2385 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, 2386 ep_index); 2387 ep->ep_state |= EP_HALTED; 2388 status = -EPIPE; 2389 break; 2390 case COMP_SPLIT_TRANSACTION_ERROR: 2391 case COMP_USB_TRANSACTION_ERROR: 2392 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", 2393 slot_id, ep_index); 2394 status = -EPROTO; 2395 break; 2396 case COMP_BABBLE_DETECTED_ERROR: 2397 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", 2398 slot_id, ep_index); 2399 status = -EOVERFLOW; 2400 break; 2401 /* Completion codes for endpoint error state */ 2402 case COMP_TRB_ERROR: 2403 xhci_warn(xhci, 2404 "WARN: TRB error for slot %u ep %u on endpoint\n", 2405 slot_id, ep_index); 2406 status = -EILSEQ; 2407 break; 2408 /* completion codes not indicating endpoint state change */ 2409 case COMP_DATA_BUFFER_ERROR: 2410 xhci_warn(xhci, 2411 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", 2412 slot_id, ep_index); 2413 status = -ENOSR; 2414 break; 2415 case COMP_BANDWIDTH_OVERRUN_ERROR: 2416 xhci_warn(xhci, 2417 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", 2418 slot_id, ep_index); 2419 break; 2420 case COMP_ISOCH_BUFFER_OVERRUN: 2421 xhci_warn(xhci, 2422 "WARN: buffer overrun event for slot %u ep %u on endpoint", 2423 slot_id, ep_index); 2424 break; 2425 case COMP_RING_UNDERRUN: 2426 /* 2427 * When the Isoch ring is empty, the xHC will generate 2428 * a Ring Overrun Event for IN Isoch endpoint or Ring 2429 * Underrun Event for OUT Isoch endpoint. 2430 */ 2431 xhci_dbg(xhci, "underrun event on endpoint\n"); 2432 if (!list_empty(&ep_ring->td_list)) 2433 xhci_dbg(xhci, "Underrun Event for slot %d ep %d " 2434 "still with TDs queued?\n", 2435 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2436 ep_index); 2437 goto cleanup; 2438 case COMP_RING_OVERRUN: 2439 xhci_dbg(xhci, "overrun event on endpoint\n"); 2440 if (!list_empty(&ep_ring->td_list)) 2441 xhci_dbg(xhci, "Overrun Event for slot %d ep %d " 2442 "still with TDs queued?\n", 2443 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2444 ep_index); 2445 goto cleanup; 2446 case COMP_MISSED_SERVICE_ERROR: 2447 /* 2448 * When encounter missed service error, one or more isoc tds 2449 * may be missed by xHC. 2450 * Set skip flag of the ep_ring; Complete the missed tds as 2451 * short transfer when process the ep_ring next time. 2452 */ 2453 ep->skip = true; 2454 xhci_dbg(xhci, 2455 "Miss service interval error for slot %u ep %u, set skip flag\n", 2456 slot_id, ep_index); 2457 goto cleanup; 2458 case COMP_NO_PING_RESPONSE_ERROR: 2459 ep->skip = true; 2460 xhci_dbg(xhci, 2461 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", 2462 slot_id, ep_index); 2463 goto cleanup; 2464 2465 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2466 /* needs disable slot command to recover */ 2467 xhci_warn(xhci, 2468 "WARN: detect an incompatible device for slot %u ep %u", 2469 slot_id, ep_index); 2470 status = -EPROTO; 2471 break; 2472 default: 2473 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { 2474 status = 0; 2475 break; 2476 } 2477 xhci_warn(xhci, 2478 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", 2479 trb_comp_code, slot_id, ep_index); 2480 goto cleanup; 2481 } 2482 2483 do { 2484 /* This TRB should be in the TD at the head of this ring's 2485 * TD list. 2486 */ 2487 if (list_empty(&ep_ring->td_list)) { 2488 /* 2489 * A stopped endpoint may generate an extra completion 2490 * event if the device was suspended. Don't print 2491 * warnings. 2492 */ 2493 if (!(trb_comp_code == COMP_STOPPED || 2494 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { 2495 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", 2496 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2497 ep_index); 2498 } 2499 if (ep->skip) { 2500 ep->skip = false; 2501 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", 2502 slot_id, ep_index); 2503 } 2504 goto cleanup; 2505 } 2506 2507 /* We've skipped all the TDs on the ep ring when ep->skip set */ 2508 if (ep->skip && td_num == 0) { 2509 ep->skip = false; 2510 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", 2511 slot_id, ep_index); 2512 goto cleanup; 2513 } 2514 2515 td = list_first_entry(&ep_ring->td_list, struct xhci_td, 2516 td_list); 2517 if (ep->skip) 2518 td_num--; 2519 2520 /* Is this a TRB in the currently executing TD? */ 2521 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, 2522 td->last_trb, ep_trb_dma, false); 2523 2524 /* 2525 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE 2526 * is not in the current TD pointed by ep_ring->dequeue because 2527 * that the hardware dequeue pointer still at the previous TRB 2528 * of the current TD. The previous TRB maybe a Link TD or the 2529 * last TRB of the previous TD. The command completion handle 2530 * will take care the rest. 2531 */ 2532 if (!ep_seg && (trb_comp_code == COMP_STOPPED || 2533 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { 2534 goto cleanup; 2535 } 2536 2537 if (!ep_seg) { 2538 if (!ep->skip || 2539 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { 2540 /* Some host controllers give a spurious 2541 * successful event after a short transfer. 2542 * Ignore it. 2543 */ 2544 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 2545 ep_ring->last_td_was_short) { 2546 ep_ring->last_td_was_short = false; 2547 goto cleanup; 2548 } 2549 /* HC is busted, give up! */ 2550 xhci_err(xhci, 2551 "ERROR Transfer event TRB DMA ptr not " 2552 "part of current TD ep_index %d " 2553 "comp_code %u\n", ep_index, 2554 trb_comp_code); 2555 trb_in_td(xhci, ep_ring->deq_seg, 2556 ep_ring->dequeue, td->last_trb, 2557 ep_trb_dma, true); 2558 return -ESHUTDOWN; 2559 } 2560 2561 skip_isoc_td(xhci, td, event, ep, &status); 2562 goto cleanup; 2563 } 2564 if (trb_comp_code == COMP_SHORT_PACKET) 2565 ep_ring->last_td_was_short = true; 2566 else 2567 ep_ring->last_td_was_short = false; 2568 2569 if (ep->skip) { 2570 xhci_dbg(xhci, 2571 "Found td. Clear skip flag for slot %u ep %u.\n", 2572 slot_id, ep_index); 2573 ep->skip = false; 2574 } 2575 2576 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / 2577 sizeof(*ep_trb)]; 2578 2579 trace_xhci_handle_transfer(ep_ring, 2580 (struct xhci_generic_trb *) ep_trb); 2581 2582 /* 2583 * No-op TRB could trigger interrupts in a case where 2584 * a URB was killed and a STALL_ERROR happens right 2585 * after the endpoint ring stopped. Reset the halted 2586 * endpoint. Otherwise, the endpoint remains stalled 2587 * indefinitely. 2588 */ 2589 if (trb_is_noop(ep_trb)) { 2590 if (trb_comp_code == COMP_STALL_ERROR || 2591 xhci_requires_manual_halt_cleanup(xhci, ep_ctx, 2592 trb_comp_code)) 2593 xhci_cleanup_halted_endpoint(xhci, slot_id, 2594 ep_index, 2595 ep_ring->stream_id, 2596 td, ep_trb, 2597 EP_HARD_RESET); 2598 goto cleanup; 2599 } 2600 2601 /* update the urb's actual_length and give back to the core */ 2602 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) 2603 process_ctrl_td(xhci, td, ep_trb, event, ep, &status); 2604 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) 2605 process_isoc_td(xhci, td, ep_trb, event, ep, &status); 2606 else 2607 process_bulk_intr_td(xhci, td, ep_trb, event, ep, 2608 &status); 2609 cleanup: 2610 handling_skipped_tds = ep->skip && 2611 trb_comp_code != COMP_MISSED_SERVICE_ERROR && 2612 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; 2613 2614 /* 2615 * Do not update event ring dequeue pointer if we're in a loop 2616 * processing missed tds. 2617 */ 2618 if (!handling_skipped_tds) 2619 inc_deq(xhci, xhci->event_ring); 2620 2621 /* 2622 * If ep->skip is set, it means there are missed tds on the 2623 * endpoint ring need to take care of. 2624 * Process them as short transfer until reach the td pointed by 2625 * the event. 2626 */ 2627 } while (handling_skipped_tds); 2628 2629 return 0; 2630 2631 err_out: 2632 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2633 (unsigned long long) xhci_trb_virt_to_dma( 2634 xhci->event_ring->deq_seg, 2635 xhci->event_ring->dequeue), 2636 lower_32_bits(le64_to_cpu(event->buffer)), 2637 upper_32_bits(le64_to_cpu(event->buffer)), 2638 le32_to_cpu(event->transfer_len), 2639 le32_to_cpu(event->flags)); 2640 return -ENODEV; 2641 } 2642 2643 /* 2644 * This function handles all OS-owned events on the event ring. It may drop 2645 * xhci->lock between event processing (e.g. to pass up port status changes). 2646 * Returns >0 for "possibly more events to process" (caller should call again), 2647 * otherwise 0 if done. In future, <0 returns should indicate error code. 2648 */ 2649 static int xhci_handle_event(struct xhci_hcd *xhci) 2650 { 2651 union xhci_trb *event; 2652 int update_ptrs = 1; 2653 int ret; 2654 2655 /* Event ring hasn't been allocated yet. */ 2656 if (!xhci->event_ring || !xhci->event_ring->dequeue) { 2657 xhci_err(xhci, "ERROR event ring not ready\n"); 2658 return -ENOMEM; 2659 } 2660 2661 event = xhci->event_ring->dequeue; 2662 /* Does the HC or OS own the TRB? */ 2663 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != 2664 xhci->event_ring->cycle_state) 2665 return 0; 2666 2667 trace_xhci_handle_event(xhci->event_ring, &event->generic); 2668 2669 /* 2670 * Barrier between reading the TRB_CYCLE (valid) flag above and any 2671 * speculative reads of the event's flags/data below. 2672 */ 2673 rmb(); 2674 /* FIXME: Handle more event types. */ 2675 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) { 2676 case TRB_TYPE(TRB_COMPLETION): 2677 handle_cmd_completion(xhci, &event->event_cmd); 2678 break; 2679 case TRB_TYPE(TRB_PORT_STATUS): 2680 handle_port_status(xhci, event); 2681 update_ptrs = 0; 2682 break; 2683 case TRB_TYPE(TRB_TRANSFER): 2684 ret = handle_tx_event(xhci, &event->trans_event); 2685 if (ret >= 0) 2686 update_ptrs = 0; 2687 break; 2688 case TRB_TYPE(TRB_DEV_NOTE): 2689 handle_device_notification(xhci, event); 2690 break; 2691 default: 2692 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= 2693 TRB_TYPE(48)) 2694 handle_vendor_event(xhci, event); 2695 else 2696 xhci_warn(xhci, "ERROR unknown event type %d\n", 2697 TRB_FIELD_TO_TYPE( 2698 le32_to_cpu(event->event_cmd.flags))); 2699 } 2700 /* Any of the above functions may drop and re-acquire the lock, so check 2701 * to make sure a watchdog timer didn't mark the host as non-responsive. 2702 */ 2703 if (xhci->xhc_state & XHCI_STATE_DYING) { 2704 xhci_dbg(xhci, "xHCI host dying, returning from " 2705 "event handler.\n"); 2706 return 0; 2707 } 2708 2709 if (update_ptrs) 2710 /* Update SW event ring dequeue pointer */ 2711 inc_deq(xhci, xhci->event_ring); 2712 2713 /* Are there more items on the event ring? Caller will call us again to 2714 * check. 2715 */ 2716 return 1; 2717 } 2718 2719 /* 2720 * xHCI spec says we can get an interrupt, and if the HC has an error condition, 2721 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of 2722 * indicators of an event TRB error, but we check the status *first* to be safe. 2723 */ 2724 irqreturn_t xhci_irq(struct usb_hcd *hcd) 2725 { 2726 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2727 union xhci_trb *event_ring_deq; 2728 irqreturn_t ret = IRQ_NONE; 2729 unsigned long flags; 2730 dma_addr_t deq; 2731 u64 temp_64; 2732 u32 status; 2733 2734 spin_lock_irqsave(&xhci->lock, flags); 2735 /* Check if the xHC generated the interrupt, or the irq is shared */ 2736 status = readl(&xhci->op_regs->status); 2737 if (status == ~(u32)0) { 2738 xhci_hc_died(xhci); 2739 ret = IRQ_HANDLED; 2740 goto out; 2741 } 2742 2743 if (!(status & STS_EINT)) 2744 goto out; 2745 2746 if (status & STS_FATAL) { 2747 xhci_warn(xhci, "WARNING: Host System Error\n"); 2748 xhci_halt(xhci); 2749 ret = IRQ_HANDLED; 2750 goto out; 2751 } 2752 2753 /* 2754 * Clear the op reg interrupt status first, 2755 * so we can receive interrupts from other MSI-X interrupters. 2756 * Write 1 to clear the interrupt status. 2757 */ 2758 status |= STS_EINT; 2759 writel(status, &xhci->op_regs->status); 2760 2761 if (!hcd->msi_enabled) { 2762 u32 irq_pending; 2763 irq_pending = readl(&xhci->ir_set->irq_pending); 2764 irq_pending |= IMAN_IP; 2765 writel(irq_pending, &xhci->ir_set->irq_pending); 2766 } 2767 2768 if (xhci->xhc_state & XHCI_STATE_DYING || 2769 xhci->xhc_state & XHCI_STATE_HALTED) { 2770 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " 2771 "Shouldn't IRQs be disabled?\n"); 2772 /* Clear the event handler busy flag (RW1C); 2773 * the event ring should be empty. 2774 */ 2775 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2776 xhci_write_64(xhci, temp_64 | ERST_EHB, 2777 &xhci->ir_set->erst_dequeue); 2778 ret = IRQ_HANDLED; 2779 goto out; 2780 } 2781 2782 event_ring_deq = xhci->event_ring->dequeue; 2783 /* FIXME this should be a delayed service routine 2784 * that clears the EHB. 2785 */ 2786 while (xhci_handle_event(xhci) > 0) {} 2787 2788 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2789 /* If necessary, update the HW's version of the event ring deq ptr. */ 2790 if (event_ring_deq != xhci->event_ring->dequeue) { 2791 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, 2792 xhci->event_ring->dequeue); 2793 if (deq == 0) 2794 xhci_warn(xhci, "WARN something wrong with SW event " 2795 "ring dequeue ptr.\n"); 2796 /* Update HC event ring dequeue pointer */ 2797 temp_64 &= ERST_PTR_MASK; 2798 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); 2799 } 2800 2801 /* Clear the event handler busy flag (RW1C); event ring is empty. */ 2802 temp_64 |= ERST_EHB; 2803 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); 2804 ret = IRQ_HANDLED; 2805 2806 out: 2807 spin_unlock_irqrestore(&xhci->lock, flags); 2808 2809 return ret; 2810 } 2811 2812 irqreturn_t xhci_msi_irq(int irq, void *hcd) 2813 { 2814 return xhci_irq(hcd); 2815 } 2816 2817 /**** Endpoint Ring Operations ****/ 2818 2819 /* 2820 * Generic function for queueing a TRB on a ring. 2821 * The caller must have checked to make sure there's room on the ring. 2822 * 2823 * @more_trbs_coming: Will you enqueue more TRBs before calling 2824 * prepare_transfer()? 2825 */ 2826 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 2827 bool more_trbs_coming, 2828 u32 field1, u32 field2, u32 field3, u32 field4) 2829 { 2830 struct xhci_generic_trb *trb; 2831 2832 trb = &ring->enqueue->generic; 2833 trb->field[0] = cpu_to_le32(field1); 2834 trb->field[1] = cpu_to_le32(field2); 2835 trb->field[2] = cpu_to_le32(field3); 2836 trb->field[3] = cpu_to_le32(field4); 2837 2838 trace_xhci_queue_trb(ring, trb); 2839 2840 inc_enq(xhci, ring, more_trbs_coming); 2841 } 2842 2843 /* 2844 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. 2845 * FIXME allocate segments if the ring is full. 2846 */ 2847 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 2848 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 2849 { 2850 unsigned int num_trbs_needed; 2851 2852 /* Make sure the endpoint has been added to xHC schedule */ 2853 switch (ep_state) { 2854 case EP_STATE_DISABLED: 2855 /* 2856 * USB core changed config/interfaces without notifying us, 2857 * or hardware is reporting the wrong state. 2858 */ 2859 xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); 2860 return -ENOENT; 2861 case EP_STATE_ERROR: 2862 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); 2863 /* FIXME event handling code for error needs to clear it */ 2864 /* XXX not sure if this should be -ENOENT or not */ 2865 return -EINVAL; 2866 case EP_STATE_HALTED: 2867 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); 2868 case EP_STATE_STOPPED: 2869 case EP_STATE_RUNNING: 2870 break; 2871 default: 2872 xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); 2873 /* 2874 * FIXME issue Configure Endpoint command to try to get the HC 2875 * back into a known state. 2876 */ 2877 return -EINVAL; 2878 } 2879 2880 while (1) { 2881 if (room_on_ring(xhci, ep_ring, num_trbs)) 2882 break; 2883 2884 if (ep_ring == xhci->cmd_ring) { 2885 xhci_err(xhci, "Do not support expand command ring\n"); 2886 return -ENOMEM; 2887 } 2888 2889 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, 2890 "ERROR no room on ep ring, try ring expansion"); 2891 num_trbs_needed = num_trbs - ep_ring->num_trbs_free; 2892 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, 2893 mem_flags)) { 2894 xhci_err(xhci, "Ring expansion failed\n"); 2895 return -ENOMEM; 2896 } 2897 } 2898 2899 while (trb_is_link(ep_ring->enqueue)) { 2900 /* If we're not dealing with 0.95 hardware or isoc rings 2901 * on AMD 0.96 host, clear the chain bit. 2902 */ 2903 if (!xhci_link_trb_quirk(xhci) && 2904 !(ep_ring->type == TYPE_ISOC && 2905 (xhci->quirks & XHCI_AMD_0x96_HOST))) 2906 ep_ring->enqueue->link.control &= 2907 cpu_to_le32(~TRB_CHAIN); 2908 else 2909 ep_ring->enqueue->link.control |= 2910 cpu_to_le32(TRB_CHAIN); 2911 2912 wmb(); 2913 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); 2914 2915 /* Toggle the cycle bit after the last ring segment. */ 2916 if (link_trb_toggles_cycle(ep_ring->enqueue)) 2917 ep_ring->cycle_state ^= 1; 2918 2919 ep_ring->enq_seg = ep_ring->enq_seg->next; 2920 ep_ring->enqueue = ep_ring->enq_seg->trbs; 2921 } 2922 return 0; 2923 } 2924 2925 static int prepare_transfer(struct xhci_hcd *xhci, 2926 struct xhci_virt_device *xdev, 2927 unsigned int ep_index, 2928 unsigned int stream_id, 2929 unsigned int num_trbs, 2930 struct urb *urb, 2931 unsigned int td_index, 2932 gfp_t mem_flags) 2933 { 2934 int ret; 2935 struct urb_priv *urb_priv; 2936 struct xhci_td *td; 2937 struct xhci_ring *ep_ring; 2938 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2939 2940 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); 2941 if (!ep_ring) { 2942 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", 2943 stream_id); 2944 return -EINVAL; 2945 } 2946 2947 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 2948 num_trbs, mem_flags); 2949 if (ret) 2950 return ret; 2951 2952 urb_priv = urb->hcpriv; 2953 td = &urb_priv->td[td_index]; 2954 2955 INIT_LIST_HEAD(&td->td_list); 2956 INIT_LIST_HEAD(&td->cancelled_td_list); 2957 2958 if (td_index == 0) { 2959 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); 2960 if (unlikely(ret)) 2961 return ret; 2962 } 2963 2964 td->urb = urb; 2965 /* Add this TD to the tail of the endpoint ring's TD list */ 2966 list_add_tail(&td->td_list, &ep_ring->td_list); 2967 td->start_seg = ep_ring->enq_seg; 2968 td->first_trb = ep_ring->enqueue; 2969 2970 return 0; 2971 } 2972 2973 static unsigned int count_trbs(u64 addr, u64 len) 2974 { 2975 unsigned int num_trbs; 2976 2977 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), 2978 TRB_MAX_BUFF_SIZE); 2979 if (num_trbs == 0) 2980 num_trbs++; 2981 2982 return num_trbs; 2983 } 2984 2985 static inline unsigned int count_trbs_needed(struct urb *urb) 2986 { 2987 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); 2988 } 2989 2990 static unsigned int count_sg_trbs_needed(struct urb *urb) 2991 { 2992 struct scatterlist *sg; 2993 unsigned int i, len, full_len, num_trbs = 0; 2994 2995 full_len = urb->transfer_buffer_length; 2996 2997 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { 2998 len = sg_dma_len(sg); 2999 num_trbs += count_trbs(sg_dma_address(sg), len); 3000 len = min_t(unsigned int, len, full_len); 3001 full_len -= len; 3002 if (full_len == 0) 3003 break; 3004 } 3005 3006 return num_trbs; 3007 } 3008 3009 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) 3010 { 3011 u64 addr, len; 3012 3013 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); 3014 len = urb->iso_frame_desc[i].length; 3015 3016 return count_trbs(addr, len); 3017 } 3018 3019 static void check_trb_math(struct urb *urb, int running_total) 3020 { 3021 if (unlikely(running_total != urb->transfer_buffer_length)) 3022 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " 3023 "queued %#x (%d), asked for %#x (%d)\n", 3024 __func__, 3025 urb->ep->desc.bEndpointAddress, 3026 running_total, running_total, 3027 urb->transfer_buffer_length, 3028 urb->transfer_buffer_length); 3029 } 3030 3031 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, 3032 unsigned int ep_index, unsigned int stream_id, int start_cycle, 3033 struct xhci_generic_trb *start_trb) 3034 { 3035 /* 3036 * Pass all the TRBs to the hardware at once and make sure this write 3037 * isn't reordered. 3038 */ 3039 wmb(); 3040 if (start_cycle) 3041 start_trb->field[3] |= cpu_to_le32(start_cycle); 3042 else 3043 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 3044 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 3045 } 3046 3047 static void check_interval(struct xhci_hcd *xhci, struct urb *urb, 3048 struct xhci_ep_ctx *ep_ctx) 3049 { 3050 int xhci_interval; 3051 int ep_interval; 3052 3053 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); 3054 ep_interval = urb->interval; 3055 3056 /* Convert to microframes */ 3057 if (urb->dev->speed == USB_SPEED_LOW || 3058 urb->dev->speed == USB_SPEED_FULL) 3059 ep_interval *= 8; 3060 3061 /* FIXME change this to a warning and a suggestion to use the new API 3062 * to set the polling interval (once the API is added). 3063 */ 3064 if (xhci_interval != ep_interval) { 3065 dev_dbg_ratelimited(&urb->dev->dev, 3066 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", 3067 ep_interval, ep_interval == 1 ? "" : "s", 3068 xhci_interval, xhci_interval == 1 ? "" : "s"); 3069 urb->interval = xhci_interval; 3070 /* Convert back to frames for LS/FS devices */ 3071 if (urb->dev->speed == USB_SPEED_LOW || 3072 urb->dev->speed == USB_SPEED_FULL) 3073 urb->interval /= 8; 3074 } 3075 } 3076 3077 /* 3078 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt 3079 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD 3080 * (comprised of sg list entries) can take several service intervals to 3081 * transmit. 3082 */ 3083 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3084 struct urb *urb, int slot_id, unsigned int ep_index) 3085 { 3086 struct xhci_ep_ctx *ep_ctx; 3087 3088 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); 3089 check_interval(xhci, urb, ep_ctx); 3090 3091 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); 3092 } 3093 3094 /* 3095 * For xHCI 1.0 host controllers, TD size is the number of max packet sized 3096 * packets remaining in the TD (*not* including this TRB). 3097 * 3098 * Total TD packet count = total_packet_count = 3099 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) 3100 * 3101 * Packets transferred up to and including this TRB = packets_transferred = 3102 * rounddown(total bytes transferred including this TRB / wMaxPacketSize) 3103 * 3104 * TD size = total_packet_count - packets_transferred 3105 * 3106 * For xHCI 0.96 and older, TD size field should be the remaining bytes 3107 * including this TRB, right shifted by 10 3108 * 3109 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. 3110 * This is taken care of in the TRB_TD_SIZE() macro 3111 * 3112 * The last TRB in a TD must have the TD size set to zero. 3113 */ 3114 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, 3115 int trb_buff_len, unsigned int td_total_len, 3116 struct urb *urb, bool more_trbs_coming) 3117 { 3118 u32 maxp, total_packet_count; 3119 3120 /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ 3121 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) 3122 return ((td_total_len - transferred) >> 10); 3123 3124 /* One TRB with a zero-length data packet. */ 3125 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || 3126 trb_buff_len == td_total_len) 3127 return 0; 3128 3129 /* for MTK xHCI, TD size doesn't include this TRB */ 3130 if (xhci->quirks & XHCI_MTK_HOST) 3131 trb_buff_len = 0; 3132 3133 maxp = usb_endpoint_maxp(&urb->ep->desc); 3134 total_packet_count = DIV_ROUND_UP(td_total_len, maxp); 3135 3136 /* Queueing functions don't count the current TRB into transferred */ 3137 return (total_packet_count - ((transferred + trb_buff_len) / maxp)); 3138 } 3139 3140 3141 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, 3142 u32 *trb_buff_len, struct xhci_segment *seg) 3143 { 3144 struct device *dev = xhci_to_hcd(xhci)->self.controller; 3145 unsigned int unalign; 3146 unsigned int max_pkt; 3147 u32 new_buff_len; 3148 3149 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 3150 unalign = (enqd_len + *trb_buff_len) % max_pkt; 3151 3152 /* we got lucky, last normal TRB data on segment is packet aligned */ 3153 if (unalign == 0) 3154 return 0; 3155 3156 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", 3157 unalign, *trb_buff_len); 3158 3159 /* is the last nornal TRB alignable by splitting it */ 3160 if (*trb_buff_len > unalign) { 3161 *trb_buff_len -= unalign; 3162 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); 3163 return 0; 3164 } 3165 3166 /* 3167 * We want enqd_len + trb_buff_len to sum up to a number aligned to 3168 * number which is divisible by the endpoint's wMaxPacketSize. IOW: 3169 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. 3170 */ 3171 new_buff_len = max_pkt - (enqd_len % max_pkt); 3172 3173 if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) 3174 new_buff_len = (urb->transfer_buffer_length - enqd_len); 3175 3176 /* create a max max_pkt sized bounce buffer pointed to by last trb */ 3177 if (usb_urb_dir_out(urb)) { 3178 sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, 3179 seg->bounce_buf, new_buff_len, enqd_len); 3180 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3181 max_pkt, DMA_TO_DEVICE); 3182 } else { 3183 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3184 max_pkt, DMA_FROM_DEVICE); 3185 } 3186 3187 if (dma_mapping_error(dev, seg->bounce_dma)) { 3188 /* try without aligning. Some host controllers survive */ 3189 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); 3190 return 0; 3191 } 3192 *trb_buff_len = new_buff_len; 3193 seg->bounce_len = new_buff_len; 3194 seg->bounce_offs = enqd_len; 3195 3196 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); 3197 3198 return 1; 3199 } 3200 3201 /* This is very similar to what ehci-q.c qtd_fill() does */ 3202 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3203 struct urb *urb, int slot_id, unsigned int ep_index) 3204 { 3205 struct xhci_ring *ring; 3206 struct urb_priv *urb_priv; 3207 struct xhci_td *td; 3208 struct xhci_generic_trb *start_trb; 3209 struct scatterlist *sg = NULL; 3210 bool more_trbs_coming = true; 3211 bool need_zero_pkt = false; 3212 bool first_trb = true; 3213 unsigned int num_trbs; 3214 unsigned int start_cycle, num_sgs = 0; 3215 unsigned int enqd_len, block_len, trb_buff_len, full_len; 3216 int sent_len, ret; 3217 u32 field, length_field, remainder; 3218 u64 addr, send_addr; 3219 3220 ring = xhci_urb_to_transfer_ring(xhci, urb); 3221 if (!ring) 3222 return -EINVAL; 3223 3224 full_len = urb->transfer_buffer_length; 3225 /* If we have scatter/gather list, we use it. */ 3226 if (urb->num_sgs) { 3227 num_sgs = urb->num_mapped_sgs; 3228 sg = urb->sg; 3229 addr = (u64) sg_dma_address(sg); 3230 block_len = sg_dma_len(sg); 3231 num_trbs = count_sg_trbs_needed(urb); 3232 } else { 3233 num_trbs = count_trbs_needed(urb); 3234 addr = (u64) urb->transfer_dma; 3235 block_len = full_len; 3236 } 3237 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3238 ep_index, urb->stream_id, 3239 num_trbs, urb, 0, mem_flags); 3240 if (unlikely(ret < 0)) 3241 return ret; 3242 3243 urb_priv = urb->hcpriv; 3244 3245 /* Deal with URB_ZERO_PACKET - need one more td/trb */ 3246 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) 3247 need_zero_pkt = true; 3248 3249 td = &urb_priv->td[0]; 3250 3251 /* 3252 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3253 * until we've finished creating all the other TRBs. The ring's cycle 3254 * state may change as we enqueue the other TRBs, so save it too. 3255 */ 3256 start_trb = &ring->enqueue->generic; 3257 start_cycle = ring->cycle_state; 3258 send_addr = addr; 3259 3260 /* Queue the TRBs, even if they are zero-length */ 3261 for (enqd_len = 0; first_trb || enqd_len < full_len; 3262 enqd_len += trb_buff_len) { 3263 field = TRB_TYPE(TRB_NORMAL); 3264 3265 /* TRB buffer should not cross 64KB boundaries */ 3266 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3267 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); 3268 3269 if (enqd_len + trb_buff_len > full_len) 3270 trb_buff_len = full_len - enqd_len; 3271 3272 /* Don't change the cycle bit of the first TRB until later */ 3273 if (first_trb) { 3274 first_trb = false; 3275 if (start_cycle == 0) 3276 field |= TRB_CYCLE; 3277 } else 3278 field |= ring->cycle_state; 3279 3280 /* Chain all the TRBs together; clear the chain bit in the last 3281 * TRB to indicate it's the last TRB in the chain. 3282 */ 3283 if (enqd_len + trb_buff_len < full_len) { 3284 field |= TRB_CHAIN; 3285 if (trb_is_link(ring->enqueue + 1)) { 3286 if (xhci_align_td(xhci, urb, enqd_len, 3287 &trb_buff_len, 3288 ring->enq_seg)) { 3289 send_addr = ring->enq_seg->bounce_dma; 3290 /* assuming TD won't span 2 segs */ 3291 td->bounce_seg = ring->enq_seg; 3292 } 3293 } 3294 } 3295 if (enqd_len + trb_buff_len >= full_len) { 3296 field &= ~TRB_CHAIN; 3297 field |= TRB_IOC; 3298 more_trbs_coming = false; 3299 td->last_trb = ring->enqueue; 3300 } 3301 3302 /* Only set interrupt on short packet for IN endpoints */ 3303 if (usb_urb_dir_in(urb)) 3304 field |= TRB_ISP; 3305 3306 /* Set the TRB length, TD size, and interrupter fields. */ 3307 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, 3308 full_len, urb, more_trbs_coming); 3309 3310 length_field = TRB_LEN(trb_buff_len) | 3311 TRB_TD_SIZE(remainder) | 3312 TRB_INTR_TARGET(0); 3313 3314 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, 3315 lower_32_bits(send_addr), 3316 upper_32_bits(send_addr), 3317 length_field, 3318 field); 3319 3320 addr += trb_buff_len; 3321 sent_len = trb_buff_len; 3322 3323 while (sg && sent_len >= block_len) { 3324 /* New sg entry */ 3325 --num_sgs; 3326 sent_len -= block_len; 3327 if (num_sgs != 0) { 3328 sg = sg_next(sg); 3329 block_len = sg_dma_len(sg); 3330 addr = (u64) sg_dma_address(sg); 3331 addr += sent_len; 3332 } 3333 } 3334 block_len -= sent_len; 3335 send_addr = addr; 3336 } 3337 3338 if (need_zero_pkt) { 3339 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3340 ep_index, urb->stream_id, 3341 1, urb, 1, mem_flags); 3342 urb_priv->td[1].last_trb = ring->enqueue; 3343 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; 3344 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); 3345 } 3346 3347 check_trb_math(urb, enqd_len); 3348 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3349 start_cycle, start_trb); 3350 return 0; 3351 } 3352 3353 /* Caller must have locked xhci->lock */ 3354 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3355 struct urb *urb, int slot_id, unsigned int ep_index) 3356 { 3357 struct xhci_ring *ep_ring; 3358 int num_trbs; 3359 int ret; 3360 struct usb_ctrlrequest *setup; 3361 struct xhci_generic_trb *start_trb; 3362 int start_cycle; 3363 u32 field; 3364 struct urb_priv *urb_priv; 3365 struct xhci_td *td; 3366 3367 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3368 if (!ep_ring) 3369 return -EINVAL; 3370 3371 /* 3372 * Need to copy setup packet into setup TRB, so we can't use the setup 3373 * DMA address. 3374 */ 3375 if (!urb->setup_packet) 3376 return -EINVAL; 3377 3378 /* 1 TRB for setup, 1 for status */ 3379 num_trbs = 2; 3380 /* 3381 * Don't need to check if we need additional event data and normal TRBs, 3382 * since data in control transfers will never get bigger than 16MB 3383 * XXX: can we get a buffer that crosses 64KB boundaries? 3384 */ 3385 if (urb->transfer_buffer_length > 0) 3386 num_trbs++; 3387 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3388 ep_index, urb->stream_id, 3389 num_trbs, urb, 0, mem_flags); 3390 if (ret < 0) 3391 return ret; 3392 3393 urb_priv = urb->hcpriv; 3394 td = &urb_priv->td[0]; 3395 3396 /* 3397 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3398 * until we've finished creating all the other TRBs. The ring's cycle 3399 * state may change as we enqueue the other TRBs, so save it too. 3400 */ 3401 start_trb = &ep_ring->enqueue->generic; 3402 start_cycle = ep_ring->cycle_state; 3403 3404 /* Queue setup TRB - see section 6.4.1.2.1 */ 3405 /* FIXME better way to translate setup_packet into two u32 fields? */ 3406 setup = (struct usb_ctrlrequest *) urb->setup_packet; 3407 field = 0; 3408 field |= TRB_IDT | TRB_TYPE(TRB_SETUP); 3409 if (start_cycle == 0) 3410 field |= 0x1; 3411 3412 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ 3413 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { 3414 if (urb->transfer_buffer_length > 0) { 3415 if (setup->bRequestType & USB_DIR_IN) 3416 field |= TRB_TX_TYPE(TRB_DATA_IN); 3417 else 3418 field |= TRB_TX_TYPE(TRB_DATA_OUT); 3419 } 3420 } 3421 3422 queue_trb(xhci, ep_ring, true, 3423 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, 3424 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, 3425 TRB_LEN(8) | TRB_INTR_TARGET(0), 3426 /* Immediate data in pointer */ 3427 field); 3428 3429 /* If there's data, queue data TRBs */ 3430 /* Only set interrupt on short packet for IN endpoints */ 3431 if (usb_urb_dir_in(urb)) 3432 field = TRB_ISP | TRB_TYPE(TRB_DATA); 3433 else 3434 field = TRB_TYPE(TRB_DATA); 3435 3436 if (urb->transfer_buffer_length > 0) { 3437 u32 length_field, remainder; 3438 3439 remainder = xhci_td_remainder(xhci, 0, 3440 urb->transfer_buffer_length, 3441 urb->transfer_buffer_length, 3442 urb, 1); 3443 length_field = TRB_LEN(urb->transfer_buffer_length) | 3444 TRB_TD_SIZE(remainder) | 3445 TRB_INTR_TARGET(0); 3446 if (setup->bRequestType & USB_DIR_IN) 3447 field |= TRB_DIR_IN; 3448 queue_trb(xhci, ep_ring, true, 3449 lower_32_bits(urb->transfer_dma), 3450 upper_32_bits(urb->transfer_dma), 3451 length_field, 3452 field | ep_ring->cycle_state); 3453 } 3454 3455 /* Save the DMA address of the last TRB in the TD */ 3456 td->last_trb = ep_ring->enqueue; 3457 3458 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ 3459 /* If the device sent data, the status stage is an OUT transfer */ 3460 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) 3461 field = 0; 3462 else 3463 field = TRB_DIR_IN; 3464 queue_trb(xhci, ep_ring, false, 3465 0, 3466 0, 3467 TRB_INTR_TARGET(0), 3468 /* Event on completion */ 3469 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); 3470 3471 giveback_first_trb(xhci, slot_id, ep_index, 0, 3472 start_cycle, start_trb); 3473 return 0; 3474 } 3475 3476 /* 3477 * The transfer burst count field of the isochronous TRB defines the number of 3478 * bursts that are required to move all packets in this TD. Only SuperSpeed 3479 * devices can burst up to bMaxBurst number of packets per service interval. 3480 * This field is zero based, meaning a value of zero in the field means one 3481 * burst. Basically, for everything but SuperSpeed devices, this field will be 3482 * zero. Only xHCI 1.0 host controllers support this field. 3483 */ 3484 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, 3485 struct urb *urb, unsigned int total_packet_count) 3486 { 3487 unsigned int max_burst; 3488 3489 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) 3490 return 0; 3491 3492 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3493 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; 3494 } 3495 3496 /* 3497 * Returns the number of packets in the last "burst" of packets. This field is 3498 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so 3499 * the last burst packet count is equal to the total number of packets in the 3500 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst 3501 * must contain (bMaxBurst + 1) number of packets, but the last burst can 3502 * contain 1 to (bMaxBurst + 1) packets. 3503 */ 3504 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, 3505 struct urb *urb, unsigned int total_packet_count) 3506 { 3507 unsigned int max_burst; 3508 unsigned int residue; 3509 3510 if (xhci->hci_version < 0x100) 3511 return 0; 3512 3513 if (urb->dev->speed >= USB_SPEED_SUPER) { 3514 /* bMaxBurst is zero based: 0 means 1 packet per burst */ 3515 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3516 residue = total_packet_count % (max_burst + 1); 3517 /* If residue is zero, the last burst contains (max_burst + 1) 3518 * number of packets, but the TLBPC field is zero-based. 3519 */ 3520 if (residue == 0) 3521 return max_burst; 3522 return residue - 1; 3523 } 3524 if (total_packet_count == 0) 3525 return 0; 3526 return total_packet_count - 1; 3527 } 3528 3529 /* 3530 * Calculates Frame ID field of the isochronous TRB identifies the 3531 * target frame that the Interval associated with this Isochronous 3532 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. 3533 * 3534 * Returns actual frame id on success, negative value on error. 3535 */ 3536 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, 3537 struct urb *urb, int index) 3538 { 3539 int start_frame, ist, ret = 0; 3540 int start_frame_id, end_frame_id, current_frame_id; 3541 3542 if (urb->dev->speed == USB_SPEED_LOW || 3543 urb->dev->speed == USB_SPEED_FULL) 3544 start_frame = urb->start_frame + index * urb->interval; 3545 else 3546 start_frame = (urb->start_frame + index * urb->interval) >> 3; 3547 3548 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): 3549 * 3550 * If bit [3] of IST is cleared to '0', software can add a TRB no 3551 * later than IST[2:0] Microframes before that TRB is scheduled to 3552 * be executed. 3553 * If bit [3] of IST is set to '1', software can add a TRB no later 3554 * than IST[2:0] Frames before that TRB is scheduled to be executed. 3555 */ 3556 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3557 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3558 ist <<= 3; 3559 3560 /* Software shall not schedule an Isoch TD with a Frame ID value that 3561 * is less than the Start Frame ID or greater than the End Frame ID, 3562 * where: 3563 * 3564 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 3565 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 3566 * 3567 * Both the End Frame ID and Start Frame ID values are calculated 3568 * in microframes. When software determines the valid Frame ID value; 3569 * The End Frame ID value should be rounded down to the nearest Frame 3570 * boundary, and the Start Frame ID value should be rounded up to the 3571 * nearest Frame boundary. 3572 */ 3573 current_frame_id = readl(&xhci->run_regs->microframe_index); 3574 start_frame_id = roundup(current_frame_id + ist + 1, 8); 3575 end_frame_id = rounddown(current_frame_id + 895 * 8, 8); 3576 3577 start_frame &= 0x7ff; 3578 start_frame_id = (start_frame_id >> 3) & 0x7ff; 3579 end_frame_id = (end_frame_id >> 3) & 0x7ff; 3580 3581 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", 3582 __func__, index, readl(&xhci->run_regs->microframe_index), 3583 start_frame_id, end_frame_id, start_frame); 3584 3585 if (start_frame_id < end_frame_id) { 3586 if (start_frame > end_frame_id || 3587 start_frame < start_frame_id) 3588 ret = -EINVAL; 3589 } else if (start_frame_id > end_frame_id) { 3590 if ((start_frame > end_frame_id && 3591 start_frame < start_frame_id)) 3592 ret = -EINVAL; 3593 } else { 3594 ret = -EINVAL; 3595 } 3596 3597 if (index == 0) { 3598 if (ret == -EINVAL || start_frame == start_frame_id) { 3599 start_frame = start_frame_id + 1; 3600 if (urb->dev->speed == USB_SPEED_LOW || 3601 urb->dev->speed == USB_SPEED_FULL) 3602 urb->start_frame = start_frame; 3603 else 3604 urb->start_frame = start_frame << 3; 3605 ret = 0; 3606 } 3607 } 3608 3609 if (ret) { 3610 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", 3611 start_frame, current_frame_id, index, 3612 start_frame_id, end_frame_id); 3613 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); 3614 return ret; 3615 } 3616 3617 return start_frame; 3618 } 3619 3620 /* This is for isoc transfer */ 3621 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3622 struct urb *urb, int slot_id, unsigned int ep_index) 3623 { 3624 struct xhci_ring *ep_ring; 3625 struct urb_priv *urb_priv; 3626 struct xhci_td *td; 3627 int num_tds, trbs_per_td; 3628 struct xhci_generic_trb *start_trb; 3629 bool first_trb; 3630 int start_cycle; 3631 u32 field, length_field; 3632 int running_total, trb_buff_len, td_len, td_remain_len, ret; 3633 u64 start_addr, addr; 3634 int i, j; 3635 bool more_trbs_coming; 3636 struct xhci_virt_ep *xep; 3637 int frame_id; 3638 3639 xep = &xhci->devs[slot_id]->eps[ep_index]; 3640 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 3641 3642 num_tds = urb->number_of_packets; 3643 if (num_tds < 1) { 3644 xhci_dbg(xhci, "Isoc URB with zero packets?\n"); 3645 return -EINVAL; 3646 } 3647 start_addr = (u64) urb->transfer_dma; 3648 start_trb = &ep_ring->enqueue->generic; 3649 start_cycle = ep_ring->cycle_state; 3650 3651 urb_priv = urb->hcpriv; 3652 /* Queue the TRBs for each TD, even if they are zero-length */ 3653 for (i = 0; i < num_tds; i++) { 3654 unsigned int total_pkt_count, max_pkt; 3655 unsigned int burst_count, last_burst_pkt_count; 3656 u32 sia_frame_id; 3657 3658 first_trb = true; 3659 running_total = 0; 3660 addr = start_addr + urb->iso_frame_desc[i].offset; 3661 td_len = urb->iso_frame_desc[i].length; 3662 td_remain_len = td_len; 3663 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 3664 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); 3665 3666 /* A zero-length transfer still involves at least one packet. */ 3667 if (total_pkt_count == 0) 3668 total_pkt_count++; 3669 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); 3670 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, 3671 urb, total_pkt_count); 3672 3673 trbs_per_td = count_isoc_trbs_needed(urb, i); 3674 3675 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, 3676 urb->stream_id, trbs_per_td, urb, i, mem_flags); 3677 if (ret < 0) { 3678 if (i == 0) 3679 return ret; 3680 goto cleanup; 3681 } 3682 td = &urb_priv->td[i]; 3683 3684 /* use SIA as default, if frame id is used overwrite it */ 3685 sia_frame_id = TRB_SIA; 3686 if (!(urb->transfer_flags & URB_ISO_ASAP) && 3687 HCC_CFC(xhci->hcc_params)) { 3688 frame_id = xhci_get_isoc_frame_id(xhci, urb, i); 3689 if (frame_id >= 0) 3690 sia_frame_id = TRB_FRAME_ID(frame_id); 3691 } 3692 /* 3693 * Set isoc specific data for the first TRB in a TD. 3694 * Prevent HW from getting the TRBs by keeping the cycle state 3695 * inverted in the first TDs isoc TRB. 3696 */ 3697 field = TRB_TYPE(TRB_ISOC) | 3698 TRB_TLBPC(last_burst_pkt_count) | 3699 sia_frame_id | 3700 (i ? ep_ring->cycle_state : !start_cycle); 3701 3702 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ 3703 if (!xep->use_extended_tbc) 3704 field |= TRB_TBC(burst_count); 3705 3706 /* fill the rest of the TRB fields, and remaining normal TRBs */ 3707 for (j = 0; j < trbs_per_td; j++) { 3708 u32 remainder = 0; 3709 3710 /* only first TRB is isoc, overwrite otherwise */ 3711 if (!first_trb) 3712 field = TRB_TYPE(TRB_NORMAL) | 3713 ep_ring->cycle_state; 3714 3715 /* Only set interrupt on short packet for IN EPs */ 3716 if (usb_urb_dir_in(urb)) 3717 field |= TRB_ISP; 3718 3719 /* Set the chain bit for all except the last TRB */ 3720 if (j < trbs_per_td - 1) { 3721 more_trbs_coming = true; 3722 field |= TRB_CHAIN; 3723 } else { 3724 more_trbs_coming = false; 3725 td->last_trb = ep_ring->enqueue; 3726 field |= TRB_IOC; 3727 /* set BEI, except for the last TD */ 3728 if (xhci->hci_version >= 0x100 && 3729 !(xhci->quirks & XHCI_AVOID_BEI) && 3730 i < num_tds - 1) 3731 field |= TRB_BEI; 3732 } 3733 /* Calculate TRB length */ 3734 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3735 if (trb_buff_len > td_remain_len) 3736 trb_buff_len = td_remain_len; 3737 3738 /* Set the TRB length, TD size, & interrupter fields. */ 3739 remainder = xhci_td_remainder(xhci, running_total, 3740 trb_buff_len, td_len, 3741 urb, more_trbs_coming); 3742 3743 length_field = TRB_LEN(trb_buff_len) | 3744 TRB_INTR_TARGET(0); 3745 3746 /* xhci 1.1 with ETE uses TD Size field for TBC */ 3747 if (first_trb && xep->use_extended_tbc) 3748 length_field |= TRB_TD_SIZE_TBC(burst_count); 3749 else 3750 length_field |= TRB_TD_SIZE(remainder); 3751 first_trb = false; 3752 3753 queue_trb(xhci, ep_ring, more_trbs_coming, 3754 lower_32_bits(addr), 3755 upper_32_bits(addr), 3756 length_field, 3757 field); 3758 running_total += trb_buff_len; 3759 3760 addr += trb_buff_len; 3761 td_remain_len -= trb_buff_len; 3762 } 3763 3764 /* Check TD length */ 3765 if (running_total != td_len) { 3766 xhci_err(xhci, "ISOC TD length unmatch\n"); 3767 ret = -EINVAL; 3768 goto cleanup; 3769 } 3770 } 3771 3772 /* store the next frame id */ 3773 if (HCC_CFC(xhci->hcc_params)) 3774 xep->next_frame_id = urb->start_frame + num_tds * urb->interval; 3775 3776 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 3777 if (xhci->quirks & XHCI_AMD_PLL_FIX) 3778 usb_amd_quirk_pll_disable(); 3779 } 3780 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; 3781 3782 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3783 start_cycle, start_trb); 3784 return 0; 3785 cleanup: 3786 /* Clean up a partially enqueued isoc transfer. */ 3787 3788 for (i--; i >= 0; i--) 3789 list_del_init(&urb_priv->td[i].td_list); 3790 3791 /* Use the first TD as a temporary variable to turn the TDs we've queued 3792 * into No-ops with a software-owned cycle bit. That way the hardware 3793 * won't accidentally start executing bogus TDs when we partially 3794 * overwrite them. td->first_trb and td->start_seg are already set. 3795 */ 3796 urb_priv->td[0].last_trb = ep_ring->enqueue; 3797 /* Every TRB except the first & last will have its cycle bit flipped. */ 3798 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); 3799 3800 /* Reset the ring enqueue back to the first TRB and its cycle bit. */ 3801 ep_ring->enqueue = urb_priv->td[0].first_trb; 3802 ep_ring->enq_seg = urb_priv->td[0].start_seg; 3803 ep_ring->cycle_state = start_cycle; 3804 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; 3805 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 3806 return ret; 3807 } 3808 3809 /* 3810 * Check transfer ring to guarantee there is enough room for the urb. 3811 * Update ISO URB start_frame and interval. 3812 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to 3813 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or 3814 * Contiguous Frame ID is not supported by HC. 3815 */ 3816 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 3817 struct urb *urb, int slot_id, unsigned int ep_index) 3818 { 3819 struct xhci_virt_device *xdev; 3820 struct xhci_ring *ep_ring; 3821 struct xhci_ep_ctx *ep_ctx; 3822 int start_frame; 3823 int num_tds, num_trbs, i; 3824 int ret; 3825 struct xhci_virt_ep *xep; 3826 int ist; 3827 3828 xdev = xhci->devs[slot_id]; 3829 xep = &xhci->devs[slot_id]->eps[ep_index]; 3830 ep_ring = xdev->eps[ep_index].ring; 3831 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 3832 3833 num_trbs = 0; 3834 num_tds = urb->number_of_packets; 3835 for (i = 0; i < num_tds; i++) 3836 num_trbs += count_isoc_trbs_needed(urb, i); 3837 3838 /* Check the ring to guarantee there is enough room for the whole urb. 3839 * Do not insert any td of the urb to the ring if the check failed. 3840 */ 3841 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 3842 num_trbs, mem_flags); 3843 if (ret) 3844 return ret; 3845 3846 /* 3847 * Check interval value. This should be done before we start to 3848 * calculate the start frame value. 3849 */ 3850 check_interval(xhci, urb, ep_ctx); 3851 3852 /* Calculate the start frame and put it in urb->start_frame. */ 3853 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { 3854 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { 3855 urb->start_frame = xep->next_frame_id; 3856 goto skip_start_over; 3857 } 3858 } 3859 3860 start_frame = readl(&xhci->run_regs->microframe_index); 3861 start_frame &= 0x3fff; 3862 /* 3863 * Round up to the next frame and consider the time before trb really 3864 * gets scheduled by hardare. 3865 */ 3866 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3867 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3868 ist <<= 3; 3869 start_frame += ist + XHCI_CFC_DELAY; 3870 start_frame = roundup(start_frame, 8); 3871 3872 /* 3873 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT 3874 * is greate than 8 microframes. 3875 */ 3876 if (urb->dev->speed == USB_SPEED_LOW || 3877 urb->dev->speed == USB_SPEED_FULL) { 3878 start_frame = roundup(start_frame, urb->interval << 3); 3879 urb->start_frame = start_frame >> 3; 3880 } else { 3881 start_frame = roundup(start_frame, urb->interval); 3882 urb->start_frame = start_frame; 3883 } 3884 3885 skip_start_over: 3886 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; 3887 3888 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); 3889 } 3890 3891 /**** Command Ring Operations ****/ 3892 3893 /* Generic function for queueing a command TRB on the command ring. 3894 * Check to make sure there's room on the command ring for one command TRB. 3895 * Also check that there's room reserved for commands that must not fail. 3896 * If this is a command that must not fail, meaning command_must_succeed = TRUE, 3897 * then only check for the number of reserved spots. 3898 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB 3899 * because the command event handler may want to resubmit a failed command. 3900 */ 3901 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 3902 u32 field1, u32 field2, 3903 u32 field3, u32 field4, bool command_must_succeed) 3904 { 3905 int reserved_trbs = xhci->cmd_ring_reserved_trbs; 3906 int ret; 3907 3908 if ((xhci->xhc_state & XHCI_STATE_DYING) || 3909 (xhci->xhc_state & XHCI_STATE_HALTED)) { 3910 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); 3911 return -ESHUTDOWN; 3912 } 3913 3914 if (!command_must_succeed) 3915 reserved_trbs++; 3916 3917 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, 3918 reserved_trbs, GFP_ATOMIC); 3919 if (ret < 0) { 3920 xhci_err(xhci, "ERR: No room for command on command ring\n"); 3921 if (command_must_succeed) 3922 xhci_err(xhci, "ERR: Reserved TRB counting for " 3923 "unfailable commands failed.\n"); 3924 return ret; 3925 } 3926 3927 cmd->command_trb = xhci->cmd_ring->enqueue; 3928 3929 /* if there are no other commands queued we start the timeout timer */ 3930 if (list_empty(&xhci->cmd_list)) { 3931 xhci->current_cmd = cmd; 3932 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 3933 } 3934 3935 list_add_tail(&cmd->cmd_list, &xhci->cmd_list); 3936 3937 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, 3938 field4 | xhci->cmd_ring->cycle_state); 3939 return 0; 3940 } 3941 3942 /* Queue a slot enable or disable request on the command ring */ 3943 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 3944 u32 trb_type, u32 slot_id) 3945 { 3946 return queue_command(xhci, cmd, 0, 0, 0, 3947 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); 3948 } 3949 3950 /* Queue an address device command TRB */ 3951 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 3952 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) 3953 { 3954 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 3955 upper_32_bits(in_ctx_ptr), 0, 3956 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) 3957 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); 3958 } 3959 3960 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 3961 u32 field1, u32 field2, u32 field3, u32 field4) 3962 { 3963 return queue_command(xhci, cmd, field1, field2, field3, field4, false); 3964 } 3965 3966 /* Queue a reset device command TRB */ 3967 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 3968 u32 slot_id) 3969 { 3970 return queue_command(xhci, cmd, 0, 0, 0, 3971 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), 3972 false); 3973 } 3974 3975 /* Queue a configure endpoint command TRB */ 3976 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 3977 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 3978 u32 slot_id, bool command_must_succeed) 3979 { 3980 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 3981 upper_32_bits(in_ctx_ptr), 0, 3982 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), 3983 command_must_succeed); 3984 } 3985 3986 /* Queue an evaluate context command TRB */ 3987 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 3988 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) 3989 { 3990 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 3991 upper_32_bits(in_ctx_ptr), 0, 3992 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), 3993 command_must_succeed); 3994 } 3995 3996 /* 3997 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop 3998 * activity on an endpoint that is about to be suspended. 3999 */ 4000 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 4001 int slot_id, unsigned int ep_index, int suspend) 4002 { 4003 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4004 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4005 u32 type = TRB_TYPE(TRB_STOP_RING); 4006 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); 4007 4008 return queue_command(xhci, cmd, 0, 0, 0, 4009 trb_slot_id | trb_ep_index | type | trb_suspend, false); 4010 } 4011 4012 /* Set Transfer Ring Dequeue Pointer command */ 4013 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 4014 unsigned int slot_id, unsigned int ep_index, 4015 struct xhci_dequeue_state *deq_state) 4016 { 4017 dma_addr_t addr; 4018 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4019 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4020 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id); 4021 u32 trb_sct = 0; 4022 u32 type = TRB_TYPE(TRB_SET_DEQ); 4023 struct xhci_virt_ep *ep; 4024 struct xhci_command *cmd; 4025 int ret; 4026 4027 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 4028 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", 4029 deq_state->new_deq_seg, 4030 (unsigned long long)deq_state->new_deq_seg->dma, 4031 deq_state->new_deq_ptr, 4032 (unsigned long long)xhci_trb_virt_to_dma( 4033 deq_state->new_deq_seg, deq_state->new_deq_ptr), 4034 deq_state->new_cycle_state); 4035 4036 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, 4037 deq_state->new_deq_ptr); 4038 if (addr == 0) { 4039 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 4040 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", 4041 deq_state->new_deq_seg, deq_state->new_deq_ptr); 4042 return; 4043 } 4044 ep = &xhci->devs[slot_id]->eps[ep_index]; 4045 if ((ep->ep_state & SET_DEQ_PENDING)) { 4046 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 4047 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); 4048 return; 4049 } 4050 4051 /* This function gets called from contexts where it cannot sleep */ 4052 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); 4053 if (!cmd) 4054 return; 4055 4056 ep->queued_deq_seg = deq_state->new_deq_seg; 4057 ep->queued_deq_ptr = deq_state->new_deq_ptr; 4058 if (deq_state->stream_id) 4059 trb_sct = SCT_FOR_TRB(SCT_PRI_TR); 4060 ret = queue_command(xhci, cmd, 4061 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, 4062 upper_32_bits(addr), trb_stream_id, 4063 trb_slot_id | trb_ep_index | type, false); 4064 if (ret < 0) { 4065 xhci_free_command(xhci, cmd); 4066 return; 4067 } 4068 4069 /* Stop the TD queueing code from ringing the doorbell until 4070 * this command completes. The HC won't set the dequeue pointer 4071 * if the ring is running, and ringing the doorbell starts the 4072 * ring running. 4073 */ 4074 ep->ep_state |= SET_DEQ_PENDING; 4075 } 4076 4077 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 4078 int slot_id, unsigned int ep_index, 4079 enum xhci_ep_reset_type reset_type) 4080 { 4081 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4082 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4083 u32 type = TRB_TYPE(TRB_RESET_EP); 4084 4085 if (reset_type == EP_SOFT_RESET) 4086 type |= TRB_TSP; 4087 4088 return queue_command(xhci, cmd, 0, 0, 0, 4089 trb_slot_id | trb_ep_index | type, false); 4090 } 4091