1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 /*
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17 *
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
29 *
30 * Cycle bit rules:
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
35 *
36 * Producer rules:
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
40 * cycle state).
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
44 *
45 * Consumer rules:
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
53 */
54
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
58 #include "xhci.h"
59 #include "xhci-trace.h"
60
61 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
64
65 /*
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
67 * address of the TRB.
68 */
xhci_trb_virt_to_dma(struct xhci_segment * seg,union xhci_trb * trb)69 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
70 union xhci_trb *trb)
71 {
72 unsigned long segment_offset;
73
74 if (!seg || !trb || trb < seg->trbs)
75 return 0;
76 /* offset in TRBs */
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
79 return 0;
80 return seg->dma + (segment_offset * sizeof(*trb));
81 }
82
trb_is_noop(union xhci_trb * trb)83 static bool trb_is_noop(union xhci_trb *trb)
84 {
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
86 }
87
trb_is_link(union xhci_trb * trb)88 static bool trb_is_link(union xhci_trb *trb)
89 {
90 return TRB_TYPE_LINK_LE32(trb->link.control);
91 }
92
last_trb_on_seg(struct xhci_segment * seg,union xhci_trb * trb)93 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
94 {
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
96 }
97
last_trb_on_ring(struct xhci_ring * ring,struct xhci_segment * seg,union xhci_trb * trb)98 static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
100 {
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
102 }
103
link_trb_toggles_cycle(union xhci_trb * trb)104 static bool link_trb_toggles_cycle(union xhci_trb *trb)
105 {
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107 }
108
last_td_in_urb(struct xhci_td * td)109 static bool last_td_in_urb(struct xhci_td *td)
110 {
111 struct urb_priv *urb_priv = td->urb->hcpriv;
112
113 return urb_priv->num_tds_done == urb_priv->num_tds;
114 }
115
inc_td_cnt(struct urb * urb)116 static void inc_td_cnt(struct urb *urb)
117 {
118 struct urb_priv *urb_priv = urb->hcpriv;
119
120 urb_priv->num_tds_done++;
121 }
122
trb_to_noop(union xhci_trb * trb,u32 noop_type)123 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
124 {
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
128 } else {
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 }
136 }
137
138 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
141 */
next_trb(struct xhci_hcd * xhci,struct xhci_ring * ring,struct xhci_segment ** seg,union xhci_trb ** trb)142 static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
146 {
147 if (trb_is_link(*trb)) {
148 *seg = (*seg)->next;
149 *trb = ((*seg)->trbs);
150 } else {
151 (*trb)++;
152 }
153 }
154
155 /*
156 * See Cycle bit rules. SW is the consumer for the event ring only.
157 */
inc_deq(struct xhci_hcd * xhci,struct xhci_ring * ring)158 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
159 {
160 unsigned int link_trb_count = 0;
161
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
165 ring->dequeue++;
166 goto out;
167 }
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
172 goto out;
173 }
174
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue))
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
179 else
180 ring->dequeue++;
181 }
182
183 while (trb_is_link(ring->dequeue)) {
184 ring->deq_seg = ring->deq_seg->next;
185 ring->dequeue = ring->deq_seg->trbs;
186
187 if (link_trb_count++ > ring->num_segs) {
188 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
189 break;
190 }
191 }
192 out:
193 trace_xhci_inc_deq(ring);
194
195 return;
196 }
197
198 /*
199 * See Cycle bit rules. SW is the consumer for the event ring only.
200 *
201 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
202 * chain bit is set), then set the chain bit in all the following link TRBs.
203 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
204 * have their chain bit cleared (so that each Link TRB is a separate TD).
205 *
206 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
207 * set, but other sections talk about dealing with the chain bit set. This was
208 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
209 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
210 *
211 * @more_trbs_coming: Will you enqueue more TRBs before calling
212 * prepare_transfer()?
213 */
inc_enq(struct xhci_hcd * xhci,struct xhci_ring * ring,bool more_trbs_coming)214 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
215 bool more_trbs_coming)
216 {
217 u32 chain;
218 union xhci_trb *next;
219 unsigned int link_trb_count = 0;
220
221 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
222
223 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
224 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
225 return;
226 }
227
228 next = ++(ring->enqueue);
229
230 /* Update the dequeue pointer further if that was a link TRB */
231 while (trb_is_link(next)) {
232
233 /*
234 * If the caller doesn't plan on enqueueing more TDs before
235 * ringing the doorbell, then we don't want to give the link TRB
236 * to the hardware just yet. We'll give the link TRB back in
237 * prepare_ring() just before we enqueue the TD at the top of
238 * the ring.
239 */
240 if (!chain && !more_trbs_coming)
241 break;
242
243 /* If we're not dealing with 0.95 hardware or isoc rings on
244 * AMD 0.96 host, carry over the chain bit of the previous TRB
245 * (which may mean the chain bit is cleared).
246 */
247 if (!(ring->type == TYPE_ISOC &&
248 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
249 !xhci_link_trb_quirk(xhci)) {
250 next->link.control &= cpu_to_le32(~TRB_CHAIN);
251 next->link.control |= cpu_to_le32(chain);
252 }
253 /* Give this link TRB to the hardware */
254 wmb();
255 next->link.control ^= cpu_to_le32(TRB_CYCLE);
256
257 /* Toggle the cycle bit after the last ring segment. */
258 if (link_trb_toggles_cycle(next))
259 ring->cycle_state ^= 1;
260
261 ring->enq_seg = ring->enq_seg->next;
262 ring->enqueue = ring->enq_seg->trbs;
263 next = ring->enqueue;
264
265 if (link_trb_count++ > ring->num_segs) {
266 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
267 break;
268 }
269 }
270
271 trace_xhci_inc_enq(ring);
272 }
273
274 /*
275 * Return number of free normal TRBs from enqueue to dequeue pointer on ring.
276 * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment.
277 * Only for transfer and command rings where driver is the producer, not for
278 * event rings.
279 */
xhci_num_trbs_free(struct xhci_hcd * xhci,struct xhci_ring * ring)280 static unsigned int xhci_num_trbs_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
281 {
282 struct xhci_segment *enq_seg = ring->enq_seg;
283 union xhci_trb *enq = ring->enqueue;
284 union xhci_trb *last_on_seg;
285 unsigned int free = 0;
286 int i = 0;
287
288 /* Ring might be empty even if enq != deq if enq is left on a link trb */
289 if (trb_is_link(enq)) {
290 enq_seg = enq_seg->next;
291 enq = enq_seg->trbs;
292 }
293
294 /* Empty ring, common case, don't walk the segments */
295 if (enq == ring->dequeue)
296 return ring->num_segs * (TRBS_PER_SEGMENT - 1);
297
298 do {
299 if (ring->deq_seg == enq_seg && ring->dequeue >= enq)
300 return free + (ring->dequeue - enq);
301 last_on_seg = &enq_seg->trbs[TRBS_PER_SEGMENT - 1];
302 free += last_on_seg - enq;
303 enq_seg = enq_seg->next;
304 enq = enq_seg->trbs;
305 } while (i++ <= ring->num_segs);
306
307 return free;
308 }
309
310 /*
311 * Check to see if there's room to enqueue num_trbs on the ring and make sure
312 * enqueue pointer will not advance into dequeue segment. See rules above.
313 * return number of new segments needed to ensure this.
314 */
315
xhci_ring_expansion_needed(struct xhci_hcd * xhci,struct xhci_ring * ring,unsigned int num_trbs)316 static unsigned int xhci_ring_expansion_needed(struct xhci_hcd *xhci, struct xhci_ring *ring,
317 unsigned int num_trbs)
318 {
319 struct xhci_segment *seg;
320 int trbs_past_seg;
321 int enq_used;
322 int new_segs;
323
324 enq_used = ring->enqueue - ring->enq_seg->trbs;
325
326 /* how many trbs will be queued past the enqueue segment? */
327 trbs_past_seg = enq_used + num_trbs - (TRBS_PER_SEGMENT - 1);
328
329 /*
330 * Consider expanding the ring already if num_trbs fills the current
331 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into
332 * the next segment. Avoids confusing full ring with special empty ring
333 * case below
334 */
335 if (trbs_past_seg < 0)
336 return 0;
337
338 /* Empty ring special case, enqueue stuck on link trb while dequeue advanced */
339 if (trb_is_link(ring->enqueue) && ring->enq_seg->next->trbs == ring->dequeue)
340 return 0;
341
342 new_segs = 1 + (trbs_past_seg / (TRBS_PER_SEGMENT - 1));
343 seg = ring->enq_seg;
344
345 while (new_segs > 0) {
346 seg = seg->next;
347 if (seg == ring->deq_seg) {
348 xhci_dbg(xhci, "Ring expansion by %d segments needed\n",
349 new_segs);
350 xhci_dbg(xhci, "Adding %d trbs moves enq %d trbs into deq seg\n",
351 num_trbs, trbs_past_seg % TRBS_PER_SEGMENT);
352 return new_segs;
353 }
354 new_segs--;
355 }
356
357 return 0;
358 }
359
360 /* Ring the host controller doorbell after placing a command on the ring */
xhci_ring_cmd_db(struct xhci_hcd * xhci)361 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
362 {
363 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
364 return;
365
366 xhci_dbg(xhci, "// Ding dong!\n");
367
368 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
369
370 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
371 /* Flush PCI posted writes */
372 readl(&xhci->dba->doorbell[0]);
373 }
374
xhci_mod_cmd_timer(struct xhci_hcd * xhci)375 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci)
376 {
377 return mod_delayed_work(system_wq, &xhci->cmd_timer,
378 msecs_to_jiffies(xhci->current_cmd->timeout_ms));
379 }
380
xhci_next_queued_cmd(struct xhci_hcd * xhci)381 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
382 {
383 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
384 cmd_list);
385 }
386
387 /*
388 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
389 * If there are other commands waiting then restart the ring and kick the timer.
390 * This must be called with command ring stopped and xhci->lock held.
391 */
xhci_handle_stopped_cmd_ring(struct xhci_hcd * xhci,struct xhci_command * cur_cmd)392 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
393 struct xhci_command *cur_cmd)
394 {
395 struct xhci_command *i_cmd;
396
397 /* Turn all aborted commands in list to no-ops, then restart */
398 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
399
400 if (i_cmd->status != COMP_COMMAND_ABORTED)
401 continue;
402
403 i_cmd->status = COMP_COMMAND_RING_STOPPED;
404
405 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
406 i_cmd->command_trb);
407
408 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
409
410 /*
411 * caller waiting for completion is called when command
412 * completion event is received for these no-op commands
413 */
414 }
415
416 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
417
418 /* ring command ring doorbell to restart the command ring */
419 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
420 !(xhci->xhc_state & XHCI_STATE_DYING)) {
421 xhci->current_cmd = cur_cmd;
422 xhci_mod_cmd_timer(xhci);
423 xhci_ring_cmd_db(xhci);
424 }
425 }
426
427 /* Must be called with xhci->lock held, releases and aquires lock back */
xhci_abort_cmd_ring(struct xhci_hcd * xhci,unsigned long flags)428 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
429 {
430 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
431 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
432 u64 crcr;
433 int ret;
434
435 xhci_dbg(xhci, "Abort command ring\n");
436
437 reinit_completion(&xhci->cmd_ring_stop_completion);
438
439 /*
440 * The control bits like command stop, abort are located in lower
441 * dword of the command ring control register.
442 * Some controllers require all 64 bits to be written to abort the ring.
443 * Make sure the upper dword is valid, pointing to the next command,
444 * avoiding corrupting the command ring pointer in case the command ring
445 * is stopped by the time the upper dword is written.
446 */
447 next_trb(xhci, NULL, &new_seg, &new_deq);
448 if (trb_is_link(new_deq))
449 next_trb(xhci, NULL, &new_seg, &new_deq);
450
451 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
452 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
453
454 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
455 * completion of the Command Abort operation. If CRR is not negated in 5
456 * seconds then driver handles it as if host died (-ENODEV).
457 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
458 * and try to recover a -ETIMEDOUT with a host controller reset.
459 */
460 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
461 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
462 if (ret < 0) {
463 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
464 xhci_halt(xhci);
465 xhci_hc_died(xhci);
466 return ret;
467 }
468 /*
469 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
470 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
471 * but the completion event in never sent. Wait 2 secs (arbitrary
472 * number) to handle those cases after negation of CMD_RING_RUNNING.
473 */
474 spin_unlock_irqrestore(&xhci->lock, flags);
475 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
476 msecs_to_jiffies(2000));
477 spin_lock_irqsave(&xhci->lock, flags);
478 if (!ret) {
479 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
480 xhci_cleanup_command_queue(xhci);
481 } else {
482 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
483 }
484 return 0;
485 }
486
xhci_ring_ep_doorbell(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id)487 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
488 unsigned int slot_id,
489 unsigned int ep_index,
490 unsigned int stream_id)
491 {
492 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
493 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
494 unsigned int ep_state = ep->ep_state;
495
496 /* Don't ring the doorbell for this endpoint if there are pending
497 * cancellations because we don't want to interrupt processing.
498 * We don't want to restart any stream rings if there's a set dequeue
499 * pointer command pending because the device can choose to start any
500 * stream once the endpoint is on the HW schedule.
501 */
502 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
503 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
504 return;
505
506 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
507
508 writel(DB_VALUE(ep_index, stream_id), db_addr);
509 /* flush the write */
510 readl(db_addr);
511 }
512
513 /* Ring the doorbell for any rings with pending URBs */
ring_doorbell_for_active_rings(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index)514 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
515 unsigned int slot_id,
516 unsigned int ep_index)
517 {
518 unsigned int stream_id;
519 struct xhci_virt_ep *ep;
520
521 ep = &xhci->devs[slot_id]->eps[ep_index];
522
523 /* A ring has pending URBs if its TD list is not empty */
524 if (!(ep->ep_state & EP_HAS_STREAMS)) {
525 if (ep->ring && !(list_empty(&ep->ring->td_list)))
526 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
527 return;
528 }
529
530 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
531 stream_id++) {
532 struct xhci_stream_info *stream_info = ep->stream_info;
533 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
534 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
535 stream_id);
536 }
537 }
538
xhci_ring_doorbell_for_active_rings(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index)539 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
540 unsigned int slot_id,
541 unsigned int ep_index)
542 {
543 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
544 }
545
xhci_get_virt_ep(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index)546 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
547 unsigned int slot_id,
548 unsigned int ep_index)
549 {
550 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
551 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
552 return NULL;
553 }
554 if (ep_index >= EP_CTX_PER_DEV) {
555 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
556 return NULL;
557 }
558 if (!xhci->devs[slot_id]) {
559 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
560 return NULL;
561 }
562
563 return &xhci->devs[slot_id]->eps[ep_index];
564 }
565
xhci_virt_ep_to_ring(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,unsigned int stream_id)566 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
567 struct xhci_virt_ep *ep,
568 unsigned int stream_id)
569 {
570 /* common case, no streams */
571 if (!(ep->ep_state & EP_HAS_STREAMS))
572 return ep->ring;
573
574 if (!ep->stream_info)
575 return NULL;
576
577 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
578 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
579 stream_id, ep->vdev->slot_id, ep->ep_index);
580 return NULL;
581 }
582
583 return ep->stream_info->stream_rings[stream_id];
584 }
585
586 /* Get the right ring for the given slot_id, ep_index and stream_id.
587 * If the endpoint supports streams, boundary check the URB's stream ID.
588 * If the endpoint doesn't support streams, return the singular endpoint ring.
589 */
xhci_triad_to_transfer_ring(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id)590 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
591 unsigned int slot_id, unsigned int ep_index,
592 unsigned int stream_id)
593 {
594 struct xhci_virt_ep *ep;
595
596 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
597 if (!ep)
598 return NULL;
599
600 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
601 }
602
603
604 /*
605 * Get the hw dequeue pointer xHC stopped on, either directly from the
606 * endpoint context, or if streams are in use from the stream context.
607 * The returned hw_dequeue contains the lowest four bits with cycle state
608 * and possbile stream context type.
609 */
xhci_get_hw_deq(struct xhci_hcd * xhci,struct xhci_virt_device * vdev,unsigned int ep_index,unsigned int stream_id)610 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
611 unsigned int ep_index, unsigned int stream_id)
612 {
613 struct xhci_ep_ctx *ep_ctx;
614 struct xhci_stream_ctx *st_ctx;
615 struct xhci_virt_ep *ep;
616
617 ep = &vdev->eps[ep_index];
618
619 if (ep->ep_state & EP_HAS_STREAMS) {
620 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
621 return le64_to_cpu(st_ctx->stream_ring);
622 }
623 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
624 return le64_to_cpu(ep_ctx->deq);
625 }
626
xhci_move_dequeue_past_td(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id,struct xhci_td * td)627 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
628 unsigned int slot_id, unsigned int ep_index,
629 unsigned int stream_id, struct xhci_td *td)
630 {
631 struct xhci_virt_device *dev = xhci->devs[slot_id];
632 struct xhci_virt_ep *ep = &dev->eps[ep_index];
633 struct xhci_ring *ep_ring;
634 struct xhci_command *cmd;
635 struct xhci_segment *new_seg;
636 union xhci_trb *new_deq;
637 int new_cycle;
638 dma_addr_t addr;
639 u64 hw_dequeue;
640 bool cycle_found = false;
641 bool td_last_trb_found = false;
642 u32 trb_sct = 0;
643 int ret;
644
645 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
646 ep_index, stream_id);
647 if (!ep_ring) {
648 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
649 stream_id);
650 return -ENODEV;
651 }
652 /*
653 * A cancelled TD can complete with a stall if HW cached the trb.
654 * In this case driver can't find td, but if the ring is empty we
655 * can move the dequeue pointer to the current enqueue position.
656 * We shouldn't hit this anymore as cached cancelled TRBs are given back
657 * after clearing the cache, but be on the safe side and keep it anyway
658 */
659 if (!td) {
660 if (list_empty(&ep_ring->td_list)) {
661 new_seg = ep_ring->enq_seg;
662 new_deq = ep_ring->enqueue;
663 new_cycle = ep_ring->cycle_state;
664 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
665 goto deq_found;
666 } else {
667 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
668 return -EINVAL;
669 }
670 }
671
672 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
673 new_seg = ep_ring->deq_seg;
674 new_deq = ep_ring->dequeue;
675 new_cycle = hw_dequeue & 0x1;
676
677 /*
678 * We want to find the pointer, segment and cycle state of the new trb
679 * (the one after current TD's last_trb). We know the cycle state at
680 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
681 * found.
682 */
683 do {
684 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
685 == (dma_addr_t)(hw_dequeue & ~0xf)) {
686 cycle_found = true;
687 if (td_last_trb_found)
688 break;
689 }
690 if (new_deq == td->last_trb)
691 td_last_trb_found = true;
692
693 if (cycle_found && trb_is_link(new_deq) &&
694 link_trb_toggles_cycle(new_deq))
695 new_cycle ^= 0x1;
696
697 next_trb(xhci, ep_ring, &new_seg, &new_deq);
698
699 /* Search wrapped around, bail out */
700 if (new_deq == ep->ring->dequeue) {
701 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
702 return -EINVAL;
703 }
704
705 } while (!cycle_found || !td_last_trb_found);
706
707 deq_found:
708
709 /* Don't update the ring cycle state for the producer (us). */
710 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
711 if (addr == 0) {
712 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
713 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
714 return -EINVAL;
715 }
716
717 if ((ep->ep_state & SET_DEQ_PENDING)) {
718 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
719 &addr);
720 return -EBUSY;
721 }
722
723 /* This function gets called from contexts where it cannot sleep */
724 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
725 if (!cmd) {
726 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
727 return -ENOMEM;
728 }
729
730 if (stream_id)
731 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
732 ret = queue_command(xhci, cmd,
733 lower_32_bits(addr) | trb_sct | new_cycle,
734 upper_32_bits(addr),
735 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
736 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
737 if (ret < 0) {
738 xhci_free_command(xhci, cmd);
739 return ret;
740 }
741 ep->queued_deq_seg = new_seg;
742 ep->queued_deq_ptr = new_deq;
743
744 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
745 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
746
747 /* Stop the TD queueing code from ringing the doorbell until
748 * this command completes. The HC won't set the dequeue pointer
749 * if the ring is running, and ringing the doorbell starts the
750 * ring running.
751 */
752 ep->ep_state |= SET_DEQ_PENDING;
753 xhci_ring_cmd_db(xhci);
754 return 0;
755 }
756
757 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
758 * (The last TRB actually points to the ring enqueue pointer, which is not part
759 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
760 */
td_to_noop(struct xhci_hcd * xhci,struct xhci_ring * ep_ring,struct xhci_td * td,bool flip_cycle)761 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
762 struct xhci_td *td, bool flip_cycle)
763 {
764 struct xhci_segment *seg = td->start_seg;
765 union xhci_trb *trb = td->first_trb;
766
767 while (1) {
768 trb_to_noop(trb, TRB_TR_NOOP);
769
770 /* flip cycle if asked to */
771 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
772 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
773
774 if (trb == td->last_trb)
775 break;
776
777 next_trb(xhci, ep_ring, &seg, &trb);
778 }
779 }
780
781 /*
782 * Must be called with xhci->lock held in interrupt context,
783 * releases and re-acquires xhci->lock
784 */
xhci_giveback_urb_in_irq(struct xhci_hcd * xhci,struct xhci_td * cur_td,int status)785 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
786 struct xhci_td *cur_td, int status)
787 {
788 struct urb *urb = cur_td->urb;
789 struct urb_priv *urb_priv = urb->hcpriv;
790 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
791
792 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
793 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
794 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
795 if (xhci->quirks & XHCI_AMD_PLL_FIX)
796 usb_amd_quirk_pll_enable();
797 }
798 }
799 xhci_urb_free_priv(urb_priv);
800 usb_hcd_unlink_urb_from_ep(hcd, urb);
801 trace_xhci_urb_giveback(urb);
802 usb_hcd_giveback_urb(hcd, urb, status);
803 }
804
xhci_unmap_td_bounce_buffer(struct xhci_hcd * xhci,struct xhci_ring * ring,struct xhci_td * td)805 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
806 struct xhci_ring *ring, struct xhci_td *td)
807 {
808 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
809 struct xhci_segment *seg = td->bounce_seg;
810 struct urb *urb = td->urb;
811 size_t len;
812
813 if (!ring || !seg || !urb)
814 return;
815
816 if (usb_urb_dir_out(urb)) {
817 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
818 DMA_TO_DEVICE);
819 return;
820 }
821
822 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
823 DMA_FROM_DEVICE);
824 /* for in tranfers we need to copy the data from bounce to sg */
825 if (urb->num_sgs) {
826 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
827 seg->bounce_len, seg->bounce_offs);
828 if (len != seg->bounce_len)
829 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
830 len, seg->bounce_len);
831 } else {
832 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
833 seg->bounce_len);
834 }
835 seg->bounce_len = 0;
836 seg->bounce_offs = 0;
837 }
838
xhci_td_cleanup(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_ring * ep_ring,int status)839 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
840 struct xhci_ring *ep_ring, int status)
841 {
842 struct urb *urb = NULL;
843
844 /* Clean up the endpoint's TD list */
845 urb = td->urb;
846
847 /* if a bounce buffer was used to align this td then unmap it */
848 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
849
850 /* Do one last check of the actual transfer length.
851 * If the host controller said we transferred more data than the buffer
852 * length, urb->actual_length will be a very big number (since it's
853 * unsigned). Play it safe and say we didn't transfer anything.
854 */
855 if (urb->actual_length > urb->transfer_buffer_length) {
856 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
857 urb->transfer_buffer_length, urb->actual_length);
858 urb->actual_length = 0;
859 status = 0;
860 }
861 /* TD might be removed from td_list if we are giving back a cancelled URB */
862 if (!list_empty(&td->td_list))
863 list_del_init(&td->td_list);
864 /* Giving back a cancelled URB, or if a slated TD completed anyway */
865 if (!list_empty(&td->cancelled_td_list))
866 list_del_init(&td->cancelled_td_list);
867
868 inc_td_cnt(urb);
869 /* Giveback the urb when all the tds are completed */
870 if (last_td_in_urb(td)) {
871 if ((urb->actual_length != urb->transfer_buffer_length &&
872 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
873 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
874 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
875 urb, urb->actual_length,
876 urb->transfer_buffer_length, status);
877
878 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
879 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
880 status = 0;
881 xhci_giveback_urb_in_irq(xhci, td, status);
882 }
883
884 return 0;
885 }
886
887
888 /* Complete the cancelled URBs we unlinked from td_list. */
xhci_giveback_invalidated_tds(struct xhci_virt_ep * ep)889 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
890 {
891 struct xhci_ring *ring;
892 struct xhci_td *td, *tmp_td;
893
894 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
895 cancelled_td_list) {
896
897 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
898
899 if (td->cancel_status == TD_CLEARED) {
900 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
901 __func__, td->urb);
902 xhci_td_cleanup(ep->xhci, td, ring, td->status);
903 } else {
904 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
905 __func__, td->urb, td->cancel_status);
906 }
907 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
908 return;
909 }
910 }
911
xhci_reset_halted_ep(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,enum xhci_ep_reset_type reset_type)912 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
913 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
914 {
915 struct xhci_command *command;
916 int ret = 0;
917
918 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
919 if (!command) {
920 ret = -ENOMEM;
921 goto done;
922 }
923
924 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
925 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
926 ep_index, slot_id);
927
928 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
929 done:
930 if (ret)
931 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
932 slot_id, ep_index, ret);
933 return ret;
934 }
935
xhci_handle_halted_endpoint(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_td * td,enum xhci_ep_reset_type reset_type)936 static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
937 struct xhci_virt_ep *ep,
938 struct xhci_td *td,
939 enum xhci_ep_reset_type reset_type)
940 {
941 unsigned int slot_id = ep->vdev->slot_id;
942 int err;
943
944 /*
945 * Avoid resetting endpoint if link is inactive. Can cause host hang.
946 * Device will be reset soon to recover the link so don't do anything
947 */
948 if (ep->vdev->flags & VDEV_PORT_ERROR)
949 return -ENODEV;
950
951 /* add td to cancelled list and let reset ep handler take care of it */
952 if (reset_type == EP_HARD_RESET) {
953 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
954 if (td && list_empty(&td->cancelled_td_list)) {
955 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
956 td->cancel_status = TD_HALTED;
957 }
958 }
959
960 if (ep->ep_state & EP_HALTED) {
961 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
962 ep->ep_index);
963 return 0;
964 }
965
966 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
967 if (err)
968 return err;
969
970 ep->ep_state |= EP_HALTED;
971
972 xhci_ring_cmd_db(xhci);
973
974 return 0;
975 }
976
977 /*
978 * Fix up the ep ring first, so HW stops executing cancelled TDs.
979 * We have the xHCI lock, so nothing can modify this list until we drop it.
980 * We're also in the event handler, so we can't get re-interrupted if another
981 * Stop Endpoint command completes.
982 *
983 * only call this when ring is not in a running state
984 */
985
xhci_invalidate_cancelled_tds(struct xhci_virt_ep * ep)986 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
987 {
988 struct xhci_hcd *xhci;
989 struct xhci_td *td = NULL;
990 struct xhci_td *tmp_td = NULL;
991 struct xhci_td *cached_td = NULL;
992 struct xhci_ring *ring;
993 u64 hw_deq;
994 unsigned int slot_id = ep->vdev->slot_id;
995 int err;
996
997 xhci = ep->xhci;
998
999 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1000 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1001 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
1002 (unsigned long long)xhci_trb_virt_to_dma(
1003 td->start_seg, td->first_trb),
1004 td->urb->stream_id, td->urb);
1005 list_del_init(&td->td_list);
1006 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
1007 if (!ring) {
1008 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1009 td->urb, td->urb->stream_id);
1010 continue;
1011 }
1012 /*
1013 * If a ring stopped on the TD we need to cancel then we have to
1014 * move the xHC endpoint ring dequeue pointer past this TD.
1015 * Rings halted due to STALL may show hw_deq is past the stalled
1016 * TD, but still require a set TR Deq command to flush xHC cache.
1017 */
1018 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
1019 td->urb->stream_id);
1020 hw_deq &= ~0xf;
1021
1022 if (td->cancel_status == TD_HALTED ||
1023 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
1024 switch (td->cancel_status) {
1025 case TD_CLEARED: /* TD is already no-op */
1026 case TD_CLEARING_CACHE: /* set TR deq command already queued */
1027 break;
1028 case TD_DIRTY: /* TD is cached, clear it */
1029 case TD_HALTED:
1030 case TD_CLEARING_CACHE_DEFERRED:
1031 if (cached_td) {
1032 if (cached_td->urb->stream_id != td->urb->stream_id) {
1033 /* Multiple streams case, defer move dq */
1034 xhci_dbg(xhci,
1035 "Move dq deferred: stream %u URB %p\n",
1036 td->urb->stream_id, td->urb);
1037 td->cancel_status = TD_CLEARING_CACHE_DEFERRED;
1038 break;
1039 }
1040
1041 /* Should never happen, but clear the TD if it does */
1042 xhci_warn(xhci,
1043 "Found multiple active URBs %p and %p in stream %u?\n",
1044 td->urb, cached_td->urb,
1045 td->urb->stream_id);
1046 td_to_noop(xhci, ring, cached_td, false);
1047 cached_td->cancel_status = TD_CLEARED;
1048 }
1049
1050 td->cancel_status = TD_CLEARING_CACHE;
1051 cached_td = td;
1052 break;
1053 }
1054 } else {
1055 td_to_noop(xhci, ring, td, false);
1056 td->cancel_status = TD_CLEARED;
1057 }
1058 }
1059
1060 /* If there's no need to move the dequeue pointer then we're done */
1061 if (!cached_td)
1062 return 0;
1063
1064 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1065 cached_td->urb->stream_id,
1066 cached_td);
1067 if (err) {
1068 /* Failed to move past cached td, just set cached TDs to no-op */
1069 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1070 /*
1071 * Deferred TDs need to have the deq pointer set after the above command
1072 * completes, so if that failed we just give up on all of them (and
1073 * complain loudly since this could cause issues due to caching).
1074 */
1075 if (td->cancel_status != TD_CLEARING_CACHE &&
1076 td->cancel_status != TD_CLEARING_CACHE_DEFERRED)
1077 continue;
1078 xhci_warn(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1079 td->urb);
1080 td_to_noop(xhci, ring, td, false);
1081 td->cancel_status = TD_CLEARED;
1082 }
1083 }
1084 return 0;
1085 }
1086
1087 /*
1088 * Returns the TD the endpoint ring halted on.
1089 * Only call for non-running rings without streams.
1090 */
find_halted_td(struct xhci_virt_ep * ep)1091 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1092 {
1093 struct xhci_td *td;
1094 u64 hw_deq;
1095
1096 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1097 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1098 hw_deq &= ~0xf;
1099 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1100 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1101 td->last_trb, hw_deq, false))
1102 return td;
1103 }
1104 return NULL;
1105 }
1106
1107 /*
1108 * When we get a command completion for a Stop Endpoint Command, we need to
1109 * unlink any cancelled TDs from the ring. There are two ways to do that:
1110 *
1111 * 1. If the HW was in the middle of processing the TD that needs to be
1112 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1113 * in the TD with a Set Dequeue Pointer Command.
1114 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1115 * bit cleared) so that the HW will skip over them.
1116 */
xhci_handle_cmd_stop_ep(struct xhci_hcd * xhci,int slot_id,union xhci_trb * trb,u32 comp_code)1117 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1118 union xhci_trb *trb, u32 comp_code)
1119 {
1120 unsigned int ep_index;
1121 struct xhci_virt_ep *ep;
1122 struct xhci_ep_ctx *ep_ctx;
1123 struct xhci_td *td = NULL;
1124 enum xhci_ep_reset_type reset_type;
1125 struct xhci_command *command;
1126 int err;
1127
1128 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1129 if (!xhci->devs[slot_id])
1130 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1131 slot_id);
1132 return;
1133 }
1134
1135 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1136 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1137 if (!ep)
1138 return;
1139
1140 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1141
1142 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1143
1144 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1145 /*
1146 * If stop endpoint command raced with a halting endpoint we need to
1147 * reset the host side endpoint first.
1148 * If the TD we halted on isn't cancelled the TD should be given back
1149 * with a proper error code, and the ring dequeue moved past the TD.
1150 * If streams case we can't find hw_deq, or the TD we halted on so do a
1151 * soft reset.
1152 *
1153 * Proper error code is unknown here, it would be -EPIPE if device side
1154 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1155 * We use -EPROTO, if device is stalled it should return a stall error on
1156 * next transfer, which then will return -EPIPE, and device side stall is
1157 * noted and cleared by class driver.
1158 */
1159 switch (GET_EP_CTX_STATE(ep_ctx)) {
1160 case EP_STATE_HALTED:
1161 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1162 if (ep->ep_state & EP_HAS_STREAMS) {
1163 reset_type = EP_SOFT_RESET;
1164 } else {
1165 reset_type = EP_HARD_RESET;
1166 td = find_halted_td(ep);
1167 if (td)
1168 td->status = -EPROTO;
1169 }
1170 /* reset ep, reset handler cleans up cancelled tds */
1171 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1172 if (err)
1173 break;
1174 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1175 return;
1176 case EP_STATE_RUNNING:
1177 /* Race, HW handled stop ep cmd before ep was running */
1178 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1179
1180 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1181 if (!command) {
1182 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1183 return;
1184 }
1185 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1186 xhci_ring_cmd_db(xhci);
1187
1188 return;
1189 default:
1190 break;
1191 }
1192 }
1193
1194 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1195 xhci_invalidate_cancelled_tds(ep);
1196 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1197
1198 /* Otherwise ring the doorbell(s) to restart queued transfers */
1199 xhci_giveback_invalidated_tds(ep);
1200 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1201 }
1202
xhci_kill_ring_urbs(struct xhci_hcd * xhci,struct xhci_ring * ring)1203 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1204 {
1205 struct xhci_td *cur_td;
1206 struct xhci_td *tmp;
1207
1208 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1209 list_del_init(&cur_td->td_list);
1210
1211 if (!list_empty(&cur_td->cancelled_td_list))
1212 list_del_init(&cur_td->cancelled_td_list);
1213
1214 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1215
1216 inc_td_cnt(cur_td->urb);
1217 if (last_td_in_urb(cur_td))
1218 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1219 }
1220 }
1221
xhci_kill_endpoint_urbs(struct xhci_hcd * xhci,int slot_id,int ep_index)1222 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1223 int slot_id, int ep_index)
1224 {
1225 struct xhci_td *cur_td;
1226 struct xhci_td *tmp;
1227 struct xhci_virt_ep *ep;
1228 struct xhci_ring *ring;
1229
1230 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1231 if (!ep)
1232 return;
1233
1234 if ((ep->ep_state & EP_HAS_STREAMS) ||
1235 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1236 int stream_id;
1237
1238 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1239 stream_id++) {
1240 ring = ep->stream_info->stream_rings[stream_id];
1241 if (!ring)
1242 continue;
1243
1244 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1245 "Killing URBs for slot ID %u, ep index %u, stream %u",
1246 slot_id, ep_index, stream_id);
1247 xhci_kill_ring_urbs(xhci, ring);
1248 }
1249 } else {
1250 ring = ep->ring;
1251 if (!ring)
1252 return;
1253 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1254 "Killing URBs for slot ID %u, ep index %u",
1255 slot_id, ep_index);
1256 xhci_kill_ring_urbs(xhci, ring);
1257 }
1258
1259 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1260 cancelled_td_list) {
1261 list_del_init(&cur_td->cancelled_td_list);
1262 inc_td_cnt(cur_td->urb);
1263
1264 if (last_td_in_urb(cur_td))
1265 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1266 }
1267 }
1268
1269 /*
1270 * host controller died, register read returns 0xffffffff
1271 * Complete pending commands, mark them ABORTED.
1272 * URBs need to be given back as usb core might be waiting with device locks
1273 * held for the URBs to finish during device disconnect, blocking host remove.
1274 *
1275 * Call with xhci->lock held.
1276 * lock is relased and re-acquired while giving back urb.
1277 */
xhci_hc_died(struct xhci_hcd * xhci)1278 void xhci_hc_died(struct xhci_hcd *xhci)
1279 {
1280 int i, j;
1281
1282 if (xhci->xhc_state & XHCI_STATE_DYING)
1283 return;
1284
1285 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1286 xhci->xhc_state |= XHCI_STATE_DYING;
1287
1288 xhci_cleanup_command_queue(xhci);
1289
1290 /* return any pending urbs, remove may be waiting for them */
1291 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1292 if (!xhci->devs[i])
1293 continue;
1294 for (j = 0; j < 31; j++)
1295 xhci_kill_endpoint_urbs(xhci, i, j);
1296 }
1297
1298 /* inform usb core hc died if PCI remove isn't already handling it */
1299 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1300 usb_hc_died(xhci_to_hcd(xhci));
1301 }
1302
update_ring_for_set_deq_completion(struct xhci_hcd * xhci,struct xhci_virt_device * dev,struct xhci_ring * ep_ring,unsigned int ep_index)1303 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1304 struct xhci_virt_device *dev,
1305 struct xhci_ring *ep_ring,
1306 unsigned int ep_index)
1307 {
1308 union xhci_trb *dequeue_temp;
1309
1310 dequeue_temp = ep_ring->dequeue;
1311
1312 /* If we get two back-to-back stalls, and the first stalled transfer
1313 * ends just before a link TRB, the dequeue pointer will be left on
1314 * the link TRB by the code in the while loop. So we have to update
1315 * the dequeue pointer one segment further, or we'll jump off
1316 * the segment into la-la-land.
1317 */
1318 if (trb_is_link(ep_ring->dequeue)) {
1319 ep_ring->deq_seg = ep_ring->deq_seg->next;
1320 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1321 }
1322
1323 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1324 /* We have more usable TRBs */
1325 ep_ring->dequeue++;
1326 if (trb_is_link(ep_ring->dequeue)) {
1327 if (ep_ring->dequeue ==
1328 dev->eps[ep_index].queued_deq_ptr)
1329 break;
1330 ep_ring->deq_seg = ep_ring->deq_seg->next;
1331 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1332 }
1333 if (ep_ring->dequeue == dequeue_temp) {
1334 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1335 break;
1336 }
1337 }
1338 }
1339
1340 /*
1341 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1342 * we need to clear the set deq pending flag in the endpoint ring state, so that
1343 * the TD queueing code can ring the doorbell again. We also need to ring the
1344 * endpoint doorbell to restart the ring, but only if there aren't more
1345 * cancellations pending.
1346 */
xhci_handle_cmd_set_deq(struct xhci_hcd * xhci,int slot_id,union xhci_trb * trb,u32 cmd_comp_code)1347 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1348 union xhci_trb *trb, u32 cmd_comp_code)
1349 {
1350 unsigned int ep_index;
1351 unsigned int stream_id;
1352 struct xhci_ring *ep_ring;
1353 struct xhci_virt_ep *ep;
1354 struct xhci_ep_ctx *ep_ctx;
1355 struct xhci_slot_ctx *slot_ctx;
1356 struct xhci_td *td, *tmp_td;
1357 bool deferred = false;
1358
1359 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1360 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1361 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1362 if (!ep)
1363 return;
1364
1365 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1366 if (!ep_ring) {
1367 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1368 stream_id);
1369 /* XXX: Harmless??? */
1370 goto cleanup;
1371 }
1372
1373 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1374 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1375 trace_xhci_handle_cmd_set_deq(slot_ctx);
1376 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1377
1378 if (cmd_comp_code != COMP_SUCCESS) {
1379 unsigned int ep_state;
1380 unsigned int slot_state;
1381
1382 switch (cmd_comp_code) {
1383 case COMP_TRB_ERROR:
1384 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1385 break;
1386 case COMP_CONTEXT_STATE_ERROR:
1387 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1388 ep_state = GET_EP_CTX_STATE(ep_ctx);
1389 slot_state = le32_to_cpu(slot_ctx->dev_state);
1390 slot_state = GET_SLOT_STATE(slot_state);
1391 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1392 "Slot state = %u, EP state = %u",
1393 slot_state, ep_state);
1394 break;
1395 case COMP_SLOT_NOT_ENABLED_ERROR:
1396 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1397 slot_id);
1398 break;
1399 default:
1400 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1401 cmd_comp_code);
1402 break;
1403 }
1404 /* OK what do we do now? The endpoint state is hosed, and we
1405 * should never get to this point if the synchronization between
1406 * queueing, and endpoint state are correct. This might happen
1407 * if the device gets disconnected after we've finished
1408 * cancelling URBs, which might not be an error...
1409 */
1410 } else {
1411 u64 deq;
1412 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1413 if (ep->ep_state & EP_HAS_STREAMS) {
1414 struct xhci_stream_ctx *ctx =
1415 &ep->stream_info->stream_ctx_array[stream_id];
1416 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1417 } else {
1418 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1419 }
1420 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1421 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1422 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1423 ep->queued_deq_ptr) == deq) {
1424 /* Update the ring's dequeue segment and dequeue pointer
1425 * to reflect the new position.
1426 */
1427 update_ring_for_set_deq_completion(xhci, ep->vdev,
1428 ep_ring, ep_index);
1429 } else {
1430 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1431 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1432 ep->queued_deq_seg, ep->queued_deq_ptr);
1433 }
1434 }
1435 /* HW cached TDs cleared from cache, give them back */
1436 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1437 cancelled_td_list) {
1438 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1439 if (td->cancel_status == TD_CLEARING_CACHE) {
1440 td->cancel_status = TD_CLEARED;
1441 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1442 __func__, td->urb);
1443 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1444 } else if (td->cancel_status == TD_CLEARING_CACHE_DEFERRED) {
1445 deferred = true;
1446 } else {
1447 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1448 __func__, td->urb, td->cancel_status);
1449 }
1450 }
1451 cleanup:
1452 ep->ep_state &= ~SET_DEQ_PENDING;
1453 ep->queued_deq_seg = NULL;
1454 ep->queued_deq_ptr = NULL;
1455
1456 if (deferred) {
1457 /* We have more streams to clear */
1458 xhci_dbg(ep->xhci, "%s: Pending TDs to clear, continuing with invalidation\n",
1459 __func__);
1460 xhci_invalidate_cancelled_tds(ep);
1461 } else {
1462 /* Restart any rings with pending URBs */
1463 xhci_dbg(ep->xhci, "%s: All TDs cleared, ring doorbell\n", __func__);
1464 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1465 }
1466 }
1467
xhci_handle_cmd_reset_ep(struct xhci_hcd * xhci,int slot_id,union xhci_trb * trb,u32 cmd_comp_code)1468 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1469 union xhci_trb *trb, u32 cmd_comp_code)
1470 {
1471 struct xhci_virt_ep *ep;
1472 struct xhci_ep_ctx *ep_ctx;
1473 unsigned int ep_index;
1474
1475 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1476 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1477 if (!ep)
1478 return;
1479
1480 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1481 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1482
1483 /* This command will only fail if the endpoint wasn't halted,
1484 * but we don't care.
1485 */
1486 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1487 "Ignoring reset ep completion code of %u", cmd_comp_code);
1488
1489 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1490 xhci_invalidate_cancelled_tds(ep);
1491
1492 /* Clear our internal halted state */
1493 ep->ep_state &= ~EP_HALTED;
1494
1495 xhci_giveback_invalidated_tds(ep);
1496
1497 /* if this was a soft reset, then restart */
1498 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1499 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1500 }
1501
xhci_handle_cmd_enable_slot(struct xhci_hcd * xhci,int slot_id,struct xhci_command * command,u32 cmd_comp_code)1502 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1503 struct xhci_command *command, u32 cmd_comp_code)
1504 {
1505 if (cmd_comp_code == COMP_SUCCESS)
1506 command->slot_id = slot_id;
1507 else
1508 command->slot_id = 0;
1509 }
1510
xhci_handle_cmd_disable_slot(struct xhci_hcd * xhci,int slot_id)1511 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1512 {
1513 struct xhci_virt_device *virt_dev;
1514 struct xhci_slot_ctx *slot_ctx;
1515
1516 virt_dev = xhci->devs[slot_id];
1517 if (!virt_dev)
1518 return;
1519
1520 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1521 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1522
1523 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1524 /* Delete default control endpoint resources */
1525 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1526 }
1527
xhci_handle_cmd_config_ep(struct xhci_hcd * xhci,int slot_id,u32 cmd_comp_code)1528 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1529 u32 cmd_comp_code)
1530 {
1531 struct xhci_virt_device *virt_dev;
1532 struct xhci_input_control_ctx *ctrl_ctx;
1533 struct xhci_ep_ctx *ep_ctx;
1534 unsigned int ep_index;
1535 u32 add_flags;
1536
1537 /*
1538 * Configure endpoint commands can come from the USB core configuration
1539 * or alt setting changes, or when streams were being configured.
1540 */
1541
1542 virt_dev = xhci->devs[slot_id];
1543 if (!virt_dev)
1544 return;
1545 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1546 if (!ctrl_ctx) {
1547 xhci_warn(xhci, "Could not get input context, bad type.\n");
1548 return;
1549 }
1550
1551 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1552
1553 /* Input ctx add_flags are the endpoint index plus one */
1554 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1555
1556 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1557 trace_xhci_handle_cmd_config_ep(ep_ctx);
1558
1559 return;
1560 }
1561
xhci_handle_cmd_addr_dev(struct xhci_hcd * xhci,int slot_id)1562 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1563 {
1564 struct xhci_virt_device *vdev;
1565 struct xhci_slot_ctx *slot_ctx;
1566
1567 vdev = xhci->devs[slot_id];
1568 if (!vdev)
1569 return;
1570 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1571 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1572 }
1573
xhci_handle_cmd_reset_dev(struct xhci_hcd * xhci,int slot_id)1574 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1575 {
1576 struct xhci_virt_device *vdev;
1577 struct xhci_slot_ctx *slot_ctx;
1578
1579 vdev = xhci->devs[slot_id];
1580 if (!vdev) {
1581 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1582 slot_id);
1583 return;
1584 }
1585 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1586 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1587
1588 xhci_dbg(xhci, "Completed reset device command.\n");
1589 }
1590
xhci_handle_cmd_nec_get_fw(struct xhci_hcd * xhci,struct xhci_event_cmd * event)1591 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1592 struct xhci_event_cmd *event)
1593 {
1594 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1595 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1596 return;
1597 }
1598 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1599 "NEC firmware version %2x.%02x",
1600 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1601 NEC_FW_MINOR(le32_to_cpu(event->status)));
1602 }
1603
xhci_complete_del_and_free_cmd(struct xhci_command * cmd,u32 status)1604 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1605 {
1606 list_del(&cmd->cmd_list);
1607
1608 if (cmd->completion) {
1609 cmd->status = status;
1610 complete(cmd->completion);
1611 } else {
1612 kfree(cmd);
1613 }
1614 }
1615
xhci_cleanup_command_queue(struct xhci_hcd * xhci)1616 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1617 {
1618 struct xhci_command *cur_cmd, *tmp_cmd;
1619 xhci->current_cmd = NULL;
1620 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1621 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1622 }
1623
xhci_handle_command_timeout(struct work_struct * work)1624 void xhci_handle_command_timeout(struct work_struct *work)
1625 {
1626 struct xhci_hcd *xhci;
1627 unsigned long flags;
1628 char str[XHCI_MSG_MAX];
1629 u64 hw_ring_state;
1630 u32 cmd_field3;
1631 u32 usbsts;
1632
1633 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1634
1635 spin_lock_irqsave(&xhci->lock, flags);
1636
1637 /*
1638 * If timeout work is pending, or current_cmd is NULL, it means we
1639 * raced with command completion. Command is handled so just return.
1640 */
1641 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1642 spin_unlock_irqrestore(&xhci->lock, flags);
1643 return;
1644 }
1645
1646 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1647 usbsts = readl(&xhci->op_regs->status);
1648 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1649
1650 /* Bail out and tear down xhci if a stop endpoint command failed */
1651 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1652 struct xhci_virt_ep *ep;
1653
1654 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1655
1656 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1657 TRB_TO_EP_INDEX(cmd_field3));
1658 if (ep)
1659 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1660
1661 xhci_halt(xhci);
1662 xhci_hc_died(xhci);
1663 goto time_out_completed;
1664 }
1665
1666 /* mark this command to be cancelled */
1667 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1668
1669 /* Make sure command ring is running before aborting it */
1670 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1671 if (hw_ring_state == ~(u64)0) {
1672 xhci_hc_died(xhci);
1673 goto time_out_completed;
1674 }
1675
1676 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1677 (hw_ring_state & CMD_RING_RUNNING)) {
1678 /* Prevent new doorbell, and start command abort */
1679 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1680 xhci_dbg(xhci, "Command timeout\n");
1681 xhci_abort_cmd_ring(xhci, flags);
1682 goto time_out_completed;
1683 }
1684
1685 /* host removed. Bail out */
1686 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1687 xhci_dbg(xhci, "host removed, ring start fail?\n");
1688 xhci_cleanup_command_queue(xhci);
1689
1690 goto time_out_completed;
1691 }
1692
1693 /* command timeout on stopped ring, ring can't be aborted */
1694 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1695 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1696
1697 time_out_completed:
1698 spin_unlock_irqrestore(&xhci->lock, flags);
1699 return;
1700 }
1701
handle_cmd_completion(struct xhci_hcd * xhci,struct xhci_event_cmd * event)1702 static void handle_cmd_completion(struct xhci_hcd *xhci,
1703 struct xhci_event_cmd *event)
1704 {
1705 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1706 u64 cmd_dma;
1707 dma_addr_t cmd_dequeue_dma;
1708 u32 cmd_comp_code;
1709 union xhci_trb *cmd_trb;
1710 struct xhci_command *cmd;
1711 u32 cmd_type;
1712
1713 if (slot_id >= MAX_HC_SLOTS) {
1714 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1715 return;
1716 }
1717
1718 cmd_dma = le64_to_cpu(event->cmd_trb);
1719 cmd_trb = xhci->cmd_ring->dequeue;
1720
1721 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1722
1723 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1724 cmd_trb);
1725 /*
1726 * Check whether the completion event is for our internal kept
1727 * command.
1728 */
1729 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1730 xhci_warn(xhci,
1731 "ERROR mismatched command completion event\n");
1732 return;
1733 }
1734
1735 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1736
1737 cancel_delayed_work(&xhci->cmd_timer);
1738
1739 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1740
1741 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1742 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1743 complete_all(&xhci->cmd_ring_stop_completion);
1744 return;
1745 }
1746
1747 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1748 xhci_err(xhci,
1749 "Command completion event does not match command\n");
1750 return;
1751 }
1752
1753 /*
1754 * Host aborted the command ring, check if the current command was
1755 * supposed to be aborted, otherwise continue normally.
1756 * The command ring is stopped now, but the xHC will issue a Command
1757 * Ring Stopped event which will cause us to restart it.
1758 */
1759 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1760 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1761 if (cmd->status == COMP_COMMAND_ABORTED) {
1762 if (xhci->current_cmd == cmd)
1763 xhci->current_cmd = NULL;
1764 goto event_handled;
1765 }
1766 }
1767
1768 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1769 switch (cmd_type) {
1770 case TRB_ENABLE_SLOT:
1771 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1772 break;
1773 case TRB_DISABLE_SLOT:
1774 xhci_handle_cmd_disable_slot(xhci, slot_id);
1775 break;
1776 case TRB_CONFIG_EP:
1777 if (!cmd->completion)
1778 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1779 break;
1780 case TRB_EVAL_CONTEXT:
1781 break;
1782 case TRB_ADDR_DEV:
1783 xhci_handle_cmd_addr_dev(xhci, slot_id);
1784 break;
1785 case TRB_STOP_RING:
1786 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1787 le32_to_cpu(cmd_trb->generic.field[3])));
1788 if (!cmd->completion)
1789 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1790 cmd_comp_code);
1791 break;
1792 case TRB_SET_DEQ:
1793 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1794 le32_to_cpu(cmd_trb->generic.field[3])));
1795 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1796 break;
1797 case TRB_CMD_NOOP:
1798 /* Is this an aborted command turned to NO-OP? */
1799 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1800 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1801 break;
1802 case TRB_RESET_EP:
1803 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1804 le32_to_cpu(cmd_trb->generic.field[3])));
1805 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1806 break;
1807 case TRB_RESET_DEV:
1808 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1809 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1810 */
1811 slot_id = TRB_TO_SLOT_ID(
1812 le32_to_cpu(cmd_trb->generic.field[3]));
1813 xhci_handle_cmd_reset_dev(xhci, slot_id);
1814 break;
1815 case TRB_NEC_GET_FW:
1816 xhci_handle_cmd_nec_get_fw(xhci, event);
1817 break;
1818 default:
1819 /* Skip over unknown commands on the event ring */
1820 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1821 break;
1822 }
1823
1824 /* restart timer if this wasn't the last command */
1825 if (!list_is_singular(&xhci->cmd_list)) {
1826 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1827 struct xhci_command, cmd_list);
1828 xhci_mod_cmd_timer(xhci);
1829 } else if (xhci->current_cmd == cmd) {
1830 xhci->current_cmd = NULL;
1831 }
1832
1833 event_handled:
1834 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1835
1836 inc_deq(xhci, xhci->cmd_ring);
1837 }
1838
handle_vendor_event(struct xhci_hcd * xhci,union xhci_trb * event,u32 trb_type)1839 static void handle_vendor_event(struct xhci_hcd *xhci,
1840 union xhci_trb *event, u32 trb_type)
1841 {
1842 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1843 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1844 handle_cmd_completion(xhci, &event->event_cmd);
1845 }
1846
handle_device_notification(struct xhci_hcd * xhci,union xhci_trb * event)1847 static void handle_device_notification(struct xhci_hcd *xhci,
1848 union xhci_trb *event)
1849 {
1850 u32 slot_id;
1851 struct usb_device *udev;
1852
1853 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1854 if (!xhci->devs[slot_id]) {
1855 xhci_warn(xhci, "Device Notification event for "
1856 "unused slot %u\n", slot_id);
1857 return;
1858 }
1859
1860 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1861 slot_id);
1862 udev = xhci->devs[slot_id]->udev;
1863 if (udev && udev->parent)
1864 usb_wakeup_notification(udev->parent, udev->portnum);
1865 }
1866
1867 /*
1868 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1869 * Controller.
1870 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1871 * If a connection to a USB 1 device is followed by another connection
1872 * to a USB 2 device.
1873 *
1874 * Reset the PHY after the USB device is disconnected if device speed
1875 * is less than HCD_USB3.
1876 * Retry the reset sequence max of 4 times checking the PLL lock status.
1877 *
1878 */
xhci_cavium_reset_phy_quirk(struct xhci_hcd * xhci)1879 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1880 {
1881 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1882 u32 pll_lock_check;
1883 u32 retry_count = 4;
1884
1885 do {
1886 /* Assert PHY reset */
1887 writel(0x6F, hcd->regs + 0x1048);
1888 udelay(10);
1889 /* De-assert the PHY reset */
1890 writel(0x7F, hcd->regs + 0x1048);
1891 udelay(200);
1892 pll_lock_check = readl(hcd->regs + 0x1070);
1893 } while (!(pll_lock_check & 0x1) && --retry_count);
1894 }
1895
handle_port_status(struct xhci_hcd * xhci,struct xhci_interrupter * ir,union xhci_trb * event)1896 static void handle_port_status(struct xhci_hcd *xhci,
1897 struct xhci_interrupter *ir,
1898 union xhci_trb *event)
1899 {
1900 struct usb_hcd *hcd;
1901 u32 port_id;
1902 u32 portsc, cmd_reg;
1903 int max_ports;
1904 int slot_id;
1905 unsigned int hcd_portnum;
1906 struct xhci_bus_state *bus_state;
1907 bool bogus_port_status = false;
1908 struct xhci_port *port;
1909
1910 /* Port status change events always have a successful completion code */
1911 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1912 xhci_warn(xhci,
1913 "WARN: xHC returned failed port status event\n");
1914
1915 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1916 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1917
1918 if ((port_id <= 0) || (port_id > max_ports)) {
1919 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1920 port_id);
1921 inc_deq(xhci, ir->event_ring);
1922 return;
1923 }
1924
1925 port = &xhci->hw_ports[port_id - 1];
1926 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1927 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1928 port_id);
1929 bogus_port_status = true;
1930 goto cleanup;
1931 }
1932
1933 /* We might get interrupts after shared_hcd is removed */
1934 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1935 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1936 bogus_port_status = true;
1937 goto cleanup;
1938 }
1939
1940 hcd = port->rhub->hcd;
1941 bus_state = &port->rhub->bus_state;
1942 hcd_portnum = port->hcd_portnum;
1943 portsc = readl(port->addr);
1944
1945 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1946 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1947
1948 trace_xhci_handle_port_status(hcd_portnum, portsc);
1949
1950 if (hcd->state == HC_STATE_SUSPENDED) {
1951 xhci_dbg(xhci, "resume root hub\n");
1952 usb_hcd_resume_root_hub(hcd);
1953 }
1954
1955 if (hcd->speed >= HCD_USB3 &&
1956 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1957 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1958 if (slot_id && xhci->devs[slot_id])
1959 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1960 }
1961
1962 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1963 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1964
1965 cmd_reg = readl(&xhci->op_regs->command);
1966 if (!(cmd_reg & CMD_RUN)) {
1967 xhci_warn(xhci, "xHC is not running.\n");
1968 goto cleanup;
1969 }
1970
1971 if (DEV_SUPERSPEED_ANY(portsc)) {
1972 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1973 /* Set a flag to say the port signaled remote wakeup,
1974 * so we can tell the difference between the end of
1975 * device and host initiated resume.
1976 */
1977 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1978 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1979 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1980 xhci_set_link_state(xhci, port, XDEV_U0);
1981 /* Need to wait until the next link state change
1982 * indicates the device is actually in U0.
1983 */
1984 bogus_port_status = true;
1985 goto cleanup;
1986 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1987 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1988 port->resume_timestamp = jiffies +
1989 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1990 set_bit(hcd_portnum, &bus_state->resuming_ports);
1991 /* Do the rest in GetPortStatus after resume time delay.
1992 * Avoid polling roothub status before that so that a
1993 * usb device auto-resume latency around ~40ms.
1994 */
1995 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1996 mod_timer(&hcd->rh_timer,
1997 port->resume_timestamp);
1998 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1999 bogus_port_status = true;
2000 }
2001 }
2002
2003 if ((portsc & PORT_PLC) &&
2004 DEV_SUPERSPEED_ANY(portsc) &&
2005 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
2006 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
2007 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
2008 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
2009 complete(&port->u3exit_done);
2010 /* We've just brought the device into U0/1/2 through either the
2011 * Resume state after a device remote wakeup, or through the
2012 * U3Exit state after a host-initiated resume. If it's a device
2013 * initiated remote wake, don't pass up the link state change,
2014 * so the roothub behavior is consistent with external
2015 * USB 3.0 hub behavior.
2016 */
2017 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
2018 if (slot_id && xhci->devs[slot_id])
2019 xhci_ring_device(xhci, slot_id);
2020 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
2021 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2022 usb_wakeup_notification(hcd->self.root_hub,
2023 hcd_portnum + 1);
2024 bogus_port_status = true;
2025 goto cleanup;
2026 }
2027 }
2028
2029 /*
2030 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
2031 * RExit to a disconnect state). If so, let the driver know it's
2032 * out of the RExit state.
2033 */
2034 if (hcd->speed < HCD_USB3 && port->rexit_active) {
2035 complete(&port->rexit_done);
2036 port->rexit_active = false;
2037 bogus_port_status = true;
2038 goto cleanup;
2039 }
2040
2041 if (hcd->speed < HCD_USB3) {
2042 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2043 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
2044 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
2045 xhci_cavium_reset_phy_quirk(xhci);
2046 }
2047
2048 cleanup:
2049 /* Update event ring dequeue pointer before dropping the lock */
2050 inc_deq(xhci, ir->event_ring);
2051
2052 /* Don't make the USB core poll the roothub if we got a bad port status
2053 * change event. Besides, at that point we can't tell which roothub
2054 * (USB 2.0 or USB 3.0) to kick.
2055 */
2056 if (bogus_port_status)
2057 return;
2058
2059 /*
2060 * xHCI port-status-change events occur when the "or" of all the
2061 * status-change bits in the portsc register changes from 0 to 1.
2062 * New status changes won't cause an event if any other change
2063 * bits are still set. When an event occurs, switch over to
2064 * polling to avoid losing status changes.
2065 */
2066 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2067 __func__, hcd->self.busnum);
2068 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2069 spin_unlock(&xhci->lock);
2070 /* Pass this up to the core */
2071 usb_hcd_poll_rh_status(hcd);
2072 spin_lock(&xhci->lock);
2073 }
2074
2075 /*
2076 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2077 * at end_trb, which may be in another segment. If the suspect DMA address is a
2078 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2079 * returns 0.
2080 */
trb_in_td(struct xhci_hcd * xhci,struct xhci_segment * start_seg,union xhci_trb * start_trb,union xhci_trb * end_trb,dma_addr_t suspect_dma,bool debug)2081 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2082 struct xhci_segment *start_seg,
2083 union xhci_trb *start_trb,
2084 union xhci_trb *end_trb,
2085 dma_addr_t suspect_dma,
2086 bool debug)
2087 {
2088 dma_addr_t start_dma;
2089 dma_addr_t end_seg_dma;
2090 dma_addr_t end_trb_dma;
2091 struct xhci_segment *cur_seg;
2092
2093 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2094 cur_seg = start_seg;
2095
2096 do {
2097 if (start_dma == 0)
2098 return NULL;
2099 /* We may get an event for a Link TRB in the middle of a TD */
2100 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2101 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2102 /* If the end TRB isn't in this segment, this is set to 0 */
2103 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2104
2105 if (debug)
2106 xhci_warn(xhci,
2107 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2108 (unsigned long long)suspect_dma,
2109 (unsigned long long)start_dma,
2110 (unsigned long long)end_trb_dma,
2111 (unsigned long long)cur_seg->dma,
2112 (unsigned long long)end_seg_dma);
2113
2114 if (end_trb_dma > 0) {
2115 /* The end TRB is in this segment, so suspect should be here */
2116 if (start_dma <= end_trb_dma) {
2117 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2118 return cur_seg;
2119 } else {
2120 /* Case for one segment with
2121 * a TD wrapped around to the top
2122 */
2123 if ((suspect_dma >= start_dma &&
2124 suspect_dma <= end_seg_dma) ||
2125 (suspect_dma >= cur_seg->dma &&
2126 suspect_dma <= end_trb_dma))
2127 return cur_seg;
2128 }
2129 return NULL;
2130 } else {
2131 /* Might still be somewhere in this segment */
2132 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2133 return cur_seg;
2134 }
2135 cur_seg = cur_seg->next;
2136 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2137 } while (cur_seg != start_seg);
2138
2139 return NULL;
2140 }
2141
xhci_clear_hub_tt_buffer(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_virt_ep * ep)2142 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2143 struct xhci_virt_ep *ep)
2144 {
2145 /*
2146 * As part of low/full-speed endpoint-halt processing
2147 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2148 */
2149 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2150 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2151 !(ep->ep_state & EP_CLEARING_TT)) {
2152 ep->ep_state |= EP_CLEARING_TT;
2153 td->urb->ep->hcpriv = td->urb->dev;
2154 if (usb_hub_clear_tt_buffer(td->urb))
2155 ep->ep_state &= ~EP_CLEARING_TT;
2156 }
2157 }
2158
2159 /* Check if an error has halted the endpoint ring. The class driver will
2160 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2161 * However, a babble and other errors also halt the endpoint ring, and the class
2162 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2163 * Ring Dequeue Pointer command manually.
2164 */
xhci_requires_manual_halt_cleanup(struct xhci_hcd * xhci,struct xhci_ep_ctx * ep_ctx,unsigned int trb_comp_code)2165 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2166 struct xhci_ep_ctx *ep_ctx,
2167 unsigned int trb_comp_code)
2168 {
2169 /* TRB completion codes that may require a manual halt cleanup */
2170 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2171 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2172 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2173 /* The 0.95 spec says a babbling control endpoint
2174 * is not halted. The 0.96 spec says it is. Some HW
2175 * claims to be 0.95 compliant, but it halts the control
2176 * endpoint anyway. Check if a babble halted the
2177 * endpoint.
2178 */
2179 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2180 return 1;
2181
2182 return 0;
2183 }
2184
xhci_is_vendor_info_code(struct xhci_hcd * xhci,unsigned int trb_comp_code)2185 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2186 {
2187 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2188 /* Vendor defined "informational" completion code,
2189 * treat as not-an-error.
2190 */
2191 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2192 trb_comp_code);
2193 xhci_dbg(xhci, "Treating code as success.\n");
2194 return 1;
2195 }
2196 return 0;
2197 }
2198
finish_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,u32 trb_comp_code)2199 static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2200 struct xhci_ring *ep_ring, struct xhci_td *td,
2201 u32 trb_comp_code)
2202 {
2203 struct xhci_ep_ctx *ep_ctx;
2204
2205 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2206
2207 switch (trb_comp_code) {
2208 case COMP_STOPPED_LENGTH_INVALID:
2209 case COMP_STOPPED_SHORT_PACKET:
2210 case COMP_STOPPED:
2211 /*
2212 * The "Stop Endpoint" completion will take care of any
2213 * stopped TDs. A stopped TD may be restarted, so don't update
2214 * the ring dequeue pointer or take this TD off any lists yet.
2215 */
2216 return 0;
2217 case COMP_USB_TRANSACTION_ERROR:
2218 case COMP_BABBLE_DETECTED_ERROR:
2219 case COMP_SPLIT_TRANSACTION_ERROR:
2220 /*
2221 * If endpoint context state is not halted we might be
2222 * racing with a reset endpoint command issued by a unsuccessful
2223 * stop endpoint completion (context error). In that case the
2224 * td should be on the cancelled list, and EP_HALTED flag set.
2225 *
2226 * Or then it's not halted due to the 0.95 spec stating that a
2227 * babbling control endpoint should not halt. The 0.96 spec
2228 * again says it should. Some HW claims to be 0.95 compliant,
2229 * but it halts the control endpoint anyway.
2230 */
2231 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2232 /*
2233 * If EP_HALTED is set and TD is on the cancelled list
2234 * the TD and dequeue pointer will be handled by reset
2235 * ep command completion
2236 */
2237 if ((ep->ep_state & EP_HALTED) &&
2238 !list_empty(&td->cancelled_td_list)) {
2239 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2240 (unsigned long long)xhci_trb_virt_to_dma(
2241 td->start_seg, td->first_trb));
2242 return 0;
2243 }
2244 /* endpoint not halted, don't reset it */
2245 break;
2246 }
2247 /* Almost same procedure as for STALL_ERROR below */
2248 xhci_clear_hub_tt_buffer(xhci, td, ep);
2249 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2250 return 0;
2251 case COMP_STALL_ERROR:
2252 /*
2253 * xhci internal endpoint state will go to a "halt" state for
2254 * any stall, including default control pipe protocol stall.
2255 * To clear the host side halt we need to issue a reset endpoint
2256 * command, followed by a set dequeue command to move past the
2257 * TD.
2258 * Class drivers clear the device side halt from a functional
2259 * stall later. Hub TT buffer should only be cleared for FS/LS
2260 * devices behind HS hubs for functional stalls.
2261 */
2262 if (ep->ep_index != 0)
2263 xhci_clear_hub_tt_buffer(xhci, td, ep);
2264
2265 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2266
2267 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2268 default:
2269 break;
2270 }
2271
2272 /* Update ring dequeue pointer */
2273 ep_ring->dequeue = td->last_trb;
2274 ep_ring->deq_seg = td->last_trb_seg;
2275 inc_deq(xhci, ep_ring);
2276
2277 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2278 }
2279
2280 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
sum_trb_lengths(struct xhci_hcd * xhci,struct xhci_ring * ring,union xhci_trb * stop_trb)2281 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2282 union xhci_trb *stop_trb)
2283 {
2284 u32 sum;
2285 union xhci_trb *trb = ring->dequeue;
2286 struct xhci_segment *seg = ring->deq_seg;
2287
2288 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2289 if (!trb_is_noop(trb) && !trb_is_link(trb))
2290 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2291 }
2292 return sum;
2293 }
2294
2295 /*
2296 * Process control tds, update urb status and actual_length.
2297 */
process_ctrl_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,union xhci_trb * ep_trb,struct xhci_transfer_event * event)2298 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2299 struct xhci_ring *ep_ring, struct xhci_td *td,
2300 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2301 {
2302 struct xhci_ep_ctx *ep_ctx;
2303 u32 trb_comp_code;
2304 u32 remaining, requested;
2305 u32 trb_type;
2306
2307 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2308 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2309 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2310 requested = td->urb->transfer_buffer_length;
2311 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2312
2313 switch (trb_comp_code) {
2314 case COMP_SUCCESS:
2315 if (trb_type != TRB_STATUS) {
2316 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2317 (trb_type == TRB_DATA) ? "data" : "setup");
2318 td->status = -ESHUTDOWN;
2319 break;
2320 }
2321 td->status = 0;
2322 break;
2323 case COMP_SHORT_PACKET:
2324 td->status = 0;
2325 break;
2326 case COMP_STOPPED_SHORT_PACKET:
2327 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2328 td->urb->actual_length = remaining;
2329 else
2330 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2331 goto finish_td;
2332 case COMP_STOPPED:
2333 switch (trb_type) {
2334 case TRB_SETUP:
2335 td->urb->actual_length = 0;
2336 goto finish_td;
2337 case TRB_DATA:
2338 case TRB_NORMAL:
2339 td->urb->actual_length = requested - remaining;
2340 goto finish_td;
2341 case TRB_STATUS:
2342 td->urb->actual_length = requested;
2343 goto finish_td;
2344 default:
2345 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2346 trb_type);
2347 goto finish_td;
2348 }
2349 case COMP_STOPPED_LENGTH_INVALID:
2350 goto finish_td;
2351 default:
2352 if (!xhci_requires_manual_halt_cleanup(xhci,
2353 ep_ctx, trb_comp_code))
2354 break;
2355 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2356 trb_comp_code, ep->ep_index);
2357 fallthrough;
2358 case COMP_STALL_ERROR:
2359 /* Did we transfer part of the data (middle) phase? */
2360 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2361 td->urb->actual_length = requested - remaining;
2362 else if (!td->urb_length_set)
2363 td->urb->actual_length = 0;
2364 goto finish_td;
2365 }
2366
2367 /* stopped at setup stage, no data transferred */
2368 if (trb_type == TRB_SETUP)
2369 goto finish_td;
2370
2371 /*
2372 * if on data stage then update the actual_length of the URB and flag it
2373 * as set, so it won't be overwritten in the event for the last TRB.
2374 */
2375 if (trb_type == TRB_DATA ||
2376 trb_type == TRB_NORMAL) {
2377 td->urb_length_set = true;
2378 td->urb->actual_length = requested - remaining;
2379 xhci_dbg(xhci, "Waiting for status stage event\n");
2380 return 0;
2381 }
2382
2383 /* at status stage */
2384 if (!td->urb_length_set)
2385 td->urb->actual_length = requested;
2386
2387 finish_td:
2388 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2389 }
2390
2391 /*
2392 * Process isochronous tds, update urb packet status and actual_length.
2393 */
process_isoc_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,union xhci_trb * ep_trb,struct xhci_transfer_event * event)2394 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2395 struct xhci_ring *ep_ring, struct xhci_td *td,
2396 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2397 {
2398 struct urb_priv *urb_priv;
2399 int idx;
2400 struct usb_iso_packet_descriptor *frame;
2401 u32 trb_comp_code;
2402 bool sum_trbs_for_length = false;
2403 u32 remaining, requested, ep_trb_len;
2404 int short_framestatus;
2405
2406 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2407 urb_priv = td->urb->hcpriv;
2408 idx = urb_priv->num_tds_done;
2409 frame = &td->urb->iso_frame_desc[idx];
2410 requested = frame->length;
2411 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2412 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2413 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2414 -EREMOTEIO : 0;
2415
2416 /* handle completion code */
2417 switch (trb_comp_code) {
2418 case COMP_SUCCESS:
2419 /* Don't overwrite status if TD had an error, see xHCI 4.9.1 */
2420 if (td->error_mid_td)
2421 break;
2422 if (remaining) {
2423 frame->status = short_framestatus;
2424 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2425 sum_trbs_for_length = true;
2426 break;
2427 }
2428 frame->status = 0;
2429 break;
2430 case COMP_SHORT_PACKET:
2431 frame->status = short_framestatus;
2432 sum_trbs_for_length = true;
2433 break;
2434 case COMP_BANDWIDTH_OVERRUN_ERROR:
2435 frame->status = -ECOMM;
2436 break;
2437 case COMP_BABBLE_DETECTED_ERROR:
2438 sum_trbs_for_length = true;
2439 fallthrough;
2440 case COMP_ISOCH_BUFFER_OVERRUN:
2441 frame->status = -EOVERFLOW;
2442 if (ep_trb != td->last_trb)
2443 td->error_mid_td = true;
2444 break;
2445 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2446 case COMP_STALL_ERROR:
2447 frame->status = -EPROTO;
2448 break;
2449 case COMP_USB_TRANSACTION_ERROR:
2450 frame->status = -EPROTO;
2451 sum_trbs_for_length = true;
2452 if (ep_trb != td->last_trb)
2453 td->error_mid_td = true;
2454 break;
2455 case COMP_STOPPED:
2456 sum_trbs_for_length = true;
2457 break;
2458 case COMP_STOPPED_SHORT_PACKET:
2459 /* field normally containing residue now contains tranferred */
2460 frame->status = short_framestatus;
2461 requested = remaining;
2462 break;
2463 case COMP_STOPPED_LENGTH_INVALID:
2464 requested = 0;
2465 remaining = 0;
2466 break;
2467 default:
2468 sum_trbs_for_length = true;
2469 frame->status = -1;
2470 break;
2471 }
2472
2473 if (td->urb_length_set)
2474 goto finish_td;
2475
2476 if (sum_trbs_for_length)
2477 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2478 ep_trb_len - remaining;
2479 else
2480 frame->actual_length = requested;
2481
2482 td->urb->actual_length += frame->actual_length;
2483
2484 finish_td:
2485 /* Don't give back TD yet if we encountered an error mid TD */
2486 if (td->error_mid_td && ep_trb != td->last_trb) {
2487 xhci_dbg(xhci, "Error mid isoc TD, wait for final completion event\n");
2488 td->urb_length_set = true;
2489 return 0;
2490 }
2491
2492 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2493 }
2494
skip_isoc_td(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_virt_ep * ep,int status)2495 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2496 struct xhci_virt_ep *ep, int status)
2497 {
2498 struct urb_priv *urb_priv;
2499 struct usb_iso_packet_descriptor *frame;
2500 int idx;
2501
2502 urb_priv = td->urb->hcpriv;
2503 idx = urb_priv->num_tds_done;
2504 frame = &td->urb->iso_frame_desc[idx];
2505
2506 /* The transfer is partly done. */
2507 frame->status = -EXDEV;
2508
2509 /* calc actual length */
2510 frame->actual_length = 0;
2511
2512 /* Update ring dequeue pointer */
2513 ep->ring->dequeue = td->last_trb;
2514 ep->ring->deq_seg = td->last_trb_seg;
2515 inc_deq(xhci, ep->ring);
2516
2517 return xhci_td_cleanup(xhci, td, ep->ring, status);
2518 }
2519
2520 /*
2521 * Process bulk and interrupt tds, update urb status and actual_length.
2522 */
process_bulk_intr_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,union xhci_trb * ep_trb,struct xhci_transfer_event * event)2523 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2524 struct xhci_ring *ep_ring, struct xhci_td *td,
2525 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2526 {
2527 struct xhci_slot_ctx *slot_ctx;
2528 u32 trb_comp_code;
2529 u32 remaining, requested, ep_trb_len;
2530
2531 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2532 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2533 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2534 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2535 requested = td->urb->transfer_buffer_length;
2536
2537 switch (trb_comp_code) {
2538 case COMP_SUCCESS:
2539 ep->err_count = 0;
2540 /* handle success with untransferred data as short packet */
2541 if (ep_trb != td->last_trb || remaining) {
2542 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2543 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2544 td->urb->ep->desc.bEndpointAddress,
2545 requested, remaining);
2546 }
2547 td->status = 0;
2548 break;
2549 case COMP_SHORT_PACKET:
2550 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2551 td->urb->ep->desc.bEndpointAddress,
2552 requested, remaining);
2553 td->status = 0;
2554 break;
2555 case COMP_STOPPED_SHORT_PACKET:
2556 td->urb->actual_length = remaining;
2557 goto finish_td;
2558 case COMP_STOPPED_LENGTH_INVALID:
2559 /* stopped on ep trb with invalid length, exclude it */
2560 td->urb->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb);
2561 goto finish_td;
2562 case COMP_USB_TRANSACTION_ERROR:
2563 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2564 (ep->err_count++ > MAX_SOFT_RETRY) ||
2565 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2566 break;
2567
2568 td->status = 0;
2569
2570 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2571 return 0;
2572 default:
2573 /* do nothing */
2574 break;
2575 }
2576
2577 if (ep_trb == td->last_trb)
2578 td->urb->actual_length = requested - remaining;
2579 else
2580 td->urb->actual_length =
2581 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2582 ep_trb_len - remaining;
2583 finish_td:
2584 if (remaining > requested) {
2585 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2586 remaining);
2587 td->urb->actual_length = 0;
2588 }
2589
2590 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2591 }
2592
2593 /*
2594 * If this function returns an error condition, it means it got a Transfer
2595 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2596 * At this point, the host controller is probably hosed and should be reset.
2597 */
handle_tx_event(struct xhci_hcd * xhci,struct xhci_interrupter * ir,struct xhci_transfer_event * event)2598 static int handle_tx_event(struct xhci_hcd *xhci,
2599 struct xhci_interrupter *ir,
2600 struct xhci_transfer_event *event)
2601 {
2602 struct xhci_virt_ep *ep;
2603 struct xhci_ring *ep_ring;
2604 unsigned int slot_id;
2605 int ep_index;
2606 struct xhci_td *td = NULL;
2607 dma_addr_t ep_trb_dma;
2608 struct xhci_segment *ep_seg;
2609 union xhci_trb *ep_trb;
2610 int status = -EINPROGRESS;
2611 struct xhci_ep_ctx *ep_ctx;
2612 u32 trb_comp_code;
2613 int td_num = 0;
2614 bool handling_skipped_tds = false;
2615
2616 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2617 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2618 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2619 ep_trb_dma = le64_to_cpu(event->buffer);
2620
2621 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2622 if (!ep) {
2623 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2624 goto err_out;
2625 }
2626
2627 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2628 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2629
2630 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2631 xhci_err(xhci,
2632 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2633 slot_id, ep_index);
2634 goto err_out;
2635 }
2636
2637 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2638 if (!ep_ring) {
2639 switch (trb_comp_code) {
2640 case COMP_STALL_ERROR:
2641 case COMP_USB_TRANSACTION_ERROR:
2642 case COMP_INVALID_STREAM_TYPE_ERROR:
2643 case COMP_INVALID_STREAM_ID_ERROR:
2644 xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2645 ep_index);
2646 if (ep->err_count++ > MAX_SOFT_RETRY)
2647 xhci_handle_halted_endpoint(xhci, ep, NULL,
2648 EP_HARD_RESET);
2649 else
2650 xhci_handle_halted_endpoint(xhci, ep, NULL,
2651 EP_SOFT_RESET);
2652 goto cleanup;
2653 case COMP_RING_UNDERRUN:
2654 case COMP_RING_OVERRUN:
2655 case COMP_STOPPED_LENGTH_INVALID:
2656 goto cleanup;
2657 default:
2658 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2659 slot_id, ep_index);
2660 goto err_out;
2661 }
2662 }
2663
2664 /* Count current td numbers if ep->skip is set */
2665 if (ep->skip)
2666 td_num += list_count_nodes(&ep_ring->td_list);
2667
2668 /* Look for common error cases */
2669 switch (trb_comp_code) {
2670 /* Skip codes that require special handling depending on
2671 * transfer type
2672 */
2673 case COMP_SUCCESS:
2674 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2675 break;
2676 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2677 ep_ring->last_td_was_short)
2678 trb_comp_code = COMP_SHORT_PACKET;
2679 else
2680 xhci_warn_ratelimited(xhci,
2681 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2682 slot_id, ep_index);
2683 break;
2684 case COMP_SHORT_PACKET:
2685 break;
2686 /* Completion codes for endpoint stopped state */
2687 case COMP_STOPPED:
2688 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2689 slot_id, ep_index);
2690 break;
2691 case COMP_STOPPED_LENGTH_INVALID:
2692 xhci_dbg(xhci,
2693 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2694 slot_id, ep_index);
2695 break;
2696 case COMP_STOPPED_SHORT_PACKET:
2697 xhci_dbg(xhci,
2698 "Stopped with short packet transfer detected for slot %u ep %u\n",
2699 slot_id, ep_index);
2700 break;
2701 /* Completion codes for endpoint halted state */
2702 case COMP_STALL_ERROR:
2703 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2704 ep_index);
2705 status = -EPIPE;
2706 break;
2707 case COMP_SPLIT_TRANSACTION_ERROR:
2708 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2709 slot_id, ep_index);
2710 status = -EPROTO;
2711 break;
2712 case COMP_USB_TRANSACTION_ERROR:
2713 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2714 slot_id, ep_index);
2715 status = -EPROTO;
2716 break;
2717 case COMP_BABBLE_DETECTED_ERROR:
2718 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2719 slot_id, ep_index);
2720 status = -EOVERFLOW;
2721 break;
2722 /* Completion codes for endpoint error state */
2723 case COMP_TRB_ERROR:
2724 xhci_warn(xhci,
2725 "WARN: TRB error for slot %u ep %u on endpoint\n",
2726 slot_id, ep_index);
2727 status = -EILSEQ;
2728 break;
2729 /* completion codes not indicating endpoint state change */
2730 case COMP_DATA_BUFFER_ERROR:
2731 xhci_warn(xhci,
2732 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2733 slot_id, ep_index);
2734 status = -ENOSR;
2735 break;
2736 case COMP_BANDWIDTH_OVERRUN_ERROR:
2737 xhci_warn(xhci,
2738 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2739 slot_id, ep_index);
2740 break;
2741 case COMP_ISOCH_BUFFER_OVERRUN:
2742 xhci_warn(xhci,
2743 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2744 slot_id, ep_index);
2745 break;
2746 case COMP_RING_UNDERRUN:
2747 /*
2748 * When the Isoch ring is empty, the xHC will generate
2749 * a Ring Overrun Event for IN Isoch endpoint or Ring
2750 * Underrun Event for OUT Isoch endpoint.
2751 */
2752 xhci_dbg(xhci, "underrun event on endpoint\n");
2753 if (!list_empty(&ep_ring->td_list))
2754 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2755 "still with TDs queued?\n",
2756 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2757 ep_index);
2758 goto cleanup;
2759 case COMP_RING_OVERRUN:
2760 xhci_dbg(xhci, "overrun event on endpoint\n");
2761 if (!list_empty(&ep_ring->td_list))
2762 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2763 "still with TDs queued?\n",
2764 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2765 ep_index);
2766 goto cleanup;
2767 case COMP_MISSED_SERVICE_ERROR:
2768 /*
2769 * When encounter missed service error, one or more isoc tds
2770 * may be missed by xHC.
2771 * Set skip flag of the ep_ring; Complete the missed tds as
2772 * short transfer when process the ep_ring next time.
2773 */
2774 ep->skip = true;
2775 xhci_dbg(xhci,
2776 "Miss service interval error for slot %u ep %u, set skip flag\n",
2777 slot_id, ep_index);
2778 goto cleanup;
2779 case COMP_NO_PING_RESPONSE_ERROR:
2780 ep->skip = true;
2781 xhci_dbg(xhci,
2782 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2783 slot_id, ep_index);
2784 goto cleanup;
2785
2786 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2787 /* needs disable slot command to recover */
2788 xhci_warn(xhci,
2789 "WARN: detect an incompatible device for slot %u ep %u",
2790 slot_id, ep_index);
2791 status = -EPROTO;
2792 break;
2793 default:
2794 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2795 status = 0;
2796 break;
2797 }
2798 xhci_warn(xhci,
2799 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2800 trb_comp_code, slot_id, ep_index);
2801 goto cleanup;
2802 }
2803
2804 do {
2805 /* This TRB should be in the TD at the head of this ring's
2806 * TD list.
2807 */
2808 if (list_empty(&ep_ring->td_list)) {
2809 /*
2810 * Don't print wanings if it's due to a stopped endpoint
2811 * generating an extra completion event if the device
2812 * was suspended. Or, a event for the last TRB of a
2813 * short TD we already got a short event for.
2814 * The short TD is already removed from the TD list.
2815 */
2816
2817 if (!(trb_comp_code == COMP_STOPPED ||
2818 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2819 ep_ring->last_td_was_short)) {
2820 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2821 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2822 ep_index);
2823 }
2824 if (ep->skip) {
2825 ep->skip = false;
2826 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2827 slot_id, ep_index);
2828 }
2829 if (trb_comp_code == COMP_STALL_ERROR ||
2830 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2831 trb_comp_code)) {
2832 xhci_handle_halted_endpoint(xhci, ep, NULL,
2833 EP_HARD_RESET);
2834 }
2835 goto cleanup;
2836 }
2837
2838 /* We've skipped all the TDs on the ep ring when ep->skip set */
2839 if (ep->skip && td_num == 0) {
2840 ep->skip = false;
2841 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2842 slot_id, ep_index);
2843 goto cleanup;
2844 }
2845
2846 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2847 td_list);
2848 if (ep->skip)
2849 td_num--;
2850
2851 /* Is this a TRB in the currently executing TD? */
2852 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2853 td->last_trb, ep_trb_dma, false);
2854
2855 /*
2856 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2857 * is not in the current TD pointed by ep_ring->dequeue because
2858 * that the hardware dequeue pointer still at the previous TRB
2859 * of the current TD. The previous TRB maybe a Link TD or the
2860 * last TRB of the previous TD. The command completion handle
2861 * will take care the rest.
2862 */
2863 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2864 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2865 goto cleanup;
2866 }
2867
2868 if (!ep_seg) {
2869
2870 if (ep->skip && usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2871 skip_isoc_td(xhci, td, ep, status);
2872 goto cleanup;
2873 }
2874
2875 /*
2876 * Some hosts give a spurious success event after a short
2877 * transfer. Ignore it.
2878 */
2879 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2880 ep_ring->last_td_was_short) {
2881 ep_ring->last_td_was_short = false;
2882 goto cleanup;
2883 }
2884
2885 /*
2886 * xhci 4.10.2 states isoc endpoints should continue
2887 * processing the next TD if there was an error mid TD.
2888 * So host like NEC don't generate an event for the last
2889 * isoc TRB even if the IOC flag is set.
2890 * xhci 4.9.1 states that if there are errors in mult-TRB
2891 * TDs xHC should generate an error for that TRB, and if xHC
2892 * proceeds to the next TD it should genete an event for
2893 * any TRB with IOC flag on the way. Other host follow this.
2894 * So this event might be for the next TD.
2895 */
2896 if (td->error_mid_td &&
2897 !list_is_last(&td->td_list, &ep_ring->td_list)) {
2898 struct xhci_td *td_next = list_next_entry(td, td_list);
2899
2900 ep_seg = trb_in_td(xhci, td_next->start_seg, td_next->first_trb,
2901 td_next->last_trb, ep_trb_dma, false);
2902 if (ep_seg) {
2903 /* give back previous TD, start handling new */
2904 xhci_dbg(xhci, "Missing TD completion event after mid TD error\n");
2905 ep_ring->dequeue = td->last_trb;
2906 ep_ring->deq_seg = td->last_trb_seg;
2907 inc_deq(xhci, ep_ring);
2908 xhci_td_cleanup(xhci, td, ep_ring, td->status);
2909 td = td_next;
2910 }
2911 }
2912
2913 if (!ep_seg) {
2914 /* HC is busted, give up! */
2915 xhci_err(xhci,
2916 "ERROR Transfer event TRB DMA ptr not "
2917 "part of current TD ep_index %d "
2918 "comp_code %u\n", ep_index,
2919 trb_comp_code);
2920 trb_in_td(xhci, ep_ring->deq_seg,
2921 ep_ring->dequeue, td->last_trb,
2922 ep_trb_dma, true);
2923 return -ESHUTDOWN;
2924 }
2925 }
2926 if (trb_comp_code == COMP_SHORT_PACKET)
2927 ep_ring->last_td_was_short = true;
2928 else
2929 ep_ring->last_td_was_short = false;
2930
2931 if (ep->skip) {
2932 xhci_dbg(xhci,
2933 "Found td. Clear skip flag for slot %u ep %u.\n",
2934 slot_id, ep_index);
2935 ep->skip = false;
2936 }
2937
2938 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2939 sizeof(*ep_trb)];
2940
2941 trace_xhci_handle_transfer(ep_ring,
2942 (struct xhci_generic_trb *) ep_trb);
2943
2944 /*
2945 * No-op TRB could trigger interrupts in a case where
2946 * a URB was killed and a STALL_ERROR happens right
2947 * after the endpoint ring stopped. Reset the halted
2948 * endpoint. Otherwise, the endpoint remains stalled
2949 * indefinitely.
2950 */
2951
2952 if (trb_is_noop(ep_trb)) {
2953 if (trb_comp_code == COMP_STALL_ERROR ||
2954 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2955 trb_comp_code))
2956 xhci_handle_halted_endpoint(xhci, ep, td,
2957 EP_HARD_RESET);
2958 goto cleanup;
2959 }
2960
2961 td->status = status;
2962
2963 /* update the urb's actual_length and give back to the core */
2964 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2965 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2966 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2967 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2968 else
2969 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2970 cleanup:
2971 handling_skipped_tds = ep->skip &&
2972 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2973 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2974
2975 /*
2976 * Do not update event ring dequeue pointer if we're in a loop
2977 * processing missed tds.
2978 */
2979 if (!handling_skipped_tds)
2980 inc_deq(xhci, ir->event_ring);
2981
2982 /*
2983 * If ep->skip is set, it means there are missed tds on the
2984 * endpoint ring need to take care of.
2985 * Process them as short transfer until reach the td pointed by
2986 * the event.
2987 */
2988 } while (handling_skipped_tds);
2989
2990 return 0;
2991
2992 err_out:
2993 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2994 (unsigned long long) xhci_trb_virt_to_dma(
2995 ir->event_ring->deq_seg,
2996 ir->event_ring->dequeue),
2997 lower_32_bits(le64_to_cpu(event->buffer)),
2998 upper_32_bits(le64_to_cpu(event->buffer)),
2999 le32_to_cpu(event->transfer_len),
3000 le32_to_cpu(event->flags));
3001 return -ENODEV;
3002 }
3003
3004 /*
3005 * This function handles all OS-owned events on the event ring. It may drop
3006 * xhci->lock between event processing (e.g. to pass up port status changes).
3007 * Returns >0 for "possibly more events to process" (caller should call again),
3008 * otherwise 0 if done. In future, <0 returns should indicate error code.
3009 */
xhci_handle_event(struct xhci_hcd * xhci,struct xhci_interrupter * ir)3010 static int xhci_handle_event(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
3011 {
3012 union xhci_trb *event;
3013 int update_ptrs = 1;
3014 u32 trb_type;
3015 int ret;
3016
3017 /* Event ring hasn't been allocated yet. */
3018 if (!ir || !ir->event_ring || !ir->event_ring->dequeue) {
3019 xhci_err(xhci, "ERROR interrupter not ready\n");
3020 return -ENOMEM;
3021 }
3022
3023 event = ir->event_ring->dequeue;
3024 /* Does the HC or OS own the TRB? */
3025 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
3026 ir->event_ring->cycle_state)
3027 return 0;
3028
3029 trace_xhci_handle_event(ir->event_ring, &event->generic);
3030
3031 /*
3032 * Barrier between reading the TRB_CYCLE (valid) flag above and any
3033 * speculative reads of the event's flags/data below.
3034 */
3035 rmb();
3036 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
3037 /* FIXME: Handle more event types. */
3038
3039 switch (trb_type) {
3040 case TRB_COMPLETION:
3041 handle_cmd_completion(xhci, &event->event_cmd);
3042 break;
3043 case TRB_PORT_STATUS:
3044 handle_port_status(xhci, ir, event);
3045 update_ptrs = 0;
3046 break;
3047 case TRB_TRANSFER:
3048 ret = handle_tx_event(xhci, ir, &event->trans_event);
3049 if (ret >= 0)
3050 update_ptrs = 0;
3051 break;
3052 case TRB_DEV_NOTE:
3053 handle_device_notification(xhci, event);
3054 break;
3055 default:
3056 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
3057 handle_vendor_event(xhci, event, trb_type);
3058 else
3059 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
3060 }
3061 /* Any of the above functions may drop and re-acquire the lock, so check
3062 * to make sure a watchdog timer didn't mark the host as non-responsive.
3063 */
3064 if (xhci->xhc_state & XHCI_STATE_DYING) {
3065 xhci_dbg(xhci, "xHCI host dying, returning from "
3066 "event handler.\n");
3067 return 0;
3068 }
3069
3070 if (update_ptrs)
3071 /* Update SW event ring dequeue pointer */
3072 inc_deq(xhci, ir->event_ring);
3073
3074 /* Are there more items on the event ring? Caller will call us again to
3075 * check.
3076 */
3077 return 1;
3078 }
3079
3080 /*
3081 * Update Event Ring Dequeue Pointer:
3082 * - When all events have finished
3083 * - To avoid "Event Ring Full Error" condition
3084 */
xhci_update_erst_dequeue(struct xhci_hcd * xhci,struct xhci_interrupter * ir,union xhci_trb * event_ring_deq,bool clear_ehb)3085 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
3086 struct xhci_interrupter *ir,
3087 union xhci_trb *event_ring_deq,
3088 bool clear_ehb)
3089 {
3090 u64 temp_64;
3091 dma_addr_t deq;
3092
3093 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3094 /* If necessary, update the HW's version of the event ring deq ptr. */
3095 if (event_ring_deq != ir->event_ring->dequeue) {
3096 deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
3097 ir->event_ring->dequeue);
3098 if (deq == 0)
3099 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
3100 /*
3101 * Per 4.9.4, Software writes to the ERDP register shall
3102 * always advance the Event Ring Dequeue Pointer value.
3103 */
3104 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
3105 ((u64) deq & (u64) ~ERST_PTR_MASK))
3106 return;
3107
3108 /* Update HC event ring dequeue pointer */
3109 temp_64 &= ERST_DESI_MASK;
3110 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
3111 }
3112
3113 /* Clear the event handler busy flag (RW1C) */
3114 if (clear_ehb)
3115 temp_64 |= ERST_EHB;
3116 xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue);
3117 }
3118
3119 /*
3120 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3121 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3122 * indicators of an event TRB error, but we check the status *first* to be safe.
3123 */
xhci_irq(struct usb_hcd * hcd)3124 irqreturn_t xhci_irq(struct usb_hcd *hcd)
3125 {
3126 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3127 union xhci_trb *event_ring_deq;
3128 struct xhci_interrupter *ir;
3129 irqreturn_t ret = IRQ_NONE;
3130 u64 temp_64;
3131 u32 status;
3132 int event_loop = 0;
3133
3134 spin_lock(&xhci->lock);
3135 /* Check if the xHC generated the interrupt, or the irq is shared */
3136 status = readl(&xhci->op_regs->status);
3137 if (status == ~(u32)0) {
3138 xhci_hc_died(xhci);
3139 ret = IRQ_HANDLED;
3140 goto out;
3141 }
3142
3143 if (!(status & STS_EINT))
3144 goto out;
3145
3146 if (status & STS_HCE) {
3147 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3148 goto out;
3149 }
3150
3151 if (status & STS_FATAL) {
3152 xhci_warn(xhci, "WARNING: Host System Error\n");
3153 xhci_halt(xhci);
3154 ret = IRQ_HANDLED;
3155 goto out;
3156 }
3157
3158 /*
3159 * Clear the op reg interrupt status first,
3160 * so we can receive interrupts from other MSI-X interrupters.
3161 * Write 1 to clear the interrupt status.
3162 */
3163 status |= STS_EINT;
3164 writel(status, &xhci->op_regs->status);
3165
3166 /* This is the handler of the primary interrupter */
3167 ir = xhci->interrupter;
3168 if (!hcd->msi_enabled) {
3169 u32 irq_pending;
3170 irq_pending = readl(&ir->ir_set->irq_pending);
3171 irq_pending |= IMAN_IP;
3172 writel(irq_pending, &ir->ir_set->irq_pending);
3173 }
3174
3175 if (xhci->xhc_state & XHCI_STATE_DYING ||
3176 xhci->xhc_state & XHCI_STATE_HALTED) {
3177 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3178 "Shouldn't IRQs be disabled?\n");
3179 /* Clear the event handler busy flag (RW1C);
3180 * the event ring should be empty.
3181 */
3182 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3183 xhci_write_64(xhci, temp_64 | ERST_EHB,
3184 &ir->ir_set->erst_dequeue);
3185 ret = IRQ_HANDLED;
3186 goto out;
3187 }
3188
3189 event_ring_deq = ir->event_ring->dequeue;
3190 /* FIXME this should be a delayed service routine
3191 * that clears the EHB.
3192 */
3193 while (xhci_handle_event(xhci, ir) > 0) {
3194 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3195 continue;
3196 xhci_update_erst_dequeue(xhci, ir, event_ring_deq, false);
3197 event_ring_deq = ir->event_ring->dequeue;
3198
3199 /* ring is half-full, force isoc trbs to interrupt more often */
3200 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3201 xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2;
3202
3203 event_loop = 0;
3204 }
3205
3206 xhci_update_erst_dequeue(xhci, ir, event_ring_deq, true);
3207 ret = IRQ_HANDLED;
3208
3209 out:
3210 spin_unlock(&xhci->lock);
3211
3212 return ret;
3213 }
3214
xhci_msi_irq(int irq,void * hcd)3215 irqreturn_t xhci_msi_irq(int irq, void *hcd)
3216 {
3217 return xhci_irq(hcd);
3218 }
3219 EXPORT_SYMBOL_GPL(xhci_msi_irq);
3220
3221 /**** Endpoint Ring Operations ****/
3222
3223 /*
3224 * Generic function for queueing a TRB on a ring.
3225 * The caller must have checked to make sure there's room on the ring.
3226 *
3227 * @more_trbs_coming: Will you enqueue more TRBs before calling
3228 * prepare_transfer()?
3229 */
queue_trb(struct xhci_hcd * xhci,struct xhci_ring * ring,bool more_trbs_coming,u32 field1,u32 field2,u32 field3,u32 field4)3230 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3231 bool more_trbs_coming,
3232 u32 field1, u32 field2, u32 field3, u32 field4)
3233 {
3234 struct xhci_generic_trb *trb;
3235
3236 trb = &ring->enqueue->generic;
3237 trb->field[0] = cpu_to_le32(field1);
3238 trb->field[1] = cpu_to_le32(field2);
3239 trb->field[2] = cpu_to_le32(field3);
3240 /* make sure TRB is fully written before giving it to the controller */
3241 wmb();
3242 trb->field[3] = cpu_to_le32(field4);
3243
3244 trace_xhci_queue_trb(ring, trb);
3245
3246 inc_enq(xhci, ring, more_trbs_coming);
3247 }
3248
3249 /*
3250 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3251 * expand ring if it start to be full.
3252 */
prepare_ring(struct xhci_hcd * xhci,struct xhci_ring * ep_ring,u32 ep_state,unsigned int num_trbs,gfp_t mem_flags)3253 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3254 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3255 {
3256 unsigned int link_trb_count = 0;
3257 unsigned int new_segs = 0;
3258
3259 /* Make sure the endpoint has been added to xHC schedule */
3260 switch (ep_state) {
3261 case EP_STATE_DISABLED:
3262 /*
3263 * USB core changed config/interfaces without notifying us,
3264 * or hardware is reporting the wrong state.
3265 */
3266 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3267 return -ENOENT;
3268 case EP_STATE_ERROR:
3269 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3270 /* FIXME event handling code for error needs to clear it */
3271 /* XXX not sure if this should be -ENOENT or not */
3272 return -EINVAL;
3273 case EP_STATE_HALTED:
3274 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3275 break;
3276 case EP_STATE_STOPPED:
3277 case EP_STATE_RUNNING:
3278 break;
3279 default:
3280 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3281 /*
3282 * FIXME issue Configure Endpoint command to try to get the HC
3283 * back into a known state.
3284 */
3285 return -EINVAL;
3286 }
3287
3288 if (ep_ring != xhci->cmd_ring) {
3289 new_segs = xhci_ring_expansion_needed(xhci, ep_ring, num_trbs);
3290 } else if (xhci_num_trbs_free(xhci, ep_ring) <= num_trbs) {
3291 xhci_err(xhci, "Do not support expand command ring\n");
3292 return -ENOMEM;
3293 }
3294
3295 if (new_segs) {
3296 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3297 "ERROR no room on ep ring, try ring expansion");
3298 if (xhci_ring_expansion(xhci, ep_ring, new_segs, mem_flags)) {
3299 xhci_err(xhci, "Ring expansion failed\n");
3300 return -ENOMEM;
3301 }
3302 }
3303
3304 while (trb_is_link(ep_ring->enqueue)) {
3305 /* If we're not dealing with 0.95 hardware or isoc rings
3306 * on AMD 0.96 host, clear the chain bit.
3307 */
3308 if (!xhci_link_trb_quirk(xhci) &&
3309 !(ep_ring->type == TYPE_ISOC &&
3310 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3311 ep_ring->enqueue->link.control &=
3312 cpu_to_le32(~TRB_CHAIN);
3313 else
3314 ep_ring->enqueue->link.control |=
3315 cpu_to_le32(TRB_CHAIN);
3316
3317 wmb();
3318 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3319
3320 /* Toggle the cycle bit after the last ring segment. */
3321 if (link_trb_toggles_cycle(ep_ring->enqueue))
3322 ep_ring->cycle_state ^= 1;
3323
3324 ep_ring->enq_seg = ep_ring->enq_seg->next;
3325 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3326
3327 /* prevent infinite loop if all first trbs are link trbs */
3328 if (link_trb_count++ > ep_ring->num_segs) {
3329 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3330 return -EINVAL;
3331 }
3332 }
3333
3334 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3335 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3336 return -EINVAL;
3337 }
3338
3339 return 0;
3340 }
3341
prepare_transfer(struct xhci_hcd * xhci,struct xhci_virt_device * xdev,unsigned int ep_index,unsigned int stream_id,unsigned int num_trbs,struct urb * urb,unsigned int td_index,gfp_t mem_flags)3342 static int prepare_transfer(struct xhci_hcd *xhci,
3343 struct xhci_virt_device *xdev,
3344 unsigned int ep_index,
3345 unsigned int stream_id,
3346 unsigned int num_trbs,
3347 struct urb *urb,
3348 unsigned int td_index,
3349 gfp_t mem_flags)
3350 {
3351 int ret;
3352 struct urb_priv *urb_priv;
3353 struct xhci_td *td;
3354 struct xhci_ring *ep_ring;
3355 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3356
3357 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3358 stream_id);
3359 if (!ep_ring) {
3360 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3361 stream_id);
3362 return -EINVAL;
3363 }
3364
3365 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3366 num_trbs, mem_flags);
3367 if (ret)
3368 return ret;
3369
3370 urb_priv = urb->hcpriv;
3371 td = &urb_priv->td[td_index];
3372
3373 INIT_LIST_HEAD(&td->td_list);
3374 INIT_LIST_HEAD(&td->cancelled_td_list);
3375
3376 if (td_index == 0) {
3377 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3378 if (unlikely(ret))
3379 return ret;
3380 }
3381
3382 td->urb = urb;
3383 /* Add this TD to the tail of the endpoint ring's TD list */
3384 list_add_tail(&td->td_list, &ep_ring->td_list);
3385 td->start_seg = ep_ring->enq_seg;
3386 td->first_trb = ep_ring->enqueue;
3387
3388 return 0;
3389 }
3390
count_trbs(u64 addr,u64 len)3391 unsigned int count_trbs(u64 addr, u64 len)
3392 {
3393 unsigned int num_trbs;
3394
3395 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3396 TRB_MAX_BUFF_SIZE);
3397 if (num_trbs == 0)
3398 num_trbs++;
3399
3400 return num_trbs;
3401 }
3402
count_trbs_needed(struct urb * urb)3403 static inline unsigned int count_trbs_needed(struct urb *urb)
3404 {
3405 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3406 }
3407
count_sg_trbs_needed(struct urb * urb)3408 static unsigned int count_sg_trbs_needed(struct urb *urb)
3409 {
3410 struct scatterlist *sg;
3411 unsigned int i, len, full_len, num_trbs = 0;
3412
3413 full_len = urb->transfer_buffer_length;
3414
3415 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3416 len = sg_dma_len(sg);
3417 num_trbs += count_trbs(sg_dma_address(sg), len);
3418 len = min_t(unsigned int, len, full_len);
3419 full_len -= len;
3420 if (full_len == 0)
3421 break;
3422 }
3423
3424 return num_trbs;
3425 }
3426
count_isoc_trbs_needed(struct urb * urb,int i)3427 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3428 {
3429 u64 addr, len;
3430
3431 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3432 len = urb->iso_frame_desc[i].length;
3433
3434 return count_trbs(addr, len);
3435 }
3436
check_trb_math(struct urb * urb,int running_total)3437 static void check_trb_math(struct urb *urb, int running_total)
3438 {
3439 if (unlikely(running_total != urb->transfer_buffer_length))
3440 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3441 "queued %#x (%d), asked for %#x (%d)\n",
3442 __func__,
3443 urb->ep->desc.bEndpointAddress,
3444 running_total, running_total,
3445 urb->transfer_buffer_length,
3446 urb->transfer_buffer_length);
3447 }
3448
giveback_first_trb(struct xhci_hcd * xhci,int slot_id,unsigned int ep_index,unsigned int stream_id,int start_cycle,struct xhci_generic_trb * start_trb)3449 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3450 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3451 struct xhci_generic_trb *start_trb)
3452 {
3453 /*
3454 * Pass all the TRBs to the hardware at once and make sure this write
3455 * isn't reordered.
3456 */
3457 wmb();
3458 if (start_cycle)
3459 start_trb->field[3] |= cpu_to_le32(start_cycle);
3460 else
3461 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3462 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3463 }
3464
check_interval(struct xhci_hcd * xhci,struct urb * urb,struct xhci_ep_ctx * ep_ctx)3465 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3466 struct xhci_ep_ctx *ep_ctx)
3467 {
3468 int xhci_interval;
3469 int ep_interval;
3470
3471 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3472 ep_interval = urb->interval;
3473
3474 /* Convert to microframes */
3475 if (urb->dev->speed == USB_SPEED_LOW ||
3476 urb->dev->speed == USB_SPEED_FULL)
3477 ep_interval *= 8;
3478
3479 /* FIXME change this to a warning and a suggestion to use the new API
3480 * to set the polling interval (once the API is added).
3481 */
3482 if (xhci_interval != ep_interval) {
3483 dev_dbg_ratelimited(&urb->dev->dev,
3484 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3485 ep_interval, ep_interval == 1 ? "" : "s",
3486 xhci_interval, xhci_interval == 1 ? "" : "s");
3487 urb->interval = xhci_interval;
3488 /* Convert back to frames for LS/FS devices */
3489 if (urb->dev->speed == USB_SPEED_LOW ||
3490 urb->dev->speed == USB_SPEED_FULL)
3491 urb->interval /= 8;
3492 }
3493 }
3494
3495 /*
3496 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3497 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3498 * (comprised of sg list entries) can take several service intervals to
3499 * transmit.
3500 */
xhci_queue_intr_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3501 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3502 struct urb *urb, int slot_id, unsigned int ep_index)
3503 {
3504 struct xhci_ep_ctx *ep_ctx;
3505
3506 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3507 check_interval(xhci, urb, ep_ctx);
3508
3509 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3510 }
3511
3512 /*
3513 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3514 * packets remaining in the TD (*not* including this TRB).
3515 *
3516 * Total TD packet count = total_packet_count =
3517 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3518 *
3519 * Packets transferred up to and including this TRB = packets_transferred =
3520 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3521 *
3522 * TD size = total_packet_count - packets_transferred
3523 *
3524 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3525 * including this TRB, right shifted by 10
3526 *
3527 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3528 * This is taken care of in the TRB_TD_SIZE() macro
3529 *
3530 * The last TRB in a TD must have the TD size set to zero.
3531 */
xhci_td_remainder(struct xhci_hcd * xhci,int transferred,int trb_buff_len,unsigned int td_total_len,struct urb * urb,bool more_trbs_coming)3532 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3533 int trb_buff_len, unsigned int td_total_len,
3534 struct urb *urb, bool more_trbs_coming)
3535 {
3536 u32 maxp, total_packet_count;
3537
3538 /* MTK xHCI 0.96 contains some features from 1.0 */
3539 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3540 return ((td_total_len - transferred) >> 10);
3541
3542 /* One TRB with a zero-length data packet. */
3543 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3544 trb_buff_len == td_total_len)
3545 return 0;
3546
3547 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3548 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3549 trb_buff_len = 0;
3550
3551 maxp = usb_endpoint_maxp(&urb->ep->desc);
3552 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3553
3554 /* Queueing functions don't count the current TRB into transferred */
3555 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3556 }
3557
3558
xhci_align_td(struct xhci_hcd * xhci,struct urb * urb,u32 enqd_len,u32 * trb_buff_len,struct xhci_segment * seg)3559 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3560 u32 *trb_buff_len, struct xhci_segment *seg)
3561 {
3562 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
3563 unsigned int unalign;
3564 unsigned int max_pkt;
3565 u32 new_buff_len;
3566 size_t len;
3567
3568 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3569 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3570
3571 /* we got lucky, last normal TRB data on segment is packet aligned */
3572 if (unalign == 0)
3573 return 0;
3574
3575 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3576 unalign, *trb_buff_len);
3577
3578 /* is the last nornal TRB alignable by splitting it */
3579 if (*trb_buff_len > unalign) {
3580 *trb_buff_len -= unalign;
3581 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3582 return 0;
3583 }
3584
3585 /*
3586 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3587 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3588 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3589 */
3590 new_buff_len = max_pkt - (enqd_len % max_pkt);
3591
3592 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3593 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3594
3595 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3596 if (usb_urb_dir_out(urb)) {
3597 if (urb->num_sgs) {
3598 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3599 seg->bounce_buf, new_buff_len, enqd_len);
3600 if (len != new_buff_len)
3601 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3602 len, new_buff_len);
3603 } else {
3604 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3605 }
3606
3607 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3608 max_pkt, DMA_TO_DEVICE);
3609 } else {
3610 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3611 max_pkt, DMA_FROM_DEVICE);
3612 }
3613
3614 if (dma_mapping_error(dev, seg->bounce_dma)) {
3615 /* try without aligning. Some host controllers survive */
3616 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3617 return 0;
3618 }
3619 *trb_buff_len = new_buff_len;
3620 seg->bounce_len = new_buff_len;
3621 seg->bounce_offs = enqd_len;
3622
3623 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3624
3625 return 1;
3626 }
3627
3628 /* This is very similar to what ehci-q.c qtd_fill() does */
xhci_queue_bulk_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3629 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3630 struct urb *urb, int slot_id, unsigned int ep_index)
3631 {
3632 struct xhci_ring *ring;
3633 struct urb_priv *urb_priv;
3634 struct xhci_td *td;
3635 struct xhci_generic_trb *start_trb;
3636 struct scatterlist *sg = NULL;
3637 bool more_trbs_coming = true;
3638 bool need_zero_pkt = false;
3639 bool first_trb = true;
3640 unsigned int num_trbs;
3641 unsigned int start_cycle, num_sgs = 0;
3642 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3643 int sent_len, ret;
3644 u32 field, length_field, remainder;
3645 u64 addr, send_addr;
3646
3647 ring = xhci_urb_to_transfer_ring(xhci, urb);
3648 if (!ring)
3649 return -EINVAL;
3650
3651 full_len = urb->transfer_buffer_length;
3652 /* If we have scatter/gather list, we use it. */
3653 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3654 num_sgs = urb->num_mapped_sgs;
3655 sg = urb->sg;
3656 addr = (u64) sg_dma_address(sg);
3657 block_len = sg_dma_len(sg);
3658 num_trbs = count_sg_trbs_needed(urb);
3659 } else {
3660 num_trbs = count_trbs_needed(urb);
3661 addr = (u64) urb->transfer_dma;
3662 block_len = full_len;
3663 }
3664 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3665 ep_index, urb->stream_id,
3666 num_trbs, urb, 0, mem_flags);
3667 if (unlikely(ret < 0))
3668 return ret;
3669
3670 urb_priv = urb->hcpriv;
3671
3672 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3673 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3674 need_zero_pkt = true;
3675
3676 td = &urb_priv->td[0];
3677
3678 /*
3679 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3680 * until we've finished creating all the other TRBs. The ring's cycle
3681 * state may change as we enqueue the other TRBs, so save it too.
3682 */
3683 start_trb = &ring->enqueue->generic;
3684 start_cycle = ring->cycle_state;
3685 send_addr = addr;
3686
3687 /* Queue the TRBs, even if they are zero-length */
3688 for (enqd_len = 0; first_trb || enqd_len < full_len;
3689 enqd_len += trb_buff_len) {
3690 field = TRB_TYPE(TRB_NORMAL);
3691
3692 /* TRB buffer should not cross 64KB boundaries */
3693 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3694 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3695
3696 if (enqd_len + trb_buff_len > full_len)
3697 trb_buff_len = full_len - enqd_len;
3698
3699 /* Don't change the cycle bit of the first TRB until later */
3700 if (first_trb) {
3701 first_trb = false;
3702 if (start_cycle == 0)
3703 field |= TRB_CYCLE;
3704 } else
3705 field |= ring->cycle_state;
3706
3707 /* Chain all the TRBs together; clear the chain bit in the last
3708 * TRB to indicate it's the last TRB in the chain.
3709 */
3710 if (enqd_len + trb_buff_len < full_len) {
3711 field |= TRB_CHAIN;
3712 if (trb_is_link(ring->enqueue + 1)) {
3713 if (xhci_align_td(xhci, urb, enqd_len,
3714 &trb_buff_len,
3715 ring->enq_seg)) {
3716 send_addr = ring->enq_seg->bounce_dma;
3717 /* assuming TD won't span 2 segs */
3718 td->bounce_seg = ring->enq_seg;
3719 }
3720 }
3721 }
3722 if (enqd_len + trb_buff_len >= full_len) {
3723 field &= ~TRB_CHAIN;
3724 field |= TRB_IOC;
3725 more_trbs_coming = false;
3726 td->last_trb = ring->enqueue;
3727 td->last_trb_seg = ring->enq_seg;
3728 if (xhci_urb_suitable_for_idt(urb)) {
3729 memcpy(&send_addr, urb->transfer_buffer,
3730 trb_buff_len);
3731 le64_to_cpus(&send_addr);
3732 field |= TRB_IDT;
3733 }
3734 }
3735
3736 /* Only set interrupt on short packet for IN endpoints */
3737 if (usb_urb_dir_in(urb))
3738 field |= TRB_ISP;
3739
3740 /* Set the TRB length, TD size, and interrupter fields. */
3741 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3742 full_len, urb, more_trbs_coming);
3743
3744 length_field = TRB_LEN(trb_buff_len) |
3745 TRB_TD_SIZE(remainder) |
3746 TRB_INTR_TARGET(0);
3747
3748 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3749 lower_32_bits(send_addr),
3750 upper_32_bits(send_addr),
3751 length_field,
3752 field);
3753 td->num_trbs++;
3754 addr += trb_buff_len;
3755 sent_len = trb_buff_len;
3756
3757 while (sg && sent_len >= block_len) {
3758 /* New sg entry */
3759 --num_sgs;
3760 sent_len -= block_len;
3761 sg = sg_next(sg);
3762 if (num_sgs != 0 && sg) {
3763 block_len = sg_dma_len(sg);
3764 addr = (u64) sg_dma_address(sg);
3765 addr += sent_len;
3766 }
3767 }
3768 block_len -= sent_len;
3769 send_addr = addr;
3770 }
3771
3772 if (need_zero_pkt) {
3773 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3774 ep_index, urb->stream_id,
3775 1, urb, 1, mem_flags);
3776 urb_priv->td[1].last_trb = ring->enqueue;
3777 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3778 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3779 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3780 urb_priv->td[1].num_trbs++;
3781 }
3782
3783 check_trb_math(urb, enqd_len);
3784 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3785 start_cycle, start_trb);
3786 return 0;
3787 }
3788
3789 /* Caller must have locked xhci->lock */
xhci_queue_ctrl_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3790 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3791 struct urb *urb, int slot_id, unsigned int ep_index)
3792 {
3793 struct xhci_ring *ep_ring;
3794 int num_trbs;
3795 int ret;
3796 struct usb_ctrlrequest *setup;
3797 struct xhci_generic_trb *start_trb;
3798 int start_cycle;
3799 u32 field;
3800 struct urb_priv *urb_priv;
3801 struct xhci_td *td;
3802
3803 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3804 if (!ep_ring)
3805 return -EINVAL;
3806
3807 /*
3808 * Need to copy setup packet into setup TRB, so we can't use the setup
3809 * DMA address.
3810 */
3811 if (!urb->setup_packet)
3812 return -EINVAL;
3813
3814 /* 1 TRB for setup, 1 for status */
3815 num_trbs = 2;
3816 /*
3817 * Don't need to check if we need additional event data and normal TRBs,
3818 * since data in control transfers will never get bigger than 16MB
3819 * XXX: can we get a buffer that crosses 64KB boundaries?
3820 */
3821 if (urb->transfer_buffer_length > 0)
3822 num_trbs++;
3823 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3824 ep_index, urb->stream_id,
3825 num_trbs, urb, 0, mem_flags);
3826 if (ret < 0)
3827 return ret;
3828
3829 urb_priv = urb->hcpriv;
3830 td = &urb_priv->td[0];
3831 td->num_trbs = num_trbs;
3832
3833 /*
3834 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3835 * until we've finished creating all the other TRBs. The ring's cycle
3836 * state may change as we enqueue the other TRBs, so save it too.
3837 */
3838 start_trb = &ep_ring->enqueue->generic;
3839 start_cycle = ep_ring->cycle_state;
3840
3841 /* Queue setup TRB - see section 6.4.1.2.1 */
3842 /* FIXME better way to translate setup_packet into two u32 fields? */
3843 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3844 field = 0;
3845 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3846 if (start_cycle == 0)
3847 field |= 0x1;
3848
3849 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3850 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3851 if (urb->transfer_buffer_length > 0) {
3852 if (setup->bRequestType & USB_DIR_IN)
3853 field |= TRB_TX_TYPE(TRB_DATA_IN);
3854 else
3855 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3856 }
3857 }
3858
3859 queue_trb(xhci, ep_ring, true,
3860 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3861 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3862 TRB_LEN(8) | TRB_INTR_TARGET(0),
3863 /* Immediate data in pointer */
3864 field);
3865
3866 /* If there's data, queue data TRBs */
3867 /* Only set interrupt on short packet for IN endpoints */
3868 if (usb_urb_dir_in(urb))
3869 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3870 else
3871 field = TRB_TYPE(TRB_DATA);
3872
3873 if (urb->transfer_buffer_length > 0) {
3874 u32 length_field, remainder;
3875 u64 addr;
3876
3877 if (xhci_urb_suitable_for_idt(urb)) {
3878 memcpy(&addr, urb->transfer_buffer,
3879 urb->transfer_buffer_length);
3880 le64_to_cpus(&addr);
3881 field |= TRB_IDT;
3882 } else {
3883 addr = (u64) urb->transfer_dma;
3884 }
3885
3886 remainder = xhci_td_remainder(xhci, 0,
3887 urb->transfer_buffer_length,
3888 urb->transfer_buffer_length,
3889 urb, 1);
3890 length_field = TRB_LEN(urb->transfer_buffer_length) |
3891 TRB_TD_SIZE(remainder) |
3892 TRB_INTR_TARGET(0);
3893 if (setup->bRequestType & USB_DIR_IN)
3894 field |= TRB_DIR_IN;
3895 queue_trb(xhci, ep_ring, true,
3896 lower_32_bits(addr),
3897 upper_32_bits(addr),
3898 length_field,
3899 field | ep_ring->cycle_state);
3900 }
3901
3902 /* Save the DMA address of the last TRB in the TD */
3903 td->last_trb = ep_ring->enqueue;
3904 td->last_trb_seg = ep_ring->enq_seg;
3905
3906 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3907 /* If the device sent data, the status stage is an OUT transfer */
3908 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3909 field = 0;
3910 else
3911 field = TRB_DIR_IN;
3912 queue_trb(xhci, ep_ring, false,
3913 0,
3914 0,
3915 TRB_INTR_TARGET(0),
3916 /* Event on completion */
3917 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3918
3919 giveback_first_trb(xhci, slot_id, ep_index, 0,
3920 start_cycle, start_trb);
3921 return 0;
3922 }
3923
3924 /*
3925 * The transfer burst count field of the isochronous TRB defines the number of
3926 * bursts that are required to move all packets in this TD. Only SuperSpeed
3927 * devices can burst up to bMaxBurst number of packets per service interval.
3928 * This field is zero based, meaning a value of zero in the field means one
3929 * burst. Basically, for everything but SuperSpeed devices, this field will be
3930 * zero. Only xHCI 1.0 host controllers support this field.
3931 */
xhci_get_burst_count(struct xhci_hcd * xhci,struct urb * urb,unsigned int total_packet_count)3932 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3933 struct urb *urb, unsigned int total_packet_count)
3934 {
3935 unsigned int max_burst;
3936
3937 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3938 return 0;
3939
3940 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3941 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3942 }
3943
3944 /*
3945 * Returns the number of packets in the last "burst" of packets. This field is
3946 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3947 * the last burst packet count is equal to the total number of packets in the
3948 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3949 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3950 * contain 1 to (bMaxBurst + 1) packets.
3951 */
xhci_get_last_burst_packet_count(struct xhci_hcd * xhci,struct urb * urb,unsigned int total_packet_count)3952 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3953 struct urb *urb, unsigned int total_packet_count)
3954 {
3955 unsigned int max_burst;
3956 unsigned int residue;
3957
3958 if (xhci->hci_version < 0x100)
3959 return 0;
3960
3961 if (urb->dev->speed >= USB_SPEED_SUPER) {
3962 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3963 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3964 residue = total_packet_count % (max_burst + 1);
3965 /* If residue is zero, the last burst contains (max_burst + 1)
3966 * number of packets, but the TLBPC field is zero-based.
3967 */
3968 if (residue == 0)
3969 return max_burst;
3970 return residue - 1;
3971 }
3972 if (total_packet_count == 0)
3973 return 0;
3974 return total_packet_count - 1;
3975 }
3976
3977 /*
3978 * Calculates Frame ID field of the isochronous TRB identifies the
3979 * target frame that the Interval associated with this Isochronous
3980 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3981 *
3982 * Returns actual frame id on success, negative value on error.
3983 */
xhci_get_isoc_frame_id(struct xhci_hcd * xhci,struct urb * urb,int index)3984 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3985 struct urb *urb, int index)
3986 {
3987 int start_frame, ist, ret = 0;
3988 int start_frame_id, end_frame_id, current_frame_id;
3989
3990 if (urb->dev->speed == USB_SPEED_LOW ||
3991 urb->dev->speed == USB_SPEED_FULL)
3992 start_frame = urb->start_frame + index * urb->interval;
3993 else
3994 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3995
3996 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3997 *
3998 * If bit [3] of IST is cleared to '0', software can add a TRB no
3999 * later than IST[2:0] Microframes before that TRB is scheduled to
4000 * be executed.
4001 * If bit [3] of IST is set to '1', software can add a TRB no later
4002 * than IST[2:0] Frames before that TRB is scheduled to be executed.
4003 */
4004 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4005 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4006 ist <<= 3;
4007
4008 /* Software shall not schedule an Isoch TD with a Frame ID value that
4009 * is less than the Start Frame ID or greater than the End Frame ID,
4010 * where:
4011 *
4012 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
4013 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
4014 *
4015 * Both the End Frame ID and Start Frame ID values are calculated
4016 * in microframes. When software determines the valid Frame ID value;
4017 * The End Frame ID value should be rounded down to the nearest Frame
4018 * boundary, and the Start Frame ID value should be rounded up to the
4019 * nearest Frame boundary.
4020 */
4021 current_frame_id = readl(&xhci->run_regs->microframe_index);
4022 start_frame_id = roundup(current_frame_id + ist + 1, 8);
4023 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
4024
4025 start_frame &= 0x7ff;
4026 start_frame_id = (start_frame_id >> 3) & 0x7ff;
4027 end_frame_id = (end_frame_id >> 3) & 0x7ff;
4028
4029 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
4030 __func__, index, readl(&xhci->run_regs->microframe_index),
4031 start_frame_id, end_frame_id, start_frame);
4032
4033 if (start_frame_id < end_frame_id) {
4034 if (start_frame > end_frame_id ||
4035 start_frame < start_frame_id)
4036 ret = -EINVAL;
4037 } else if (start_frame_id > end_frame_id) {
4038 if ((start_frame > end_frame_id &&
4039 start_frame < start_frame_id))
4040 ret = -EINVAL;
4041 } else {
4042 ret = -EINVAL;
4043 }
4044
4045 if (index == 0) {
4046 if (ret == -EINVAL || start_frame == start_frame_id) {
4047 start_frame = start_frame_id + 1;
4048 if (urb->dev->speed == USB_SPEED_LOW ||
4049 urb->dev->speed == USB_SPEED_FULL)
4050 urb->start_frame = start_frame;
4051 else
4052 urb->start_frame = start_frame << 3;
4053 ret = 0;
4054 }
4055 }
4056
4057 if (ret) {
4058 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4059 start_frame, current_frame_id, index,
4060 start_frame_id, end_frame_id);
4061 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
4062 return ret;
4063 }
4064
4065 return start_frame;
4066 }
4067
4068 /* Check if we should generate event interrupt for a TD in an isoc URB */
trb_block_event_intr(struct xhci_hcd * xhci,int num_tds,int i)4069 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
4070 {
4071 if (xhci->hci_version < 0x100)
4072 return false;
4073 /* always generate an event interrupt for the last TD */
4074 if (i == num_tds - 1)
4075 return false;
4076 /*
4077 * If AVOID_BEI is set the host handles full event rings poorly,
4078 * generate an event at least every 8th TD to clear the event ring
4079 */
4080 if (i && xhci->quirks & XHCI_AVOID_BEI)
4081 return !!(i % xhci->isoc_bei_interval);
4082
4083 return true;
4084 }
4085
4086 /* This is for isoc transfer */
xhci_queue_isoc_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)4087 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
4088 struct urb *urb, int slot_id, unsigned int ep_index)
4089 {
4090 struct xhci_ring *ep_ring;
4091 struct urb_priv *urb_priv;
4092 struct xhci_td *td;
4093 int num_tds, trbs_per_td;
4094 struct xhci_generic_trb *start_trb;
4095 bool first_trb;
4096 int start_cycle;
4097 u32 field, length_field;
4098 int running_total, trb_buff_len, td_len, td_remain_len, ret;
4099 u64 start_addr, addr;
4100 int i, j;
4101 bool more_trbs_coming;
4102 struct xhci_virt_ep *xep;
4103 int frame_id;
4104
4105 xep = &xhci->devs[slot_id]->eps[ep_index];
4106 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
4107
4108 num_tds = urb->number_of_packets;
4109 if (num_tds < 1) {
4110 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4111 return -EINVAL;
4112 }
4113 start_addr = (u64) urb->transfer_dma;
4114 start_trb = &ep_ring->enqueue->generic;
4115 start_cycle = ep_ring->cycle_state;
4116
4117 urb_priv = urb->hcpriv;
4118 /* Queue the TRBs for each TD, even if they are zero-length */
4119 for (i = 0; i < num_tds; i++) {
4120 unsigned int total_pkt_count, max_pkt;
4121 unsigned int burst_count, last_burst_pkt_count;
4122 u32 sia_frame_id;
4123
4124 first_trb = true;
4125 running_total = 0;
4126 addr = start_addr + urb->iso_frame_desc[i].offset;
4127 td_len = urb->iso_frame_desc[i].length;
4128 td_remain_len = td_len;
4129 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4130 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4131
4132 /* A zero-length transfer still involves at least one packet. */
4133 if (total_pkt_count == 0)
4134 total_pkt_count++;
4135 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4136 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4137 urb, total_pkt_count);
4138
4139 trbs_per_td = count_isoc_trbs_needed(urb, i);
4140
4141 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4142 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4143 if (ret < 0) {
4144 if (i == 0)
4145 return ret;
4146 goto cleanup;
4147 }
4148 td = &urb_priv->td[i];
4149 td->num_trbs = trbs_per_td;
4150 /* use SIA as default, if frame id is used overwrite it */
4151 sia_frame_id = TRB_SIA;
4152 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4153 HCC_CFC(xhci->hcc_params)) {
4154 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4155 if (frame_id >= 0)
4156 sia_frame_id = TRB_FRAME_ID(frame_id);
4157 }
4158 /*
4159 * Set isoc specific data for the first TRB in a TD.
4160 * Prevent HW from getting the TRBs by keeping the cycle state
4161 * inverted in the first TDs isoc TRB.
4162 */
4163 field = TRB_TYPE(TRB_ISOC) |
4164 TRB_TLBPC(last_burst_pkt_count) |
4165 sia_frame_id |
4166 (i ? ep_ring->cycle_state : !start_cycle);
4167
4168 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4169 if (!xep->use_extended_tbc)
4170 field |= TRB_TBC(burst_count);
4171
4172 /* fill the rest of the TRB fields, and remaining normal TRBs */
4173 for (j = 0; j < trbs_per_td; j++) {
4174 u32 remainder = 0;
4175
4176 /* only first TRB is isoc, overwrite otherwise */
4177 if (!first_trb)
4178 field = TRB_TYPE(TRB_NORMAL) |
4179 ep_ring->cycle_state;
4180
4181 /* Only set interrupt on short packet for IN EPs */
4182 if (usb_urb_dir_in(urb))
4183 field |= TRB_ISP;
4184
4185 /* Set the chain bit for all except the last TRB */
4186 if (j < trbs_per_td - 1) {
4187 more_trbs_coming = true;
4188 field |= TRB_CHAIN;
4189 } else {
4190 more_trbs_coming = false;
4191 td->last_trb = ep_ring->enqueue;
4192 td->last_trb_seg = ep_ring->enq_seg;
4193 field |= TRB_IOC;
4194 if (trb_block_event_intr(xhci, num_tds, i))
4195 field |= TRB_BEI;
4196 }
4197 /* Calculate TRB length */
4198 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4199 if (trb_buff_len > td_remain_len)
4200 trb_buff_len = td_remain_len;
4201
4202 /* Set the TRB length, TD size, & interrupter fields. */
4203 remainder = xhci_td_remainder(xhci, running_total,
4204 trb_buff_len, td_len,
4205 urb, more_trbs_coming);
4206
4207 length_field = TRB_LEN(trb_buff_len) |
4208 TRB_INTR_TARGET(0);
4209
4210 /* xhci 1.1 with ETE uses TD Size field for TBC */
4211 if (first_trb && xep->use_extended_tbc)
4212 length_field |= TRB_TD_SIZE_TBC(burst_count);
4213 else
4214 length_field |= TRB_TD_SIZE(remainder);
4215 first_trb = false;
4216
4217 queue_trb(xhci, ep_ring, more_trbs_coming,
4218 lower_32_bits(addr),
4219 upper_32_bits(addr),
4220 length_field,
4221 field);
4222 running_total += trb_buff_len;
4223
4224 addr += trb_buff_len;
4225 td_remain_len -= trb_buff_len;
4226 }
4227
4228 /* Check TD length */
4229 if (running_total != td_len) {
4230 xhci_err(xhci, "ISOC TD length unmatch\n");
4231 ret = -EINVAL;
4232 goto cleanup;
4233 }
4234 }
4235
4236 /* store the next frame id */
4237 if (HCC_CFC(xhci->hcc_params))
4238 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4239
4240 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4241 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4242 usb_amd_quirk_pll_disable();
4243 }
4244 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4245
4246 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4247 start_cycle, start_trb);
4248 return 0;
4249 cleanup:
4250 /* Clean up a partially enqueued isoc transfer. */
4251
4252 for (i--; i >= 0; i--)
4253 list_del_init(&urb_priv->td[i].td_list);
4254
4255 /* Use the first TD as a temporary variable to turn the TDs we've queued
4256 * into No-ops with a software-owned cycle bit. That way the hardware
4257 * won't accidentally start executing bogus TDs when we partially
4258 * overwrite them. td->first_trb and td->start_seg are already set.
4259 */
4260 urb_priv->td[0].last_trb = ep_ring->enqueue;
4261 /* Every TRB except the first & last will have its cycle bit flipped. */
4262 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4263
4264 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4265 ep_ring->enqueue = urb_priv->td[0].first_trb;
4266 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4267 ep_ring->cycle_state = start_cycle;
4268 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4269 return ret;
4270 }
4271
4272 /*
4273 * Check transfer ring to guarantee there is enough room for the urb.
4274 * Update ISO URB start_frame and interval.
4275 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4276 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4277 * Contiguous Frame ID is not supported by HC.
4278 */
xhci_queue_isoc_tx_prepare(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)4279 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4280 struct urb *urb, int slot_id, unsigned int ep_index)
4281 {
4282 struct xhci_virt_device *xdev;
4283 struct xhci_ring *ep_ring;
4284 struct xhci_ep_ctx *ep_ctx;
4285 int start_frame;
4286 int num_tds, num_trbs, i;
4287 int ret;
4288 struct xhci_virt_ep *xep;
4289 int ist;
4290
4291 xdev = xhci->devs[slot_id];
4292 xep = &xhci->devs[slot_id]->eps[ep_index];
4293 ep_ring = xdev->eps[ep_index].ring;
4294 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4295
4296 num_trbs = 0;
4297 num_tds = urb->number_of_packets;
4298 for (i = 0; i < num_tds; i++)
4299 num_trbs += count_isoc_trbs_needed(urb, i);
4300
4301 /* Check the ring to guarantee there is enough room for the whole urb.
4302 * Do not insert any td of the urb to the ring if the check failed.
4303 */
4304 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4305 num_trbs, mem_flags);
4306 if (ret)
4307 return ret;
4308
4309 /*
4310 * Check interval value. This should be done before we start to
4311 * calculate the start frame value.
4312 */
4313 check_interval(xhci, urb, ep_ctx);
4314
4315 /* Calculate the start frame and put it in urb->start_frame. */
4316 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4317 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4318 urb->start_frame = xep->next_frame_id;
4319 goto skip_start_over;
4320 }
4321 }
4322
4323 start_frame = readl(&xhci->run_regs->microframe_index);
4324 start_frame &= 0x3fff;
4325 /*
4326 * Round up to the next frame and consider the time before trb really
4327 * gets scheduled by hardare.
4328 */
4329 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4330 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4331 ist <<= 3;
4332 start_frame += ist + XHCI_CFC_DELAY;
4333 start_frame = roundup(start_frame, 8);
4334
4335 /*
4336 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4337 * is greate than 8 microframes.
4338 */
4339 if (urb->dev->speed == USB_SPEED_LOW ||
4340 urb->dev->speed == USB_SPEED_FULL) {
4341 start_frame = roundup(start_frame, urb->interval << 3);
4342 urb->start_frame = start_frame >> 3;
4343 } else {
4344 start_frame = roundup(start_frame, urb->interval);
4345 urb->start_frame = start_frame;
4346 }
4347
4348 skip_start_over:
4349
4350 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4351 }
4352
4353 /**** Command Ring Operations ****/
4354
4355 /* Generic function for queueing a command TRB on the command ring.
4356 * Check to make sure there's room on the command ring for one command TRB.
4357 * Also check that there's room reserved for commands that must not fail.
4358 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4359 * then only check for the number of reserved spots.
4360 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4361 * because the command event handler may want to resubmit a failed command.
4362 */
queue_command(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 field1,u32 field2,u32 field3,u32 field4,bool command_must_succeed)4363 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4364 u32 field1, u32 field2,
4365 u32 field3, u32 field4, bool command_must_succeed)
4366 {
4367 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4368 int ret;
4369
4370 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4371 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4372 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4373 return -ESHUTDOWN;
4374 }
4375
4376 if (!command_must_succeed)
4377 reserved_trbs++;
4378
4379 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4380 reserved_trbs, GFP_ATOMIC);
4381 if (ret < 0) {
4382 xhci_err(xhci, "ERR: No room for command on command ring\n");
4383 if (command_must_succeed)
4384 xhci_err(xhci, "ERR: Reserved TRB counting for "
4385 "unfailable commands failed.\n");
4386 return ret;
4387 }
4388
4389 cmd->command_trb = xhci->cmd_ring->enqueue;
4390
4391 /* if there are no other commands queued we start the timeout timer */
4392 if (list_empty(&xhci->cmd_list)) {
4393 xhci->current_cmd = cmd;
4394 xhci_mod_cmd_timer(xhci);
4395 }
4396
4397 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4398
4399 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4400 field4 | xhci->cmd_ring->cycle_state);
4401 return 0;
4402 }
4403
4404 /* Queue a slot enable or disable request on the command ring */
xhci_queue_slot_control(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 trb_type,u32 slot_id)4405 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4406 u32 trb_type, u32 slot_id)
4407 {
4408 return queue_command(xhci, cmd, 0, 0, 0,
4409 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4410 }
4411
4412 /* Queue an address device command TRB */
xhci_queue_address_device(struct xhci_hcd * xhci,struct xhci_command * cmd,dma_addr_t in_ctx_ptr,u32 slot_id,enum xhci_setup_dev setup)4413 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4414 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4415 {
4416 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4417 upper_32_bits(in_ctx_ptr), 0,
4418 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4419 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4420 }
4421
xhci_queue_vendor_command(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 field1,u32 field2,u32 field3,u32 field4)4422 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4423 u32 field1, u32 field2, u32 field3, u32 field4)
4424 {
4425 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4426 }
4427
4428 /* Queue a reset device command TRB */
xhci_queue_reset_device(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 slot_id)4429 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4430 u32 slot_id)
4431 {
4432 return queue_command(xhci, cmd, 0, 0, 0,
4433 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4434 false);
4435 }
4436
4437 /* Queue a configure endpoint command TRB */
xhci_queue_configure_endpoint(struct xhci_hcd * xhci,struct xhci_command * cmd,dma_addr_t in_ctx_ptr,u32 slot_id,bool command_must_succeed)4438 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4439 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4440 u32 slot_id, bool command_must_succeed)
4441 {
4442 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4443 upper_32_bits(in_ctx_ptr), 0,
4444 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4445 command_must_succeed);
4446 }
4447
4448 /* Queue an evaluate context command TRB */
xhci_queue_evaluate_context(struct xhci_hcd * xhci,struct xhci_command * cmd,dma_addr_t in_ctx_ptr,u32 slot_id,bool command_must_succeed)4449 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4450 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4451 {
4452 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4453 upper_32_bits(in_ctx_ptr), 0,
4454 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4455 command_must_succeed);
4456 }
4457
4458 /*
4459 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4460 * activity on an endpoint that is about to be suspended.
4461 */
xhci_queue_stop_endpoint(struct xhci_hcd * xhci,struct xhci_command * cmd,int slot_id,unsigned int ep_index,int suspend)4462 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4463 int slot_id, unsigned int ep_index, int suspend)
4464 {
4465 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4466 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4467 u32 type = TRB_TYPE(TRB_STOP_RING);
4468 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4469
4470 return queue_command(xhci, cmd, 0, 0, 0,
4471 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4472 }
4473
xhci_queue_reset_ep(struct xhci_hcd * xhci,struct xhci_command * cmd,int slot_id,unsigned int ep_index,enum xhci_ep_reset_type reset_type)4474 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4475 int slot_id, unsigned int ep_index,
4476 enum xhci_ep_reset_type reset_type)
4477 {
4478 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4479 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4480 u32 type = TRB_TYPE(TRB_RESET_EP);
4481
4482 if (reset_type == EP_SOFT_RESET)
4483 type |= TRB_TSP;
4484
4485 return queue_command(xhci, cmd, 0, 0, 0,
4486 trb_slot_id | trb_ep_index | type, false);
4487 }
4488