1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver for R-Car SoCs 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 */ 7 8 #include <linux/firmware.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/of.h> 12 #include <linux/usb/phy.h> 13 #include <linux/sys_soc.h> 14 15 #include "xhci.h" 16 #include "xhci-plat.h" 17 #include "xhci-rcar.h" 18 19 /* 20 * - The V3 firmware is for r8a7796 (with good performance) and r8a7795 es2.0 21 * or later. 22 * - The V2 firmware can be used on both r8a7795 (es1.x) and r8a7796. 23 * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes 24 * performance degradation. So, this driver continues to use the V1 if R-Car 25 * Gen2. 26 * - The V1 firmware is impossible to use on R-Car Gen3. 27 */ 28 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1); 29 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2); 30 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3); 31 32 /*** Register Offset ***/ 33 #define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */ 34 #define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */ 35 #define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */ 36 37 #define RCAR_USB3_LCLK 0xa44 /* LCLK Select */ 38 #define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */ 39 #define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */ 40 #define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */ 41 #define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */ 42 #define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */ 43 44 /*** Register Settings ***/ 45 /* Interrupt Enable */ 46 #define RCAR_USB3_INT_XHC_ENA 0x00000001 47 #define RCAR_USB3_INT_PME_ENA 0x00000002 48 #define RCAR_USB3_INT_HSE_ENA 0x00000004 49 #define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \ 50 RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA) 51 52 /* FW Download Control & Status */ 53 #define RCAR_USB3_DL_CTRL_ENABLE 0x00000001 54 #define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010 55 #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100 56 57 /* LCLK Select */ 58 #define RCAR_USB3_LCLK_ENA_VAL 0x01030001 59 60 /* USB3.0 Configuration */ 61 #define RCAR_USB3_CONF1_VAL 0x00030204 62 #define RCAR_USB3_CONF2_VAL 0x00030300 63 #define RCAR_USB3_CONF3_VAL 0x13802007 64 65 /* USB3.0 Polarity */ 66 #define RCAR_USB3_RX_POL_VAL BIT(21) 67 #define RCAR_USB3_TX_POL_VAL BIT(4) 68 69 /* For soc_device_attribute */ 70 #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */ 71 #define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */ 72 73 static const struct soc_device_attribute rcar_quirks_match[] = { 74 { 75 .soc_id = "r8a7795", .revision = "ES1.*", 76 .data = (void *)RCAR_XHCI_FIRMWARE_V2, 77 }, 78 { 79 .soc_id = "r8a7795", 80 .data = (void *)RCAR_XHCI_FIRMWARE_V3, 81 }, 82 { 83 .soc_id = "r8a7796", 84 .data = (void *)RCAR_XHCI_FIRMWARE_V3, 85 }, 86 { /* sentinel */ }, 87 }; 88 89 static void xhci_rcar_start_gen2(struct usb_hcd *hcd) 90 { 91 /* LCLK Select */ 92 writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK); 93 /* USB3.0 Configuration */ 94 writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1); 95 writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2); 96 writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3); 97 /* USB3.0 Polarity */ 98 writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL); 99 writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL); 100 } 101 102 static int xhci_rcar_is_gen2(struct device *dev) 103 { 104 struct device_node *node = dev->of_node; 105 106 return of_device_is_compatible(node, "renesas,xhci-r8a7790") || 107 of_device_is_compatible(node, "renesas,xhci-r8a7791") || 108 of_device_is_compatible(node, "renesas,xhci-r8a7793") || 109 of_device_is_compatible(node, "renensas,rcar-gen2-xhci"); 110 } 111 112 static int xhci_rcar_is_gen3(struct device *dev) 113 { 114 struct device_node *node = dev->of_node; 115 116 return of_device_is_compatible(node, "renesas,xhci-r8a7795") || 117 of_device_is_compatible(node, "renesas,xhci-r8a7796") || 118 of_device_is_compatible(node, "renesas,rcar-gen3-xhci"); 119 } 120 121 void xhci_rcar_start(struct usb_hcd *hcd) 122 { 123 u32 temp; 124 125 if (hcd->regs != NULL) { 126 /* Interrupt Enable */ 127 temp = readl(hcd->regs + RCAR_USB3_INT_ENA); 128 temp |= RCAR_USB3_INT_ENA_VAL; 129 writel(temp, hcd->regs + RCAR_USB3_INT_ENA); 130 if (xhci_rcar_is_gen2(hcd->self.controller)) 131 xhci_rcar_start_gen2(hcd); 132 } 133 } 134 135 static int xhci_rcar_download_firmware(struct usb_hcd *hcd) 136 { 137 struct device *dev = hcd->self.controller; 138 void __iomem *regs = hcd->regs; 139 struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); 140 const struct firmware *fw; 141 int retval, index, j, time; 142 int timeout = 10000; 143 u32 data, val, temp; 144 u32 quirks = 0; 145 const struct soc_device_attribute *attr; 146 const char *firmware_name; 147 148 attr = soc_device_match(rcar_quirks_match); 149 if (attr) 150 quirks = (uintptr_t)attr->data; 151 152 if (quirks & RCAR_XHCI_FIRMWARE_V2) 153 firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2; 154 else if (quirks & RCAR_XHCI_FIRMWARE_V3) 155 firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3; 156 else 157 firmware_name = priv->firmware_name; 158 159 /* request R-Car USB3.0 firmware */ 160 retval = request_firmware(&fw, firmware_name, dev); 161 if (retval) 162 return retval; 163 164 /* download R-Car USB3.0 firmware */ 165 temp = readl(regs + RCAR_USB3_DL_CTRL); 166 temp |= RCAR_USB3_DL_CTRL_ENABLE; 167 writel(temp, regs + RCAR_USB3_DL_CTRL); 168 169 for (index = 0; index < fw->size; index += 4) { 170 /* to avoid reading beyond the end of the buffer */ 171 for (data = 0, j = 3; j >= 0; j--) { 172 if ((j + index) < fw->size) 173 data |= fw->data[index + j] << (8 * j); 174 } 175 writel(data, regs + RCAR_USB3_FW_DATA0); 176 temp = readl(regs + RCAR_USB3_DL_CTRL); 177 temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0; 178 writel(temp, regs + RCAR_USB3_DL_CTRL); 179 180 for (time = 0; time < timeout; time++) { 181 val = readl(regs + RCAR_USB3_DL_CTRL); 182 if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0) 183 break; 184 udelay(1); 185 } 186 if (time == timeout) { 187 retval = -ETIMEDOUT; 188 break; 189 } 190 } 191 192 temp = readl(regs + RCAR_USB3_DL_CTRL); 193 temp &= ~RCAR_USB3_DL_CTRL_ENABLE; 194 writel(temp, regs + RCAR_USB3_DL_CTRL); 195 196 for (time = 0; time < timeout; time++) { 197 val = readl(regs + RCAR_USB3_DL_CTRL); 198 if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) { 199 retval = 0; 200 break; 201 } 202 udelay(1); 203 } 204 if (time == timeout) 205 retval = -ETIMEDOUT; 206 207 release_firmware(fw); 208 209 return retval; 210 } 211 212 /* This function needs to initialize a "phy" of usb before */ 213 int xhci_rcar_init_quirk(struct usb_hcd *hcd) 214 { 215 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 216 217 /* If hcd->regs is NULL, we don't just call the following function */ 218 if (!hcd->regs) 219 return 0; 220 221 /* 222 * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set 223 * to 1. However, these SoCs don't support 64-bit address memory 224 * pointers. So, this driver clears the AC64 bit of xhci->hcc_params 225 * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in 226 * xhci_gen_setup(). 227 */ 228 if (xhci_rcar_is_gen2(hcd->self.controller) || 229 xhci_rcar_is_gen3(hcd->self.controller)) 230 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 231 232 return xhci_rcar_download_firmware(hcd); 233 } 234 235 int xhci_rcar_resume_quirk(struct usb_hcd *hcd) 236 { 237 int ret; 238 239 ret = xhci_rcar_download_firmware(hcd); 240 if (!ret) 241 xhci_rcar_start(hcd); 242 243 return ret; 244 } 245