1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/acpi.h> 27 28 #include "xhci.h" 29 #include "xhci-trace.h" 30 31 #define SSIC_PORT_NUM 2 32 #define SSIC_PORT_CFG2 0x880c 33 #define SSIC_PORT_CFG2_OFFSET 0x30 34 #define PROG_DONE (1 << 30) 35 #define SSIC_PORT_UNUSED (1 << 31) 36 37 /* Device for a quirk */ 38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 42 43 #define PCI_VENDOR_ID_ETRON 0x1b6f 44 #define PCI_DEVICE_ID_EJ168 0x7023 45 46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 54 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 55 56 static const char hcd_name[] = "xhci_hcd"; 57 58 static struct hc_driver __read_mostly xhci_pci_hc_driver; 59 60 static int xhci_pci_setup(struct usb_hcd *hcd); 61 62 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 63 .reset = xhci_pci_setup, 64 }; 65 66 /* called after powerup, by probe or system-pm "wakeup" */ 67 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 68 { 69 /* 70 * TODO: Implement finding debug ports later. 71 * TODO: see if there are any quirks that need to be added to handle 72 * new extended capabilities. 73 */ 74 75 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 76 if (!pci_set_mwi(pdev)) 77 xhci_dbg(xhci, "MWI active\n"); 78 79 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 80 return 0; 81 } 82 83 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 84 { 85 struct pci_dev *pdev = to_pci_dev(dev); 86 87 /* Look for vendor-specific quirks */ 88 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 89 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 90 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 91 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 92 pdev->revision == 0x0) { 93 xhci->quirks |= XHCI_RESET_EP_QUIRK; 94 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 95 "QUIRK: Fresco Logic xHC needs configure" 96 " endpoint cmd after reset endpoint"); 97 } 98 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 99 pdev->revision == 0x4) { 100 xhci->quirks |= XHCI_SLOW_SUSPEND; 101 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 102 "QUIRK: Fresco Logic xHC revision %u" 103 "must be suspended extra slowly", 104 pdev->revision); 105 } 106 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 107 xhci->quirks |= XHCI_BROKEN_STREAMS; 108 /* Fresco Logic confirms: all revisions of this chip do not 109 * support MSI, even though some of them claim to in their PCI 110 * capabilities. 111 */ 112 xhci->quirks |= XHCI_BROKEN_MSI; 113 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 114 "QUIRK: Fresco Logic revision %u " 115 "has broken MSI implementation", 116 pdev->revision); 117 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 118 } 119 120 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 121 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 122 xhci->quirks |= XHCI_BROKEN_STREAMS; 123 124 if (pdev->vendor == PCI_VENDOR_ID_NEC) 125 xhci->quirks |= XHCI_NEC_HOST; 126 127 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 128 xhci->quirks |= XHCI_AMD_0x96_HOST; 129 130 /* AMD PLL quirk */ 131 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 132 xhci->quirks |= XHCI_AMD_PLL_FIX; 133 134 if (pdev->vendor == PCI_VENDOR_ID_AMD) 135 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 136 137 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 138 xhci->quirks |= XHCI_LPM_SUPPORT; 139 xhci->quirks |= XHCI_INTEL_HOST; 140 xhci->quirks |= XHCI_AVOID_BEI; 141 } 142 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 143 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 144 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 145 xhci->limit_active_eps = 64; 146 xhci->quirks |= XHCI_SW_BW_CHECKING; 147 /* 148 * PPT desktop boards DH77EB and DH77DF will power back on after 149 * a few seconds of being shutdown. The fix for this is to 150 * switch the ports from xHCI to EHCI on shutdown. We can't use 151 * DMI information to find those particular boards (since each 152 * vendor will change the board name), so we have to key off all 153 * PPT chipsets. 154 */ 155 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 156 } 157 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 158 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 159 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 160 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 161 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 162 } 163 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 164 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 165 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 166 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 167 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 168 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 169 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) { 170 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 171 } 172 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 173 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { 174 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 175 } 176 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 177 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 178 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 179 xhci->quirks |= XHCI_MISSING_CAS; 180 181 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 182 pdev->device == PCI_DEVICE_ID_EJ168) { 183 xhci->quirks |= XHCI_RESET_ON_RESUME; 184 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 185 xhci->quirks |= XHCI_BROKEN_STREAMS; 186 } 187 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 188 pdev->device == 0x0015) 189 xhci->quirks |= XHCI_RESET_ON_RESUME; 190 if (pdev->vendor == PCI_VENDOR_ID_VIA) 191 xhci->quirks |= XHCI_RESET_ON_RESUME; 192 193 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 194 if (pdev->vendor == PCI_VENDOR_ID_VIA && 195 pdev->device == 0x3432) 196 xhci->quirks |= XHCI_BROKEN_STREAMS; 197 198 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 199 pdev->device == 0x1042) 200 xhci->quirks |= XHCI_BROKEN_STREAMS; 201 202 if (xhci->quirks & XHCI_RESET_ON_RESUME) 203 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 204 "QUIRK: Resetting on resume"); 205 } 206 207 #ifdef CONFIG_ACPI 208 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 209 { 210 static const u8 intel_dsm_uuid[] = { 211 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, 212 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23, 213 }; 214 union acpi_object *obj; 215 216 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, 217 NULL); 218 ACPI_FREE(obj); 219 } 220 #else 221 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 222 #endif /* CONFIG_ACPI */ 223 224 /* called during probe() after chip reset completes */ 225 static int xhci_pci_setup(struct usb_hcd *hcd) 226 { 227 struct xhci_hcd *xhci; 228 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 229 int retval; 230 231 xhci = hcd_to_xhci(hcd); 232 if (!xhci->sbrn) 233 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 234 235 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 236 if (retval) 237 return retval; 238 239 if (!usb_hcd_is_primary_hcd(hcd)) 240 return 0; 241 242 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 243 244 /* Find any debug ports */ 245 retval = xhci_pci_reinit(xhci, pdev); 246 if (!retval) 247 return retval; 248 249 return retval; 250 } 251 252 /* 253 * We need to register our own PCI probe function (instead of the USB core's 254 * function) in order to create a second roothub under xHCI. 255 */ 256 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 257 { 258 int retval; 259 struct xhci_hcd *xhci; 260 struct hc_driver *driver; 261 struct usb_hcd *hcd; 262 263 driver = (struct hc_driver *)id->driver_data; 264 265 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 266 pm_runtime_get_noresume(&dev->dev); 267 268 /* Register the USB 2.0 roothub. 269 * FIXME: USB core must know to register the USB 2.0 roothub first. 270 * This is sort of silly, because we could just set the HCD driver flags 271 * to say USB 2.0, but I'm not sure what the implications would be in 272 * the other parts of the HCD code. 273 */ 274 retval = usb_hcd_pci_probe(dev, id); 275 276 if (retval) 277 goto put_runtime_pm; 278 279 /* USB 2.0 roothub is stored in the PCI device now. */ 280 hcd = dev_get_drvdata(&dev->dev); 281 xhci = hcd_to_xhci(hcd); 282 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 283 pci_name(dev), hcd); 284 if (!xhci->shared_hcd) { 285 retval = -ENOMEM; 286 goto dealloc_usb2_hcd; 287 } 288 289 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 290 IRQF_SHARED); 291 if (retval) 292 goto put_usb3_hcd; 293 /* Roothub already marked as USB 3.0 speed */ 294 295 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 296 HCC_MAX_PSA(xhci->hcc_params) >= 4) 297 xhci->shared_hcd->can_do_streams = 1; 298 299 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 300 xhci_pme_acpi_rtd3_enable(dev); 301 302 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 303 pm_runtime_put_noidle(&dev->dev); 304 305 return 0; 306 307 put_usb3_hcd: 308 usb_put_hcd(xhci->shared_hcd); 309 dealloc_usb2_hcd: 310 usb_hcd_pci_remove(dev); 311 put_runtime_pm: 312 pm_runtime_put_noidle(&dev->dev); 313 return retval; 314 } 315 316 static void xhci_pci_remove(struct pci_dev *dev) 317 { 318 struct xhci_hcd *xhci; 319 320 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 321 xhci->xhc_state |= XHCI_STATE_REMOVING; 322 if (xhci->shared_hcd) { 323 usb_remove_hcd(xhci->shared_hcd); 324 usb_put_hcd(xhci->shared_hcd); 325 } 326 327 /* Workaround for spurious wakeups at shutdown with HSW */ 328 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 329 pci_set_power_state(dev, PCI_D3hot); 330 331 usb_hcd_pci_remove(dev); 332 } 333 334 #ifdef CONFIG_PM 335 /* 336 * In some Intel xHCI controllers, in order to get D3 working, 337 * through a vendor specific SSIC CONFIG register at offset 0x883c, 338 * SSIC PORT need to be marked as "unused" before putting xHCI 339 * into D3. After D3 exit, the SSIC port need to be marked as "used". 340 * Without this change, xHCI might not enter D3 state. 341 */ 342 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 343 { 344 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 345 u32 val; 346 void __iomem *reg; 347 int i; 348 349 for (i = 0; i < SSIC_PORT_NUM; i++) { 350 reg = (void __iomem *) xhci->cap_regs + 351 SSIC_PORT_CFG2 + 352 i * SSIC_PORT_CFG2_OFFSET; 353 354 /* Notify SSIC that SSIC profile programming is not done. */ 355 val = readl(reg) & ~PROG_DONE; 356 writel(val, reg); 357 358 /* Mark SSIC port as unused(suspend) or used(resume) */ 359 val = readl(reg); 360 if (suspend) 361 val |= SSIC_PORT_UNUSED; 362 else 363 val &= ~SSIC_PORT_UNUSED; 364 writel(val, reg); 365 366 /* Notify SSIC that SSIC profile programming is done */ 367 val = readl(reg) | PROG_DONE; 368 writel(val, reg); 369 readl(reg); 370 } 371 } 372 373 /* 374 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 375 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 376 */ 377 static void xhci_pme_quirk(struct usb_hcd *hcd) 378 { 379 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 380 void __iomem *reg; 381 u32 val; 382 383 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 384 val = readl(reg); 385 writel(val | BIT(28), reg); 386 readl(reg); 387 } 388 389 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 390 { 391 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 392 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 393 int ret; 394 395 /* 396 * Systems with the TI redriver that loses port status change events 397 * need to have the registers polled during D3, so avoid D3cold. 398 */ 399 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 400 pci_d3cold_disable(pdev); 401 402 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 403 xhci_pme_quirk(hcd); 404 405 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 406 xhci_ssic_port_unused_quirk(hcd, true); 407 408 ret = xhci_suspend(xhci, do_wakeup); 409 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 410 xhci_ssic_port_unused_quirk(hcd, false); 411 412 return ret; 413 } 414 415 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 416 { 417 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 418 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 419 int retval = 0; 420 421 /* The BIOS on systems with the Intel Panther Point chipset may or may 422 * not support xHCI natively. That means that during system resume, it 423 * may switch the ports back to EHCI so that users can use their 424 * keyboard to select a kernel from GRUB after resume from hibernate. 425 * 426 * The BIOS is supposed to remember whether the OS had xHCI ports 427 * enabled before resume, and switch the ports back to xHCI when the 428 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 429 * writers. 430 * 431 * Unconditionally switch the ports back to xHCI after a system resume. 432 * It should not matter whether the EHCI or xHCI controller is 433 * resumed first. It's enough to do the switchover in xHCI because 434 * USB core won't notice anything as the hub driver doesn't start 435 * running again until after all the devices (including both EHCI and 436 * xHCI host controllers) have been resumed. 437 */ 438 439 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 440 usb_enable_intel_xhci_ports(pdev); 441 442 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 443 xhci_ssic_port_unused_quirk(hcd, false); 444 445 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 446 xhci_pme_quirk(hcd); 447 448 retval = xhci_resume(xhci, hibernated); 449 return retval; 450 } 451 #endif /* CONFIG_PM */ 452 453 /*-------------------------------------------------------------------------*/ 454 455 /* PCI driver selection metadata; PCI hotplugging uses this */ 456 static const struct pci_device_id pci_ids[] = { { 457 /* handle any USB 3.0 xHCI controller */ 458 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 459 .driver_data = (unsigned long) &xhci_pci_hc_driver, 460 }, 461 { /* end: all zeroes */ } 462 }; 463 MODULE_DEVICE_TABLE(pci, pci_ids); 464 465 /* pci driver glue; this is a "new style" PCI driver module */ 466 static struct pci_driver xhci_pci_driver = { 467 .name = (char *) hcd_name, 468 .id_table = pci_ids, 469 470 .probe = xhci_pci_probe, 471 .remove = xhci_pci_remove, 472 /* suspend and resume implemented later */ 473 474 .shutdown = usb_hcd_pci_shutdown, 475 #ifdef CONFIG_PM 476 .driver = { 477 .pm = &usb_hcd_pci_pm_ops 478 }, 479 #endif 480 }; 481 482 static int __init xhci_pci_init(void) 483 { 484 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 485 #ifdef CONFIG_PM 486 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 487 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 488 #endif 489 return pci_register_driver(&xhci_pci_driver); 490 } 491 module_init(xhci_pci_init); 492 493 static void __exit xhci_pci_exit(void) 494 { 495 pci_unregister_driver(&xhci_pci_driver); 496 } 497 module_exit(xhci_pci_exit); 498 499 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 500 MODULE_LICENSE("GPL"); 501