1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 #include <linux/reset.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 #include "xhci-pci.h" 20 21 #define SSIC_PORT_NUM 2 22 #define SSIC_PORT_CFG2 0x880c 23 #define SSIC_PORT_CFG2_OFFSET 0x30 24 #define PROG_DONE (1 << 30) 25 #define SSIC_PORT_UNUSED (1 << 31) 26 #define SPARSE_DISABLE_BIT 17 27 #define SPARSE_CNTL_ENABLE 0xC12C 28 29 /* Device for a quirk */ 30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 35 36 #define PCI_VENDOR_ID_ETRON 0x1b6f 37 #define PCI_DEVICE_ID_EJ168 0x7023 38 39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e 62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI 0x464e 63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 64 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI 0xa71e 65 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI 0x7ec0 66 67 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 71 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a 73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b 74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d 75 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e 76 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6 77 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7 78 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c 79 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f 80 81 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 82 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 83 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 84 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 85 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 86 87 static const char hcd_name[] = "xhci_hcd"; 88 89 static struct hc_driver __read_mostly xhci_pci_hc_driver; 90 91 static int xhci_pci_setup(struct usb_hcd *hcd); 92 93 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 94 .reset = xhci_pci_setup, 95 }; 96 97 /* called after powerup, by probe or system-pm "wakeup" */ 98 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 99 { 100 /* 101 * TODO: Implement finding debug ports later. 102 * TODO: see if there are any quirks that need to be added to handle 103 * new extended capabilities. 104 */ 105 106 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 107 if (!pci_set_mwi(pdev)) 108 xhci_dbg(xhci, "MWI active\n"); 109 110 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 111 return 0; 112 } 113 114 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 115 { 116 struct pci_dev *pdev = to_pci_dev(dev); 117 struct xhci_driver_data *driver_data; 118 const struct pci_device_id *id; 119 120 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev); 121 122 if (id && id->driver_data) { 123 driver_data = (struct xhci_driver_data *)id->driver_data; 124 xhci->quirks |= driver_data->quirks; 125 } 126 127 /* Look for vendor-specific quirks */ 128 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 129 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 130 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 131 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 132 pdev->revision == 0x0) { 133 xhci->quirks |= XHCI_RESET_EP_QUIRK; 134 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 135 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 136 } 137 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 138 pdev->revision == 0x4) { 139 xhci->quirks |= XHCI_SLOW_SUSPEND; 140 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 141 "QUIRK: Fresco Logic xHC revision %u" 142 "must be suspended extra slowly", 143 pdev->revision); 144 } 145 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 146 xhci->quirks |= XHCI_BROKEN_STREAMS; 147 /* Fresco Logic confirms: all revisions of this chip do not 148 * support MSI, even though some of them claim to in their PCI 149 * capabilities. 150 */ 151 xhci->quirks |= XHCI_BROKEN_MSI; 152 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 153 "QUIRK: Fresco Logic revision %u " 154 "has broken MSI implementation", 155 pdev->revision); 156 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 157 } 158 159 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 160 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 161 xhci->quirks |= XHCI_BROKEN_STREAMS; 162 163 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 164 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 165 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 166 167 if (pdev->vendor == PCI_VENDOR_ID_NEC) 168 xhci->quirks |= XHCI_NEC_HOST; 169 170 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 171 xhci->quirks |= XHCI_AMD_0x96_HOST; 172 173 /* AMD PLL quirk */ 174 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 175 xhci->quirks |= XHCI_AMD_PLL_FIX; 176 177 if (pdev->vendor == PCI_VENDOR_ID_AMD && 178 (pdev->device == 0x145c || 179 pdev->device == 0x15e0 || 180 pdev->device == 0x15e1 || 181 pdev->device == 0x43bb)) 182 xhci->quirks |= XHCI_SUSPEND_DELAY; 183 184 if (pdev->vendor == PCI_VENDOR_ID_AMD && 185 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 186 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 187 188 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 189 xhci->quirks |= XHCI_DISABLE_SPARSE; 190 xhci->quirks |= XHCI_RESET_ON_RESUME; 191 } 192 193 if (pdev->vendor == PCI_VENDOR_ID_AMD) 194 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 195 196 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 197 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 198 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 199 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 200 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 201 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 202 203 if (pdev->vendor == PCI_VENDOR_ID_AMD && 204 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 205 xhci->quirks |= XHCI_BROKEN_D3COLD; 206 207 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 208 xhci->quirks |= XHCI_LPM_SUPPORT; 209 xhci->quirks |= XHCI_INTEL_HOST; 210 xhci->quirks |= XHCI_AVOID_BEI; 211 } 212 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 213 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 214 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 215 xhci->limit_active_eps = 64; 216 xhci->quirks |= XHCI_SW_BW_CHECKING; 217 /* 218 * PPT desktop boards DH77EB and DH77DF will power back on after 219 * a few seconds of being shutdown. The fix for this is to 220 * switch the ports from xHCI to EHCI on shutdown. We can't use 221 * DMI information to find those particular boards (since each 222 * vendor will change the board name), so we have to key off all 223 * PPT chipsets. 224 */ 225 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 226 } 227 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 228 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 229 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 230 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 231 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 232 } 233 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 234 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 235 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 236 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 237 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 238 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 239 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 240 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 241 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 242 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 243 } 244 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 245 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 246 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 247 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 248 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 249 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 250 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 251 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 252 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 253 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 254 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 255 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 256 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 257 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 258 xhci->quirks |= XHCI_MISSING_CAS; 259 260 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 261 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 262 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 263 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 264 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 265 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 266 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 267 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 268 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 269 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 270 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 271 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI || 272 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI || 273 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI || 274 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 275 pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI || 276 pdev->device == PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI)) 277 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 278 279 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 280 pdev->device == PCI_DEVICE_ID_EJ168) { 281 xhci->quirks |= XHCI_RESET_ON_RESUME; 282 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 283 xhci->quirks |= XHCI_BROKEN_STREAMS; 284 } 285 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 286 pdev->device == 0x0014) { 287 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 288 xhci->quirks |= XHCI_ZERO_64B_REGS; 289 } 290 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 291 pdev->device == 0x0015) { 292 xhci->quirks |= XHCI_RESET_ON_RESUME; 293 xhci->quirks |= XHCI_ZERO_64B_REGS; 294 } 295 if (pdev->vendor == PCI_VENDOR_ID_VIA) 296 xhci->quirks |= XHCI_RESET_ON_RESUME; 297 298 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 299 if (pdev->vendor == PCI_VENDOR_ID_VIA && 300 pdev->device == 0x3432) 301 xhci->quirks |= XHCI_BROKEN_STREAMS; 302 303 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 304 xhci->quirks |= XHCI_LPM_SUPPORT; 305 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; 306 } 307 308 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 309 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) 310 xhci->quirks |= XHCI_BROKEN_STREAMS; 311 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 312 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 313 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 314 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 315 } 316 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 317 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 318 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 319 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 320 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 321 322 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 323 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 324 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 325 326 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 327 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 328 329 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 330 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 331 pdev->device == 0x9026) 332 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 333 334 if (pdev->vendor == PCI_VENDOR_ID_AMD && 335 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 336 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 337 xhci->quirks |= XHCI_NO_SOFT_RETRY; 338 339 if (pdev->vendor == PCI_VENDOR_ID_AMD && 340 (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 || 341 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 || 342 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 || 343 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 || 344 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 || 345 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 || 346 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 || 347 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8)) 348 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 349 350 if (xhci->quirks & XHCI_RESET_ON_RESUME) 351 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 352 "QUIRK: Resetting on resume"); 353 } 354 355 #ifdef CONFIG_ACPI 356 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 357 { 358 static const guid_t intel_dsm_guid = 359 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 360 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 361 union acpi_object *obj; 362 363 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 364 NULL); 365 ACPI_FREE(obj); 366 } 367 #else 368 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 369 #endif /* CONFIG_ACPI */ 370 371 /* called during probe() after chip reset completes */ 372 static int xhci_pci_setup(struct usb_hcd *hcd) 373 { 374 struct xhci_hcd *xhci; 375 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 376 int retval; 377 378 xhci = hcd_to_xhci(hcd); 379 if (!xhci->sbrn) 380 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 381 382 /* imod_interval is the interrupt moderation value in nanoseconds. */ 383 xhci->imod_interval = 40000; 384 385 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 386 if (retval) 387 return retval; 388 389 if (!usb_hcd_is_primary_hcd(hcd)) 390 return 0; 391 392 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 393 xhci_pme_acpi_rtd3_enable(pdev); 394 395 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 396 397 /* Find any debug ports */ 398 return xhci_pci_reinit(xhci, pdev); 399 } 400 401 /* 402 * We need to register our own PCI probe function (instead of the USB core's 403 * function) in order to create a second roothub under xHCI. 404 */ 405 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 406 { 407 int retval; 408 struct xhci_hcd *xhci; 409 struct usb_hcd *hcd; 410 struct xhci_driver_data *driver_data; 411 struct reset_control *reset; 412 413 driver_data = (struct xhci_driver_data *)id->driver_data; 414 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 415 retval = renesas_xhci_check_request_fw(dev, id); 416 if (retval) 417 return retval; 418 } 419 420 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 421 if (IS_ERR(reset)) 422 return PTR_ERR(reset); 423 reset_control_reset(reset); 424 425 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 426 pm_runtime_get_noresume(&dev->dev); 427 428 /* Register the USB 2.0 roothub. 429 * FIXME: USB core must know to register the USB 2.0 roothub first. 430 * This is sort of silly, because we could just set the HCD driver flags 431 * to say USB 2.0, but I'm not sure what the implications would be in 432 * the other parts of the HCD code. 433 */ 434 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 435 436 if (retval) 437 goto put_runtime_pm; 438 439 /* USB 2.0 roothub is stored in the PCI device now. */ 440 hcd = dev_get_drvdata(&dev->dev); 441 xhci = hcd_to_xhci(hcd); 442 xhci->reset = reset; 443 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 444 pci_name(dev), hcd); 445 if (!xhci->shared_hcd) { 446 retval = -ENOMEM; 447 goto dealloc_usb2_hcd; 448 } 449 450 retval = xhci_ext_cap_init(xhci); 451 if (retval) 452 goto put_usb3_hcd; 453 454 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 455 IRQF_SHARED); 456 if (retval) 457 goto put_usb3_hcd; 458 /* Roothub already marked as USB 3.0 speed */ 459 460 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 461 HCC_MAX_PSA(xhci->hcc_params) >= 4) 462 xhci->shared_hcd->can_do_streams = 1; 463 464 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 465 pm_runtime_put_noidle(&dev->dev); 466 467 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 468 pm_runtime_allow(&dev->dev); 469 470 return 0; 471 472 put_usb3_hcd: 473 usb_put_hcd(xhci->shared_hcd); 474 dealloc_usb2_hcd: 475 usb_hcd_pci_remove(dev); 476 put_runtime_pm: 477 pm_runtime_put_noidle(&dev->dev); 478 return retval; 479 } 480 481 static void xhci_pci_remove(struct pci_dev *dev) 482 { 483 struct xhci_hcd *xhci; 484 485 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 486 487 xhci->xhc_state |= XHCI_STATE_REMOVING; 488 489 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 490 pm_runtime_forbid(&dev->dev); 491 492 if (xhci->shared_hcd) { 493 usb_remove_hcd(xhci->shared_hcd); 494 usb_put_hcd(xhci->shared_hcd); 495 xhci->shared_hcd = NULL; 496 } 497 498 /* Workaround for spurious wakeups at shutdown with HSW */ 499 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 500 pci_set_power_state(dev, PCI_D3hot); 501 502 usb_hcd_pci_remove(dev); 503 } 504 505 #ifdef CONFIG_PM 506 /* 507 * In some Intel xHCI controllers, in order to get D3 working, 508 * through a vendor specific SSIC CONFIG register at offset 0x883c, 509 * SSIC PORT need to be marked as "unused" before putting xHCI 510 * into D3. After D3 exit, the SSIC port need to be marked as "used". 511 * Without this change, xHCI might not enter D3 state. 512 */ 513 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 514 { 515 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 516 u32 val; 517 void __iomem *reg; 518 int i; 519 520 for (i = 0; i < SSIC_PORT_NUM; i++) { 521 reg = (void __iomem *) xhci->cap_regs + 522 SSIC_PORT_CFG2 + 523 i * SSIC_PORT_CFG2_OFFSET; 524 525 /* Notify SSIC that SSIC profile programming is not done. */ 526 val = readl(reg) & ~PROG_DONE; 527 writel(val, reg); 528 529 /* Mark SSIC port as unused(suspend) or used(resume) */ 530 val = readl(reg); 531 if (suspend) 532 val |= SSIC_PORT_UNUSED; 533 else 534 val &= ~SSIC_PORT_UNUSED; 535 writel(val, reg); 536 537 /* Notify SSIC that SSIC profile programming is done */ 538 val = readl(reg) | PROG_DONE; 539 writel(val, reg); 540 readl(reg); 541 } 542 } 543 544 /* 545 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 546 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 547 */ 548 static void xhci_pme_quirk(struct usb_hcd *hcd) 549 { 550 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 551 void __iomem *reg; 552 u32 val; 553 554 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 555 val = readl(reg); 556 writel(val | BIT(28), reg); 557 readl(reg); 558 } 559 560 static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 561 { 562 u32 reg; 563 564 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 565 reg &= ~BIT(SPARSE_DISABLE_BIT); 566 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 567 } 568 569 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 570 { 571 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 572 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 573 int ret; 574 575 /* 576 * Systems with the TI redriver that loses port status change events 577 * need to have the registers polled during D3, so avoid D3cold. 578 */ 579 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 580 pci_d3cold_disable(pdev); 581 582 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 583 xhci_pme_quirk(hcd); 584 585 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 586 xhci_ssic_port_unused_quirk(hcd, true); 587 588 if (xhci->quirks & XHCI_DISABLE_SPARSE) 589 xhci_sparse_control_quirk(hcd); 590 591 ret = xhci_suspend(xhci, do_wakeup); 592 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 593 xhci_ssic_port_unused_quirk(hcd, false); 594 595 return ret; 596 } 597 598 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 599 { 600 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 601 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 602 int retval = 0; 603 604 reset_control_reset(xhci->reset); 605 606 /* The BIOS on systems with the Intel Panther Point chipset may or may 607 * not support xHCI natively. That means that during system resume, it 608 * may switch the ports back to EHCI so that users can use their 609 * keyboard to select a kernel from GRUB after resume from hibernate. 610 * 611 * The BIOS is supposed to remember whether the OS had xHCI ports 612 * enabled before resume, and switch the ports back to xHCI when the 613 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 614 * writers. 615 * 616 * Unconditionally switch the ports back to xHCI after a system resume. 617 * It should not matter whether the EHCI or xHCI controller is 618 * resumed first. It's enough to do the switchover in xHCI because 619 * USB core won't notice anything as the hub driver doesn't start 620 * running again until after all the devices (including both EHCI and 621 * xHCI host controllers) have been resumed. 622 */ 623 624 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 625 usb_enable_intel_xhci_ports(pdev); 626 627 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 628 xhci_ssic_port_unused_quirk(hcd, false); 629 630 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 631 xhci_pme_quirk(hcd); 632 633 retval = xhci_resume(xhci, hibernated); 634 return retval; 635 } 636 637 static void xhci_pci_shutdown(struct usb_hcd *hcd) 638 { 639 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 640 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 641 642 xhci_shutdown(hcd); 643 644 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 645 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 646 pci_set_power_state(pdev, PCI_D3hot); 647 } 648 #endif /* CONFIG_PM */ 649 650 /*-------------------------------------------------------------------------*/ 651 652 static const struct xhci_driver_data reneses_data = { 653 .quirks = XHCI_RENESAS_FW_QUIRK, 654 .firmware = "renesas_usb_fw.mem", 655 }; 656 657 /* PCI driver selection metadata; PCI hotplugging uses this */ 658 static const struct pci_device_id pci_ids[] = { 659 { PCI_DEVICE(0x1912, 0x0014), 660 .driver_data = (unsigned long)&reneses_data, 661 }, 662 { PCI_DEVICE(0x1912, 0x0015), 663 .driver_data = (unsigned long)&reneses_data, 664 }, 665 /* handle any USB 3.0 xHCI controller */ 666 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 667 }, 668 { /* end: all zeroes */ } 669 }; 670 MODULE_DEVICE_TABLE(pci, pci_ids); 671 672 /* 673 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 674 * load firmware, so don't encumber the xhci-pci driver with it. 675 */ 676 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 677 MODULE_FIRMWARE("renesas_usb_fw.mem"); 678 #endif 679 680 /* pci driver glue; this is a "new style" PCI driver module */ 681 static struct pci_driver xhci_pci_driver = { 682 .name = hcd_name, 683 .id_table = pci_ids, 684 685 .probe = xhci_pci_probe, 686 .remove = xhci_pci_remove, 687 /* suspend and resume implemented later */ 688 689 .shutdown = usb_hcd_pci_shutdown, 690 #ifdef CONFIG_PM 691 .driver = { 692 .pm = &usb_hcd_pci_pm_ops 693 }, 694 #endif 695 }; 696 697 static int __init xhci_pci_init(void) 698 { 699 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 700 #ifdef CONFIG_PM 701 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 702 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 703 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 704 #endif 705 return pci_register_driver(&xhci_pci_driver); 706 } 707 module_init(xhci_pci_init); 708 709 static void __exit xhci_pci_exit(void) 710 { 711 pci_unregister_driver(&xhci_pci_driver); 712 } 713 module_exit(xhci_pci_exit); 714 715 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 716 MODULE_LICENSE("GPL"); 717