1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 48 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 53 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 54 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 56 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 57 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 58 59 static const char hcd_name[] = "xhci_hcd"; 60 61 static struct hc_driver __read_mostly xhci_pci_hc_driver; 62 63 static int xhci_pci_setup(struct usb_hcd *hcd); 64 65 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 66 .reset = xhci_pci_setup, 67 }; 68 69 /* called after powerup, by probe or system-pm "wakeup" */ 70 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 71 { 72 /* 73 * TODO: Implement finding debug ports later. 74 * TODO: see if there are any quirks that need to be added to handle 75 * new extended capabilities. 76 */ 77 78 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 79 if (!pci_set_mwi(pdev)) 80 xhci_dbg(xhci, "MWI active\n"); 81 82 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 83 return 0; 84 } 85 86 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 87 { 88 struct pci_dev *pdev = to_pci_dev(dev); 89 90 /* Look for vendor-specific quirks */ 91 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 92 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 93 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 94 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 95 pdev->revision == 0x0) { 96 xhci->quirks |= XHCI_RESET_EP_QUIRK; 97 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 98 "QUIRK: Fresco Logic xHC needs configure" 99 " endpoint cmd after reset endpoint"); 100 } 101 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 102 pdev->revision == 0x4) { 103 xhci->quirks |= XHCI_SLOW_SUSPEND; 104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 105 "QUIRK: Fresco Logic xHC revision %u" 106 "must be suspended extra slowly", 107 pdev->revision); 108 } 109 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 110 xhci->quirks |= XHCI_BROKEN_STREAMS; 111 /* Fresco Logic confirms: all revisions of this chip do not 112 * support MSI, even though some of them claim to in their PCI 113 * capabilities. 114 */ 115 xhci->quirks |= XHCI_BROKEN_MSI; 116 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 117 "QUIRK: Fresco Logic revision %u " 118 "has broken MSI implementation", 119 pdev->revision); 120 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 121 } 122 123 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 124 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 125 xhci->quirks |= XHCI_BROKEN_STREAMS; 126 127 if (pdev->vendor == PCI_VENDOR_ID_NEC) 128 xhci->quirks |= XHCI_NEC_HOST; 129 130 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 131 xhci->quirks |= XHCI_AMD_0x96_HOST; 132 133 /* AMD PLL quirk */ 134 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 135 xhci->quirks |= XHCI_AMD_PLL_FIX; 136 137 if (pdev->vendor == PCI_VENDOR_ID_AMD && 138 (pdev->device == 0x15e0 || 139 pdev->device == 0x15e1 || 140 pdev->device == 0x43bb)) 141 xhci->quirks |= XHCI_SUSPEND_DELAY; 142 143 if (pdev->vendor == PCI_VENDOR_ID_AMD && 144 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 145 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 146 147 if (pdev->vendor == PCI_VENDOR_ID_AMD) 148 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 149 150 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 151 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 152 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 153 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 154 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 155 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 156 157 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 158 xhci->quirks |= XHCI_LPM_SUPPORT; 159 xhci->quirks |= XHCI_INTEL_HOST; 160 xhci->quirks |= XHCI_AVOID_BEI; 161 } 162 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 163 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 164 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 165 xhci->limit_active_eps = 64; 166 xhci->quirks |= XHCI_SW_BW_CHECKING; 167 /* 168 * PPT desktop boards DH77EB and DH77DF will power back on after 169 * a few seconds of being shutdown. The fix for this is to 170 * switch the ports from xHCI to EHCI on shutdown. We can't use 171 * DMI information to find those particular boards (since each 172 * vendor will change the board name), so we have to key off all 173 * PPT chipsets. 174 */ 175 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 176 } 177 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 178 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 179 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 180 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 181 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 182 } 183 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 184 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 185 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 186 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 187 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 188 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 189 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 190 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 191 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 192 } 193 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 194 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 195 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 196 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 197 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 198 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 199 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 200 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 201 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 202 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 203 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 204 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 205 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 206 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 207 xhci->quirks |= XHCI_MISSING_CAS; 208 209 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 210 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 211 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 212 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 213 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 214 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 215 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 216 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 217 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI)) 218 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 219 220 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 221 pdev->device == PCI_DEVICE_ID_EJ168) { 222 xhci->quirks |= XHCI_RESET_ON_RESUME; 223 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 224 xhci->quirks |= XHCI_BROKEN_STREAMS; 225 } 226 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 227 pdev->device == 0x0014) { 228 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 229 xhci->quirks |= XHCI_ZERO_64B_REGS; 230 } 231 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 232 pdev->device == 0x0015) { 233 xhci->quirks |= XHCI_RESET_ON_RESUME; 234 xhci->quirks |= XHCI_ZERO_64B_REGS; 235 } 236 if (pdev->vendor == PCI_VENDOR_ID_VIA) 237 xhci->quirks |= XHCI_RESET_ON_RESUME; 238 239 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 240 if (pdev->vendor == PCI_VENDOR_ID_VIA && 241 pdev->device == 0x3432) 242 xhci->quirks |= XHCI_BROKEN_STREAMS; 243 244 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 245 pdev->device == 0x1042) 246 xhci->quirks |= XHCI_BROKEN_STREAMS; 247 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 248 pdev->device == 0x1142) 249 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 250 251 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 252 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 253 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 254 255 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 256 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 257 258 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 259 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 260 pdev->device == 0x9026) 261 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 262 263 if (xhci->quirks & XHCI_RESET_ON_RESUME) 264 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 265 "QUIRK: Resetting on resume"); 266 } 267 268 #ifdef CONFIG_ACPI 269 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 270 { 271 static const guid_t intel_dsm_guid = 272 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 273 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 274 union acpi_object *obj; 275 276 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 277 NULL); 278 ACPI_FREE(obj); 279 } 280 #else 281 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 282 #endif /* CONFIG_ACPI */ 283 284 /* called during probe() after chip reset completes */ 285 static int xhci_pci_setup(struct usb_hcd *hcd) 286 { 287 struct xhci_hcd *xhci; 288 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 289 int retval; 290 291 xhci = hcd_to_xhci(hcd); 292 if (!xhci->sbrn) 293 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 294 295 /* imod_interval is the interrupt moderation value in nanoseconds. */ 296 xhci->imod_interval = 40000; 297 298 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 299 if (retval) 300 return retval; 301 302 if (!usb_hcd_is_primary_hcd(hcd)) 303 return 0; 304 305 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 306 307 /* Find any debug ports */ 308 return xhci_pci_reinit(xhci, pdev); 309 } 310 311 /* 312 * We need to register our own PCI probe function (instead of the USB core's 313 * function) in order to create a second roothub under xHCI. 314 */ 315 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 316 { 317 int retval; 318 struct xhci_hcd *xhci; 319 struct hc_driver *driver; 320 struct usb_hcd *hcd; 321 322 driver = (struct hc_driver *)id->driver_data; 323 324 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 325 pm_runtime_get_noresume(&dev->dev); 326 327 /* Register the USB 2.0 roothub. 328 * FIXME: USB core must know to register the USB 2.0 roothub first. 329 * This is sort of silly, because we could just set the HCD driver flags 330 * to say USB 2.0, but I'm not sure what the implications would be in 331 * the other parts of the HCD code. 332 */ 333 retval = usb_hcd_pci_probe(dev, id); 334 335 if (retval) 336 goto put_runtime_pm; 337 338 /* USB 2.0 roothub is stored in the PCI device now. */ 339 hcd = dev_get_drvdata(&dev->dev); 340 xhci = hcd_to_xhci(hcd); 341 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 342 pci_name(dev), hcd); 343 if (!xhci->shared_hcd) { 344 retval = -ENOMEM; 345 goto dealloc_usb2_hcd; 346 } 347 348 retval = xhci_ext_cap_init(xhci); 349 if (retval) 350 goto put_usb3_hcd; 351 352 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 353 IRQF_SHARED); 354 if (retval) 355 goto put_usb3_hcd; 356 /* Roothub already marked as USB 3.0 speed */ 357 358 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 359 HCC_MAX_PSA(xhci->hcc_params) >= 4) 360 xhci->shared_hcd->can_do_streams = 1; 361 362 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 363 xhci_pme_acpi_rtd3_enable(dev); 364 365 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 366 pm_runtime_put_noidle(&dev->dev); 367 368 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 369 pm_runtime_allow(&dev->dev); 370 371 return 0; 372 373 put_usb3_hcd: 374 usb_put_hcd(xhci->shared_hcd); 375 dealloc_usb2_hcd: 376 usb_hcd_pci_remove(dev); 377 put_runtime_pm: 378 pm_runtime_put_noidle(&dev->dev); 379 return retval; 380 } 381 382 static void xhci_pci_remove(struct pci_dev *dev) 383 { 384 struct xhci_hcd *xhci; 385 386 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 387 xhci->xhc_state |= XHCI_STATE_REMOVING; 388 389 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 390 pm_runtime_forbid(&dev->dev); 391 392 if (xhci->shared_hcd) { 393 usb_remove_hcd(xhci->shared_hcd); 394 usb_put_hcd(xhci->shared_hcd); 395 xhci->shared_hcd = NULL; 396 } 397 398 /* Workaround for spurious wakeups at shutdown with HSW */ 399 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 400 pci_set_power_state(dev, PCI_D3hot); 401 402 usb_hcd_pci_remove(dev); 403 } 404 405 #ifdef CONFIG_PM 406 /* 407 * In some Intel xHCI controllers, in order to get D3 working, 408 * through a vendor specific SSIC CONFIG register at offset 0x883c, 409 * SSIC PORT need to be marked as "unused" before putting xHCI 410 * into D3. After D3 exit, the SSIC port need to be marked as "used". 411 * Without this change, xHCI might not enter D3 state. 412 */ 413 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 414 { 415 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 416 u32 val; 417 void __iomem *reg; 418 int i; 419 420 for (i = 0; i < SSIC_PORT_NUM; i++) { 421 reg = (void __iomem *) xhci->cap_regs + 422 SSIC_PORT_CFG2 + 423 i * SSIC_PORT_CFG2_OFFSET; 424 425 /* Notify SSIC that SSIC profile programming is not done. */ 426 val = readl(reg) & ~PROG_DONE; 427 writel(val, reg); 428 429 /* Mark SSIC port as unused(suspend) or used(resume) */ 430 val = readl(reg); 431 if (suspend) 432 val |= SSIC_PORT_UNUSED; 433 else 434 val &= ~SSIC_PORT_UNUSED; 435 writel(val, reg); 436 437 /* Notify SSIC that SSIC profile programming is done */ 438 val = readl(reg) | PROG_DONE; 439 writel(val, reg); 440 readl(reg); 441 } 442 } 443 444 /* 445 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 446 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 447 */ 448 static void xhci_pme_quirk(struct usb_hcd *hcd) 449 { 450 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 451 void __iomem *reg; 452 u32 val; 453 454 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 455 val = readl(reg); 456 writel(val | BIT(28), reg); 457 readl(reg); 458 } 459 460 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 461 { 462 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 463 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 464 int ret; 465 466 /* 467 * Systems with the TI redriver that loses port status change events 468 * need to have the registers polled during D3, so avoid D3cold. 469 */ 470 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 471 pci_d3cold_disable(pdev); 472 473 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 474 xhci_pme_quirk(hcd); 475 476 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 477 xhci_ssic_port_unused_quirk(hcd, true); 478 479 ret = xhci_suspend(xhci, do_wakeup); 480 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 481 xhci_ssic_port_unused_quirk(hcd, false); 482 483 return ret; 484 } 485 486 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 487 { 488 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 489 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 490 int retval = 0; 491 492 /* The BIOS on systems with the Intel Panther Point chipset may or may 493 * not support xHCI natively. That means that during system resume, it 494 * may switch the ports back to EHCI so that users can use their 495 * keyboard to select a kernel from GRUB after resume from hibernate. 496 * 497 * The BIOS is supposed to remember whether the OS had xHCI ports 498 * enabled before resume, and switch the ports back to xHCI when the 499 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 500 * writers. 501 * 502 * Unconditionally switch the ports back to xHCI after a system resume. 503 * It should not matter whether the EHCI or xHCI controller is 504 * resumed first. It's enough to do the switchover in xHCI because 505 * USB core won't notice anything as the hub driver doesn't start 506 * running again until after all the devices (including both EHCI and 507 * xHCI host controllers) have been resumed. 508 */ 509 510 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 511 usb_enable_intel_xhci_ports(pdev); 512 513 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 514 xhci_ssic_port_unused_quirk(hcd, false); 515 516 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 517 xhci_pme_quirk(hcd); 518 519 retval = xhci_resume(xhci, hibernated); 520 return retval; 521 } 522 523 static void xhci_pci_shutdown(struct usb_hcd *hcd) 524 { 525 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 526 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 527 528 xhci_shutdown(hcd); 529 530 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 531 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 532 pci_set_power_state(pdev, PCI_D3hot); 533 } 534 #endif /* CONFIG_PM */ 535 536 /*-------------------------------------------------------------------------*/ 537 538 /* PCI driver selection metadata; PCI hotplugging uses this */ 539 static const struct pci_device_id pci_ids[] = { { 540 /* handle any USB 3.0 xHCI controller */ 541 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 542 .driver_data = (unsigned long) &xhci_pci_hc_driver, 543 }, 544 { /* end: all zeroes */ } 545 }; 546 MODULE_DEVICE_TABLE(pci, pci_ids); 547 548 /* pci driver glue; this is a "new style" PCI driver module */ 549 static struct pci_driver xhci_pci_driver = { 550 .name = (char *) hcd_name, 551 .id_table = pci_ids, 552 553 .probe = xhci_pci_probe, 554 .remove = xhci_pci_remove, 555 /* suspend and resume implemented later */ 556 557 .shutdown = usb_hcd_pci_shutdown, 558 #ifdef CONFIG_PM 559 .driver = { 560 .pm = &usb_hcd_pci_pm_ops 561 }, 562 #endif 563 }; 564 565 static int __init xhci_pci_init(void) 566 { 567 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 568 #ifdef CONFIG_PM 569 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 570 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 571 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 572 #endif 573 return pci_register_driver(&xhci_pci_driver); 574 } 575 module_init(xhci_pci_init); 576 577 static void __exit xhci_pci_exit(void) 578 { 579 pci_unregister_driver(&xhci_pci_driver); 580 } 581 module_exit(xhci_pci_exit); 582 583 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 584 MODULE_LICENSE("GPL"); 585