1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 48 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 51 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 52 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 53 54 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 56 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 58 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 59 60 static const char hcd_name[] = "xhci_hcd"; 61 62 static struct hc_driver __read_mostly xhci_pci_hc_driver; 63 64 static int xhci_pci_setup(struct usb_hcd *hcd); 65 66 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 67 .reset = xhci_pci_setup, 68 }; 69 70 /* called after powerup, by probe or system-pm "wakeup" */ 71 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 72 { 73 /* 74 * TODO: Implement finding debug ports later. 75 * TODO: see if there are any quirks that need to be added to handle 76 * new extended capabilities. 77 */ 78 79 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 80 if (!pci_set_mwi(pdev)) 81 xhci_dbg(xhci, "MWI active\n"); 82 83 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 84 return 0; 85 } 86 87 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 88 { 89 struct pci_dev *pdev = to_pci_dev(dev); 90 91 /* Look for vendor-specific quirks */ 92 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 93 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 94 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 95 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 96 pdev->revision == 0x0) { 97 xhci->quirks |= XHCI_RESET_EP_QUIRK; 98 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 99 "QUIRK: Fresco Logic xHC needs configure" 100 " endpoint cmd after reset endpoint"); 101 } 102 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 103 pdev->revision == 0x4) { 104 xhci->quirks |= XHCI_SLOW_SUSPEND; 105 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 106 "QUIRK: Fresco Logic xHC revision %u" 107 "must be suspended extra slowly", 108 pdev->revision); 109 } 110 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 111 xhci->quirks |= XHCI_BROKEN_STREAMS; 112 /* Fresco Logic confirms: all revisions of this chip do not 113 * support MSI, even though some of them claim to in their PCI 114 * capabilities. 115 */ 116 xhci->quirks |= XHCI_BROKEN_MSI; 117 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 118 "QUIRK: Fresco Logic revision %u " 119 "has broken MSI implementation", 120 pdev->revision); 121 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 122 } 123 124 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 125 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 126 xhci->quirks |= XHCI_BROKEN_STREAMS; 127 128 if (pdev->vendor == PCI_VENDOR_ID_NEC) 129 xhci->quirks |= XHCI_NEC_HOST; 130 131 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 132 xhci->quirks |= XHCI_AMD_0x96_HOST; 133 134 /* AMD PLL quirk */ 135 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 136 xhci->quirks |= XHCI_AMD_PLL_FIX; 137 138 if (pdev->vendor == PCI_VENDOR_ID_AMD && 139 (pdev->device == 0x15e0 || 140 pdev->device == 0x15e1 || 141 pdev->device == 0x43bb)) 142 xhci->quirks |= XHCI_SUSPEND_DELAY; 143 144 if (pdev->vendor == PCI_VENDOR_ID_AMD && 145 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 146 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 147 148 if (pdev->vendor == PCI_VENDOR_ID_AMD) 149 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 150 151 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 152 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 153 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 154 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 155 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 156 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 157 158 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 159 xhci->quirks |= XHCI_LPM_SUPPORT; 160 xhci->quirks |= XHCI_INTEL_HOST; 161 xhci->quirks |= XHCI_AVOID_BEI; 162 } 163 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 164 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 165 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 166 xhci->limit_active_eps = 64; 167 xhci->quirks |= XHCI_SW_BW_CHECKING; 168 /* 169 * PPT desktop boards DH77EB and DH77DF will power back on after 170 * a few seconds of being shutdown. The fix for this is to 171 * switch the ports from xHCI to EHCI on shutdown. We can't use 172 * DMI information to find those particular boards (since each 173 * vendor will change the board name), so we have to key off all 174 * PPT chipsets. 175 */ 176 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 177 } 178 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 179 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 180 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 181 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 182 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 183 } 184 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 185 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 186 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 187 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 188 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 189 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 190 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 191 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 192 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 193 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 194 } 195 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 196 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 197 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 198 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 199 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 200 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 201 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 202 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 203 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 204 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 205 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 206 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 207 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 208 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 209 xhci->quirks |= XHCI_MISSING_CAS; 210 211 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 212 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 213 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 214 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 215 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 216 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 217 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 218 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 219 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI)) 220 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 221 222 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 223 pdev->device == PCI_DEVICE_ID_EJ168) { 224 xhci->quirks |= XHCI_RESET_ON_RESUME; 225 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 226 xhci->quirks |= XHCI_BROKEN_STREAMS; 227 } 228 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 229 pdev->device == 0x0014) { 230 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 231 xhci->quirks |= XHCI_ZERO_64B_REGS; 232 } 233 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 234 pdev->device == 0x0015) { 235 xhci->quirks |= XHCI_RESET_ON_RESUME; 236 xhci->quirks |= XHCI_ZERO_64B_REGS; 237 } 238 if (pdev->vendor == PCI_VENDOR_ID_VIA) 239 xhci->quirks |= XHCI_RESET_ON_RESUME; 240 241 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 242 if (pdev->vendor == PCI_VENDOR_ID_VIA && 243 pdev->device == 0x3432) 244 xhci->quirks |= XHCI_BROKEN_STREAMS; 245 246 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 247 pdev->device == 0x1042) 248 xhci->quirks |= XHCI_BROKEN_STREAMS; 249 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 250 pdev->device == 0x1142) 251 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 252 253 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 254 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 255 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 256 257 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 258 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 259 260 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 261 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 262 pdev->device == 0x9026) 263 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 264 265 if (xhci->quirks & XHCI_RESET_ON_RESUME) 266 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 267 "QUIRK: Resetting on resume"); 268 } 269 270 #ifdef CONFIG_ACPI 271 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 272 { 273 static const guid_t intel_dsm_guid = 274 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 275 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 276 union acpi_object *obj; 277 278 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 279 NULL); 280 ACPI_FREE(obj); 281 } 282 #else 283 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 284 #endif /* CONFIG_ACPI */ 285 286 /* called during probe() after chip reset completes */ 287 static int xhci_pci_setup(struct usb_hcd *hcd) 288 { 289 struct xhci_hcd *xhci; 290 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 291 int retval; 292 293 xhci = hcd_to_xhci(hcd); 294 if (!xhci->sbrn) 295 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 296 297 /* imod_interval is the interrupt moderation value in nanoseconds. */ 298 xhci->imod_interval = 40000; 299 300 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 301 if (retval) 302 return retval; 303 304 if (!usb_hcd_is_primary_hcd(hcd)) 305 return 0; 306 307 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 308 xhci_pme_acpi_rtd3_enable(pdev); 309 310 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 311 312 /* Find any debug ports */ 313 return xhci_pci_reinit(xhci, pdev); 314 } 315 316 /* 317 * We need to register our own PCI probe function (instead of the USB core's 318 * function) in order to create a second roothub under xHCI. 319 */ 320 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 321 { 322 int retval; 323 struct xhci_hcd *xhci; 324 struct hc_driver *driver; 325 struct usb_hcd *hcd; 326 327 driver = (struct hc_driver *)id->driver_data; 328 329 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 330 pm_runtime_get_noresume(&dev->dev); 331 332 /* Register the USB 2.0 roothub. 333 * FIXME: USB core must know to register the USB 2.0 roothub first. 334 * This is sort of silly, because we could just set the HCD driver flags 335 * to say USB 2.0, but I'm not sure what the implications would be in 336 * the other parts of the HCD code. 337 */ 338 retval = usb_hcd_pci_probe(dev, id); 339 340 if (retval) 341 goto put_runtime_pm; 342 343 /* USB 2.0 roothub is stored in the PCI device now. */ 344 hcd = dev_get_drvdata(&dev->dev); 345 xhci = hcd_to_xhci(hcd); 346 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 347 pci_name(dev), hcd); 348 if (!xhci->shared_hcd) { 349 retval = -ENOMEM; 350 goto dealloc_usb2_hcd; 351 } 352 353 retval = xhci_ext_cap_init(xhci); 354 if (retval) 355 goto put_usb3_hcd; 356 357 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 358 IRQF_SHARED); 359 if (retval) 360 goto put_usb3_hcd; 361 /* Roothub already marked as USB 3.0 speed */ 362 363 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 364 HCC_MAX_PSA(xhci->hcc_params) >= 4) 365 xhci->shared_hcd->can_do_streams = 1; 366 367 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 368 pm_runtime_put_noidle(&dev->dev); 369 370 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 371 pm_runtime_allow(&dev->dev); 372 373 return 0; 374 375 put_usb3_hcd: 376 usb_put_hcd(xhci->shared_hcd); 377 dealloc_usb2_hcd: 378 usb_hcd_pci_remove(dev); 379 put_runtime_pm: 380 pm_runtime_put_noidle(&dev->dev); 381 return retval; 382 } 383 384 static void xhci_pci_remove(struct pci_dev *dev) 385 { 386 struct xhci_hcd *xhci; 387 388 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 389 xhci->xhc_state |= XHCI_STATE_REMOVING; 390 391 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 392 pm_runtime_forbid(&dev->dev); 393 394 if (xhci->shared_hcd) { 395 usb_remove_hcd(xhci->shared_hcd); 396 usb_put_hcd(xhci->shared_hcd); 397 xhci->shared_hcd = NULL; 398 } 399 400 /* Workaround for spurious wakeups at shutdown with HSW */ 401 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 402 pci_set_power_state(dev, PCI_D3hot); 403 404 usb_hcd_pci_remove(dev); 405 } 406 407 #ifdef CONFIG_PM 408 /* 409 * In some Intel xHCI controllers, in order to get D3 working, 410 * through a vendor specific SSIC CONFIG register at offset 0x883c, 411 * SSIC PORT need to be marked as "unused" before putting xHCI 412 * into D3. After D3 exit, the SSIC port need to be marked as "used". 413 * Without this change, xHCI might not enter D3 state. 414 */ 415 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 416 { 417 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 418 u32 val; 419 void __iomem *reg; 420 int i; 421 422 for (i = 0; i < SSIC_PORT_NUM; i++) { 423 reg = (void __iomem *) xhci->cap_regs + 424 SSIC_PORT_CFG2 + 425 i * SSIC_PORT_CFG2_OFFSET; 426 427 /* Notify SSIC that SSIC profile programming is not done. */ 428 val = readl(reg) & ~PROG_DONE; 429 writel(val, reg); 430 431 /* Mark SSIC port as unused(suspend) or used(resume) */ 432 val = readl(reg); 433 if (suspend) 434 val |= SSIC_PORT_UNUSED; 435 else 436 val &= ~SSIC_PORT_UNUSED; 437 writel(val, reg); 438 439 /* Notify SSIC that SSIC profile programming is done */ 440 val = readl(reg) | PROG_DONE; 441 writel(val, reg); 442 readl(reg); 443 } 444 } 445 446 /* 447 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 448 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 449 */ 450 static void xhci_pme_quirk(struct usb_hcd *hcd) 451 { 452 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 453 void __iomem *reg; 454 u32 val; 455 456 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 457 val = readl(reg); 458 writel(val | BIT(28), reg); 459 readl(reg); 460 } 461 462 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 463 { 464 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 465 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 466 int ret; 467 468 /* 469 * Systems with the TI redriver that loses port status change events 470 * need to have the registers polled during D3, so avoid D3cold. 471 */ 472 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 473 pci_d3cold_disable(pdev); 474 475 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 476 xhci_pme_quirk(hcd); 477 478 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 479 xhci_ssic_port_unused_quirk(hcd, true); 480 481 ret = xhci_suspend(xhci, do_wakeup); 482 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 483 xhci_ssic_port_unused_quirk(hcd, false); 484 485 return ret; 486 } 487 488 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 489 { 490 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 491 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 492 int retval = 0; 493 494 /* The BIOS on systems with the Intel Panther Point chipset may or may 495 * not support xHCI natively. That means that during system resume, it 496 * may switch the ports back to EHCI so that users can use their 497 * keyboard to select a kernel from GRUB after resume from hibernate. 498 * 499 * The BIOS is supposed to remember whether the OS had xHCI ports 500 * enabled before resume, and switch the ports back to xHCI when the 501 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 502 * writers. 503 * 504 * Unconditionally switch the ports back to xHCI after a system resume. 505 * It should not matter whether the EHCI or xHCI controller is 506 * resumed first. It's enough to do the switchover in xHCI because 507 * USB core won't notice anything as the hub driver doesn't start 508 * running again until after all the devices (including both EHCI and 509 * xHCI host controllers) have been resumed. 510 */ 511 512 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 513 usb_enable_intel_xhci_ports(pdev); 514 515 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 516 xhci_ssic_port_unused_quirk(hcd, false); 517 518 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 519 xhci_pme_quirk(hcd); 520 521 retval = xhci_resume(xhci, hibernated); 522 return retval; 523 } 524 525 static void xhci_pci_shutdown(struct usb_hcd *hcd) 526 { 527 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 528 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 529 530 xhci_shutdown(hcd); 531 532 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 533 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 534 pci_set_power_state(pdev, PCI_D3hot); 535 } 536 #endif /* CONFIG_PM */ 537 538 /*-------------------------------------------------------------------------*/ 539 540 /* PCI driver selection metadata; PCI hotplugging uses this */ 541 static const struct pci_device_id pci_ids[] = { { 542 /* handle any USB 3.0 xHCI controller */ 543 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 544 .driver_data = (unsigned long) &xhci_pci_hc_driver, 545 }, 546 { /* end: all zeroes */ } 547 }; 548 MODULE_DEVICE_TABLE(pci, pci_ids); 549 550 /* pci driver glue; this is a "new style" PCI driver module */ 551 static struct pci_driver xhci_pci_driver = { 552 .name = (char *) hcd_name, 553 .id_table = pci_ids, 554 555 .probe = xhci_pci_probe, 556 .remove = xhci_pci_remove, 557 /* suspend and resume implemented later */ 558 559 .shutdown = usb_hcd_pci_shutdown, 560 #ifdef CONFIG_PM 561 .driver = { 562 .pm = &usb_hcd_pci_pm_ops 563 }, 564 #endif 565 }; 566 567 static int __init xhci_pci_init(void) 568 { 569 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 570 #ifdef CONFIG_PM 571 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 572 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 573 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 574 #endif 575 return pci_register_driver(&xhci_pci_driver); 576 } 577 module_init(xhci_pci_init); 578 579 static void __exit xhci_pci_exit(void) 580 { 581 pci_unregister_driver(&xhci_pci_driver); 582 } 583 module_exit(xhci_pci_exit); 584 585 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 586 MODULE_LICENSE("GPL"); 587