1 /* 2 * xHCI host controller driver PCI Bus Glue. 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/acpi.h> 27 28 #include "xhci.h" 29 #include "xhci-trace.h" 30 31 #define SSIC_PORT_NUM 2 32 #define SSIC_PORT_CFG2 0x880c 33 #define SSIC_PORT_CFG2_OFFSET 0x30 34 #define PROG_DONE (1 << 30) 35 #define SSIC_PORT_UNUSED (1 << 31) 36 37 /* Device for a quirk */ 38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 42 43 #define PCI_VENDOR_ID_ETRON 0x1b6f 44 #define PCI_DEVICE_ID_EJ168 0x7023 45 46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 54 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 56 57 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 58 59 static const char hcd_name[] = "xhci_hcd"; 60 61 static struct hc_driver __read_mostly xhci_pci_hc_driver; 62 63 static int xhci_pci_setup(struct usb_hcd *hcd); 64 65 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 66 .reset = xhci_pci_setup, 67 }; 68 69 /* called after powerup, by probe or system-pm "wakeup" */ 70 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 71 { 72 /* 73 * TODO: Implement finding debug ports later. 74 * TODO: see if there are any quirks that need to be added to handle 75 * new extended capabilities. 76 */ 77 78 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 79 if (!pci_set_mwi(pdev)) 80 xhci_dbg(xhci, "MWI active\n"); 81 82 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 83 return 0; 84 } 85 86 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 87 { 88 struct pci_dev *pdev = to_pci_dev(dev); 89 90 /* Look for vendor-specific quirks */ 91 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 92 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 93 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 94 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 95 pdev->revision == 0x0) { 96 xhci->quirks |= XHCI_RESET_EP_QUIRK; 97 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 98 "QUIRK: Fresco Logic xHC needs configure" 99 " endpoint cmd after reset endpoint"); 100 } 101 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 102 pdev->revision == 0x4) { 103 xhci->quirks |= XHCI_SLOW_SUSPEND; 104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 105 "QUIRK: Fresco Logic xHC revision %u" 106 "must be suspended extra slowly", 107 pdev->revision); 108 } 109 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 110 xhci->quirks |= XHCI_BROKEN_STREAMS; 111 /* Fresco Logic confirms: all revisions of this chip do not 112 * support MSI, even though some of them claim to in their PCI 113 * capabilities. 114 */ 115 xhci->quirks |= XHCI_BROKEN_MSI; 116 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 117 "QUIRK: Fresco Logic revision %u " 118 "has broken MSI implementation", 119 pdev->revision); 120 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 121 } 122 123 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 124 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 125 xhci->quirks |= XHCI_BROKEN_STREAMS; 126 127 if (pdev->vendor == PCI_VENDOR_ID_NEC) 128 xhci->quirks |= XHCI_NEC_HOST; 129 130 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 131 xhci->quirks |= XHCI_AMD_0x96_HOST; 132 133 /* AMD PLL quirk */ 134 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 135 xhci->quirks |= XHCI_AMD_PLL_FIX; 136 137 if (pdev->vendor == PCI_VENDOR_ID_AMD) 138 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 139 140 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 141 xhci->quirks |= XHCI_LPM_SUPPORT; 142 xhci->quirks |= XHCI_INTEL_HOST; 143 xhci->quirks |= XHCI_AVOID_BEI; 144 } 145 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 146 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 147 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 148 xhci->limit_active_eps = 64; 149 xhci->quirks |= XHCI_SW_BW_CHECKING; 150 /* 151 * PPT desktop boards DH77EB and DH77DF will power back on after 152 * a few seconds of being shutdown. The fix for this is to 153 * switch the ports from xHCI to EHCI on shutdown. We can't use 154 * DMI information to find those particular boards (since each 155 * vendor will change the board name), so we have to key off all 156 * PPT chipsets. 157 */ 158 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 159 } 160 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 161 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 162 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 163 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 164 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 165 } 166 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 167 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 168 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 169 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 170 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 171 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 172 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 173 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 174 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 175 } 176 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 177 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { 178 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 179 } 180 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 181 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 182 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 183 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 184 xhci->quirks |= XHCI_MISSING_CAS; 185 186 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 187 pdev->device == PCI_DEVICE_ID_EJ168) { 188 xhci->quirks |= XHCI_RESET_ON_RESUME; 189 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 190 xhci->quirks |= XHCI_BROKEN_STREAMS; 191 } 192 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 193 pdev->device == 0x0015) 194 xhci->quirks |= XHCI_RESET_ON_RESUME; 195 if (pdev->vendor == PCI_VENDOR_ID_VIA) 196 xhci->quirks |= XHCI_RESET_ON_RESUME; 197 198 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 199 if (pdev->vendor == PCI_VENDOR_ID_VIA && 200 pdev->device == 0x3432) 201 xhci->quirks |= XHCI_BROKEN_STREAMS; 202 203 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 204 pdev->device == 0x1042) 205 xhci->quirks |= XHCI_BROKEN_STREAMS; 206 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 207 pdev->device == 0x1142) 208 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 209 210 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 211 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 212 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 213 214 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 215 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 216 217 if (xhci->quirks & XHCI_RESET_ON_RESUME) 218 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 219 "QUIRK: Resetting on resume"); 220 } 221 222 #ifdef CONFIG_ACPI 223 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 224 { 225 static const guid_t intel_dsm_guid = 226 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 227 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 228 union acpi_object *obj; 229 230 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 231 NULL); 232 ACPI_FREE(obj); 233 } 234 #else 235 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 236 #endif /* CONFIG_ACPI */ 237 238 /* called during probe() after chip reset completes */ 239 static int xhci_pci_setup(struct usb_hcd *hcd) 240 { 241 struct xhci_hcd *xhci; 242 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 243 int retval; 244 245 xhci = hcd_to_xhci(hcd); 246 if (!xhci->sbrn) 247 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 248 249 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 250 if (retval) 251 return retval; 252 253 if (!usb_hcd_is_primary_hcd(hcd)) 254 return 0; 255 256 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 257 258 /* Find any debug ports */ 259 return xhci_pci_reinit(xhci, pdev); 260 } 261 262 /* 263 * We need to register our own PCI probe function (instead of the USB core's 264 * function) in order to create a second roothub under xHCI. 265 */ 266 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 267 { 268 int retval; 269 struct xhci_hcd *xhci; 270 struct hc_driver *driver; 271 struct usb_hcd *hcd; 272 273 driver = (struct hc_driver *)id->driver_data; 274 275 /* For some HW implementation, a XHCI reset is just not enough... */ 276 if (usb_xhci_needs_pci_reset(dev)) { 277 dev_info(&dev->dev, "Resetting\n"); 278 if (pci_reset_function_locked(dev)) 279 dev_warn(&dev->dev, "Reset failed"); 280 } 281 282 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 283 pm_runtime_get_noresume(&dev->dev); 284 285 /* Register the USB 2.0 roothub. 286 * FIXME: USB core must know to register the USB 2.0 roothub first. 287 * This is sort of silly, because we could just set the HCD driver flags 288 * to say USB 2.0, but I'm not sure what the implications would be in 289 * the other parts of the HCD code. 290 */ 291 retval = usb_hcd_pci_probe(dev, id); 292 293 if (retval) 294 goto put_runtime_pm; 295 296 /* USB 2.0 roothub is stored in the PCI device now. */ 297 hcd = dev_get_drvdata(&dev->dev); 298 xhci = hcd_to_xhci(hcd); 299 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 300 pci_name(dev), hcd); 301 if (!xhci->shared_hcd) { 302 retval = -ENOMEM; 303 goto dealloc_usb2_hcd; 304 } 305 306 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 307 IRQF_SHARED); 308 if (retval) 309 goto put_usb3_hcd; 310 /* Roothub already marked as USB 3.0 speed */ 311 312 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 313 HCC_MAX_PSA(xhci->hcc_params) >= 4) 314 xhci->shared_hcd->can_do_streams = 1; 315 316 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 317 xhci_pme_acpi_rtd3_enable(dev); 318 319 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 320 pm_runtime_put_noidle(&dev->dev); 321 322 return 0; 323 324 put_usb3_hcd: 325 usb_put_hcd(xhci->shared_hcd); 326 dealloc_usb2_hcd: 327 usb_hcd_pci_remove(dev); 328 put_runtime_pm: 329 pm_runtime_put_noidle(&dev->dev); 330 return retval; 331 } 332 333 static void xhci_pci_remove(struct pci_dev *dev) 334 { 335 struct xhci_hcd *xhci; 336 337 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 338 xhci->xhc_state |= XHCI_STATE_REMOVING; 339 if (xhci->shared_hcd) { 340 usb_remove_hcd(xhci->shared_hcd); 341 usb_put_hcd(xhci->shared_hcd); 342 } 343 344 /* Workaround for spurious wakeups at shutdown with HSW */ 345 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 346 pci_set_power_state(dev, PCI_D3hot); 347 348 usb_hcd_pci_remove(dev); 349 } 350 351 #ifdef CONFIG_PM 352 /* 353 * In some Intel xHCI controllers, in order to get D3 working, 354 * through a vendor specific SSIC CONFIG register at offset 0x883c, 355 * SSIC PORT need to be marked as "unused" before putting xHCI 356 * into D3. After D3 exit, the SSIC port need to be marked as "used". 357 * Without this change, xHCI might not enter D3 state. 358 */ 359 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 360 { 361 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 362 u32 val; 363 void __iomem *reg; 364 int i; 365 366 for (i = 0; i < SSIC_PORT_NUM; i++) { 367 reg = (void __iomem *) xhci->cap_regs + 368 SSIC_PORT_CFG2 + 369 i * SSIC_PORT_CFG2_OFFSET; 370 371 /* Notify SSIC that SSIC profile programming is not done. */ 372 val = readl(reg) & ~PROG_DONE; 373 writel(val, reg); 374 375 /* Mark SSIC port as unused(suspend) or used(resume) */ 376 val = readl(reg); 377 if (suspend) 378 val |= SSIC_PORT_UNUSED; 379 else 380 val &= ~SSIC_PORT_UNUSED; 381 writel(val, reg); 382 383 /* Notify SSIC that SSIC profile programming is done */ 384 val = readl(reg) | PROG_DONE; 385 writel(val, reg); 386 readl(reg); 387 } 388 } 389 390 /* 391 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 392 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 393 */ 394 static void xhci_pme_quirk(struct usb_hcd *hcd) 395 { 396 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 397 void __iomem *reg; 398 u32 val; 399 400 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 401 val = readl(reg); 402 writel(val | BIT(28), reg); 403 readl(reg); 404 } 405 406 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 407 { 408 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 409 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 410 int ret; 411 412 /* 413 * Systems with the TI redriver that loses port status change events 414 * need to have the registers polled during D3, so avoid D3cold. 415 */ 416 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 417 pci_d3cold_disable(pdev); 418 419 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 420 xhci_pme_quirk(hcd); 421 422 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 423 xhci_ssic_port_unused_quirk(hcd, true); 424 425 ret = xhci_suspend(xhci, do_wakeup); 426 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 427 xhci_ssic_port_unused_quirk(hcd, false); 428 429 return ret; 430 } 431 432 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 433 { 434 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 435 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 436 int retval = 0; 437 438 /* The BIOS on systems with the Intel Panther Point chipset may or may 439 * not support xHCI natively. That means that during system resume, it 440 * may switch the ports back to EHCI so that users can use their 441 * keyboard to select a kernel from GRUB after resume from hibernate. 442 * 443 * The BIOS is supposed to remember whether the OS had xHCI ports 444 * enabled before resume, and switch the ports back to xHCI when the 445 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 446 * writers. 447 * 448 * Unconditionally switch the ports back to xHCI after a system resume. 449 * It should not matter whether the EHCI or xHCI controller is 450 * resumed first. It's enough to do the switchover in xHCI because 451 * USB core won't notice anything as the hub driver doesn't start 452 * running again until after all the devices (including both EHCI and 453 * xHCI host controllers) have been resumed. 454 */ 455 456 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 457 usb_enable_intel_xhci_ports(pdev); 458 459 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 460 xhci_ssic_port_unused_quirk(hcd, false); 461 462 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 463 xhci_pme_quirk(hcd); 464 465 retval = xhci_resume(xhci, hibernated); 466 return retval; 467 } 468 #endif /* CONFIG_PM */ 469 470 /*-------------------------------------------------------------------------*/ 471 472 /* PCI driver selection metadata; PCI hotplugging uses this */ 473 static const struct pci_device_id pci_ids[] = { { 474 /* handle any USB 3.0 xHCI controller */ 475 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 476 .driver_data = (unsigned long) &xhci_pci_hc_driver, 477 }, 478 { /* end: all zeroes */ } 479 }; 480 MODULE_DEVICE_TABLE(pci, pci_ids); 481 482 /* pci driver glue; this is a "new style" PCI driver module */ 483 static struct pci_driver xhci_pci_driver = { 484 .name = (char *) hcd_name, 485 .id_table = pci_ids, 486 487 .probe = xhci_pci_probe, 488 .remove = xhci_pci_remove, 489 /* suspend and resume implemented later */ 490 491 .shutdown = usb_hcd_pci_shutdown, 492 #ifdef CONFIG_PM 493 .driver = { 494 .pm = &usb_hcd_pci_pm_ops 495 }, 496 #endif 497 }; 498 499 static int __init xhci_pci_init(void) 500 { 501 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 502 #ifdef CONFIG_PM 503 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 504 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 505 #endif 506 return pci_register_driver(&xhci_pci_driver); 507 } 508 module_init(xhci_pci_init); 509 510 static void __exit xhci_pci_exit(void) 511 { 512 pci_unregister_driver(&xhci_pci_driver); 513 } 514 module_exit(xhci_pci_exit); 515 516 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 517 MODULE_LICENSE("GPL"); 518